From patchwork Thu Jan 16 23:21:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 13942469 Received: from out-178.mta1.migadu.com (out-178.mta1.migadu.com [95.215.58.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 301BB22CBDA for ; Thu, 16 Jan 2025 23:21:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737069695; cv=none; b=bUjoDX2mDI/50N5+2UFC6+FDnbGCHPcf/hn+s7QZV67koAODhi1W6V++ZQRJ6LaWExJa6/N5/blFXSIm4WG/I7MPVlAxENX3TCW28FAZa1JJVHNfrfxU9yrePh0ifmnZvruXcxuAR8xLBD3JirtmSxAEWHBRfXeXMV2q9uuiZoY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737069695; c=relaxed/simple; bh=GrQ1dOEYG/QwkhK9cDDIQ/lwHCD2HXQ+Be10NTa2QtM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=oXqm+71Pv54uYs7q/tfdgvIrCja1XILATuACNHilRjoWQMJZr1gl5TcgITsff18oe4QdosqP4cdX4mU5+o0+Jfgl4BjeRcfbtLyul29zJL9m5XEsEv485RpXcTU/aL9H6fF+V2/cvvtWWk1NBnh6NksdjCP6Rv7Owh0YqbrkCC4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=uZ29omjN; arc=none smtp.client-ip=95.215.58.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="uZ29omjN" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1737069691; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7PJS6kM+DJ2GGwqhWw1shA8+yZPnGkjZF8pz2SUSzfI=; b=uZ29omjNcU4UbYfhIsF0VAP9GJd018ZmYttfHmmZNzR1FIOC3X6U+Ii7BkAzAI1EUTCAJW MCcAyP7yvKL6rQ6AjEcLJNvDpRI0AdQQF4CEnS9BddjgAETgDn5wrADuaE/4/xCo51+h7P nBy/dHyVn8tBKSr5Tgr/U6a/Hru5OxM= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , linux-arm-kernel@lists.infradead.org, Amit Kumar Mahapatra , linux-kernel@vger.kernel.org, Miquel Raynal , Sean Anderson , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH 1/7] dt-bindings: spi: zynqmp-qspi: Split the bus Date: Thu, 16 Jan 2025 18:21:11 -0500 Message-Id: <20250116232118.2694169-2-sean.anderson@linux.dev> In-Reply-To: <20250116232118.2694169-1-sean.anderson@linux.dev> References: <20250116232118.2694169-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT This device supports two separate SPI busses: "lower" (SPI0) and "upper" (SPI1). Each SPI bus has separate clock and data lines, as well as a hardware-controlled chip select. The current binding does not model this situation. It exposes one bus, where CS 0 uses the lower bus and the lower chip select, and CS 1 uses the upper bus and the upper chip select. It is not possible to use the upper chip select with the lower bus (or vice versa). GPIO chip selects are unsupported, and there would be no way to specify which bus to use if they were. Split the "merged" bus into an upper and lower bus, each with their own subnodes. Signed-off-by: Sean Anderson --- .../bindings/spi/spi-zynqmp-qspi.yaml | 43 +++++++++++++++++-- 1 file changed, 40 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml index 901e15fcce2d..12c547c4f1ba 100644 --- a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml @@ -39,6 +39,18 @@ properties: resets: maxItems: 1 + spi-lower: + type: object + $ref: spi-controller.yaml# + unevaluatedProperties: false + description: The "lower" bus (SPI0). On the ZynqMP this uses MIO pins 0-5. + + spi-upper: + type: object + $ref: spi-controller.yaml# + unevaluatedProperties: false + description: The "upper" bus (SPI1). On the ZynqMP this uses MIO pins 7-12. + required: - compatible - reg @@ -50,8 +62,6 @@ required: unevaluatedProperties: false allOf: - - $ref: spi-controller.yaml# - - if: properties: compatible: @@ -75,7 +85,7 @@ examples: #address-cells = <2>; #size-cells = <2>; - qspi: spi@ff0f0000 { + qspi: spi-controller@ff0f0000 { compatible = "xlnx,zynqmp-qspi-1.0"; clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; clock-names = "ref_clk", "pclk"; @@ -84,5 +94,32 @@ examples: resets = <&zynqmp_reset ZYNQMP_RESET_QSPI>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; + + spi-lower { + #address-cells = <1>; + #size-cells = <0>; + num-cs = <2>; + cs-gpios = <0>, <&gpio 5>; + + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + }; + + flash@1 { + reg = <1>; + compatible = "jedec,spi-nor"; + }; + }; + + spi-upper { + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + }; + }; }; }; From patchwork Thu Jan 16 23:21:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 13942470 Received: from out-176.mta1.migadu.com (out-176.mta1.migadu.com [95.215.58.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBCFB241A05 for ; Thu, 16 Jan 2025 23:21:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737069696; cv=none; b=In3Psaf+2+5B1UphTpfvkbDCxpFdnUyc2If7XkgQ5Zm1+Am79okoEYPSisOFQG2TGZUriMCjKkjCvR97pxOfYqbsNMfM9fT9za1BYmsdbT0Yd4+VP9NkG+dKqas8kxKxlgY/kRt0UMAF+2Qnv3TjqkzEPHTXr/aiv9HEJHFaKrc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737069696; c=relaxed/simple; bh=cGARqq8IjWrrcZ6KdmSNFZSMwkTjtVepKJsEOxCEYMc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=VquQ0W+9dUiwM1kfMY/gSi3k62w5uGicrv8VN3QXh+7+SF1vkYjsjpa+OAGClG62yGX0xXVdlchm25Z0qLStDxu5dcF78yY+Q+4FkdsbvzeovLDYRAbWmSPEZzlDI2VVb3CdZnmFQHvMeveGpizCh/MEApR1Wqwy20j3RAlGZ0g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=OZHlBT2E; arc=none smtp.client-ip=95.215.58.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="OZHlBT2E" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1737069692; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=f3kAvIiPvuDbscly1USvzOsklcOMjk05ZoOBm2Yut2w=; b=OZHlBT2EInsgKHaSkHw4Zp/mu/U8KYfBsgR4roeno+oDlFuiQYLIY+Noe2l/rde4Wuidmb bL9U8Dq/8IkbRrP3mXDLK1JcJyKPvpqyhSkeg0dUGrVOwPBgNw7k8EJp91Q6LVN+uVG91h of0+hZ4S9RHUXh/QZ+BL20EnQoVPhQ4= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , linux-arm-kernel@lists.infradead.org, Amit Kumar Mahapatra , linux-kernel@vger.kernel.org, Miquel Raynal , Sean Anderson Subject: [PATCH 2/7] spi: zynqmp-gqspi: Pass speed/mode directly to config_op Date: Thu, 16 Jan 2025 18:21:12 -0500 Message-Id: <20250116232118.2694169-3-sean.anderson@linux.dev> In-Reply-To: <20250116232118.2694169-1-sean.anderson@linux.dev> References: <20250116232118.2694169-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT In preparation for supporting transfer_one, which supplies the speed from the spi_transfer instead of the spi_device, convert config_op to take the speed and mode directly. Signed-off-by: Sean Anderson --- drivers/spi/spi-zynqmp-gqspi.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index 95eea7d75f71..ba12adec8632 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -545,8 +545,8 @@ static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi, /** * zynqmp_qspi_config_op - Configure QSPI controller for specified * transfer - * @xqspi: Pointer to the zynqmp_qspi structure - * @qspi: Pointer to the spi_device structure + * @xqspi: Pointer to the zynqmp_qspi structure + * @req_speed_hz: Requested frequency * * Sets the operational mode of QSPI controller for the next QSPI transfer and * sets the requested clock frequency. @@ -563,13 +563,10 @@ static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi, * by the QSPI controller the driver will set the highest or lowest * frequency supported by controller. */ -static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi, - struct spi_device *qspi) +static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi, u32 req_speed_hz) { ulong clk_rate; - u32 config_reg, req_speed_hz, baud_rate_val = 0; - - req_speed_hz = qspi->max_speed_hz; + u32 config_reg, baud_rate_val = 0; if (xqspi->speed_hz != req_speed_hz) { xqspi->speed_hz = req_speed_hz; @@ -1094,7 +1091,7 @@ static int zynqmp_qspi_exec_op(struct spi_mem *mem, op->dummy.buswidth, op->data.buswidth); mutex_lock(&xqspi->op_lock); - zynqmp_qspi_config_op(xqspi, mem->spi); + zynqmp_qspi_config_op(xqspi, mem->spi->max_speed_hz); zynqmp_qspi_chipselect(mem->spi, false); genfifoentry |= xqspi->genfifocs; genfifoentry |= xqspi->genfifobus; From patchwork Thu Jan 16 23:21:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 13942471 Received: from out-187.mta1.migadu.com (out-187.mta1.migadu.com [95.215.58.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AA8F1DDC02 for ; Thu, 16 Jan 2025 23:21:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737069698; cv=none; b=CXfJywDncuk4bQWSmycH9YoHsDl6YhSb0t9lh2uOqXK6s5DiaBVq59DXm9B3zQrRHBKsapPgr5MFmT6iKTKiht5XBh9xuL+0JHjC32Wf1FyEAnhOUSHnJB1dzOLNLLw8ygguWDnxkouwDlo4s2RHAOJi35QuZuNZeO/l6tB1F3I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737069698; c=relaxed/simple; bh=OOK781rmzkzLoj6MaztFylLTWOfajTWMn0Kdy0HlWJY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ChQYYsDC6HGpFP9pkQrk2GvWgdgbV+YyqM+K4iGrt3t41/9N0630wwoAlF5VZDUc29nfRQ01HAAaz9yYRGnURIfrA6BKHukR5yUefz61YbJV2m8+rp8HxGCOBn+4qD0uI6MGS8eQyasMW4uWoJEIxnqBiCkfHayFNiVJeSbiM68= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=Jh8CpEMO; arc=none smtp.client-ip=95.215.58.187 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="Jh8CpEMO" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1737069694; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tR7y50rU9pbEgmCCWcpvtHmGNRcuzBMssivVLFdASTM=; b=Jh8CpEMOdwgu6Pnxq6Tet2VsuOjmAyePO/p+VNLWKjABgzvL3GoB5J3dnw7d+pGa15dY7k S5bmlvFxriK1IFnsBAEETSMU66FWKCV5JGzYlVxaZm6Wm0r/gAyWaPfX387I8VOl3zrlj3 v0NQ8XVoezZsntJrgtUCD6hgn6XMByw= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , linux-arm-kernel@lists.infradead.org, Amit Kumar Mahapatra , linux-kernel@vger.kernel.org, Miquel Raynal , Sean Anderson Subject: [PATCH 3/7] spi: zynqmp-gqspi: Configure SPI mode dynamically Date: Thu, 16 Jan 2025 18:21:13 -0500 Message-Id: <20250116232118.2694169-4-sean.anderson@linux.dev> In-Reply-To: <20250116232118.2694169-1-sean.anderson@linux.dev> References: <20250116232118.2694169-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT The SPI mode (phase /polarity) can change between spi_transfers. In preparation for transfer_one support, program the SPI mode on every operation instead of once during init. Signed-off-by: Sean Anderson --- drivers/spi/spi-zynqmp-gqspi.c | 43 +++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 14 deletions(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index ba12adec8632..a1233897dc88 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -186,7 +186,8 @@ struct qspi_platform_data { * @mode: Defines the mode in which QSPI is operating * @data_completion: completion structure * @op_lock: Operational lock - * @speed_hz: Current SPI bus clock speed in hz + * @speed_hz: Current SPI bus clock speed in hz + * @spi_mode: Current SPI bus mode * @has_tapdelay: Used for tapdelay register available in qspi */ struct zynqmp_qspi { @@ -210,6 +211,7 @@ struct zynqmp_qspi { struct completion data_completion; struct mutex op_lock; u32 speed_hz; + u32 spi_mode; bool has_tapdelay; }; @@ -397,16 +399,11 @@ static int zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi) config_reg |= GQSPI_CFG_WP_HOLD_MASK; /* Clear pre-scalar by default */ config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK; - /* Set CPHA */ - if (xqspi->ctlr->mode_bits & SPI_CPHA) - config_reg |= GQSPI_CFG_CLK_PHA_MASK; - else - config_reg &= ~GQSPI_CFG_CLK_PHA_MASK; - /* Set CPOL */ - if (xqspi->ctlr->mode_bits & SPI_CPOL) - config_reg |= GQSPI_CFG_CLK_POL_MASK; - else - config_reg &= ~GQSPI_CFG_CLK_POL_MASK; + + /* Set default mode */ + xqspi->spi_mode = SPI_MODE_3; + config_reg |= GQSPI_CFG_CLK_PHA_MASK; + config_reg |= GQSPI_CFG_CLK_POL_MASK; /* Set the clock frequency */ clk_rate = clk_get_rate(xqspi->refclk); @@ -547,6 +544,7 @@ static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi, * transfer * @xqspi: Pointer to the zynqmp_qspi structure * @req_speed_hz: Requested frequency + * @mode: Requested SPI mode * * Sets the operational mode of QSPI controller for the next QSPI transfer and * sets the requested clock frequency. @@ -563,7 +561,8 @@ static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi, * by the QSPI controller the driver will set the highest or lowest * frequency supported by controller. */ -static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi, u32 req_speed_hz) +static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi, u32 req_speed_hz, + u32 mode) { ulong clk_rate; u32 config_reg, baud_rate_val = 0; @@ -589,7 +588,23 @@ static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi, u32 req_speed_hz) zynqmp_qspi_set_tapdelay(xqspi, baud_rate_val); } - dev_dbg(xqspi->dev, "config speed %u\n", req_speed_hz); + mode &= SPI_MODE_X_MASK; + if (xqspi->spi_mode != mode) { + xqspi->spi_mode = mode; + + config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); + if (mode & SPI_CPHA) + config_reg |= GQSPI_CFG_CLK_PHA_MASK; + else + config_reg &= ~GQSPI_CFG_CLK_PHA_MASK; + if (mode & SPI_CPOL) + config_reg |= GQSPI_CFG_CLK_POL_MASK; + else + config_reg &= ~GQSPI_CFG_CLK_POL_MASK; + zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); + } + + dev_dbg(xqspi->dev, "config speed %u mode %x\n", req_speed_hz, mode); return 0; } @@ -1091,7 +1106,7 @@ static int zynqmp_qspi_exec_op(struct spi_mem *mem, op->dummy.buswidth, op->data.buswidth); mutex_lock(&xqspi->op_lock); - zynqmp_qspi_config_op(xqspi, mem->spi->max_speed_hz); + zynqmp_qspi_config_op(xqspi, mem->spi->max_speed_hz, mem->spi->mode); zynqmp_qspi_chipselect(mem->spi, false); genfifoentry |= xqspi->genfifocs; genfifoentry |= xqspi->genfifobus; From patchwork Thu Jan 16 23:21:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 13942472 Received: from out-175.mta1.migadu.com (out-175.mta1.migadu.com [95.215.58.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EAAA0236EAE for ; Thu, 16 Jan 2025 23:21:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737069699; cv=none; b=fV8760g9w0ePks8n3gmaGPMreZd4bb3i0gs5qOEHdiewWVXJuqzSocVGw5Oqp7q4HhesxX2Q3QTXBi9GCpXTXKRYijoO0GceVu/4vR8eH48kx0YD5o/BwKraaZxmvHXYtEt1pT2Mtc93SnLwXbcBCbEHOge/k6lhAN5rjNSdW5c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737069699; c=relaxed/simple; bh=cmpt93uTXNc+OJZHAOkMie/0u7D5Kgb/EnQQoR11n7Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=toLtOKHT45POZJXZBh2BSkUZs22MtJyVRBdjYK2g6UCy/HjksW49hjkpkd9BiSknQYQekKHgulssnMSPRA6SXzz/Kih7T7nY9zbQSkQ1xFIx4x8XtUrksaSKSqqLOmONPBpyCWSz/6I7bhQR7JgwSL4QqFBCtWvOQr+pmiWqwQE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=Thjwuswf; arc=none smtp.client-ip=95.215.58.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="Thjwuswf" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1737069696; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fStIbrCOb/5ColUxilUsQxP712qLdfKYYHDEiYij27w=; b=ThjwuswfDNPcj2UE4dP0vdjjWbWAYcdXs2jMVU1jT+42ZK8CguBj+r51yWDkZtt6SNPocY uq6JTjleQaOmNDEM6GilRXNXu+lpqzziHkkZ0CRwOPmgLqGihk+FvJxlzmrBqqURYVM9n5 9TXbQ2KWJ39SCpmjBnJ0f7UclKrYQso= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , linux-arm-kernel@lists.infradead.org, Amit Kumar Mahapatra , linux-kernel@vger.kernel.org, Miquel Raynal , Sean Anderson Subject: [PATCH 4/7] spi: zynqmp-gqspi: Refactor out controller initialization Date: Thu, 16 Jan 2025 18:21:14 -0500 Message-Id: <20250116232118.2694169-5-sean.anderson@linux.dev> In-Reply-To: <20250116232118.2694169-1-sean.anderson@linux.dev> References: <20250116232118.2694169-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT In preparation for having multiple SPI busses, refactor out the controller initialization into a separate function. No functional change intended. Signed-off-by: Sean Anderson --- drivers/spi/spi-zynqmp-gqspi.c | 42 +++++++++++++++++++++------------- 1 file changed, 26 insertions(+), 16 deletions(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index a1233897dc88..d78e114e17e0 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -1253,6 +1253,29 @@ static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = { .exec_op = zynqmp_qspi_exec_op, }; +static int zynqmp_qspi_register_ctlr(struct zynqmp_qspi *xqspi, + struct spi_controller *ctlr) +{ + int ret; + + if (!ctlr) + return 0; + + ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD | + SPI_TX_DUAL | SPI_TX_QUAD; + ctlr->max_speed_hz = xqspi->speed_hz; + ctlr->bits_per_word_mask = SPI_BPW_MASK(8); + ctlr->mem_ops = &zynqmp_qspi_mem_ops; + ctlr->setup = zynqmp_qspi_setup_op; + ctlr->auto_runtime_pm = true; + + ret = devm_spi_register_controller(xqspi->dev, ctlr); + if (ret) + dev_err_probe(xqspi->dev, ret, "could not register %pOF\n", + ctlr->dev.of_node); + return ret; +} + /** * zynqmp_qspi_probe - Probe method for the QSPI driver * @pdev: Pointer to the platform_device structure @@ -1329,12 +1352,8 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) goto clk_dis_all; } - ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD | - SPI_TX_DUAL | SPI_TX_QUAD; - ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2; - xqspi->speed_hz = ctlr->max_speed_hz; - /* QSPI controller initializations */ + xqspi->speed_hz = clk_get_rate(xqspi->refclk) / 2; ret = zynqmp_qspi_init_hw(xqspi); if (ret) goto clk_dis_all; @@ -1368,18 +1387,9 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) ctlr->num_chipselect = num_cs; } - ctlr->bits_per_word_mask = SPI_BPW_MASK(8); - ctlr->mem_ops = &zynqmp_qspi_mem_ops; - ctlr->setup = zynqmp_qspi_setup_op; - ctlr->bits_per_word_mask = SPI_BPW_MASK(8); - ctlr->dev.of_node = np; - ctlr->auto_runtime_pm = true; - - ret = devm_spi_register_controller(&pdev->dev, ctlr); - if (ret) { - dev_err(&pdev->dev, "spi_register_controller failed\n"); + ret = zynqmp_qspi_register_ctlr(xqspi, ctlr); + if (ret) goto clk_dis_all; - } pm_runtime_mark_last_busy(&pdev->dev); pm_runtime_put_autosuspend(&pdev->dev); From patchwork Thu Jan 16 23:21:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 13942475 Received: from out-186.mta1.migadu.com (out-186.mta1.migadu.com [95.215.58.186]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 332CF2442D0 for ; Thu, 16 Jan 2025 23:21:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.186 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737069705; cv=none; b=RBjJw4HHeJ/0buhohrEfIgmQcIyH6ZmCMTEsP/21xw/qqfsZ/e8e7sSd4icglGMTz2sfOxcUyvSYF3jzbmmYYEyCdwSLUxiDLsd+bTU+RkakARntZV+gKH52UCZu2c8d7PpGPPAO6dCrm9B44+1EUS1GcovOHGimHPQ3WbtRtKc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737069705; c=relaxed/simple; bh=H/cFoJO8k1ct30ihhvF4ET0+AF+lsfzgR0c326wEI3A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Oo1Lke4OJ/eajg3xJAqoelNbg70abUQAykoexTa9Bfxs4dW5FuwjLZoV8BwaqzQMrxRGihESpCJDXSMdUjUwiLLCxdN7y+/RaW5gy/+rYwG1OZX81mGyuv8NOLXjJLcOS27X+c29JkL6JlUkGX4qNgC8jEGki7SCKALi96wzWcw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=tcPnw3UZ; arc=none smtp.client-ip=95.215.58.186 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="tcPnw3UZ" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1737069698; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WWociCl4bVfAjOOY4p6sldW8VifVxjxPHAFfPT85y74=; b=tcPnw3UZ2J0b92pJLokBFDODxVsw+0vMfWPLiEUFE/LQfXGgrs6i2KG+8BMGu944i4IN+o mKC1M9buWhD5qpqjnHr3cpn7qWHk30w+dDUDcqt+HLBrA957RXEg52OLynMam0eA6SS8Xt mOz4colEOoTkvmPXElTMNtUXrAzz7t8= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , linux-arm-kernel@lists.infradead.org, Amit Kumar Mahapatra , linux-kernel@vger.kernel.org, Miquel Raynal , Sean Anderson Subject: [PATCH 5/7] spi: zynqmp-gqspi: Split the bus Date: Thu, 16 Jan 2025 18:21:15 -0500 Message-Id: <20250116232118.2694169-6-sean.anderson@linux.dev> In-Reply-To: <20250116232118.2694169-1-sean.anderson@linux.dev> References: <20250116232118.2694169-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT This device supports two separate SPI busses: "lower" (SPI0) and "upper" (SPI1). Each SPI bus has separate clock and data lines, as well as a hardware-controlled chip select. The busses may be driven independently, with only one bus active at a time, or in concert, with both busses active. If both busses are driven at once, data may either be duplicated on each bus or striped (bitwise) across both busses. The current driver does not model this situation. It exposes one bus, where CS 0 uses the lower bus and the lower chip select, and CS 1 uses the upper bus and the upper chip select. It is not possible to use the upper chip select with the lower bus (or vice versa). GPIO chip selects are unsupported, and there would be no way to specify which bus to use if they were. To conserve pins, designers may wish to place multiple devices on a single SPI bus. Add support for this by splitting the "merged" bus into an upper and lower bus. Each bus uses a separate devicetree node and has a single native chipselect 0. If "lower" and "upper" nodes are absent from the devicetree, we register the merged bus instead, which maintains the current behavior. Signed-off-by: Sean Anderson --- drivers/spi/spi-zynqmp-gqspi.c | 155 ++++++++++++++++++++++++++------- 1 file changed, 125 insertions(+), 30 deletions(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index d78e114e17e0..9823d710c4d6 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -167,6 +167,10 @@ struct qspi_platform_data { /** * struct zynqmp_qspi - Defines qspi driver instance + * @lower Pointer to "lower" SPI bus + * @upper Pointer to "upper" SPI bus + * @merged Pointer to legacy SPI bus which is a combination of + * @lower and @upper * @ctlr: Pointer to the spi controller information * @regs: Virtual address of the QSPI controller registers * @refclk: Pointer to the peripheral clock @@ -191,7 +195,7 @@ struct qspi_platform_data { * @has_tapdelay: Used for tapdelay register available in qspi */ struct zynqmp_qspi { - struct spi_controller *ctlr; + struct spi_controller *lower, *upper, *merged; void __iomem *regs; struct clk *refclk; struct clk *pclk; @@ -467,20 +471,33 @@ static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi, */ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high) { - struct zynqmp_qspi *xqspi = spi_controller_get_devdata(qspi->controller); + struct spi_controller *ctlr = qspi->controller; + struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr); ulong timeout; u32 genfifoentry = 0, statusreg; genfifoentry |= GQSPI_GENFIFO_MODE_SPI; if (!is_high) { - if (!spi_get_chipselect(qspi, 0)) { - xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER; - xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER; + bool upper; + + if (ctlr == xqspi->lower) { + upper = false; + } else if (ctlr == xqspi->upper) { + upper = true; } else { + WARN_ON_ONCE(ctlr != xqspi->merged); + upper = spi_get_chipselect(qspi, 0); + } + + if (upper) { xqspi->genfifobus = GQSPI_GENFIFO_BUS_UPPER; xqspi->genfifocs = GQSPI_GENFIFO_CS_UPPER; + } else { + xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER; + xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER; } + genfifoentry |= xqspi->genfifobus; genfifoentry |= xqspi->genfifocs; genfifoentry |= GQSPI_GENFIFO_CS_SETUP; @@ -962,12 +979,28 @@ static int zynqmp_qspi_read_op(struct zynqmp_qspi *xqspi, u8 rx_nbits, static int __maybe_unused zynqmp_qspi_suspend(struct device *dev) { struct zynqmp_qspi *xqspi = dev_get_drvdata(dev); - struct spi_controller *ctlr = xqspi->ctlr; int ret; - ret = spi_controller_suspend(ctlr); - if (ret) - return ret; + if (xqspi->merged) { + ret = spi_controller_suspend(xqspi->merged); + if (ret) + return ret; + } else { + if (xqspi->lower) { + ret = spi_controller_suspend(xqspi->lower); + if (ret) + return ret; + } + + if (xqspi->upper) { + ret = spi_controller_suspend(xqspi->upper); + if (ret) { + if (xqspi->lower) + spi_controller_resume(xqspi->lower); + return ret; + } + } + } zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0); @@ -986,13 +1019,18 @@ static int __maybe_unused zynqmp_qspi_suspend(struct device *dev) static int __maybe_unused zynqmp_qspi_resume(struct device *dev) { struct zynqmp_qspi *xqspi = dev_get_drvdata(dev); - struct spi_controller *ctlr = xqspi->ctlr; + int ret = 0; zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK); - spi_controller_resume(ctlr); + if (xqspi->merged) + ret = spi_controller_resume(xqspi->merged); + if (xqspi->lower) + ret = spi_controller_resume(xqspi->lower) ?: ret; + if (xqspi->upper) + ret = spi_controller_resume(xqspi->upper) ?: ret; - return 0; + return ret; } /** @@ -1253,6 +1291,41 @@ static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = { .exec_op = zynqmp_qspi_exec_op, }; +static void zynqmp_qspi_release_node(void *of_node) +{ + of_node_put(of_node); +} + +static struct spi_controller * +zynqmp_qspi_alloc_split(struct zynqmp_qspi *xqspi, const char *name) +{ + struct spi_controller *ctlr; + struct device_node *np; + u32 num_cs; + int err; + + np = of_get_child_by_name(xqspi->dev->of_node, name); + if (!np) + return NULL; + + err = devm_add_action_or_reset(xqspi->dev, zynqmp_qspi_release_node, + np); + if (err) + return ERR_PTR(err); + + ctlr = devm_spi_alloc_host(xqspi->dev, 0); + if (!ctlr) + return ERR_PTR(-ENOMEM); + + ctlr->dev.of_node = np; + if (of_property_read_u32(np, "num-cs", &num_cs)) + ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS; + else + ctlr->num_chipselect = num_cs; + + return ctlr; +} + static int zynqmp_qspi_register_ctlr(struct zynqmp_qspi *xqspi, struct spi_controller *ctlr) { @@ -1261,6 +1334,7 @@ static int zynqmp_qspi_register_ctlr(struct zynqmp_qspi *xqspi, if (!ctlr) return 0; + spi_controller_set_devdata(ctlr, xqspi); ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; ctlr->max_speed_hz = xqspi->speed_hz; @@ -1287,22 +1361,47 @@ static int zynqmp_qspi_register_ctlr(struct zynqmp_qspi *xqspi, static int zynqmp_qspi_probe(struct platform_device *pdev) { int ret = 0; - struct spi_controller *ctlr; struct zynqmp_qspi *xqspi; struct device *dev = &pdev->dev; - struct device_node *np = dev->of_node; - u32 num_cs; const struct qspi_platform_data *p_data; - ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*xqspi)); - if (!ctlr) + xqspi = devm_kzalloc(dev, sizeof(*xqspi), GFP_KERNEL); + if (!xqspi) return -ENOMEM; - xqspi = spi_controller_get_devdata(ctlr); xqspi->dev = dev; - xqspi->ctlr = ctlr; platform_set_drvdata(pdev, xqspi); + xqspi->lower = zynqmp_qspi_alloc_split(xqspi, "spi-lower"); + if (IS_ERR(xqspi->lower)) + return PTR_ERR(xqspi->lower); + + xqspi->upper = zynqmp_qspi_alloc_split(xqspi, "spi-upper"); + if (IS_ERR(xqspi->upper)) + return PTR_ERR(xqspi->upper); + + if (!xqspi->lower && !xqspi->upper) { + struct spi_controller *ctlr = devm_spi_alloc_host(dev, 0); + u32 num_cs; + + if (!ctlr) + return -ENOMEM; + + ret = of_property_read_u32(dev->of_node, "num-cs", &num_cs); + if (ret < 0) { + ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS; + } else if (num_cs > GQSPI_MAX_NUM_CS) { + dev_err(dev, "only %d chip selects are available\n", + GQSPI_MAX_NUM_CS); + return -EINVAL; + } else { + ctlr->num_chipselect = num_cs; + } + + ctlr->dev.of_node = dev->of_node; + xqspi->merged = ctlr; + } + p_data = of_device_get_match_data(&pdev->dev); if (p_data && (p_data->quirks & QSPI_QUIRK_HAS_TAPDELAY)) xqspi->has_tapdelay = true; @@ -1375,19 +1474,15 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) if (ret) goto clk_dis_all; - ret = of_property_read_u32(np, "num-cs", &num_cs); - if (ret < 0) { - ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS; - } else if (num_cs > GQSPI_MAX_NUM_CS) { - ret = -EINVAL; - dev_err(&pdev->dev, "only %d chip selects are available\n", - GQSPI_MAX_NUM_CS); + ret = zynqmp_qspi_register_ctlr(xqspi, xqspi->lower); + if (ret) goto clk_dis_all; - } else { - ctlr->num_chipselect = num_cs; - } - ret = zynqmp_qspi_register_ctlr(xqspi, ctlr); + ret = zynqmp_qspi_register_ctlr(xqspi, xqspi->upper); + if (ret) + goto clk_dis_all; + + ret = zynqmp_qspi_register_ctlr(xqspi, xqspi->merged); if (ret) goto clk_dis_all; From patchwork Thu Jan 16 23:21:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 13942474 Received: from out-185.mta1.migadu.com (out-185.mta1.migadu.com [95.215.58.185]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEB2E241A0B for ; Thu, 16 Jan 2025 23:21:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.185 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737069703; cv=none; b=HlMRRZ+Y93S5xtocQf5h39Z570+2FjtnOBG12CTYsTS8/U5ZmeDgqwzHLqUOwfGi0v6gUD94yugVHRUPs3MeFv9S7eIxOeC1SISrvTciUVZceRfI/U5h3yHwQsswgYWNl2Sf/9EE9FLj1p3p+PKvz8nwk/At9I4O9rdTFtHwQko= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737069703; c=relaxed/simple; bh=t+jiC9zkX1Xh/vs8ZAOS/bTNB7s03aofjGiFfqcq76Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=S+DKfBkUyR6EAxGgw24cU2pUgqreVr+uBq1FjY/Bf/Kf2OKdTygie35pe+I4lVWQherQTHvp+TUIlKOlamhEE57W/c+fABhpywLVIdXh5PrFv5qdkqUrzDgAMDsbkIAHTd9gP/POFlVa18d5+VNWD12otN+8VuttqQ6gqVoP6Bc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=FC8PcUCx; arc=none smtp.client-ip=95.215.58.185 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="FC8PcUCx" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1737069700; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iHGW05zMsRoR73u/6yei3oxj4qrZbmDsPW4oXB+eZkU=; b=FC8PcUCx4FLk+kJ5dUK5PmZ4kNCi7FHBtSOZdcTd1NI9Cv+mzt3FYqh/GEDIQAJplr2LTH +CB0MonTZo3qbrYkTjhmYQ+MJi4fEyQvvGxfpkgZDbrZGPv7+x6WldnxUDrN/3AQR2rY+B g9rKRJZXgpZvbq+Te/7nPRvzt3Y89cM= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , linux-arm-kernel@lists.infradead.org, Amit Kumar Mahapatra , linux-kernel@vger.kernel.org, Miquel Raynal , Sean Anderson Subject: [PATCH 6/7] spi: zynqmp-gqspi: Support GPIO chip selects Date: Thu, 16 Jan 2025 18:21:16 -0500 Message-Id: <20250116232118.2694169-7-sean.anderson@linux.dev> In-Reply-To: <20250116232118.2694169-1-sean.anderson@linux.dev> References: <20250116232118.2694169-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT GPIO chipselects use the traditional SPU API instead of the SPIMEM API. Implement it with transfer_one and set_cs (for non-GPIO chipselects). At the moment we only support half-duplex transfers, which is good enough to access SPI flashes. Signed-off-by: Sean Anderson --- drivers/spi/spi-zynqmp-gqspi.c | 83 ++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index 9823d710c4d6..efd01e06b77a 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -528,6 +528,15 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high) dev_err(xqspi->dev, "Chip select timed out\n"); } +static void zynqmp_qspi_set_cs(struct spi_device *qspi, bool is_high) +{ + struct zynqmp_qspi *xqspi = spi_controller_get_devdata(qspi->controller); + + mutex_lock(&xqspi->op_lock); + zynqmp_qspi_chipselect(qspi, is_high); + mutex_unlock(&xqspi->op_lock); +} + /** * zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4. * @xqspi: xqspi is a pointer to the GQSPI instance @@ -1271,6 +1280,75 @@ static int zynqmp_qspi_exec_op(struct spi_mem *mem, return err; } +static int zynqmp_qspi_transfer_one(struct spi_controller *ctlr, + struct spi_device *spi, + struct spi_transfer *transfer) +{ + struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr); + unsigned long timeout; + u32 genfifoentry; + u32 mask = 0; + int ret; + + dev_dbg(xqspi->dev, "xfer %u/%u %u\n", transfer->tx_nbits, + transfer->rx_nbits, transfer->len); + + if (transfer->tx_nbits && transfer->rx_nbits) + return -EOPNOTSUPP; + + guard(mutex)(&xqspi->op_lock); + zynqmp_qspi_config_op(xqspi, transfer->speed_hz, spi->mode); + if (spi_get_csgpiod(spi, 0)) { + if (ctlr == xqspi->lower) { + xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER; + } else { + WARN_ON_ONCE(ctlr != xqspi->upper); + xqspi->genfifobus = GQSPI_GENFIFO_BUS_UPPER; + } + xqspi->genfifocs = 0; + } + genfifoentry = xqspi->genfifocs | xqspi->genfifobus; + + reinit_completion(&xqspi->data_completion); + if (transfer->tx_nbits) { + xqspi->txbuf = transfer->tx_buf; + xqspi->rxbuf = NULL; + xqspi->bytes_to_transfer = transfer->len; + xqspi->bytes_to_receive = 0; + zynqmp_qspi_write_op(xqspi, transfer->tx_nbits, genfifoentry); + mask = GQSPI_IER_TXEMPTY_MASK | GQSPI_IER_GENFIFOEMPTY_MASK | + GQSPI_IER_TXNOT_FULL_MASK; + timeout = zynqmp_qspi_timeout(xqspi, transfer->tx_nbits, + transfer->len); + } else { + xqspi->txbuf = NULL; + xqspi->rxbuf = transfer->rx_buf; + xqspi->bytes_to_transfer = 0; + xqspi->bytes_to_receive = transfer->len; + ret = zynqmp_qspi_read_op(xqspi, transfer->rx_nbits, + genfifoentry); + if (ret) + return ret; + + if (xqspi->mode != GQSPI_MODE_DMA) + mask = GQSPI_IER_GENFIFOEMPTY_MASK | + GQSPI_IER_RXNEMPTY_MASK | GQSPI_IER_RXEMPTY_MASK; + timeout = zynqmp_qspi_timeout(xqspi, transfer->rx_nbits, + transfer->len); + } + + zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, + zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) | + GQSPI_CFG_START_GEN_FIFO_MASK); + if (mask) + zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST, mask); + else + zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_EN_OFST, + GQSPI_QSPIDMA_DST_I_EN_DONE_MASK); + + return zynqmp_qspi_wait(xqspi, timeout); +} + static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = { SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend, zynqmp_runtime_resume, NULL) @@ -1318,6 +1396,7 @@ zynqmp_qspi_alloc_split(struct zynqmp_qspi *xqspi, const char *name) return ERR_PTR(-ENOMEM); ctlr->dev.of_node = np; + ctlr->max_native_cs = 1; if (of_property_read_u32(np, "num-cs", &num_cs)) ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS; else @@ -1337,11 +1416,15 @@ static int zynqmp_qspi_register_ctlr(struct zynqmp_qspi *xqspi, spi_controller_set_devdata(ctlr, xqspi); ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; + ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX; ctlr->max_speed_hz = xqspi->speed_hz; ctlr->bits_per_word_mask = SPI_BPW_MASK(8); ctlr->mem_ops = &zynqmp_qspi_mem_ops; ctlr->setup = zynqmp_qspi_setup_op; + ctlr->set_cs = zynqmp_qspi_set_cs; + ctlr->transfer_one = zynqmp_qspi_transfer_one; ctlr->auto_runtime_pm = true; + ctlr->use_gpio_descriptors = true; ret = devm_spi_register_controller(xqspi->dev, ctlr); if (ret) From patchwork Thu Jan 16 23:21:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 13942476 Received: from out-177.mta1.migadu.com (out-177.mta1.migadu.com [95.215.58.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D5F0244FA9 for ; Thu, 16 Jan 2025 23:21:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737069707; cv=none; b=D4355yBAC0fdcxCz1OYit3FzxkVf2N2B1ewuSY5JebJ/19lcRZfI2g14mjvlhz+mxLQiS6JVhg4UbihfPH/qWpSm2uLC9C/CJUv7FNWkYVXF45/Wwn7lskB9JbIfx9Tjr2KEK+5z8K6cD5da+ikkAXpTcDyL2O5nT5YDVGIYbMM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737069707; c=relaxed/simple; bh=UQpviLb6rFo0Nakm4Q7xmYgcU6KPPAhHi2AiICH1T/g=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Zzvd+hs16bBMPV4GgpP9ehWwyzos8q60tmKvW0byyZIMnXtnupvXbriCzTEdGJX+620IQWNuSBk6FExWA6crIt9Li1Kj7nAnA6sv8R+RedjllaFLYyeZ7VGa9LCFOfOb/fiDxd7vqUC72/0nsfpAoKXEbVHMIBRpNNbEHLhgXwo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=I5ESkJp7; arc=none smtp.client-ip=95.215.58.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="I5ESkJp7" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1737069703; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6Y9p6ibc/bj3AV8FXwHT1h+AI01HJG79MMwLbgeY3aY=; b=I5ESkJp7jccj+p7MTg/3SaqOFMdzqlC543kNhuKXyIO5ET2tSkUSKe4SclpJmgArTud0qH rVfVlL921C/RGjRtFB+PYcyrGq5sPHZbegg5CffrVDVyF1PVBsKx2d5Zk19i9Sa6UGtjgy 8xPc/CE0qvORpLcVkAYDDRHzUhMCkZQ= From: Sean Anderson To: Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , linux-arm-kernel@lists.infradead.org, Amit Kumar Mahapatra , linux-kernel@vger.kernel.org, Miquel Raynal , Sean Anderson , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH 7/7] ARM64: xilinx: zynqmp: Convert to split QSPI bus Date: Thu, 16 Jan 2025 18:21:17 -0500 Message-Id: <20250116232118.2694169-8-sean.anderson@linux.dev> In-Reply-To: <20250116232118.2694169-1-sean.anderson@linux.dev> References: <20250116232118.2694169-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT Convert the ZynqMP devicetrees to use the split QSPI bus binding. This is pretty simple, since all boards use only CS0. Signed-off-by: Sean Anderson --- arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 5 ++++- arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 5 ++++- arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 5 ++++- .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 5 ++++- .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 5 ++++- arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 5 ++++- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 5 ++++- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 5 ++++- arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 5 ++++- arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 5 ++++- .../arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts | 5 ++++- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 15 +++++++++++---- 12 files changed, 55 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index bfa7ea6b9224..64b90de5b4ce 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -35,7 +35,7 @@ aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; - spi0 = &qspi; + spi0 = &qspi_lower; spi1 = &spi0; spi2 = &spi1; usb0 = &usb0; @@ -129,6 +129,9 @@ mux { &qspi { /* MIO 0-5 - U143 */ status = "okay"; +}; + +&qspi_lower { spi_flash: flash@0 { /* MT25QU512A */ compatible = "jedec,spi-nor"; /* 64MB */ reg = <0>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts index 04079d1704f1..8927e0463cf4 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts @@ -19,7 +19,7 @@ / { aliases { serial0 = &uart0; serial1 = &dcc; - spi0 = &qspi; + spi0 = &qspi_lower; }; chosen { @@ -39,6 +39,9 @@ &dcc { &qspi { status = "okay"; +}; + +&qspi_lower { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts index 3dec57cf18be..da07b58706f0 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts @@ -20,7 +20,7 @@ / { aliases { serial0 = &uart0; serial1 = &dcc; - spi0 = &qspi; + spi0 = &qspi_lower; }; chosen { @@ -40,6 +40,9 @@ &dcc { &qspi { status = "okay"; +}; + +&qspi_lower { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index 6aff22d43361..ec570d68a4ae 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -27,7 +27,7 @@ aliases { mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; - spi0 = &qspi; + spi0 = &qspi_lower; usb0 = &usb0; }; @@ -354,6 +354,9 @@ &psgtr { &qspi { status = "okay"; +}; + +&qspi_lower { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts index 6ec1d9813973..e1cfdc0db51e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts @@ -26,7 +26,7 @@ aliases { rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; - spi0 = &qspi; + spi0 = &qspi_lower; }; chosen { @@ -172,6 +172,9 @@ &i2c1 { &qspi { status = "okay"; +}; + +&qspi_lower { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 7e26489a1539..18e323e2aad7 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -31,7 +31,7 @@ aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; - spi0 = &qspi; + spi0 = &qspi_lower; usb0 = &usb0; }; @@ -953,6 +953,9 @@ &psgtr { &qspi { status = "okay"; +}; + +&qspi_lower { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */ #address-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index eb2090673ec1..026053c4116a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -29,7 +29,7 @@ aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; - spi0 = &qspi; + spi0 = &qspi_lower; usb0 = &usb0; }; @@ -439,6 +439,9 @@ &psgtr { &qspi { status = "okay"; +}; + +&qspi_lower { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 4694d0a841f1..da56e532dc2b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -29,7 +29,7 @@ aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; - spi0 = &qspi; + spi0 = &qspi_lower; usb0 = &usb0; }; @@ -451,6 +451,9 @@ &psgtr { &qspi { status = "okay"; +}; + +&qspi_lower { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 7beedd730f94..8dd73b035969 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -31,7 +31,7 @@ aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; - spi0 = &qspi; + spi0 = &qspi_lower; usb0 = &usb0; }; @@ -959,6 +959,9 @@ &psgtr { &qspi { status = "okay"; +}; + +&qspi_lower { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */ #address-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index b67ff7ecf3c3..9ed7972c3b4e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -30,7 +30,7 @@ aliases { rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; - spi0 = &qspi; + spi0 = &qspi_lower; usb0 = &usb0; }; @@ -789,6 +789,9 @@ &psgtr { &qspi { status = "okay"; +}; + +&qspi_lower { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */ #address-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts index a38c2baeba6c..99d007b3bfae 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts @@ -20,7 +20,7 @@ / { aliases { serial0 = &uart0; serial1 = &dcc; - spi0 = &qspi; + spi0 = &qspi_lower; }; chosen { @@ -44,6 +44,9 @@ &gpio { &qspi { status = "okay"; +}; + +&qspi_lower { flash@0 { compatible = "m25p80", "jedec,spi-nor"; reg = <0x0>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 5dac0542a48d..470e0b90382f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -972,21 +972,28 @@ pcie_intc: legacy-interrupt-controller { }; }; - qspi: spi@ff0f0000 { + qspi: spi-controller@ff0f0000 { bootph-all; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = ; interrupt-parent = <&gic>; - num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; - #address-cells = <1>; - #size-cells = <0>; /* iommus = <&smmu 0x873>; */ power-domains = <&zynqmp_firmware PD_QSPI>; resets = <&zynqmp_reset ZYNQMP_RESET_QSPI>; + + qspi_lower: spi-lower { + #address-cells = <1>; + #size-cells = <0>; + }; + + qspi_upper: spi-upper { + #address-cells = <1>; + #size-cells = <0>; + }; }; psgtr: phy@fd400000 {