From patchwork Thu Jan 16 23:23:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Saini X-Patchwork-Id: 13942677 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 05758C02183 for ; Thu, 16 Jan 2025 23:33:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=bH78J9VP5ficnGV2dvBvEUQV0y++qVoeHqjErfV0eHE=; b=DeBVqP3U2pQTVRWJlJvTZYMk5G YrjDNHCO+ZRJGP4Yd7t/9IR7DfcOZi/aItFfQ3tUg0hPyrvn2juycy9+bu6Jz5TKA5jLyJCXG0teX tyWhmnQsPwSi8lsszjbCM5bPmRwRl56Y3Sn7Z6ptq3iw2dvTlsSynPdT/1rCifHE6ViRDuskGvaLU 1TArVKBltBaogDKwwB8hQFSEhB3K6E0K65pm2Lm652oKQV3n5l8Hr0XBbFw6RJPDq2fPdCS9d1JJ+ iPk5yFWCksSb8AvKv+mxAMX6Ih2JyGmv0LqJNA2Pf66KMwOn8P5CF93DJ0mXYGQUc1jJfrvWnhljq P0jOrfEw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tYZMK-0000000GUpu-0W7h; Thu, 16 Jan 2025 23:33:08 +0000 Received: from linux.microsoft.com ([13.77.154.182]) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tYZCm-0000000GPiZ-1gwB for linux-arm-kernel@lists.infradead.org; Thu, 16 Jan 2025 23:23:17 +0000 Received: from thinkpad-p16sg1.corp.microsoft.com (unknown [20.236.10.66]) by linux.microsoft.com (Postfix) with ESMTPSA id 00E9220591AB; Thu, 16 Jan 2025 15:23:14 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 00E9220591AB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1737069795; bh=bH78J9VP5ficnGV2dvBvEUQV0y++qVoeHqjErfV0eHE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fsY2vTPsopRlT2ivKJccsz24SyonfDNFDTJtw8mQp86qab/2OYgIJv4cfi6g957io 6kNe61Orz/E2fYfbuTokuulXEEB39uGSRqYBGsvA/UiNVIwp3P2tRgIAEJzFSyfSsk sV7wfkaIeEvMZybLUmt51QezKGMG0Gg4b5gfh++w= From: Shyam Saini To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, virtualization@lists.linux.dev Cc: will@kernel.org, jacob.pan@linux.microsoft.com, eric.auger@redhat.com, code@tyhicks.com, eahariha@linux.microsoft.com, vijayb@linux.microsoft.com Subject: [PATCH 1/3] dt-bindings: iommu: add "arm,smmu-pci-msi-iova-data" property Date: Thu, 16 Jan 2025 15:23:07 -0800 Message-Id: <20250116232307.1436693-4-shyamsaini@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250116232307.1436693-1-shyamsaini@linux.microsoft.com> References: <20250116232307.1436693-1-shyamsaini@linux.microsoft.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250116_152316_485869_9F70589A X-CRM114-Status: GOOD ( 12.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org By default ARM SMMU drivers use MSI_IOVA_BASE macro to reserve PCI MSI IOVA memory range, this assumes that all the platforms have MSI_IOVA_BASE address available for MSI reservation. However, this is not always the case, as some platforms may have the default address reserved for some other purposes and as a consequence ARM SMMU drivers can't reserve MSI memory for those platforms. To address this issue, add a new dts property "arm,smmu-pci-msi-iova-data" which can be used to hold custom PCI MSI IOVA address and its address length. This property can be passed to ARM SMMU drivers via device tree to reserve specified memory range for MSI. Signed-off-by: Shyam Saini --- .../devicetree/bindings/iommu/arm,smmu-v3.yaml | 12 ++++++++++++ .../devicetree/bindings/iommu/arm,smmu.yaml | 12 ++++++++++++ 2 files changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml index 75fcf4cb52d9f..dbad612886604 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml @@ -56,6 +56,17 @@ properties: NOTE: this only applies to the SMMU itself, not masters connected upstream of the SMMU. + arm,smmu-pci-msi-iova-data: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + Specifies a custom PCI MSI base I/O Virtual Address and its memory range + size for ARM SMMU drivers. This allows setting a custom address and + memory size pair if the default MSI_IOVA_BASE_DEFAULT address and + MSI_IOVA_LENGTH_DEFAULT size are not suitable for the intended platform. + items: + - description: MSI IOVA base address + - description: MSI IOVA address length + msi-parent: true hisilicon,broken-prefetch-cmd: @@ -92,4 +103,5 @@ examples: dma-coherent; #iommu-cells = <1>; msi-parent = <&its 0xff0000>; + arm,smmu-pci-msi-iova-data = <0xa0000000 0x100000>; }; diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 032fdc27127bf..d080b13765d1f 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -207,6 +207,17 @@ properties: NOTE: this only applies to the SMMU itself, not masters connected upstream of the SMMU. + arm,smmu-pci-msi-iova-data: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + Specifies a custom PCI MSI base I/O Virtual Address and its memory range + size for ARM SMMU drivers. This allows setting a custom address and + memory size pair if the default MSI_IOVA_BASE_DEFAULT address and + MSI_IOVA_LENGTH_DEFAULT size are not suitable for the intended platform. + items: + - description: MSI IOVA base address + - description: MSI IOVA address length + calxeda,smmu-secure-config-access: type: boolean description: @@ -679,6 +690,7 @@ examples: #iommu-cells = <1>; /* always ignore appended 5-bit TBU number */ stream-match-mask = <0x7c00>; + arm,smmu-pci-msi-iova-data = <0xa0000000 0x100000>; }; bus { From patchwork Thu Jan 16 23:23:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Saini X-Patchwork-Id: 13942713 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1E847C02187 for ; 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Thu, 16 Jan 2025 23:23:21 +0000 Received: from thinkpad-p16sg1.corp.microsoft.com (unknown [20.236.10.66]) by linux.microsoft.com (Postfix) with ESMTPSA id A6B9620591AA; Thu, 16 Jan 2025 15:23:14 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com A6B9620591AA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1737069794; bh=P4jWpJL3m1B1x7U4cIHota00Kj8/WCnEujqgPgEJRxo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ENqnNakSMHsmOehkMhdCS86XVVsyp0OqocXw//ub6IESyVXTwFgTXnVwkrObPMfqe ddnrIOQI27nypt9wuBDgIzGjNWBpQLwdczEJfRH+XqGHgmfklza1bVLj2r4duK9tJE 8YtDQmTf6hhwW52FrQB9WbAayAuV27zb5/mL0Bwc= From: Shyam Saini To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, virtualization@lists.linux.dev Cc: will@kernel.org, jacob.pan@linux.microsoft.com, eric.auger@redhat.com, code@tyhicks.com, eahariha@linux.microsoft.com, vijayb@linux.microsoft.com Subject: [PATCH 2/3] iommu: consolidate MSI_IOVA macro definitions Date: Thu, 16 Jan 2025 15:23:06 -0800 Message-Id: <20250116232307.1436693-3-shyamsaini@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250116232307.1436693-1-shyamsaini@linux.microsoft.com> References: <20250116232307.1436693-1-shyamsaini@linux.microsoft.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250116_232320_363593_2FD5CDE2 X-CRM114-Status: GOOD ( 10.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org MSI_IOVA* macros are common among different iommu/smu drivers, so move them to common iommu.h header file. This doesn't change anything wrt functionality of the IOMMU subsystem. Suggested-by: Jacob Pan Signed-off-by: Shyam Saini --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 3 --- drivers/iommu/virtio-iommu.c | 2 -- include/linux/iommu.h | 3 +++ 4 files changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index bd9d7c85576a2..d1713f6bbe6d1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -502,9 +502,6 @@ static inline unsigned int arm_smmu_cdtab_l2_idx(unsigned int ssid) #define ARM_SMMU_POLL_TIMEOUT_US 1000000 /* 1s! */ #define ARM_SMMU_POLL_SPIN_COUNT 10 -#define MSI_IOVA_BASE 0x8000000 -#define MSI_IOVA_LENGTH 0x100000 - enum pri_resp { PRI_RESP_DENY = 0, PRI_RESP_FAIL = 1, diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 79afc92e1d8b9..287f8e8d25890 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -49,9 +49,6 @@ */ #define QCOM_DUMMY_VAL -1 -#define MSI_IOVA_BASE 0x8000000 -#define MSI_IOVA_LENGTH 0x100000 - static int force_stage; module_param(force_stage, int, S_IRUGO); MODULE_PARM_DESC(force_stage, diff --git a/drivers/iommu/virtio-iommu.c b/drivers/iommu/virtio-iommu.c index b85ce6310ddbd..8c8783c8b31be 100644 --- a/drivers/iommu/virtio-iommu.c +++ b/drivers/iommu/virtio-iommu.c @@ -24,8 +24,6 @@ #include "dma-iommu.h" -#define MSI_IOVA_BASE 0x8000000 -#define MSI_IOVA_LENGTH 0x100000 #define VIOMMU_REQUEST_VQ 0 #define VIOMMU_EVENT_VQ 1 diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 38c65e92ecd09..2a26d3e18b24e 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -1505,6 +1505,9 @@ static inline void iommu_debugfs_setup(void) {} #ifdef CONFIG_IOMMU_DMA #include +#define MSI_IOVA_BASE 0x8000000 +#define MSI_IOVA_LENGTH 0x100000 + int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base); int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr); From patchwork Thu Jan 16 23:23:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Saini X-Patchwork-Id: 13942714 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 75120C02183 for ; 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Thu, 16 Jan 2025 23:23:21 +0000 Received: from thinkpad-p16sg1.corp.microsoft.com (unknown [20.236.10.66]) by linux.microsoft.com (Postfix) with ESMTPSA id 64A4920591A9; Thu, 16 Jan 2025 15:23:14 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 64A4920591A9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1737069794; bh=ST/uwYj8FbdGl2sV7queyr7M4lWHLEgBHKORDgGElUw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mNltCitoyFhAJ3HY+1fuvvbcID2aKoAS4gmW+dzqEGa+4F0DHl67YAGr24gAMGhg3 juvidvkXMFhQEROq2EvoWCaOytxEIN+HG0u7ORRNJGChtWKJenvpDhsYvDrTK3ZB7R ammoFXmKbmpfz+TgQJfpMLE4G9c/1D/h0Iz6SjRI= From: Shyam Saini To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, virtualization@lists.linux.dev Cc: will@kernel.org, jacob.pan@linux.microsoft.com, eric.auger@redhat.com, code@tyhicks.com, eahariha@linux.microsoft.com, vijayb@linux.microsoft.com Subject: [PATCH 3/3] arm-smmu: use dts passed MSI IOVA address and length Date: Thu, 16 Jan 2025 15:23:05 -0800 Message-Id: <20250116232307.1436693-2-shyamsaini@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250116232307.1436693-1-shyamsaini@linux.microsoft.com> References: <20250116232307.1436693-1-shyamsaini@linux.microsoft.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250116_232320_470906_ADEB2289 X-CRM114-Status: GOOD ( 18.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently ARM SMMU drivers hardcode PCI MSI IOVA address. Not all the platform have same memory mappings and some platform could have this address already being mapped for something else. This can lead to collision and as a consequence the MSI IOVA addr range is never reserved. Fix this by passing PCI MSI IOVA address via dts property "arm,smmu-pci-msi-iova-data". Likewise this property can be used to set custom MSI IOVA address length, by default it should be set to MSI IOVA default length value i.e, 0x100000. If this property is not found in the dtb for the given platform then the driver falls back on the default MSI IOVA address. Since this change allows configuration of custom MSI IOVA base address and length, rename existing as MSI_IOVA* macros accordingly. Signed-off-by: Shyam Saini --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 10 ++++- drivers/iommu/arm/arm-smmu/arm-smmu.c | 10 ++++- drivers/iommu/virtio-iommu.c | 6 +-- include/linux/iommu.h | 45 ++++++++++++++++++++- 4 files changed, 62 insertions(+), 9 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 0e4cbb2c64d73..91e88025424f9 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -32,6 +32,8 @@ #include "arm-smmu-v3.h" #include "../../dma-iommu.h" +struct msi_iova_data msi_data_smmu_v3; + static bool disable_msipolling; module_param(disable_msipolling, bool, 0444); MODULE_PARM_DESC(disable_msipolling, @@ -3540,8 +3542,9 @@ static void arm_smmu_get_resv_regions(struct device *dev, struct iommu_resv_region *region; int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; - region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, - prot, IOMMU_RESV_SW_MSI, GFP_KERNEL); + region = iommu_alloc_resv_region(msi_data_smmu_v3.msi_iova_base, + msi_data_smmu_v3.msi_iova_length, prot, + IOMMU_RESV_SW_MSI, GFP_KERNEL); if (!region) return; @@ -4569,6 +4572,9 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev, struct device *dev = &pdev->dev; u32 cells; int ret = -EINVAL; + struct msi_iova_data *msi_data_ptr = &msi_data_smmu_v3; + + iommu_configure_msi_iova(dev, "arm,smmu-pci-msi-iova-data", msi_data_ptr); if (of_property_read_u32(dev->of_node, "#iommu-cells", &cells)) dev_err(dev, "missing #iommu-cells property\n"); diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 287f8e8d25890..b636ea302cee0 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -49,6 +49,8 @@ */ #define QCOM_DUMMY_VAL -1 +struct msi_iova_data msi_data; + static int force_stage; module_param(force_stage, int, S_IRUGO); MODULE_PARM_DESC(force_stage, @@ -1593,8 +1595,9 @@ static void arm_smmu_get_resv_regions(struct device *dev, struct iommu_resv_region *region; int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; - region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, - prot, IOMMU_RESV_SW_MSI, GFP_KERNEL); + region = iommu_alloc_resv_region(msi_data.msi_iova_base, + msi_data.msi_iova_length, prot, + IOMMU_RESV_SW_MSI, GFP_KERNEL); if (!region) return; @@ -2029,6 +2032,9 @@ static int arm_smmu_device_dt_probe(struct arm_smmu_device *smmu, const struct arm_smmu_match_data *data; struct device *dev = smmu->dev; bool legacy_binding; + struct msi_iova_data *msi_data_ptr = &msi_data; + + iommu_configure_msi_iova(dev, "arm,smmu-pci-msi-iova-data", msi_data_ptr); if (of_property_read_u32(dev->of_node, "#global-interrupts", global_irqs)) return dev_err_probe(dev, -ENODEV, diff --git a/drivers/iommu/virtio-iommu.c b/drivers/iommu/virtio-iommu.c index 8c8783c8b31be..ca50dee09f352 100644 --- a/drivers/iommu/virtio-iommu.c +++ b/drivers/iommu/virtio-iommu.c @@ -958,9 +958,9 @@ static void viommu_get_resv_regions(struct device *dev, struct list_head *head) * software-mapped region. */ if (!msi) { - msi = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, - prot, IOMMU_RESV_SW_MSI, - GFP_KERNEL); + msi = iommu_alloc_resv_region(MSI_IOVA_BASE_DEFAULT, + MSI_IOVA_LENGTH_DEFAULT, prot, + IOMMU_RESV_SW_MSI, GFP_KERNEL); if (!msi) return; diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 2a26d3e18b24e..412a89200f094 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -1505,8 +1505,43 @@ static inline void iommu_debugfs_setup(void) {} #ifdef CONFIG_IOMMU_DMA #include -#define MSI_IOVA_BASE 0x8000000 -#define MSI_IOVA_LENGTH 0x100000 +/* MSI_IOVA_BASE_DEFAULT address can be overridden by dts specified address */ +#define MSI_IOVA_BASE_DEFAULT 0x8000000 +#define MSI_IOVA_LENGTH_DEFAULT 0x100000 + +struct msi_iova_data { + u32 msi_iova_base; + u32 msi_iova_length; +}; + +static inline void iommu_configure_msi_iova(struct device *iommu_dev, + const char *msi_iova_prop, + struct msi_iova_data *msi_data) +{ + static bool is_msi_base_set_from_dt; + u32 msi_data_from_dt[2]; + int rc; + + rc = of_property_read_u32_array(iommu_dev->of_node, msi_iova_prop, + msi_data_from_dt, 2); + if (!rc && !is_msi_base_set_from_dt) { + msi_data->msi_iova_base = msi_data_from_dt[0]; + msi_data->msi_iova_length = msi_data_from_dt[1]; + dev_info(iommu_dev, "setting custom MSI IOVA base to 0x%x\n", + msi_data->msi_iova_base); + is_msi_base_set_from_dt = true; + } else if (is_msi_base_set_from_dt && + msi_data->msi_iova_base != msi_data_from_dt[0]) + dev_warn(iommu_dev, "custom MSI IOVA base already set to 0x%x," + " skip resetting it to 0x%x\n", + msi_data->msi_iova_base, msi_data_from_dt[0]); + else if (!is_msi_base_set_from_dt && rc == -EINVAL) { + msi_data->msi_iova_base = MSI_IOVA_BASE_DEFAULT; + msi_data->msi_iova_length = MSI_IOVA_LENGTH_DEFAULT; + dev_info(iommu_dev, "using default MSI IOVA base: 0x%x\n", + msi_data->msi_iova_base); + } +} int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base); @@ -1518,6 +1553,12 @@ void iommu_dma_compose_msi_msg(struct msi_desc *desc, struct msi_msg *msg); struct msi_desc; struct msi_msg; +static inline void iommu_configure_msi_iova(struct device *iommu_dev, + const char *msi_iova_prop, + u32 (*msi_addr)[2]) +{ +} + static inline int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base) { return -ENODEV;