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-extern crate bilge_impl; -extern crate qemu_api; - use qemu_api::c_str; pub mod device; From patchwork Fri Jan 17 09:26:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 13943055 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4696FC02185 for ; Fri, 17 Jan 2025 09:28:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tYidE-0002XL-9s; Fri, 17 Jan 2025 04:27:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tYidC-0002Wb-C9 for qemu-devel@nongnu.org; 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Fri, 17 Jan 2025 01:27:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IHM0mJvtY8pA+DH5mVS/e7Ey0Sz1Ooyy8eupg8JIcJnYdQkWvqa0bYjt8ezufRBrw2WpLuJxw== X-Received: by 2002:a17:906:cec6:b0:ab3:85eb:377b with SMTP id a640c23a62f3a-ab38b4c6c1emr183548266b.53.1737106023163; Fri, 17 Jan 2025 01:27:03 -0800 (PST) Received: from [192.168.10.3] ([176.206.124.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384c74cd8sm139482366b.3.2025.01.17.01.27.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jan 2025 01:27:02 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: qemu-rust@nongnu.org Subject: [PATCH 02/10] rust: pl011: hide unnecessarily "pub" items from outside pl011::device Date: Fri, 17 Jan 2025 10:26:49 +0100 Message-ID: <20250117092657.1051233-3-pbonzini@redhat.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250117092657.1051233-1-pbonzini@redhat.com> References: <20250117092657.1051233-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.093, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The only public interfaces for pl011 are TYPE_PL011 and pl011_create. Remove pub from everything else. Note: the "allow(dead_code)" is removed later. Signed-off-by: Paolo Bonzini --- rust/hw/char/pl011/src/device.rs | 2 +- rust/hw/char/pl011/src/device_class.rs | 2 +- rust/hw/char/pl011/src/lib.rs | 13 ++++++++----- 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs index 11a87664c7a..e85e46ba0bb 100644 --- a/rust/hw/char/pl011/src/device.rs +++ b/rust/hw/char/pl011/src/device.rs @@ -565,7 +565,7 @@ pub fn post_load(&mut self, _version_id: u32) -> Result<(), ()> { } /// Which bits in the interrupt status matter for each outbound IRQ line ? -pub const IRQMASK: [u32; 6] = [ +const IRQMASK: [u32; 6] = [ /* combined IRQ */ Interrupt::E | Interrupt::MS diff --git a/rust/hw/char/pl011/src/device_class.rs b/rust/hw/char/pl011/src/device_class.rs index b052d98803f..2fd805fd12d 100644 --- a/rust/hw/char/pl011/src/device_class.rs +++ b/rust/hw/char/pl011/src/device_class.rs @@ -21,7 +21,7 @@ extern "C" fn pl011_clock_needed(opaque: *mut c_void) -> bool { } /// Migration subsection for [`PL011State`] clock. -pub static VMSTATE_PL011_CLOCK: VMStateDescription = VMStateDescription { +static VMSTATE_PL011_CLOCK: VMStateDescription = VMStateDescription { name: c_str!("pl011/clock").as_ptr(), version_id: 1, minimum_version_id: 1, diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs index d10f0805aac..2baacba2306 100644 --- a/rust/hw/char/pl011/src/lib.rs +++ b/rust/hw/char/pl011/src/lib.rs @@ -27,9 +27,11 @@ use qemu_api::c_str; -pub mod device; -pub mod device_class; -pub mod memory_ops; +mod device; +mod device_class; +mod memory_ops; + +pub use device::pl011_create; pub const TYPE_PL011: &::std::ffi::CStr = c_str!("pl011"); pub const TYPE_PL011_LUMINARY: &::std::ffi::CStr = c_str!("pl011_luminary"); @@ -42,7 +44,7 @@ #[allow(non_camel_case_types)] #[repr(u64)] #[derive(Debug, qemu_api_macros::TryInto)] -pub enum RegisterOffset { +enum RegisterOffset { /// Data Register /// /// A write to this register initiates the actual data transmission @@ -98,7 +100,8 @@ pub enum RegisterOffset { //Reserved = 0x04C, } -pub mod registers { +#[allow(dead_code)] +mod registers { //! Device registers exposed as typed structs which are backed by arbitrary //! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc. use bilge::prelude::*; From patchwork Fri Jan 17 09:26:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 13943052 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 960EFC02185 for ; Fri, 17 Jan 2025 09:27:41 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tYidG-0002YW-OF; Fri, 17 Jan 2025 04:27:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tYidE-0002Xr-VD for qemu-devel@nongnu.org; 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Signed-off-by: Paolo Bonzini --- rust/hw/char/pl011/src/device.rs | 114 +++++++++++++++++-------------- 1 file changed, 63 insertions(+), 51 deletions(-) diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs index e85e46ba0bb..6d662865182 100644 --- a/rust/hw/char/pl011/src/device.rs +++ b/rust/hw/char/pl011/src/device.rs @@ -5,6 +5,7 @@ use core::ptr::{addr_of_mut, NonNull}; use std::{ ffi::CStr, + ops::ControlFlow, os::raw::{c_int, c_uint, c_void}, }; @@ -214,19 +215,11 @@ fn post_init(&self) { } } - pub fn read(&mut self, offset: hwaddr, _size: c_uint) -> std::ops::ControlFlow { + fn regs_read(&mut self, offset: RegisterOffset) -> ControlFlow { use RegisterOffset::*; - let value = match RegisterOffset::try_from(offset) { - Err(v) if (0x3f8..0x400).contains(&(v >> 2)) => { - let device_id = self.get_class().device_id; - u32::from(device_id[(offset - 0xfe0) >> 2]) - } - Err(_) => { - // qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset 0x%x\n", (int)offset); - 0 - } - Ok(DR) => { + std::ops::ControlFlow::Break(match offset { + DR => { self.flags.set_receive_fifo_full(false); let c = self.read_fifo[self.read_pos]; if self.read_count > 0 { @@ -243,39 +236,33 @@ pub fn read(&mut self, offset: hwaddr, _size: c_uint) -> std::ops::ControlFlow u32::from(self.receive_status_error_clear), - Ok(FR) => u32::from(self.flags), - Ok(FBRD) => self.fbrd, - Ok(ILPR) => self.ilpr, - Ok(IBRD) => self.ibrd, - Ok(LCR_H) => u32::from(self.line_control), - Ok(CR) => u32::from(self.control), - Ok(FLS) => self.ifl, - Ok(IMSC) => self.int_enabled, - Ok(RIS) => self.int_level, - Ok(MIS) => self.int_level & self.int_enabled, - Ok(ICR) => { + return ControlFlow::Continue(u32::from(c)); + }, + RSR => u32::from(self.receive_status_error_clear), + FR => u32::from(self.flags), + FBRD => self.fbrd, + ILPR => self.ilpr, + IBRD => self.ibrd, + LCR_H => u32::from(self.line_control), + CR => u32::from(self.control), + FLS => self.ifl, + IMSC => self.int_enabled, + RIS => self.int_level, + MIS => self.int_level & self.int_enabled, + ICR => { // "The UARTICR Register is the interrupt clear register and is write-only" // Source: ARM DDI 0183G 3.3.13 Interrupt Clear Register, UARTICR 0 - } - Ok(DMACR) => self.dmacr, - }; - std::ops::ControlFlow::Break(value.into()) + }, + DMACR => self.dmacr, + }) } - pub fn write(&mut self, offset: hwaddr, value: u64) { + fn regs_write(&mut self, offset: RegisterOffset, value: u32) { // eprintln!("write offset {offset} value {value}"); use RegisterOffset::*; - let value: u32 = value as u32; - match RegisterOffset::try_from(offset) { - Err(_bad_offset) => { - eprintln!("write bad offset {offset} value {value}"); - } - Ok(DR) => { + match offset { + DR => { // ??? Check if transmitter is enabled. let ch: u8 = value as u8; // XXX this blocks entire thread. Rewrite to use @@ -290,22 +277,22 @@ pub fn write(&mut self, offset: hwaddr, value: u64) { self.int_level |= registers::INT_TX; self.update(); } - Ok(RSR) => { - self.receive_status_error_clear.reset(); + RSR => { + self.receive_status_error_clear = 0.into(); } - Ok(FR) => { + FR => { // flag writes are ignored } - Ok(ILPR) => { + ILPR => { self.ilpr = value; } - Ok(IBRD) => { + IBRD => { self.ibrd = value; } - Ok(FBRD) => { + FBRD => { self.fbrd = value; } - Ok(LCR_H) => { + LCR_H => { let new_val: registers::LineControl = value.into(); // Reset the FIFO state on FIFO enable or disable if self.line_control.fifos_enabled() != new_val.fifos_enabled() { @@ -328,26 +315,26 @@ pub fn write(&mut self, offset: hwaddr, value: u64) { self.line_control = new_val; self.set_read_trigger(); } - Ok(CR) => { + CR => { // ??? Need to implement the enable bit. self.control = value.into(); self.loopback_mdmctrl(); } - Ok(FLS) => { + FLS => { self.ifl = value; self.set_read_trigger(); } - Ok(IMSC) => { + IMSC => { self.int_enabled = value; self.update(); } - Ok(RIS) => {} - Ok(MIS) => {} - Ok(ICR) => { + RIS => {} + MIS => {} + ICR => { self.int_level &= !value; self.update(); } - Ok(DMACR) => { + DMACR => { self.dmacr = value; if value & 3 > 0 { // qemu_log_mask(LOG_UNIMP, "pl011: DMA not implemented\n"); @@ -562,6 +549,31 @@ pub fn post_load(&mut self, _version_id: u32) -> Result<(), ()> { Ok(()) } + + pub fn read(&mut self, offset: hwaddr, _size: u32) -> ControlFlow { + match RegisterOffset::try_from(offset) { + Err(v) if (0x3f8..0x400).contains(&(v >> 2)) => { + let device_id = self.get_class().device_id; + ControlFlow::Break(u64::from(device_id[(offset - 0xfe0) >> 2])) + } + Err(_) => { + // qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset 0x%x\n", (int)offset); + ControlFlow::Break(0) + } + Ok(field) => match self.regs_read(field) { + ControlFlow::Break(value) => ControlFlow::Break(value.into()), + ControlFlow::Continue(value) => ControlFlow::Continue(value.into()), + } + } + } + + pub fn write(&mut self, offset: hwaddr, value: u64) { + if let Ok(field) = RegisterOffset::try_from(offset) { + self.regs_write(field, value as u32); + } else { + eprintln!("write bad offset {offset} value {value}"); + } + } } /// Which bits in the interrupt status matter for each outbound IRQ line ? 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Signed-off-by: Paolo Bonzini --- rust/hw/char/pl011/src/device.rs | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs index 6d662865182..2e8707aef97 100644 --- a/rust/hw/char/pl011/src/device.rs +++ b/rust/hw/char/pl011/src/device.rs @@ -6,7 +6,7 @@ use std::{ ffi::CStr, ops::ControlFlow, - os::raw::{c_int, c_uint, c_void}, + os::raw::{c_int, c_void}, }; use qemu_api::{ @@ -480,6 +480,12 @@ pub fn can_receive(&self) -> bool { self.read_count < self.fifo_depth() } + pub fn receive(&mut self, ch: u32) { + if !self.loopback_enabled() { + self.put_fifo(ch) + } + } + pub fn event(&mut self, event: QEMUChrEvent) { if event == bindings::QEMUChrEvent::CHR_EVENT_BREAK && !self.loopback_enabled() { self.put_fifo(registers::Data::BREAK.into()); @@ -505,7 +511,7 @@ pub fn fifo_depth(&self) -> u32 { 1 } - pub fn put_fifo(&mut self, value: c_uint) { + pub fn put_fifo(&mut self, value: u32) { let depth = self.fifo_depth(); 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Fri, 17 Jan 2025 01:27:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IGHhRa8RaSJ9NpeAmOvSfs3cxied5hB/iXsr+26UCo3MWxX3lVniKyIWzlY51SautRHczjLZg== X-Received: by 2002:a17:907:9710:b0:aa6:a21b:2a9 with SMTP id a640c23a62f3a-ab38b3e2ed0mr197952366b.57.1737106030038; Fri, 17 Jan 2025 01:27:10 -0800 (PST) Received: from [192.168.10.3] ([176.206.124.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384f2903esm138579566b.109.2025.01.17.01.27.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jan 2025 01:27:08 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: qemu-rust@nongnu.org Subject: [PATCH 05/10] rust: pl011: pull interrupt updates out of read/write ops Date: Fri, 17 Jan 2025 10:26:52 +0100 Message-ID: <20250117092657.1051233-6-pbonzini@redhat.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250117092657.1051233-1-pbonzini@redhat.com> References: <20250117092657.1051233-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.093, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org qemu_irqs are not part of the vmstate, therefore they will remain in PL011State. Update them if needed after regs_read()/regs_write(). Apply #[must_use] to functions that return whether the interrupt state could have changed, so that it's harder to forget the call to update(). Signed-off-by: Paolo Bonzini --- rust/hw/char/pl011/src/device.rs | 68 ++++++++++++++++++-------------- 1 file changed, 38 insertions(+), 30 deletions(-) diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs index 2e8707aef97..67c3e63baa1 100644 --- a/rust/hw/char/pl011/src/device.rs +++ b/rust/hw/char/pl011/src/device.rs @@ -234,7 +234,6 @@ fn regs_read(&mut self, offset: RegisterOffset) -> ControlFlow { } // Update error bits. self.receive_status_error_clear.set_from_data(c); - self.update(); // Must call qemu_chr_fe_accept_input, so return Continue: return ControlFlow::Continue(u32::from(c)); }, @@ -258,7 +257,7 @@ fn regs_read(&mut self, offset: RegisterOffset) -> ControlFlow { }) } - fn regs_write(&mut self, offset: RegisterOffset, value: u32) { + fn regs_write(&mut self, offset: RegisterOffset, value: u32) -> bool { // eprintln!("write offset {offset} value {value}"); use RegisterOffset::*; match offset { @@ -273,9 +272,10 @@ fn regs_write(&mut self, offset: RegisterOffset, value: u32) { unsafe { qemu_chr_fe_write_all(addr_of_mut!(self.char_backend), &ch, 1); } - self.loopback_tx(value); + // interrupts always checked + let _ = self.loopback_tx(value); self.int_level |= registers::INT_TX; - self.update(); + return true; } RSR => { self.receive_status_error_clear = 0.into(); @@ -299,7 +299,7 @@ fn regs_write(&mut self, offset: RegisterOffset, value: u32) { self.reset_rx_fifo(); self.reset_tx_fifo(); } - if self.line_control.send_break() ^ new_val.send_break() { + let update = (self.line_control.send_break() != new_val.send_break()) && { let mut break_enable: c_int = new_val.send_break().into(); // SAFETY: self.char_backend is a valid CharBackend instance after it's been // initialized in realize(). @@ -310,15 +310,16 @@ fn regs_write(&mut self, offset: RegisterOffset, value: u32) { addr_of_mut!(break_enable).cast::(), ); } - self.loopback_break(break_enable > 0); - } + self.loopback_break(break_enable > 0) + }; self.line_control = new_val; self.set_read_trigger(); + return update; } CR => { // ??? Need to implement the enable bit. self.control = value.into(); - self.loopback_mdmctrl(); + return self.loopback_mdmctrl(); } FLS => { self.ifl = value; @@ -326,13 +327,13 @@ fn regs_write(&mut self, offset: RegisterOffset, value: u32) { } IMSC => { self.int_enabled = value; - self.update(); + return true; } RIS => {} MIS => {} ICR => { self.int_level &= !value; - self.update(); + return true; } DMACR => { self.dmacr = value; @@ -342,14 +343,12 @@ fn regs_write(&mut self, offset: RegisterOffset, value: u32) { } } } + false } #[inline] - fn loopback_tx(&mut self, value: u32) { - if !self.loopback_enabled() { - return; - } - + #[must_use] + fn loopback_tx(&mut self, value: u32) -> bool { // Caveat: // // In real hardware, TX loopback happens at the serial-bit level @@ -367,12 +366,13 @@ fn loopback_tx(&mut self, value: u32) { // hardware flow-control is enabled. // // For simplicity, the above described is not emulated. - self.put_fifo(value); + self.loopback_enabled() && self.put_fifo(value) } - fn loopback_mdmctrl(&mut self) { + #[must_use] + fn loopback_mdmctrl(&mut self) -> bool { if !self.loopback_enabled() { - return; + return false; } /* @@ -413,13 +413,11 @@ fn loopback_mdmctrl(&mut self) { il |= Interrupt::RI as u32; } self.int_level = il; - self.update(); + true } - fn loopback_break(&mut self, enable: bool) { - if enable { - self.loopback_tx(registers::Data::BREAK.into()); - } + fn loopback_break(&mut self, enable: bool) -> bool { + enable && self.loopback_tx(registers::Data::BREAK.into()) } fn set_read_trigger(&mut self) { @@ -481,14 +479,17 @@ pub fn can_receive(&self) -> bool { } pub fn receive(&mut self, ch: u32) { - if !self.loopback_enabled() { - self.put_fifo(ch) + if !self.loopback_enabled() && self.put_fifo(ch) { + self.update(); } } pub fn event(&mut self, event: QEMUChrEvent) { if event == bindings::QEMUChrEvent::CHR_EVENT_BREAK && !self.loopback_enabled() { - self.put_fifo(registers::Data::BREAK.into()); + let update = self.put_fifo(registers::Data::BREAK.into()); + if update { + self.update(); + } } } @@ -511,7 +512,8 @@ pub fn fifo_depth(&self) -> u32 { 1 } - pub fn put_fifo(&mut self, value: u32) { + #[must_use] + pub fn put_fifo(&mut self, value: u32) -> bool { let depth = self.fifo_depth(); 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helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -39 X-Spam_score: -4.0 X-Spam_bar: ---- X-Spam_report: (-4.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.093, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-1.797, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Pull all the mutable fields of PL011State into a separate struct. Signed-off-by: Paolo Bonzini --- rust/hw/char/pl011/src/device.rs | 251 ++++++++++++++----------- rust/hw/char/pl011/src/device_class.rs | 46 +++-- 2 files changed, 168 insertions(+), 129 deletions(-) diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs index 67c3e63baa1..476abe765a9 100644 --- a/rust/hw/char/pl011/src/device.rs +++ b/rust/hw/char/pl011/src/device.rs @@ -78,11 +78,8 @@ fn index(&self, idx: u32) -> &Self::Output { } #[repr(C)] -#[derive(Debug, qemu_api_macros::Object, qemu_api_macros::offsets)] -/// PL011 Device Model in QEMU -pub struct PL011State { - pub parent_obj: ParentField, - pub iomem: MemoryRegion, +#[derive(Debug, Default, qemu_api_macros::offsets)] +pub struct PL011Registers { #[doc(alias = "fr")] pub flags: registers::Flags, #[doc(alias = "lcr")] @@ -102,8 +99,17 @@ pub struct PL011State { pub read_pos: u32, pub read_count: u32, pub read_trigger: u32, +} + +#[repr(C)] +#[derive(Debug, qemu_api_macros::Object, qemu_api_macros::offsets)] +/// PL011 Device Model in QEMU +pub struct PL011State { + pub parent_obj: ParentField, + pub iomem: MemoryRegion, #[doc(alias = "chr")] pub char_backend: CharBackend, + pub regs: PL011Registers, /// QEMU interrupts /// /// ```text @@ -161,61 +167,8 @@ fn vmsd() -> Option<&'static VMStateDescription> { const RESET: Option = Some(Self::reset); } -impl PL011State { - /// Initializes a pre-allocated, unitialized instance of `PL011State`. - /// - /// # Safety - /// - /// `self` must point to a correctly sized and aligned location for the - /// `PL011State` type. It must not be called more than once on the same - /// location/instance. All its fields are expected to hold unitialized - /// values with the sole exception of `parent_obj`. - unsafe fn init(&mut self) { - const CLK_NAME: &CStr = c_str!("clk"); - - // SAFETY: - // - // self and self.iomem are guaranteed to be valid at this point since callers - // must make sure the `self` reference is valid. - unsafe { - memory_region_init_io( - addr_of_mut!(self.iomem), - addr_of_mut!(*self).cast::(), - &PL011_OPS, - addr_of_mut!(*self).cast::(), - Self::TYPE_NAME.as_ptr(), - 0x1000, - ); - } - - // SAFETY: - // - // self.clock is not initialized at this point; but since `NonNull<_>` is Copy, - // we can overwrite the undefined value without side effects. This is - // safe since all PL011State instances are created by QOM code which - // calls this function to initialize the fields; therefore no code is - // able to access an invalid self.clock value. - unsafe { - let dev: &mut DeviceState = self.upcast_mut(); - self.clock = NonNull::new(qdev_init_clock_in( - dev, - CLK_NAME.as_ptr(), - None, /* pl011_clock_update */ - addr_of_mut!(*self).cast::(), - ClockEvent::ClockUpdate.0, - )) - .unwrap(); - } - } - - fn post_init(&self) { - self.init_mmio(&self.iomem); - for irq in self.interrupts.iter() { - self.init_irq(irq); - } - } - - fn regs_read(&mut self, offset: RegisterOffset) -> ControlFlow { +impl PL011Registers { + pub(self) fn read(&mut self, offset: RegisterOffset) -> ControlFlow { use RegisterOffset::*; std::ops::ControlFlow::Break(match offset { @@ -257,7 +210,12 @@ fn regs_read(&mut self, offset: RegisterOffset) -> ControlFlow { }) } - fn regs_write(&mut self, offset: RegisterOffset, value: u32) -> bool { + pub(self) fn write( + &mut self, + offset: RegisterOffset, + value: u32, + char_backend: *mut CharBackend, + ) -> bool { // eprintln!("write offset {offset} value {value}"); use RegisterOffset::*; match offset { @@ -267,10 +225,10 @@ fn regs_write(&mut self, offset: RegisterOffset, value: u32) -> bool { // XXX this blocks entire thread. Rewrite to use // qemu_chr_fe_write and background I/O callbacks - // SAFETY: self.char_backend is a valid CharBackend instance after it's been + // SAFETY: char_backend is a valid CharBackend instance after it's been // initialized in realize(). unsafe { - qemu_chr_fe_write_all(addr_of_mut!(self.char_backend), &ch, 1); + qemu_chr_fe_write_all(char_backend, &ch, 1); } // interrupts always checked let _ = self.loopback_tx(value); @@ -305,7 +263,7 @@ fn regs_write(&mut self, offset: RegisterOffset, value: u32) -> bool { // initialized in realize(). unsafe { qemu_chr_fe_ioctl( - addr_of_mut!(self.char_backend), + char_backend, CHR_IOCTL_SERIAL_SET_BREAK as i32, addr_of_mut!(break_enable).cast::(), ); @@ -424,23 +382,6 @@ fn set_read_trigger(&mut self) { self.read_trigger = 1; } - pub fn realize(&mut self) { - // SAFETY: self.char_backend has the correct size and alignment for a - // CharBackend object, and its callbacks are of the correct types. - unsafe { - qemu_chr_fe_set_handlers( - addr_of_mut!(self.char_backend), - Some(pl011_can_receive), - Some(pl011_receive), - Some(pl011_event), - None, - addr_of_mut!(*self).cast::(), - core::ptr::null_mut(), - true, - ); - } - } - pub fn reset(&mut self) { self.line_control.reset(); self.receive_status_error_clear.reset(); @@ -473,26 +414,6 @@ pub fn reset_tx_fifo(&mut self) { self.flags.set_transmit_fifo_empty(true); } - pub fn can_receive(&self) -> bool { - // trace_pl011_can_receive(s->lcr, s->read_count, r); - self.read_count < self.fifo_depth() - } - - pub fn receive(&mut self, ch: u32) { - if !self.loopback_enabled() && self.put_fifo(ch) { - self.update(); - } - } - - pub fn event(&mut self, event: QEMUChrEvent) { - if event == bindings::QEMUChrEvent::CHR_EVENT_BREAK && !self.loopback_enabled() { - let update = self.put_fifo(registers::Data::BREAK.into()); - if update { - self.update(); - } - } - } - #[inline] pub fn fifo_enabled(&self) -> bool { self.line_control.fifos_enabled() == registers::Mode::FIFO @@ -531,14 +452,7 @@ pub fn put_fifo(&mut self, value: u32) -> bool { false } - pub fn update(&self) { - let flags = self.int_level & self.int_enabled; - for (irq, i) in self.interrupts.iter().zip(IRQMASK) { - irq.set(flags & i != 0); - } - } - - pub fn post_load(&mut self, _version_id: u32) -> Result<(), ()> { + pub fn post_load(&mut self) -> Result<(), ()> { /* Sanity-check input state */ if self.read_pos >= self.read_fifo.len() || self.read_count > self.read_fifo.len() { return Err(()); @@ -558,8 +472,66 @@ pub fn post_load(&mut self, _version_id: u32) -> Result<(), ()> { Ok(()) } +} + +impl PL011State { + /// Initializes a pre-allocated, unitialized instance of `PL011State`. + /// + /// # Safety + /// + /// `self` must point to a correctly sized and aligned location for the + /// `PL011State` type. It must not be called more than once on the same + /// location/instance. All its fields are expected to hold unitialized + /// values with the sole exception of `parent_obj`. + unsafe fn init(&mut self) { + const CLK_NAME: &CStr = c_str!("clk"); + + // SAFETY: + // + // self and self.iomem are guaranteed to be valid at this point since callers + // must make sure the `self` reference is valid. + unsafe { + memory_region_init_io( + addr_of_mut!(self.iomem), + addr_of_mut!(*self).cast::(), + &PL011_OPS, + addr_of_mut!(*self).cast::(), + Self::TYPE_NAME.as_ptr(), + 0x1000, + ); + } + + self.regs = Default::default(); + + // SAFETY: + // + // self.clock is not initialized at this point; but since `NonNull<_>` is Copy, + // we can overwrite the undefined value without side effects. This is + // safe since all PL011State instances are created by QOM code which + // calls this function to initialize the fields; therefore no code is + // able to access an invalid self.clock value. + unsafe { + let dev: &mut DeviceState = self.upcast_mut(); + self.clock = NonNull::new(qdev_init_clock_in( + dev, + CLK_NAME.as_ptr(), + None, /* pl011_clock_update */ + addr_of_mut!(*self).cast::(), + ClockEvent::ClockUpdate.0, + )) + .unwrap(); + } + } + + fn post_init(&self) { + self.init_mmio(&self.iomem); + for irq in self.interrupts.iter() { + self.init_irq(irq); + } + } pub fn read(&mut self, offset: hwaddr, _size: u32) -> ControlFlow { + let regs = &mut self.regs; match RegisterOffset::try_from(offset) { Err(v) if (0x3f8..0x400).contains(&(v >> 2)) => { let device_id = self.get_class().device_id; @@ -569,7 +541,7 @@ pub fn read(&mut self, offset: hwaddr, _size: u32) -> ControlFlow { // qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset 0x%x\n", (int)offset); ControlFlow::Break(0) } - Ok(field) => match self.regs_read(field) { + Ok(field) => match regs.read(field) { ControlFlow::Break(value) => ControlFlow::Break(value.into()), ControlFlow::Continue(value) => { self.update(); @@ -580,14 +552,71 @@ pub fn read(&mut self, offset: hwaddr, _size: u32) -> ControlFlow { } pub fn write(&mut self, offset: hwaddr, value: u64) { + let regs = &mut self.regs; if let Ok(field) = RegisterOffset::try_from(offset) { - if self.regs_write(field, value as u32) { + if regs.write(field, value as u32, &mut self.char_backend) { self.update(); } } else { eprintln!("write bad offset {offset} value {value}"); } } + + pub fn can_receive(&self) -> bool { + // trace_pl011_can_receive(s->lcr, s->read_count, r); + let regs = &self.regs; + regs.read_count < regs.fifo_depth() + } + + pub fn receive(&mut self, ch: u32) { + let regs = &mut self.regs; + if !regs.loopback_enabled() && regs.put_fifo(ch) { + self.update(); + } + } + + pub fn event(&mut self, event: QEMUChrEvent) { + let regs = &mut self.regs; + if event == bindings::QEMUChrEvent::CHR_EVENT_BREAK && !regs.loopback_enabled() { + let update = regs.put_fifo(registers::Data::BREAK.into()); + if update { + self.update() + } + } + } + + pub fn realize(&mut self) { + // SAFETY: self.char_backend has the correct size and alignment for a + // CharBackend object, and its callbacks are of the correct types. + unsafe { + qemu_chr_fe_set_handlers( + addr_of_mut!(self.char_backend), + Some(pl011_can_receive), + Some(pl011_receive), + Some(pl011_event), + None, + addr_of_mut!(*self).cast::(), + core::ptr::null_mut(), + true, + ); + } + } + + pub fn reset(&mut self) { + self.regs.reset(); + } + + pub fn update(&self) { + let regs = &self.regs; + let flags = regs.int_level & regs.int_enabled; + for (irq, i) in self.interrupts.iter().zip(IRQMASK) { + irq.set(flags & i != 0); + } + } + + pub fn post_load(&mut self, _version_id: u32) -> Result<(), ()> { + self.regs.post_load() + } } /// Which bits in the interrupt status matter for each outbound IRQ line ? diff --git a/rust/hw/char/pl011/src/device_class.rs b/rust/hw/char/pl011/src/device_class.rs index 2fd805fd12d..e25645ceb0d 100644 --- a/rust/hw/char/pl011/src/device_class.rs +++ b/rust/hw/char/pl011/src/device_class.rs @@ -6,11 +6,11 @@ use std::os::raw::{c_int, c_void}; use qemu_api::{ - bindings::*, c_str, vmstate_clock, vmstate_fields, vmstate_of, vmstate_subsections, - vmstate_unused, zeroable::Zeroable, + bindings::*, c_str, vmstate_clock, vmstate_fields, vmstate_of, vmstate_struct, + vmstate_subsections, vmstate_unused, zeroable::Zeroable, }; -use crate::device::PL011State; +use crate::device::{PL011Registers, PL011State}; extern "C" fn pl011_clock_needed(opaque: *mut c_void) -> bool { unsafe { @@ -45,6 +45,30 @@ extern "C" fn pl011_post_load(opaque: *mut c_void, version_id: c_int) -> c_int { } } +static VMSTATE_PL011_REGS: VMStateDescription = VMStateDescription { + name: c_str!("pl011").as_ptr(), + version_id: 2, + minimum_version_id: 2, + fields: vmstate_fields! { + vmstate_of!(PL011Registers, flags), + vmstate_of!(PL011Registers, line_control), + vmstate_of!(PL011Registers, receive_status_error_clear), + vmstate_of!(PL011Registers, control), + vmstate_of!(PL011Registers, dmacr), + vmstate_of!(PL011Registers, int_enabled), + vmstate_of!(PL011Registers, int_level), + vmstate_of!(PL011Registers, read_fifo), + vmstate_of!(PL011Registers, ilpr), + vmstate_of!(PL011Registers, ibrd), + vmstate_of!(PL011Registers, fbrd), + vmstate_of!(PL011Registers, ifl), + vmstate_of!(PL011Registers, read_pos), + vmstate_of!(PL011Registers, read_count), + vmstate_of!(PL011Registers, read_trigger), + }, + ..Zeroable::ZERO +}; + pub static VMSTATE_PL011: VMStateDescription = VMStateDescription { name: c_str!("pl011").as_ptr(), version_id: 2, @@ -52,21 +76,7 @@ extern "C" fn pl011_post_load(opaque: *mut c_void, version_id: c_int) -> c_int { post_load: Some(pl011_post_load), fields: vmstate_fields! { vmstate_unused!(core::mem::size_of::()), - vmstate_of!(PL011State, flags), - vmstate_of!(PL011State, line_control), - vmstate_of!(PL011State, receive_status_error_clear), - vmstate_of!(PL011State, control), - vmstate_of!(PL011State, dmacr), - vmstate_of!(PL011State, int_enabled), - vmstate_of!(PL011State, int_level), - vmstate_of!(PL011State, read_fifo), - vmstate_of!(PL011State, ilpr), - vmstate_of!(PL011State, ibrd), - vmstate_of!(PL011State, fbrd), - vmstate_of!(PL011State, ifl), - vmstate_of!(PL011State, read_pos), - vmstate_of!(PL011State, read_count), - vmstate_of!(PL011State, read_trigger), + vmstate_struct!(PL011State, regs, &VMSTATE_PL011_REGS, PL011Registers), }, subsections: vmstate_subsections! { VMSTATE_PL011_CLOCK From patchwork Fri Jan 17 09:26:54 2025 Content-Type: text/plain; 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helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.093, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This is a step towards making memory ops use a shared reference to the device type; it's not yet possible due to the calls to character device functions. Signed-off-by: Paolo Bonzini --- rust/hw/char/pl011/src/device.rs | 38 +++++++++++++------------- rust/hw/char/pl011/src/device_class.rs | 8 +++--- rust/hw/char/pl011/src/memory_ops.rs | 2 +- 3 files changed, 24 insertions(+), 24 deletions(-) diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs index 476abe765a9..1d3da59e481 100644 --- a/rust/hw/char/pl011/src/device.rs +++ b/rust/hw/char/pl011/src/device.rs @@ -102,14 +102,14 @@ pub struct PL011Registers { } #[repr(C)] -#[derive(Debug, qemu_api_macros::Object, qemu_api_macros::offsets)] +#[derive(qemu_api_macros::Object, qemu_api_macros::offsets)] /// PL011 Device Model in QEMU pub struct PL011State { pub parent_obj: ParentField, pub iomem: MemoryRegion, #[doc(alias = "chr")] pub char_backend: CharBackend, - pub regs: PL011Registers, + pub regs: BqlRefCell, /// QEMU interrupts /// /// ```text @@ -530,8 +530,8 @@ fn post_init(&self) { } } + #[allow(clippy::needless_pass_by_ref_mut)] pub fn read(&mut self, offset: hwaddr, _size: u32) -> ControlFlow { - let regs = &mut self.regs; match RegisterOffset::try_from(offset) { Err(v) if (0x3f8..0x400).contains(&(v >> 2)) => { let device_id = self.get_class().device_id; @@ -541,7 +541,7 @@ pub fn read(&mut self, offset: hwaddr, _size: u32) -> ControlFlow { // qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset 0x%x\n", (int)offset); ControlFlow::Break(0) } - Ok(field) => match regs.read(field) { + Ok(field) => match self.regs.borrow_mut().read(field) { ControlFlow::Break(value) => ControlFlow::Break(value.into()), ControlFlow::Continue(value) => { self.update(); @@ -552,7 +552,7 @@ pub fn read(&mut self, offset: hwaddr, _size: u32) -> ControlFlow { } pub fn write(&mut self, offset: hwaddr, value: u64) { - let regs = &mut self.regs; + let mut regs = self.regs.borrow_mut(); if let Ok(field) = RegisterOffset::try_from(offset) { if regs.write(field, value as u32, &mut self.char_backend) { self.update(); @@ -564,19 +564,19 @@ pub fn write(&mut self, offset: hwaddr, value: u64) { pub fn can_receive(&self) -> bool { // trace_pl011_can_receive(s->lcr, s->read_count, r); - let regs = &self.regs; + let regs = self.regs.borrow(); regs.read_count < regs.fifo_depth() } - pub fn receive(&mut self, ch: u32) { - let regs = &mut self.regs; + pub fn receive(&self, ch: u32) { + let mut regs = self.regs.borrow_mut(); if !regs.loopback_enabled() && regs.put_fifo(ch) { self.update(); } } - pub fn event(&mut self, event: QEMUChrEvent) { - let regs = &mut self.regs; + pub fn event(&self, event: QEMUChrEvent) { + let mut regs = self.regs.borrow_mut(); if event == bindings::QEMUChrEvent::CHR_EVENT_BREAK && !regs.loopback_enabled() { let update = regs.put_fifo(registers::Data::BREAK.into()); if update { @@ -603,19 +603,19 @@ pub fn realize(&mut self) { } pub fn reset(&mut self) { - self.regs.reset(); + self.regs.borrow_mut().reset(); } pub fn update(&self) { - let regs = &self.regs; + let regs = self.regs.borrow(); let flags = regs.int_level & regs.int_enabled; for (irq, i) in self.interrupts.iter().zip(IRQMASK) { irq.set(flags & i != 0); } } - pub fn post_load(&mut self, _version_id: u32) -> Result<(), ()> { - self.regs.post_load() + pub fn post_load(&self, _version_id: u32) -> Result<(), ()> { + self.regs.borrow_mut().post_load() } } @@ -657,10 +657,10 @@ pub fn post_load(&mut self, _version_id: u32) -> Result<(), ()> { pub unsafe extern "C" fn pl011_receive(opaque: *mut c_void, buf: *const u8, size: c_int) { unsafe { debug_assert!(!opaque.is_null()); - let mut state = NonNull::new_unchecked(opaque.cast::()); + let state = NonNull::new_unchecked(opaque.cast::()); if size > 0 { debug_assert!(!buf.is_null()); - state.as_mut().receive(u32::from(buf.read_volatile())); + state.as_ref().receive(u32::from(buf.read_volatile())); } } } @@ -673,8 +673,8 @@ pub fn post_load(&mut self, _version_id: u32) -> Result<(), ()> { pub unsafe extern "C" fn pl011_event(opaque: *mut c_void, event: QEMUChrEvent) { unsafe { debug_assert!(!opaque.is_null()); - let mut state = NonNull::new_unchecked(opaque.cast::()); - state.as_mut().event(event) + let state = NonNull::new_unchecked(opaque.cast::()); + state.as_ref().event(event) } } @@ -700,7 +700,7 @@ pub fn post_load(&mut self, _version_id: u32) -> Result<(), ()> { } #[repr(C)] -#[derive(Debug, qemu_api_macros::Object)] +#[derive(qemu_api_macros::Object)] /// PL011 Luminary device model. pub struct PL011Luminary { parent_obj: ParentField, diff --git a/rust/hw/char/pl011/src/device_class.rs b/rust/hw/char/pl011/src/device_class.rs index e25645ceb0d..06178778a8e 100644 --- a/rust/hw/char/pl011/src/device_class.rs +++ b/rust/hw/char/pl011/src/device_class.rs @@ -6,7 +6,7 @@ use std::os::raw::{c_int, c_void}; use qemu_api::{ - bindings::*, c_str, vmstate_clock, vmstate_fields, vmstate_of, vmstate_struct, + bindings::*, c_str, prelude::*, vmstate_clock, vmstate_fields, vmstate_of, vmstate_struct, vmstate_subsections, vmstate_unused, zeroable::Zeroable, }; @@ -35,8 +35,8 @@ extern "C" fn pl011_clock_needed(opaque: *mut c_void) -> bool { extern "C" fn pl011_post_load(opaque: *mut c_void, version_id: c_int) -> c_int { unsafe { debug_assert!(!opaque.is_null()); - let mut state = NonNull::new_unchecked(opaque.cast::()); - let result = state.as_mut().post_load(version_id as u32); + let state = NonNull::new_unchecked(opaque.cast::()); + let result = state.as_ref().post_load(version_id as u32); if result.is_err() { -1 } else { @@ -76,7 +76,7 @@ extern "C" fn pl011_post_load(opaque: *mut c_void, version_id: c_int) -> c_int { post_load: Some(pl011_post_load), fields: vmstate_fields! { vmstate_unused!(core::mem::size_of::()), - vmstate_struct!(PL011State, regs, &VMSTATE_PL011_REGS, PL011Registers), + vmstate_struct!(PL011State, regs, &VMSTATE_PL011_REGS, BqlRefCell), }, subsections: vmstate_subsections! { VMSTATE_PL011_CLOCK diff --git a/rust/hw/char/pl011/src/memory_ops.rs b/rust/hw/char/pl011/src/memory_ops.rs index c4e8599ba43..8f66c8d492c 100644 --- a/rust/hw/char/pl011/src/memory_ops.rs +++ b/rust/hw/char/pl011/src/memory_ops.rs @@ -26,7 +26,7 @@ unsafe extern "C" fn pl011_read(opaque: *mut c_void, addr: hwaddr, size: c_uint) -> u64 { assert!(!opaque.is_null()); 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Fri, 17 Jan 2025 01:27:17 -0800 (PST) X-Google-Smtp-Source: AGHT+IGVqG+RfH01JbScVMhK0hergPcEkoF02jSu7bcLe4UjTPb/cCZHpm3dL7gwCCHZiJ7iTX4U9Q== X-Received: by 2002:a17:907:7da2:b0:aa6:8a1b:8b84 with SMTP id a640c23a62f3a-ab38b5342demr211526766b.57.1737106037144; Fri, 17 Jan 2025 01:27:17 -0800 (PST) Received: from [192.168.10.3] ([176.206.124.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384c61388sm138174466b.20.2025.01.17.01.27.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jan 2025 01:27:16 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: qemu-rust@nongnu.org Subject: [PATCH 08/10] rust: pl011: remove duplicate definitions Date: Fri, 17 Jan 2025 10:26:55 +0100 Message-ID: <20250117092657.1051233-9-pbonzini@redhat.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250117092657.1051233-1-pbonzini@redhat.com> References: <20250117092657.1051233-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; 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The "int_level" and "int_enabled" fields could use a crate such as "bitflags". Signed-off-by: Paolo Bonzini --- rust/hw/char/pl011/src/device.rs | 36 ++++++++++++------------- rust/hw/char/pl011/src/lib.rs | 46 +++++++++++--------------------- 2 files changed, 33 insertions(+), 49 deletions(-) diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs index 1d3da59e481..6ecbfb9ac84 100644 --- a/rust/hw/char/pl011/src/device.rs +++ b/rust/hw/char/pl011/src/device.rs @@ -183,7 +183,7 @@ pub(self) fn read(&mut self, offset: RegisterOffset) -> ControlFlow { self.flags.set_receive_fifo_empty(true); } if self.read_count + 1 == self.read_trigger { - self.int_level &= !registers::INT_RX; + self.int_level &= !Interrupt::RX.0; } // Update error bits. self.receive_status_error_clear.set_from_data(c); @@ -232,7 +232,7 @@ pub(self) fn write( } // interrupts always checked let _ = self.loopback_tx(value); - self.int_level |= registers::INT_TX; + self.int_level |= Interrupt::TX.0; return true; } RSR => { @@ -356,19 +356,19 @@ fn loopback_mdmctrl(&mut self) -> bool { // Change interrupts based on updated FR let mut il = self.int_level; - il &= !Interrupt::MS; + il &= !Interrupt::MS.0; if self.flags.data_set_ready() { - il |= Interrupt::DSR as u32; + il |= Interrupt::DSR.0; } if self.flags.data_carrier_detect() { - il |= Interrupt::DCD as u32; + il |= Interrupt::DCD.0; } if self.flags.clear_to_send() { - il |= Interrupt::CTS as u32; + il |= Interrupt::CTS.0; } if self.flags.ring_indicator() { - il |= Interrupt::RI as u32; + il |= Interrupt::RI.0; } self.int_level = il; true @@ -446,7 +446,7 @@ pub fn put_fifo(&mut self, value: u32) -> bool { } if self.read_count == self.read_trigger { - self.int_level |= registers::INT_RX; + self.int_level |= Interrupt::RX.0; return true; } false @@ -622,16 +622,16 @@ pub fn post_load(&self, _version_id: u32) -> Result<(), ()> { /// Which bits in the interrupt status matter for each outbound IRQ line ? const IRQMASK: [u32; 6] = [ /* combined IRQ */ - Interrupt::E - | Interrupt::MS - | Interrupt::RT as u32 - | Interrupt::TX as u32 - | Interrupt::RX as u32, - Interrupt::RX as u32, - Interrupt::TX as u32, - Interrupt::RT as u32, - Interrupt::MS, - Interrupt::E, + Interrupt::E.0 + | Interrupt::MS.0 + | Interrupt::RT.0 + | Interrupt::TX.0 + | Interrupt::RX.0, + Interrupt::RX.0, + Interrupt::TX.0, + Interrupt::RT.0, + Interrupt::MS.0, + Interrupt::E.0, ]; /// # Safety diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs index 2baacba2306..300c732ae1d 100644 --- a/rust/hw/char/pl011/src/lib.rs +++ b/rust/hw/char/pl011/src/lib.rs @@ -100,7 +100,6 @@ enum RegisterOffset { //Reserved = 0x04C, } -#[allow(dead_code)] mod registers { //! Device registers exposed as typed structs which are backed by arbitrary //! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc. @@ -521,38 +520,23 @@ fn default() -> Self { } /// Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC - pub const INT_OE: u32 = 1 << 10; - pub const INT_BE: u32 = 1 << 9; - pub const INT_PE: u32 = 1 << 8; - pub const INT_FE: u32 = 1 << 7; - pub const INT_RT: u32 = 1 << 6; - pub const INT_TX: u32 = 1 << 5; - pub const INT_RX: u32 = 1 << 4; - pub const INT_DSR: u32 = 1 << 3; - pub const INT_DCD: u32 = 1 << 2; - pub const INT_CTS: u32 = 1 << 1; - pub const INT_RI: u32 = 1 << 0; - pub const INT_E: u32 = INT_OE | INT_BE | INT_PE | INT_FE; - pub const INT_MS: u32 = INT_RI | INT_DSR | INT_DCD | INT_CTS; - - #[repr(u32)] - pub enum Interrupt { - OE = 1 << 10, - BE = 1 << 9, - PE = 1 << 8, - FE = 1 << 7, - RT = 1 << 6, - TX = 1 << 5, - RX = 1 << 4, - DSR = 1 << 3, - DCD = 1 << 2, - CTS = 1 << 1, - RI = 1 << 0, - } + pub struct Interrupt(pub u32); impl Interrupt { - pub const E: u32 = INT_OE | INT_BE | INT_PE | INT_FE; - pub const MS: u32 = INT_RI | INT_DSR | INT_DCD | INT_CTS; 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envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -39 X-Spam_score: -4.0 X-Spam_bar: ---- X-Spam_report: (-4.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.093, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-1.797, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org read() can now return a simple u64. Signed-off-by: Paolo Bonzini --- rust/hw/char/pl011/src/device.rs | 16 +++++++++------- rust/hw/char/pl011/src/memory_ops.rs | 23 ++++------------------- 2 files changed, 13 insertions(+), 26 deletions(-) diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs index 6ecbfb9ac84..af0f451deb2 100644 --- a/rust/hw/char/pl011/src/device.rs +++ b/rust/hw/char/pl011/src/device.rs @@ -171,7 +171,7 @@ impl PL011Registers { pub(self) fn read(&mut self, offset: RegisterOffset) -> ControlFlow { use RegisterOffset::*; - std::ops::ControlFlow::Break(match offset { + ControlFlow::Break(match offset { DR => { self.flags.set_receive_fifo_full(false); let c = self.read_fifo[self.read_pos]; @@ -530,22 +530,24 @@ fn post_init(&self) { } } - #[allow(clippy::needless_pass_by_ref_mut)] - pub fn read(&mut self, offset: hwaddr, _size: u32) -> ControlFlow { + pub fn read(&mut self, offset: hwaddr, _size: u32) -> u64 { match RegisterOffset::try_from(offset) { Err(v) if (0x3f8..0x400).contains(&(v >> 2)) => { let device_id = self.get_class().device_id; - ControlFlow::Break(u64::from(device_id[(offset - 0xfe0) >> 2])) + u64::from(device_id[(offset - 0xfe0) >> 2]) } Err(_) => { // qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset 0x%x\n", (int)offset); - ControlFlow::Break(0) + 0 } Ok(field) => match self.regs.borrow_mut().read(field) { - ControlFlow::Break(value) => ControlFlow::Break(value.into()), + ControlFlow::Break(value) => value.into(), ControlFlow::Continue(value) => { self.update(); - ControlFlow::Continue(value.into()) + unsafe { + qemu_chr_fe_accept_input(&mut self.char_backend); + } + value.into() }, } } diff --git a/rust/hw/char/pl011/src/memory_ops.rs b/rust/hw/char/pl011/src/memory_ops.rs index 8f66c8d492c..95b4df794e4 100644 --- a/rust/hw/char/pl011/src/memory_ops.rs +++ b/rust/hw/char/pl011/src/memory_ops.rs @@ -26,26 +26,11 @@ unsafe extern "C" fn pl011_read(opaque: *mut c_void, addr: hwaddr, size: c_uint) -> u64 { assert!(!opaque.is_null()); let mut state = unsafe { NonNull::new_unchecked(opaque.cast::()) }; - let val = unsafe { state.as_mut() }.read(addr, size); - match val { - std::ops::ControlFlow::Break(val) => val, - std::ops::ControlFlow::Continue(val) => { - // SAFETY: self.char_backend is a valid CharBackend instance after it's been - // initialized in realize(). - let cb_ptr = unsafe { core::ptr::addr_of_mut!(state.as_mut().char_backend) }; - unsafe { - qemu_chr_fe_accept_input(cb_ptr); - } - - val - } - } + unsafe { state.as_mut() }.read(addr, size) } unsafe extern "C" fn pl011_write(opaque: *mut c_void, addr: hwaddr, data: u64, _size: c_uint) { - unsafe { - assert!(!opaque.is_null()); - let mut state = NonNull::new_unchecked(opaque.cast::()); - state.as_mut().write(addr, data) - } + assert!(!opaque.is_null()); + let mut state = unsafe { NonNull::new_unchecked(opaque.cast::()) }; + unsafe { state.as_mut() }.write(addr, data); } From patchwork Fri Jan 17 09:26:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 13943057 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BEAD1C02188 for ; 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helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -39 X-Spam_score: -4.0 X-Spam_bar: ---- X-Spam_report: (-4.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.093, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-1.797, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Because register reset is within a borrow_mut() call, reset does not need anymore a mut reference to the PL011State. Signed-off-by: Paolo Bonzini --- rust/hw/char/pl011/src/device.rs | 4 ++-- rust/qemu-api/src/qdev.rs | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs index af0f451deb2..019c1617807 100644 --- a/rust/hw/char/pl011/src/device.rs +++ b/rust/hw/char/pl011/src/device.rs @@ -164,7 +164,7 @@ fn vmsd() -> Option<&'static VMStateDescription> { Some(&device_class::VMSTATE_PL011) } const REALIZE: Option = Some(Self::realize); - const RESET: Option = Some(Self::reset); + const RESET: Option = Some(Self::reset); } impl PL011Registers { @@ -604,7 +604,7 @@ pub fn realize(&mut self) { } } - pub fn reset(&mut self) { + pub fn reset(&self) { self.regs.borrow_mut().reset(); } diff --git a/rust/qemu-api/src/qdev.rs b/rust/qemu-api/src/qdev.rs index 686054e737a..4658409bebb 100644 --- a/rust/qemu-api/src/qdev.rs +++ b/rust/qemu-api/src/qdev.rs @@ -30,7 +30,7 @@ pub trait DeviceImpl { /// /// Rust does not yet support the three-phase reset protocol; this is /// usually okay for leaf classes. - const RESET: Option = None; + const RESET: Option = None; /// An array providing the properties that the user can set on the /// device. Not a `const` because referencing statics in constants