From patchwork Fri Jan 17 17:22:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13943671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A440BC02185 for ; Fri, 17 Jan 2025 17:24:03 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tYq43-0007e3-Bq; Fri, 17 Jan 2025 12:23:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tYq3f-0007TQ-Tn; Fri, 17 Jan 2025 12:23:00 -0500 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tYq3e-00061n-Ee; Fri, 17 Jan 2025 12:22:59 -0500 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-21644aca3a0so57567655ad.3; Fri, 17 Jan 2025 09:22:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737134577; x=1737739377; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G13bQK8MBtUoRPpnIFDO8Sgsudp2y54/cquE6DK8iMs=; b=dS/bpNDpDPE5z/WHH5MVvvxpzGbkccFnGecvXHk0H8vvYfR6N6aADKVvWBXa19zVId fJpma1Hn+VOdiTFjcM6q3uyZHZaDjihc+wd+PJouY4Z6cahdX3Y2Qet7Thw3MOrrKRl/ CaiqofeYqlmqkXghmVqzlU/BSYDTqd58+kbDGwJYeLjamYE2Ihn7VZyKyVK4opnfKQZe x6ctcQ6hrQjuGFScn8ARRnOzWdLwvngy7xCf2fBFIqtfCiY7+YkGXhk7Mcu4ZH7Gv0d5 EPjPYT1z+8LNLc4AYr3Thw9piPfoc6yghaIsTtL9RuoDUIHVjyHApCyhqWnoa210eZle J+cA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737134577; x=1737739377; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G13bQK8MBtUoRPpnIFDO8Sgsudp2y54/cquE6DK8iMs=; b=snx5veIuHcxKXcOq94EAorJN5T3xwAb4kEK7roTAyGo9jZ7fcHHHFOOkNxVehmUydV PeY61sV/kXGqJlOcC0j/EQdKTC3aM7gh+bby04GeYyEujBYgUbH6Q6s3V2e77fFB9Xmz I2Y9RFJAnv1mfhjj5QYXlsMhJgm+kai/t6VplSoVKWJSi6p4rydbQvZ45Cq6q8Pql4GM USMPCNpZBQLRmf/O3NlP67OKiqfhug6Ro390iQgyH2hEnk29xzh8DGQxyL4tWxRZq7mr Uu8MjvxJoNfz9GVZxAyru62My7gTg1xUrOQPgIYmwNZ74fKn/TCYjQZcMuyA/7iRM8// +9hw== X-Forwarded-Encrypted: i=1; AJvYcCWnluaONcQcBst3MqNdRZZbkMQf2z0Ta2ONJf0ytnvGAiOfnBNQy74/itxoD2dJ/PtSekhMKPfVm6a2@nongnu.org, AJvYcCX6nmq1qQFXPs3mFBEjmCPkbXIgoQp12Gt3I+LOGNyTP/LS62MnC3xWdGVfscYk+2s0bq3tWaia/+Mg/A==@nongnu.org X-Gm-Message-State: AOJu0YwN0VD4kU8H8zsaCvix896kg+6juKIGy0BVQo8ilc4MHcReqnCU D9dIwWJ6fdTryuGHZs8hfn1uLP7HLAbevrLmAw4WN7s7GSIbD896 X-Gm-Gg: ASbGncsHRa8wI7BV97JQ5d1qrYYbRpIybCprbU5b/4l6Vuf86l973uW2z7WVeAQC5rQ EbfcUJL9WMS0452Sy7YQOiuKBggxDzbjRxoR6EO2q+BvtLNrzeMz/ZbhyE9B4YLtIciwIaxwQ5g /ec1PhyKyeG3rbzohj4QLrC37LTVk+2HGZFp5rKEkRrCnP2fotZGlgdo+LKy2tFDpQcvWNzZpju HgCBCK1vHBYdbZMgnNMR5PMadlxOEgB3gHEST0zCm7exx5BN2psHp24dGoULgHR6WWjBC0USTF9 O1qPrS/oJDv8HR0= X-Google-Smtp-Source: AGHT+IGqhYxRWQ7UPyszVEfBKnwbxGfHpuVJRP3bSNzwKy7WcFIzq+50tyPyw3fJb3i8pRITYzYGow== X-Received: by 2002:a05:6a00:2d19:b0:725:ffe:4dae with SMTP id d2e1a72fcca58-72dafa44ce7mr5543345b3a.10.1737134576830; Fri, 17 Jan 2025 09:22:56 -0800 (PST) Received: from wheely.local0.net (124-169-212-233.tpgi.com.au. [124.169.212.233]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72daba511a4sm2235950b3a.140.2025.01.17.09.22.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jan 2025 09:22:56 -0800 (PST) From: Nicholas Piggin To: Fabiano Rosas Cc: Nicholas Piggin , John Snow , Laurent Vivier , Paolo Bonzini , Akihiko Odaki , "Michael S . Tsirkin" , Marcel Apfelbaum , qemu-block@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 1/4] qtest/libqos/pci: Do not write to PBA memory Date: Sat, 18 Jan 2025 03:22:40 +1000 Message-ID: <20250117172244.406206-2-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250117172244.406206-1-npiggin@gmail.com> References: <20250117172244.406206-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The PCI Local Bus Specification says the result of writes to MSI-X PBA memory is undefined. QEMU implements them as no-ops, so remove the pointless write from qpci_msix_pending(). Signed-off-by: Nicholas Piggin --- tests/qtest/libqos/pci.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c index b23d72346b6..a59197b9922 100644 --- a/tests/qtest/libqos/pci.c +++ b/tests/qtest/libqos/pci.c @@ -328,8 +328,6 @@ bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry) g_assert(dev->msix_enabled); pba_entry = qpci_io_readl(dev, dev->msix_pba_bar, dev->msix_pba_off + off); - qpci_io_writel(dev, dev->msix_pba_bar, dev->msix_pba_off + off, - pba_entry & ~(1 << bit_n)); return (pba_entry & (1 << bit_n)) != 0; } From patchwork Fri Jan 17 17:22:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13943674 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5B7DBC02183 for ; Fri, 17 Jan 2025 17:24:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tYq46-0007kg-PZ; Fri, 17 Jan 2025 12:23:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tYq3k-0007Uq-Uk; Fri, 17 Jan 2025 12:23:05 -0500 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tYq3j-00063I-9c; Fri, 17 Jan 2025 12:23:04 -0500 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-21675fd60feso53732115ad.2; Fri, 17 Jan 2025 09:23:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737134581; x=1737739381; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1QIwrFyIStAPgOTMlYQifj6PiT67/GJsSNdwJzc5QhY=; b=hfd4nnNc2yZxZRg+PQMNVfxThBqRgmUJ/btWjv953lUZ5ir6atRs8McRwDKqQoKQ5B oDyDR3gD9xpIXhg+EOwO2SecCIu1ii/9Yjy6c3havCZiY5xM5SNDl9RbA+7HMWuxpUPy qbL9nT27QBN3dtN5Ibxk6cUTnUU+d+9V4ciLp53AkDc0FB/81wCugvOnUWkPqswK/Tuv hMsy9WutyCEcFIBikA13GDeoSudVjfceVXZfCFF7PvYIMcU+FXqEHDZgmHEkim6Iyjy5 jRAc0OQv/8uyshUPweXI5+Fr1DYE66MBBW5HONKWYjgjTwzsa7TScfWA4PLecEdAKaZ6 Wy1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737134581; x=1737739381; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1QIwrFyIStAPgOTMlYQifj6PiT67/GJsSNdwJzc5QhY=; b=D3DMxn6yA2qGOKawmwQn4T0NWwvdtd+4beLk1lj+LdMcLDQLGSBXnWzI2B1EgkJWMm GHoVMQsRto7Y4Vu7l3qAgbFOZBJ+7vR801o25xVmPSDIStmxz+XR6WzKl7gXLNFv4smf 4iX3k5dMfNR7LLoRb/1Qeadm1184a5JePHhBsaQVnWhU430LsjM5wYzN+W9pNV2BDnW3 535eRtYxH3ce7mvZR49c/lc0k+gnmTqIM2L3dGK7evGctzJL2q12Y9LruksMsyVuVPb6 zUq9x8Qv7CQyC9ww5g2Wv18O/oSN43t4V/GpKdYEuC1cdQQLgkY5/cW+Bg5VjTItNzHW 9OQA== X-Forwarded-Encrypted: i=1; AJvYcCUTplks0pElR48WSszWM179alrozLuHOvmPAfqjLE/rIiQro4MaEVAm1I4VCbFfvSf3isEuPMmYWMz0@nongnu.org, AJvYcCWAAejxerKPsVaQuABHWlMnb2gRfJrMPGh1Ohpe3Mx4xqUuFc7hEoE1JULQT5uN1jjUhm0N7x4fnzFnzQ==@nongnu.org X-Gm-Message-State: AOJu0Yxkp1fHiPL+daBdZf6NTqYqiHpc8bv6j6gJq02p59PqBH1AAyNs 45A2jUH8PKHDPLXxy26UAuQ4wkCqmPnTfJheJ5RUWb5ygZwkHuTg X-Gm-Gg: ASbGncv4kR6zENJcNzIY2ojhET3d89AqMEok2f5sN9dMh16eTi4qkVhWus4nJKHQJB9 25fp6cmgSfIpLZUmyhMbo8a/7rEsYhlluoQEgDcMjo3WHLNHn+L1AOoX8DmnRnEjfnt1oFPGYwz qguBpcK0xA6gQiVNqZKgoNwld6GdPCaOPpjPyuYMmxl2dvWZFr9E+eJ9jP/cQYrQSWcAIwRHDTx ix+OiiHSJrwiJgR+ZdmTuAWj/edZbIsCQgW38OI38auyXZxf2Zh9JsnJQlMU69C9dlyxmQ5YSC/ DK1H3ocUI5oKDhM= X-Google-Smtp-Source: AGHT+IH4DUtk0f5fuhqap0s3zLrGN2cK0ZOCQqHKqvZMGgFDa1mv1pFj87J6AAYmhgQsHrfvHLcxcA== X-Received: by 2002:a05:6a20:244e:b0:1e0:d4f4:5b39 with SMTP id adf61e73a8af0-1eb214caa0emr5688547637.24.1737134581339; Fri, 17 Jan 2025 09:23:01 -0800 (PST) Received: from wheely.local0.net (124-169-212-233.tpgi.com.au. [124.169.212.233]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72daba511a4sm2235950b3a.140.2025.01.17.09.22.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jan 2025 09:23:00 -0800 (PST) From: Nicholas Piggin To: Fabiano Rosas Cc: Nicholas Piggin , John Snow , Laurent Vivier , Paolo Bonzini , Akihiko Odaki , "Michael S . Tsirkin" , Marcel Apfelbaum , qemu-block@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 2/4] qtest/libqos/pci: Enforce balanced iomap/unmap Date: Sat, 18 Jan 2025 03:22:41 +1000 Message-ID: <20250117172244.406206-3-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250117172244.406206-1-npiggin@gmail.com> References: <20250117172244.406206-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add assertions to ensure a BAR is not mapped twice, and only previously mapped BARs are unmapped. This can help catch some bugs. Reviewed-by: Fabiano Rosas Signed-off-by: Nicholas Piggin --- tests/qtest/libqos/ahci.h | 1 + tests/qtest/libqos/pci.h | 2 ++ tests/qtest/libqos/virtio-pci.h | 1 + tests/qtest/ahci-test.c | 2 ++ tests/qtest/libqos/ahci.c | 6 ++++++ tests/qtest/libqos/pci.c | 32 +++++++++++++++++++++++++++++++- tests/qtest/libqos/virtio-pci.c | 6 +++++- 7 files changed, 48 insertions(+), 2 deletions(-) diff --git a/tests/qtest/libqos/ahci.h b/tests/qtest/libqos/ahci.h index a0487a1557d..5d7e26aee2a 100644 --- a/tests/qtest/libqos/ahci.h +++ b/tests/qtest/libqos/ahci.h @@ -575,6 +575,7 @@ QPCIDevice *get_ahci_device(QTestState *qts, uint32_t *fingerprint); void free_ahci_device(QPCIDevice *dev); void ahci_pci_enable(AHCIQState *ahci); void start_ahci_device(AHCIQState *ahci); +void stop_ahci_device(AHCIQState *ahci); void ahci_hba_enable(AHCIQState *ahci); /* Port Management */ diff --git a/tests/qtest/libqos/pci.h b/tests/qtest/libqos/pci.h index 83896145235..9dc82ea723a 100644 --- a/tests/qtest/libqos/pci.h +++ b/tests/qtest/libqos/pci.h @@ -65,6 +65,8 @@ struct QPCIDevice { QPCIBus *bus; int devfn; + bool bars_mapped[6]; + QPCIBar bars[6]; bool msix_enabled; QPCIBar msix_table_bar, msix_pba_bar; uint64_t msix_table_off, msix_pba_off; diff --git a/tests/qtest/libqos/virtio-pci.h b/tests/qtest/libqos/virtio-pci.h index f5115cacba2..efdf904b254 100644 --- a/tests/qtest/libqos/virtio-pci.h +++ b/tests/qtest/libqos/virtio-pci.h @@ -26,6 +26,7 @@ typedef struct QVirtioPCIDevice { uint64_t config_msix_addr; uint32_t config_msix_data; + bool enabled; int bar_idx; /* VIRTIO 1.0 */ diff --git a/tests/qtest/ahci-test.c b/tests/qtest/ahci-test.c index 5a1923f721b..b3dae7a8ce4 100644 --- a/tests/qtest/ahci-test.c +++ b/tests/qtest/ahci-test.c @@ -1483,6 +1483,8 @@ static void test_reset_pending_callback(void) /* Wait for throttled write to finish. */ sleep(1); + stop_ahci_device(ahci); + /* Start again. */ ahci_clean_mem(ahci); ahci_pci_enable(ahci); diff --git a/tests/qtest/libqos/ahci.c b/tests/qtest/libqos/ahci.c index 34a75b7f43b..cfc435b6663 100644 --- a/tests/qtest/libqos/ahci.c +++ b/tests/qtest/libqos/ahci.c @@ -217,6 +217,12 @@ void start_ahci_device(AHCIQState *ahci) qpci_device_enable(ahci->dev); } +void stop_ahci_device(AHCIQState *ahci) +{ + /* Map AHCI's ABAR (BAR5) */ + qpci_iounmap(ahci->dev, ahci->hba_bar); +} + /** * Test and initialize the AHCI's HBA memory areas. * Initialize and start any ports with devices attached. diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c index a59197b9922..05089a5f24f 100644 --- a/tests/qtest/libqos/pci.c +++ b/tests/qtest/libqos/pci.c @@ -93,12 +93,17 @@ QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn) void qpci_device_init(QPCIDevice *dev, QPCIBus *bus, QPCIAddress *addr) { uint16_t vendor_id, device_id; + int i; qpci_device_set(dev, bus, addr->devfn); vendor_id = qpci_config_readw(dev, PCI_VENDOR_ID); device_id = qpci_config_readw(dev, PCI_DEVICE_ID); g_assert(!addr->vendor_id || vendor_id == addr->vendor_id); g_assert(!addr->device_id || device_id == addr->device_id); + + for (i = 0; i < 6; i++) { + g_assert(!dev->bars_mapped[i]); + } } static uint8_t qpci_find_resource_reserve_capability(QPCIDevice *dev) @@ -529,6 +534,8 @@ QPCIBar qpci_iomap(QPCIDevice *dev, int barno, uint64_t *sizeptr) uint64_t loc; g_assert(barno >= 0 && barno <= 5); + g_assert(!dev->bars_mapped[barno]); + bar_reg = bar_reg_map[barno]; qpci_config_writel(dev, bar_reg, 0xFFFFFFFF); @@ -572,12 +579,35 @@ QPCIBar qpci_iomap(QPCIDevice *dev, int barno, uint64_t *sizeptr) } bar.addr = loc; + + dev->bars_mapped[barno] = true; + dev->bars[barno] = bar; + return bar; } void qpci_iounmap(QPCIDevice *dev, QPCIBar bar) { - /* FIXME */ + static const int bar_reg_map[] = { + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2, + PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5, + }; + int bar_reg; + int i; + + for (i = 0; i < 6; i++) { + if (!dev->bars_mapped[i]) { + continue; + } + if (dev->bars[i].addr == bar.addr) { + dev->bars_mapped[i] = false; + bar_reg = bar_reg_map[i]; + qpci_config_writel(dev, bar_reg, 0xFFFFFFFF); + /* FIXME: the address space is leaked */ + return; + } + } + g_assert_not_reached(); } QPCIBar qpci_legacy_iomap(QPCIDevice *dev, uint16_t addr) diff --git a/tests/qtest/libqos/virtio-pci.c b/tests/qtest/libqos/virtio-pci.c index 485b8f6b7e0..2b59fb181c9 100644 --- a/tests/qtest/libqos/virtio-pci.c +++ b/tests/qtest/libqos/virtio-pci.c @@ -304,11 +304,15 @@ void qvirtio_pci_device_enable(QVirtioPCIDevice *d) { qpci_device_enable(d->pdev); d->bar = qpci_iomap(d->pdev, d->bar_idx, NULL); + d->enabled = true; } void qvirtio_pci_device_disable(QVirtioPCIDevice *d) { - qpci_iounmap(d->pdev, d->bar); + if (d->enabled) { + qpci_iounmap(d->pdev, d->bar); + d->enabled = false; + } } void qvirtqueue_pci_msix_setup(QVirtioPCIDevice *d, QVirtQueuePCI *vqpci, From patchwork Fri Jan 17 17:22:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13943669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18274C02183 for ; Fri, 17 Jan 2025 17:23:41 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tYq46-0007jo-9N; Fri, 17 Jan 2025 12:23:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tYq3p-0007Wu-L6; Fri, 17 Jan 2025 12:23:14 -0500 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tYq3o-00063w-1K; Fri, 17 Jan 2025 12:23:09 -0500 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-21628b3fe7dso45544505ad.3; Fri, 17 Jan 2025 09:23:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737134586; x=1737739386; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BH1wCV8PXHzuAt3MSEu+tLtfIzMOQCTZueYB6tyK/1s=; b=kdc9x2GbfCVPFkbOewZY+IzY/9CaehyR6KacuWsl1GB5x5zJ99D6999V1HLrkudcHh 8GiwA9YPOwGkKz29oYWAB7VFr9Rjj4IkArCJ4U6POWqmV+3wSbsjtdvWpGJUi6uUq6dn R7cU2tqkAjhXemA3V4H/yiiSDTAc4+paM1MZX13Mz3/5Mpu8x5ur+tu4/wgBChCaTJv3 0vbwa+fnmldj73ViSdJ9iGMZXLfNdKFqjEATnjrJuhbe5W0N7Rff42/aw/jFGvJ2it/+ yC1AdQ20EUFZJ4zBuq7YhLCCyPmJ58po0ihOWvja73FjH6YGFP0CLChdqBQNV8SE9EMA EnOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737134586; x=1737739386; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BH1wCV8PXHzuAt3MSEu+tLtfIzMOQCTZueYB6tyK/1s=; b=lEvMH9YAsAWTGAVWsJHQsPr/ZvKOjn7vHGetyoEG3QxeFfQ+q498hDi5m8djrgFdOV xzADY9QnUFUCf7ZdVzhUA7TvmteJOacZQn1vrgHcAiPEa+/Z0WVmAP6Isb6IR5uHeHw+ zq1x4c6AB90ONYvZ13Q6lgnQ1BqXTcSgs673NowvjA2LLP9Q4xiHbwQXXReqRxx4zx+Y V+qGU47syGSzWoh50YChUxxHjHDaGkmR4RA3ZbxrBzyvHUmzRvfMIc+hdTAqN32jrPwf eKeqykOdTmJTpm3RQ+NStO0j+8DW/MLwgqa929ZG7Miet9eGxpzCxgOgQqAEZRiVoVjG OAEQ== X-Forwarded-Encrypted: i=1; AJvYcCViPngm2hmNHkUyjEcwodX7lWurnxNal8yd/zgkHak/tw3pz16GINgmT/h6ZDXUJvIfrs5jjlFGVImxIQ==@nongnu.org, AJvYcCW8nle8GN1OBMUh9pIbQs2tpWR1RK+xSfHbAyRvMYx8TIOniCufXhU6AonMAaGaRCB3YWTctEXGo4Jl@nongnu.org X-Gm-Message-State: AOJu0Yy8Y75rw/C32pMUV7xnj/xAZuOk9Rl1CF78RtxipKBCAiOpxmt/ WYVoQb4NSJrIW4y3v2jIXdQsppJ0EfKyihOFuaE1pO3NsYUG6qGH X-Gm-Gg: ASbGncvcTUXODkU13cjJVcJIcW2Zc84VqTjCPh767b1Zlcmg0K7RMQD/vFMGC3sIQOq nvgbh+gb7UrV9dTbcS35JQ2ikjtqFSfj5AI8whJSh9nsfPuUaSHRfr1kf4nXI08jHMYTlHrZh9r sa1L1LH65KBADfCPXozDT2Yt62VWOrNGepNZkkm18VPfkfwxgqx1KuNFyFgnaGJlqwnxxy/NVND C4xus4Cm1ncCMoeNz6iZcxCsxqnY9kQajmUK6Q8/zbjGpto12urSV7to17lIMC27WlXiHoR8HNL SrwB89hVlmZQsrU= X-Google-Smtp-Source: AGHT+IG4HNyccLh6DnfBYjHTltMuqjvdN3N+aIw9dZCcsUT5oLtB9c3sVKmqLSoLdxD73EsDKUdPEg== X-Received: by 2002:a05:6a00:994:b0:725:f376:f4f4 with SMTP id d2e1a72fcca58-72daf97af6emr4543340b3a.13.1737134585921; Fri, 17 Jan 2025 09:23:05 -0800 (PST) Received: from wheely.local0.net (124-169-212-233.tpgi.com.au. [124.169.212.233]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72daba511a4sm2235950b3a.140.2025.01.17.09.23.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jan 2025 09:23:05 -0800 (PST) From: Nicholas Piggin To: Fabiano Rosas Cc: Nicholas Piggin , John Snow , Laurent Vivier , Paolo Bonzini , Akihiko Odaki , "Michael S . Tsirkin" , Marcel Apfelbaum , qemu-block@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 3/4] qtest/libqos/pci: Fix qpci_msix_enable sharing bar0 Date: Sat, 18 Jan 2025 03:22:42 +1000 Message-ID: <20250117172244.406206-4-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250117172244.406206-1-npiggin@gmail.com> References: <20250117172244.406206-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=npiggin@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Devices where the MSI-X addresses are shared with other MMIO on BAR0 can not use msi_enable because it unmaps and remaps BAR0, which interferes with device MMIO mappings. xhci-nec is one such device we would like to test msix with. Use the BAR iomap tracking structure introduced in the previous change to have qpci_misx_enable() use existing iomaps if msix bars are already mapped. Reviewed-by: Fabiano Rosas Signed-off-by: Nicholas Piggin --- tests/qtest/libqos/pci.h | 1 + tests/qtest/libqos/pci.c | 40 ++++++++++++++++++++++++++++++++++------ 2 files changed, 35 insertions(+), 6 deletions(-) diff --git a/tests/qtest/libqos/pci.h b/tests/qtest/libqos/pci.h index 9dc82ea723a..5a7b2454ad5 100644 --- a/tests/qtest/libqos/pci.h +++ b/tests/qtest/libqos/pci.h @@ -68,6 +68,7 @@ struct QPCIDevice bool bars_mapped[6]; QPCIBar bars[6]; bool msix_enabled; + bool msix_table_bar_iomap, msix_pba_bar_iomap; QPCIBar msix_table_bar, msix_pba_bar; uint64_t msix_table_off, msix_pba_off; }; diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c index 05089a5f24f..a187349d30a 100644 --- a/tests/qtest/libqos/pci.c +++ b/tests/qtest/libqos/pci.c @@ -288,15 +288,21 @@ void qpci_msix_enable(QPCIDevice *dev) table = qpci_config_readl(dev, addr + PCI_MSIX_TABLE); bir_table = table & PCI_MSIX_FLAGS_BIRMASK; - dev->msix_table_bar = qpci_iomap(dev, bir_table, NULL); + if (dev->bars_mapped[bir_table]) { + dev->msix_table_bar = dev->bars[bir_table]; + } else { + dev->msix_table_bar_iomap = true; + dev->msix_table_bar = qpci_iomap(dev, bir_table, NULL); + } dev->msix_table_off = table & ~PCI_MSIX_FLAGS_BIRMASK; table = qpci_config_readl(dev, addr + PCI_MSIX_PBA); bir_pba = table & PCI_MSIX_FLAGS_BIRMASK; - if (bir_pba != bir_table) { - dev->msix_pba_bar = qpci_iomap(dev, bir_pba, NULL); + if (dev->bars_mapped[bir_pba]) { + dev->msix_pba_bar = dev->bars[bir_pba]; } else { - dev->msix_pba_bar = dev->msix_table_bar; + dev->msix_pba_bar_iomap = true; + dev->msix_pba_bar = qpci_iomap(dev, bir_pba, NULL); } dev->msix_pba_off = table & ~PCI_MSIX_FLAGS_BIRMASK; @@ -307,6 +313,7 @@ void qpci_msix_disable(QPCIDevice *dev) { uint8_t addr; uint16_t val; + uint32_t table; g_assert(dev->msix_enabled); addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0); @@ -315,10 +322,31 @@ void qpci_msix_disable(QPCIDevice *dev) qpci_config_writew(dev, addr + PCI_MSIX_FLAGS, val & ~PCI_MSIX_FLAGS_ENABLE); - if (dev->msix_pba_bar.addr != dev->msix_table_bar.addr) { + if (dev->msix_pba_bar_iomap) { + dev->msix_pba_bar_iomap = false; qpci_iounmap(dev, dev->msix_pba_bar); + } else { + /* + * If we had reused an existing iomap, ensure it is still mapped + * otherwise it would be a bug if it were unmapped before msix is + * disabled. A refcounting iomap implementation could avoid this + * issue entirely, but let's wait until that's needed. + */ + uint8_t bir_pba; + table = qpci_config_readl(dev, addr + PCI_MSIX_PBA); + bir_pba = table & PCI_MSIX_FLAGS_BIRMASK; + g_assert(dev->bars_mapped[bir_pba]); + } + + if (dev->msix_table_bar_iomap) { + dev->msix_table_bar_iomap = false; + qpci_iounmap(dev, dev->msix_table_bar); + } else { + uint8_t bir_table; + table = qpci_config_readl(dev, addr + PCI_MSIX_TABLE); + bir_table = table & PCI_MSIX_FLAGS_BIRMASK; + g_assert(dev->bars_mapped[bir_table]); } - qpci_iounmap(dev, dev->msix_table_bar); dev->msix_enabled = 0; dev->msix_table_off = 0; From patchwork Fri Jan 17 17:22:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13943670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C631AC02185 for ; Fri, 17 Jan 2025 17:23:53 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tYq4B-0007pm-3Q; Fri, 17 Jan 2025 12:23:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tYq3v-0007aR-Gf; Fri, 17 Jan 2025 12:23:15 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tYq3s-00064O-NS; Fri, 17 Jan 2025 12:23:15 -0500 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-2166651f752so57170005ad.3; Fri, 17 Jan 2025 09:23:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737134591; x=1737739391; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y3c/7dluxFVgKgfwsUNU3hoWNyxHyfAlaCqectWwk2w=; b=f36HBKQNvLwOxJdMVU66USfFK/78vCtjV1x0uvC1i46auX5bYwPLVQRKp2KjoAK25G C1cKKKv9TbyJ9fbawfOS27fYqJ4dUSuyugBK6F3KD379Q3z9qyszVEotHPB/N1kP8FNf OxFKVv1Moww3jq/AXxtccUk0SXe8/0zXtIU7BIpKAhStnBTFnXH4dUIZxKWsIrVZR5Xj t1iiSQ3L7EgFaPMUGbyub9a9SMhVWxN/3vOxZfQam2wlbCZ0ACWQxPz5iPls3UpyHY+z XQEul/35vjB9pJNcxF70KP+INg0UOMl56ReR2o3LC11va1BRrF1YKf32a+MMToY9Qk9v 3mwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737134591; x=1737739391; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y3c/7dluxFVgKgfwsUNU3hoWNyxHyfAlaCqectWwk2w=; b=ezKd/1tuVVm/UdQ8G3vxelD86emLNolfK7LdYaa9iFnxc7tBj+uM3FvZZKC66rMvMK HpdGingao5wm9GIPEJksXeoHuaad0J9psLNrfWEnStPaaPm8Psx+br7p4MFNQor5EQCG ++Yzm3biE8Ox8DLaor4sOCUoX9++Fq9/KheI4RKOhXlKKdZJSB28chr7YBefu4a6Wv5n Wq2sPlwV35FmAuNGjjoeLXnbBdCeUMw631swDrFWejFJ0OMvw8wnA8aniyvEfxDkVhRd HTLD5iFIl0xkda5WszTZG3ieQRZGsLf/tpHtYidaW7qjl3w0V2ZQgSbg3mSgJhFUxRfX UZlA== X-Forwarded-Encrypted: i=1; AJvYcCWLPSiwOj78NmwIY56W0iUeDULL7EMKc5+DfNx52uwIEvWKbLrdvxKPWH/L86CQZtWDffz8yzJ6bdOl@nongnu.org, AJvYcCXzVD0tIYMGnfbUUif+LqE9SErfDn107+/tUXQBAe199l/YnosX2sBTEAqBNnwvZ/FgjSUFVxfKyxiZMw==@nongnu.org X-Gm-Message-State: AOJu0Yy+ZMrscLGFyXqHkJbQDR1qiFt0IH4yE0JIpG7j7ZH/6PrKQlY1 t4QFuYrYGn1YTTKzmhjWj+njb7OwGk5ZjZX2fPeaLODhP2BqhtUy X-Gm-Gg: ASbGncv+E//jMHo4aqxJirLOwpXSMWAjzcrNGkVgZjJyqwVKH9Hn24pnvTDTRGmxFaa Yi8aaq/pUBsXg+YBqL26io1uL+O8ZL8HbP98nylX5Cyp2Cnuw4imeD+k7KAINBSvl+kUwx/ZYo0 Vp6GCGVb9/BiuZzfa26BjGrvr5qW1DTCJI5xiVY5OHJaCTv8ZbMQxKTZ1HKazePblfPzZffiYKf z3nvp7Mdp5GAzzCuG2O0J4TPL396cSayy2kmiBhnW4tsMgTUnuGgjuXPOSs709T0U5+dOqwSqq5 Qwah5kAOmpI3Dhc= X-Google-Smtp-Source: AGHT+IE2SYtsbmNnEdBkKhXsrEZWoltXsNsj+QMQCY3IiQ5YCEwiI/WUUNX9mjE/+J/ZhA00rrzQrA== X-Received: by 2002:a05:6a00:3e16:b0:728:ea15:6d68 with SMTP id d2e1a72fcca58-72dafb90858mr5080395b3a.18.1737134590760; Fri, 17 Jan 2025 09:23:10 -0800 (PST) Received: from wheely.local0.net (124-169-212-233.tpgi.com.au. [124.169.212.233]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72daba511a4sm2235950b3a.140.2025.01.17.09.23.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jan 2025 09:23:10 -0800 (PST) From: Nicholas Piggin To: Fabiano Rosas Cc: Nicholas Piggin , John Snow , Laurent Vivier , Paolo Bonzini , Akihiko Odaki , "Michael S . Tsirkin" , Marcel Apfelbaum , qemu-block@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 4/4] qtest/libqos/pci: Factor msix entry helpers into pci common code Date: Sat, 18 Jan 2025 03:22:43 +1000 Message-ID: <20250117172244.406206-5-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250117172244.406206-1-npiggin@gmail.com> References: <20250117172244.406206-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=npiggin@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Setting msix entry address and data and masking is moved into common code helpers from virtio tests. For now that remains the only user, but there are changes under development to enable msix vectors for msix, e1000e, and xhci tests, which can make use of them. Signed-off-by: Nicholas Piggin --- tests/qtest/libqos/pci.h | 3 ++ tests/qtest/libqos/pci.c | 53 +++++++++++++++++++++++++++++++++ tests/qtest/libqos/virtio-pci.c | 48 ++++------------------------- 3 files changed, 61 insertions(+), 43 deletions(-) diff --git a/tests/qtest/libqos/pci.h b/tests/qtest/libqos/pci.h index 5a7b2454ad5..d46ce4239f0 100644 --- a/tests/qtest/libqos/pci.h +++ b/tests/qtest/libqos/pci.h @@ -93,8 +93,11 @@ void qpci_device_enable(QPCIDevice *dev); uint8_t qpci_find_capability(QPCIDevice *dev, uint8_t id, uint8_t start_addr); void qpci_msix_enable(QPCIDevice *dev); void qpci_msix_disable(QPCIDevice *dev); +void qpci_msix_set_entry(QPCIDevice *dev, uint16_t entry, + uint64_t guest_addr, uint32_t data); bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry); bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry); +void qpci_msix_set_masked(QPCIDevice *dev, uint16_t entry, bool masked); uint16_t qpci_msix_table_size(QPCIDevice *dev); uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset); diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c index a187349d30a..47632c4b403 100644 --- a/tests/qtest/libqos/pci.c +++ b/tests/qtest/libqos/pci.c @@ -353,6 +353,25 @@ void qpci_msix_disable(QPCIDevice *dev) dev->msix_pba_off = 0; } +void qpci_msix_set_entry(QPCIDevice *dev, uint16_t entry, + uint64_t guest_addr, uint32_t data) +{ + uint64_t vector_off = dev->msix_table_off + entry * PCI_MSIX_ENTRY_SIZE; + + g_assert(dev->msix_enabled); + g_assert_cmpint(entry, >=, 0); + g_assert_cmpint(entry, <, qpci_msix_table_size(dev)); + + qpci_io_writel(dev, dev->msix_table_bar, + vector_off + PCI_MSIX_ENTRY_LOWER_ADDR, guest_addr & ~0UL); + qpci_io_writel(dev, dev->msix_table_bar, + vector_off + PCI_MSIX_ENTRY_UPPER_ADDR, + (guest_addr >> 32) & ~0UL); + + qpci_io_writel(dev, dev->msix_table_bar, + vector_off + PCI_MSIX_ENTRY_DATA, data); +} + bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry) { uint32_t pba_entry; @@ -360,6 +379,9 @@ bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry) uint64_t off = (entry / 32) * PCI_MSIX_ENTRY_SIZE / 4; g_assert(dev->msix_enabled); + g_assert_cmpint(entry, >=, 0); + g_assert_cmpint(entry, <, qpci_msix_table_size(dev)); + pba_entry = qpci_io_readl(dev, dev->msix_pba_bar, dev->msix_pba_off + off); return (pba_entry & (1 << bit_n)) != 0; } @@ -371,6 +393,9 @@ bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry) uint64_t vector_off = dev->msix_table_off + entry * PCI_MSIX_ENTRY_SIZE; g_assert(dev->msix_enabled); + g_assert_cmpint(entry, >=, 0); + g_assert_cmpint(entry, <, qpci_msix_table_size(dev)); + addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0); g_assert_cmphex(addr, !=, 0); val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS); @@ -384,6 +409,34 @@ bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry) } } +void qpci_msix_set_masked(QPCIDevice *dev, uint16_t entry, bool masked) +{ + uint8_t addr; + uint16_t val; + uint64_t vector_off = dev->msix_table_off + entry * PCI_MSIX_ENTRY_SIZE; + + g_assert(dev->msix_enabled); + g_assert_cmpint(entry, >=, 0); + g_assert_cmpint(entry, <, qpci_msix_table_size(dev)); + + addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0); + g_assert_cmphex(addr, !=, 0); + val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS); + g_assert(!(val & PCI_MSIX_FLAGS_MASKALL)); + + val = qpci_io_readl(dev, dev->msix_table_bar, + vector_off + PCI_MSIX_ENTRY_VECTOR_CTRL); + if (masked && !(val & PCI_MSIX_ENTRY_CTRL_MASKBIT)) { + qpci_io_writel(dev, dev->msix_table_bar, + vector_off + PCI_MSIX_ENTRY_VECTOR_CTRL, + val | PCI_MSIX_ENTRY_CTRL_MASKBIT); + } else if (!masked && (val & PCI_MSIX_ENTRY_CTRL_MASKBIT)) { + qpci_io_writel(dev, dev->msix_table_bar, + vector_off + PCI_MSIX_ENTRY_VECTOR_CTRL, + val & ~PCI_MSIX_ENTRY_CTRL_MASKBIT); + } +} + uint16_t qpci_msix_table_size(QPCIDevice *dev) { uint8_t addr; diff --git a/tests/qtest/libqos/virtio-pci.c b/tests/qtest/libqos/virtio-pci.c index 2b59fb181c9..ed7f50e41a5 100644 --- a/tests/qtest/libqos/virtio-pci.c +++ b/tests/qtest/libqos/virtio-pci.c @@ -318,64 +318,26 @@ void qvirtio_pci_device_disable(QVirtioPCIDevice *d) void qvirtqueue_pci_msix_setup(QVirtioPCIDevice *d, QVirtQueuePCI *vqpci, QGuestAllocator *alloc, uint16_t entry) { - uint32_t control; - uint64_t off; - g_assert(d->pdev->msix_enabled); - off = d->pdev->msix_table_off + (entry * 16); - - g_assert_cmpint(entry, >=, 0); - g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev)); vqpci->msix_entry = entry; - vqpci->msix_addr = guest_alloc(alloc, 4); - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_LOWER_ADDR, vqpci->msix_addr & ~0UL); - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_UPPER_ADDR, - (vqpci->msix_addr >> 32) & ~0UL); - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_DATA, vqpci->msix_data); - - control = qpci_io_readl(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_VECTOR_CTRL); - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_VECTOR_CTRL, - control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT); + qpci_msix_set_entry(d->pdev, entry, vqpci->msix_addr, vqpci->msix_data); + qpci_msix_set_masked(d->pdev, entry, false); d->msix_ops->set_queue_vector(d, vqpci->vq.index, entry); } void qvirtio_pci_set_msix_configuration_vector(QVirtioPCIDevice *d, QGuestAllocator *alloc, uint16_t entry) { - uint32_t control; - uint64_t off; - g_assert(d->pdev->msix_enabled); - off = d->pdev->msix_table_off + (entry * 16); - - g_assert_cmpint(entry, >=, 0); - g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev)); d->config_msix_entry = entry; - d->config_msix_data = 0x12345678; d->config_msix_addr = guest_alloc(alloc, 4); - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_LOWER_ADDR, d->config_msix_addr & ~0UL); - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_UPPER_ADDR, - (d->config_msix_addr >> 32) & ~0UL); - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_DATA, d->config_msix_data); - - control = qpci_io_readl(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_VECTOR_CTRL); - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_VECTOR_CTRL, - control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT); - + qpci_msix_set_entry(d->pdev, entry, d->config_msix_addr, + d->config_msix_data); + qpci_msix_set_masked(d->pdev, entry, false); d->msix_ops->set_config_vector(d, entry); }