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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.12.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:12:38 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Craig Blackmore , Daniel Henrique Barboza , Max Chou , Richard Henderson , Alistair Francis Subject: [PULL v2 01/50] target/riscv: rvv: fix typo in vext continuous ldst function names Date: Sun, 19 Jan 2025 11:11:36 +1000 Message-ID: <20250119011225.11452-2-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Craig Blackmore Replace `continus` with `continuous`. Signed-off-by: Craig Blackmore Reviewed-by: Daniel Henrique Barboza Reviewed-by: Max Chou Reviewed-by: Richard Henderson Message-ID: <20241218142353.1027938-2-craig.blackmore@embecosm.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index a85dd1d200..0f57e48cc5 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -195,7 +195,7 @@ GEN_VEXT_ST_ELEM(ste_w, uint32_t, H4, stl) GEN_VEXT_ST_ELEM(ste_d, uint64_t, H8, stq) static inline QEMU_ALWAYS_INLINE void -vext_continus_ldst_tlb(CPURISCVState *env, vext_ldst_elem_fn_tlb *ldst_tlb, +vext_continuous_ldst_tlb(CPURISCVState *env, vext_ldst_elem_fn_tlb *ldst_tlb, void *vd, uint32_t evl, target_ulong addr, uint32_t reg_start, uintptr_t ra, uint32_t esz, bool is_load) @@ -207,7 +207,7 @@ vext_continus_ldst_tlb(CPURISCVState *env, vext_ldst_elem_fn_tlb *ldst_tlb, } static inline QEMU_ALWAYS_INLINE void -vext_continus_ldst_host(CPURISCVState *env, vext_ldst_elem_fn_host *ldst_host, +vext_continuous_ldst_host(CPURISCVState *env, vext_ldst_elem_fn_host *ldst_host, void *vd, uint32_t evl, uint32_t reg_start, void *host, uint32_t esz, bool is_load) { @@ -342,8 +342,8 @@ vext_page_ldst_us(CPURISCVState *env, void *vd, target_ulong addr, if (flags == 0) { if (nf == 1) { - vext_continus_ldst_host(env, ldst_host, vd, evl, env->vstart, host, - esz, is_load); + vext_continuous_ldst_host(env, ldst_host, vd, evl, env->vstart, + host, esz, is_load); } else { for (i = env->vstart; i < evl; ++i) { k = 0; @@ -357,7 +357,7 @@ vext_page_ldst_us(CPURISCVState *env, void *vd, target_ulong addr, env->vstart += elems; } else { if (nf == 1) { - vext_continus_ldst_tlb(env, ldst_tlb, vd, evl, addr, env->vstart, + vext_continuous_ldst_tlb(env, ldst_tlb, vd, evl, addr, env->vstart, ra, esz, is_load); } else { /* load bytes from guest memory */ From patchwork Sun Jan 19 01:11:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944327 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ECE90C02188 for ; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.12.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:12:43 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Craig Blackmore , Helene CHELIN , Paolo Savini , Daniel Henrique Barboza , Richard Henderson , Alistair Francis Subject: [PULL v2 02/50] target/riscv: rvv: speed up small unit-stride loads and stores Date: Sun, 19 Jan 2025 11:11:37 +1000 Message-ID: <20250119011225.11452-3-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Craig Blackmore Calling `vext_continuous_ldst_tlb` for load/stores up to 6 bytes significantly improves performance. Co-authored-by: Helene CHELIN Co-authored-by: Paolo Savini Co-authored-by: Craig Blackmore Signed-off-by: Helene CHELIN Signed-off-by: Paolo Savini Signed-off-by: Craig Blackmore Reviewed-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson Message-ID: <20241218142353.1027938-3-craig.blackmore@embecosm.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 0f57e48cc5..ead3ec5194 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -393,6 +393,22 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, return; } +#if defined(CONFIG_USER_ONLY) + /* + * For data sizes <= 6 bytes we get better performance by simply calling + * vext_continuous_ldst_tlb + */ + if (nf == 1 && (evl << log2_esz) <= 6) { + addr = base + (env->vstart << log2_esz); + vext_continuous_ldst_tlb(env, ldst_tlb, vd, evl, addr, env->vstart, ra, + esz, is_load); + + env->vstart = 0; + vext_set_tail_elems_1s(evl, vd, desc, nf, esz, max_elems); + return; + } +#endif + /* Calculate the page range of first page */ addr = base + ((env->vstart * nf) << log2_esz); page_split = -(addr | TARGET_PAGE_MASK); From patchwork Sun Jan 19 01:11:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944284 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E407C02185 for ; Sun, 19 Jan 2025 01:13:51 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJrv-000135-Hs; Sat, 18 Jan 2025 20:12:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJrt-00012Z-NG for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:12:49 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJrs-00038m-9Y for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:12:49 -0500 Received: by mail-pj1-x102c.google.com with SMTP id 98e67ed59e1d1-2ee76befe58so5795436a91.2 for ; Sat, 18 Jan 2025 17:12:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249166; x=1737853966; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MPHsueaOT0a7n8Avkp+AlyLkA7DW96RFcdAuFjHGVlc=; b=kNAc8yJS0oYGpqD5NxJ0CWar7Q4UD4BzFmmcKjkyTtUCsSzqU3bZqBtb5vFZx6mV1o /wgX4l7PEA+VSxEwymYe0PjROABEWj4INJku2pB+roxmAOohPuTf0IGhOi0x3C7PFhE3 1MKs3F6Dob2a1b+hv6RhSKYgUhGXArA5hMIPOkmnt9VGkdSH0E1VSS9MYxzpjdS7hKa7 JMlKHkkr+LxYqCKLdaxzsUs1Nh38odsE6p0k+FbI9rW1tEn2pgQ5U7bDkr1ehb/7sp51 FO4SRuQTBhVQhoqqNmB4VQHCuufu1HCL/yr1PpPFDqQEcqucbHOx4EQOZw9vwAOvkW6r CCTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249166; x=1737853966; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MPHsueaOT0a7n8Avkp+AlyLkA7DW96RFcdAuFjHGVlc=; b=lNXqLBjfh7ivxFc3GvKzhzpzyTX5HlAlvJ0p0uupyySaVjzXbjnZMBvacKuaP+U49P SOTMeXNeLPKsISTCfMyWK4Qd66essrQLIJeft1D8oMSZhD179B9w/8Hg2Nya+YVZ3n/s lFel//OqIlnFlBqzmZYAx9016lyYbhHADhaUMvQYBYletjzW2JnGX5hXRLOhZQ7Elq3f Jcc2ykCnoGrLCZNq6etyomrPvLs38HiGloNk3PF3qIlvqojJpYjKp6ZFLFX3S9cvpCKa WrKpSgpUYzcw6M7844FCV/vX3xUwakHg14yAgxVX77Cpdy+WaEvbgpFb/awgBxFoWaeh AGcw== X-Gm-Message-State: AOJu0YxpWjVIyTR+7C9xlxJgmRelim2okvKtjYSJhwLvgR0h6hb2eXfT F9WdQTPSIsm0h1EuODNiI2Tr6qc6LKWde1fduQ1lIW3G6+7HjPduqzrz8QBn X-Gm-Gg: ASbGncsaHz8QBfEfLzX/PiTak7djdouZ32dLBC+gaLyGWwgmk3haEERw2CRbFkmEEut vKypCTIB2cmdk2DJAT+LrqaPXxn+q29nssDS8VS/JIKLhHZiCdG40zptvbPyb6HSmg/VMatSJ5o V8ltE+ReGhRMpYQXYI6rmDJhrDJyy6W7rM5AJ39jdTeKMVZRW1iF60HmNhUJzys6TLKSEHdw2lD wldRZgsGI2/opluCP7R0ewQc4DeTZ6wjwIYAXj5x2U/pBcohLBv+szmtUHm8WxL5IOcveUyjvTQ uxaJEDPV+SuHWar7qrFcknfA/iZCPtN1Oz3e82vdnlkD/7vzavc/Pq+peOHveucPkFaoFqhf3A= = X-Google-Smtp-Source: AGHT+IHBP/Xc75bkcu5rtG2Nt8FrC2E4ClVMbluMI2t+G4INTe4U2n9sscaCgT/zXuWGt5eoYoRd3w== X-Received: by 2002:a17:90b:2c83:b0:2ee:c918:cd42 with SMTP id 98e67ed59e1d1-2f782d4eea7mr10295572a91.22.1737249166639; Sat, 18 Jan 2025 17:12:46 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.12.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:12:46 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Yanfeng Liu , Alistair Francis Subject: [PULL v2 03/50] riscv/gdbstub: add V bit to priv reg Date: Sun, 19 Jan 2025 11:11:38 +1000 Message-ID: <20250119011225.11452-4-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Yanfeng Liu This adds virtualization mode (V bit) as bit(2) of register `priv` per RiscV debug spec v1.0.0-rc4. Checked with gdb-multiarch v12.1. Note that GDB may display `INVALID` tag for `priv` reg when V bit is set, this doesn't affect actual access to the bit though. Signed-off-by: Yanfeng Liu Reviewed-by: Alistair Francis Message-ID: Signed-off-by: Alistair Francis --- target/riscv/gdbstub.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index c07df972f1..18e88f416a 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -213,7 +213,10 @@ static int riscv_gdb_get_virtual(CPUState *cs, GByteArray *buf, int n) RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; - return gdb_get_regl(buf, env->priv); + /* Per RiscV debug spec v1.0.0 rc4 */ + target_ulong vbit = (env->virt_enabled) ? BIT(2) : 0; + + return gdb_get_regl(buf, env->priv | vbit); #endif } return 0; @@ -226,10 +229,22 @@ static int riscv_gdb_set_virtual(CPUState *cs, uint8_t *mem_buf, int n) RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; - env->priv = ldtul_p(mem_buf) & 0x3; - if (env->priv == PRV_RESERVED) { - env->priv = PRV_S; + target_ulong new_priv = ldtul_p(mem_buf) & 0x3; + bool new_virt = 0; + + if (new_priv == PRV_RESERVED) { + new_priv = PRV_S; + } + + if (new_priv != PRV_M) { + new_virt = (ldtul_p(mem_buf) & BIT(2)) >> 2; } + + if (riscv_has_ext(env, RVH) && new_virt != env->virt_enabled) { + riscv_cpu_swap_hypervisor_regs(env); + } + + riscv_cpu_set_mode(env, new_priv, new_virt); #endif return sizeof(target_ulong); } From patchwork Sun Jan 19 01:11:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944285 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9ED37C02185 for ; Sun, 19 Jan 2025 01:14:08 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJs0-00013T-4A; Sat, 18 Jan 2025 20:12:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJry-00013A-IE for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:12:54 -0500 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJrx-000399-24 for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:12:54 -0500 Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-2ee76befe58so5795517a91.2 for ; Sat, 18 Jan 2025 17:12:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249170; x=1737853970; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zWsQs1jxZ/+3ne+7ik2niz81I2v6BydOgtfx06Z55s4=; b=S5zf+Ncnhr+STOWt//OL9LaXPRT7wB2iceFVoX2mR2VpPahvl3/WyH/RJEciD3EhH+ fTNZFnfo5lQvbB9MyW3/8qmJ2r8Gz1a+EoU9paHJ2wS0IfyHzpiWE7Nnl3KHGk7yQjgq mEUyzRthd9WGlztvEtRpp3DkMcihvN5whI+1LIAZf9hRADFzvnZIxMAQMS3awXo9WFln aytrmKRUockEi0RZDfJuH+UbbultpLBFi3ubpgFVAZI4MZkuOqMdsGhIloW0PlNkncve b46dXTfWEpn6FzTaxSR23LbVXAz/ep/oEYDmV8aNh1lfaV5Ij67ICbjy3nmIgHZGxEea Cf7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249170; x=1737853970; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zWsQs1jxZ/+3ne+7ik2niz81I2v6BydOgtfx06Z55s4=; b=gY7dmEcTEv7OA2zCG91yqmN6BRvqnUFxsGMSmy0dMQIG1KTJ+a0/2R/P2Tvje1ZfDX A3+CZJyDAAC+ucMMdNtEAdOYNwhpfSegrOGB2tkpdMoBvYRUyK9+XSOvMaFX+i5YRYqI ezsN3bHTf+j6v3/LoUR3ZYsfKvAzm/uOTFQ7AL0ZqZQsWwFiwBU+2e4GwjXpOVt/ARJM JkLHIyVN1ehQDDVf7EvW8dSWj0YDmiqH+uS8mblQ5CltfXqNhYmrw15eWVZyvc5FNTzZ PFVg25A6V8YVcZkbx0JUWe8urkmx9fi7b67YmS0ZdWT2PShBVQl74guTmsagu+qTMSvh 0Yog== X-Gm-Message-State: AOJu0YwnTtnWZ1eyivhXuzvo5NgR/icM10CLHJlU5unkfLGh4Ww0hrRD 6IrFov36t4n4Q16Z0tHgiGz7t1jTMV+iUY2mjkFoiVbNjRR8n3Rdma36QgNQ X-Gm-Gg: ASbGncvVn418Z+gl1G1y6hbGJaUnrolUlADfAy+rlcMArkE9siymuTV9V6mKt8GZG5D hVqwdORk1urR2649FX8iwRX4bTOXG/Co4ivA4gwPVBEXQAqeElHwEHXkcutlRNlQtS5BKlkQ2o2 90wPTRk8aVpshn7AyXKinfXs6McNU2sL/dxOpOYgvSFrIW31OWobySiibMExBth6bimIt3uqppp kXDZ20OnE9eqH1nb0JaXFZ3nbwL2rLVQDLnuE+btaTrG27bVaxXXT7hanqznJ0yuSztpHDWTjhD DYCDCJDOB5PSfKxEkB6b4BeRBHBDdZYqnw1It+jc5ANiCIaiV2Eqm1bdj5w3QHoiwqiC6EvrLg= = X-Google-Smtp-Source: AGHT+IGmFg+Wea3FMJhJBOEdDeIt3fj5wyxF7ham6EEaJ3wsH6tFIe6CaC34pCrT/xjiJTr/gqAZVA== X-Received: by 2002:a17:90b:2c83:b0:2ee:c918:cd42 with SMTP id 98e67ed59e1d1-2f782d4eea7mr10295762a91.22.1737249170230; Sat, 18 Jan 2025 17:12:50 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.12.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:12:49 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 04/50] target/riscv: add shcounterenw Date: Sun, 19 Jan 2025 11:11:39 +1000 Message-ID: <20250119011225.11452-5-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1032.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Daniel Henrique Barboza shcounterenw is defined in RVA22 as: "For any hpmcounter that is not read-only zero, the corresponding bit in hcounteren must be writable." This is always true in TCG so let's claim support for it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20241218114026.1652352-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + tests/data/acpi/riscv64/virt/RHCT | Bin 332 -> 346 bytes 2 files changed, 1 insertion(+) diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT index 4f231735ab..460808d017 100644 Binary files a/tests/data/acpi/riscv64/virt/RHCT and b/tests/data/acpi/riscv64/virt/RHCT differ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b8d5120106..07bcf96e86 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -183,6 +183,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), + ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), From patchwork Sun Jan 19 01:11:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944281 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1ADF3C02187 for ; Sun, 19 Jan 2025 01:13:20 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJs1-000148-Ue; Sat, 18 Jan 2025 20:12:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJs0-00013i-Dk for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:12:56 -0500 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJry-00039O-WC for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:12:56 -0500 Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-2ee9a780de4so4365575a91.3 for ; Sat, 18 Jan 2025 17:12:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249173; x=1737853973; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wwddsRds/Fqnl1W3d1XlTTvUOcsVbxRQegi+2IouezM=; b=BqDyMe1OSHCVnPYSPukE8r9i7hPD6NWjtEy3/Q3E3EQsXinc63ttSVTjL8qo35GFP0 IPEFz0vUFGycI7puAssVh+ANSU+Lr1ytIygiEh7QPatS5bhtxZgEJ8FNRdR4v8wYNrI0 qVl+iVbiGGRJjdvAboiZ6WChN2mpoZb+BDKHM4exk0r0GETv3RT2WkHRWf/erCQ4Qpss lmfvaDQ9dQQlvQ4YER8CqYmm4mQIANzcLI+dmbTfqKfIFzYWPQWn0fC3BKJ61kagGThM rrENiA2NpF2ODBpo3pUQETMHi/hrwCUQsYtL0CeOKh7LPsZzl0bPi9zP7NDHRZQxb7V6 Ec+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249173; x=1737853973; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wwddsRds/Fqnl1W3d1XlTTvUOcsVbxRQegi+2IouezM=; b=v097Z4RQBzUEamuL9ADgdDlBmpkYr6wZR5qjfSnTrPkS4IUmKJQDG+vcEZ/tvcRGxR YQc1pa30kRtGBgpH6AoQo6a6E9EiRXqn6qKw/Zqd3FdsxpVRmR9Ia4Alxb1xhigQIZvK 1A4NN2YL/nybNPYm+I0RJzXSrh0c9euT1I4HQ32LtI6Js+RBNAtnCjzzZPgnyOcbXh3K eNKjHJR92ph8sOGADTe5OMxKfuffF5aRPKS/IIDp/arQJwMoSQ4idcEbHY53g02cvLss 6uozJO8rMrJzZk0sEkHBg6A1AqYRaYxfXsNPXnJmdD+nYJEC2E6DdhA8vV9MaK5b1tK7 5SdQ== X-Gm-Message-State: AOJu0YysxTdYrh43I5dkU5thmfHKtx+buR+8hP6iAGb3cI7jhU7zMiZs KAVi2VYY0TLg5z1H3KBS69JC7N/HTU9MQsA32cvxwpgJU3A1Oqhb+p60tV8h X-Gm-Gg: ASbGncsH8vyvIia0dbDSvK0qn+5AP4mLlfL28TBB3ver2WZNnq4K+amGkOsJ7zYVBrL COk1PmbfgRt05XcRsAXxhLnlZ/pcmzRBjl6yseibx8eR7D14dNQu84gRhmh3aVIVWPdaO6JasZx tO9pUHjTyKsj0dcZQm1mJ4O3zfjmYc4exIk5tRaUcWsvDQqmFCUXspryOfFDFRM2ySuySudjQgR y13zkinBgCb89xA4eREqo6dXiqyg2j9AoqA/Mz8LEIgW9ZEA38eY0YKofHaGiEsS/FT51s+QO/0 JvfuzrkEzse38MekLOUk+IZrX+zc+yvO+16Xsllx6V5aAwy9Unlnw3mbHwqLsIkEvWHk1afRxg= = X-Google-Smtp-Source: AGHT+IFZkRQt34X8JpQ/omMiDPL0vJrrFyyTmXBpj0RmQxaaRSAFW8KSTM4EBPaNv63roPa+CXObvw== X-Received: by 2002:a17:90b:2748:b0:2ea:59e3:2d2e with SMTP id 98e67ed59e1d1-2f782c73b7fmr12336408a91.10.1737249173344; Sat, 18 Jan 2025 17:12:53 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.12.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:12:52 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 05/50] target/riscv: add shvstvala Date: Sun, 19 Jan 2025 11:11:40 +1000 Message-ID: <20250119011225.11452-6-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1032.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Daniel Henrique Barboza shvstvala is defined in RVA22 as: "vstval must be written in all cases described above for stval." By "cases describe above" the doc refer to the description of sstvala: "stval must be written with the faulting virtual address for load, store, and instruction page-fault, access-fault, and misaligned exceptions, and for breakpoint exceptions other than those caused by execution of the EBREAK or C.EBREAK instructions. For virtual-instruction and illegal-instruction exceptions, stval must be written with the faulting instruction." We already have sstvala, and our vstval follows the same rules as stval, so we can claim to support shvstvala too. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20241218114026.1652352-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + tests/data/acpi/riscv64/virt/RHCT | Bin 346 -> 356 bytes 2 files changed, 1 insertion(+) diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT index 460808d017..15b82b5bb1 100644 Binary files a/tests/data/acpi/riscv64/virt/RHCT and b/tests/data/acpi/riscv64/virt/RHCT differ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 07bcf96e86..4f76efc298 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -184,6 +184,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), + ISA_EXT_DATA_ENTRY(shvstvala, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), From patchwork Sun Jan 19 01:11:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 04E3AC02185 for ; Sun, 19 Jan 2025 01:15:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJs5-00014e-Br; Sat, 18 Jan 2025 20:13:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJs4-00014H-Cr for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:13:00 -0500 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJs2-00039z-TC for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:13:00 -0500 Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-2f13acbe29bso7008492a91.1 for ; Sat, 18 Jan 2025 17:12:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249177; x=1737853977; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0oe4ixlLoNm05J1Uam0Ub0O9tzxvxA5rEYMLk9bmud0=; b=NuBf2hVtJjPSx3XfCw+ah/ZchbRws236ptS5F4d9gKndHKPTN7xsXvbWIcgAeVkxvT D5tQ38UQJCE09eCngLgCw4+HnUx8KYHpzs5mjgtIR8L+xI4i5TqKgSAaQReI1d7WJQMQ q6odp9QMhPGU2G74p451lMATX9Al9Hh200yHIKlQIxwsqr2FBvHkDqTWF32K9A9UU5Zy DLmw6m4pevTlo6Rcqf3TcT7swpWBArZmqR1K7ZiiSVipyAn1ciTV58ccAp5wAucHNpqR zmKWRQJ2yzV6apgKHTXvVw6S6cDRS+UsaQA0SrqJt0vw0uBxaLWqoj00QNqZPXW5Rh4E fGnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249177; x=1737853977; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0oe4ixlLoNm05J1Uam0Ub0O9tzxvxA5rEYMLk9bmud0=; b=YG4ee6/pok+6HvOxBpsx3On7uhr4XrO48C2Nu2iVJT8q2TnrqQyjOc+k63LB9qFVSE 9sYes0ZLjUaeiUODW+3ctO4v+Nnv+uZR7hcxbGhfB+PbpV37vLri7aeAm9DFPLMKMY7B DEUvlwVfsMKOLclPYPKgo6hjTZHqa7LSS+UtDradKR2ais5Z4FIZf7HY6vE1+3lQYO98 FFvOeoh178c3eiWclSF7YhoNBg+wF8GkqFd7g0WZRfCpwsF42n5EBPmqKYGVc2rgr138 aLD6VuexdTi9rjgcG4ffvvrJRCNsaYv8Ar99Z+I6q+tmS8F4BisM3g4qOAN7b1GgCRiZ PD0A== X-Gm-Message-State: AOJu0YxpoSXdA/1iI6POoane1Y9mVRMuEcsbd8+b7OJ9DfiKOye7tGvM ppzSZICDu/a5EkO1AMKpF/imt5hUoBNwHPTkdjZdsui/x8B/QkysRA9cb/al X-Gm-Gg: ASbGncuX8c2ouv8Ee5TQiJMGaXSVaQ9NiL1EJ6Ty3HFnVwxVpgp5nXahKMCLfao7kxB GYqmS+AWQUT9HgwBXay3+qshAR+Wlrh/wGdScSiMYQQbzSi0vyv12KVEIe7s0tYuXBY145zv/Ig t9TxPWhCpmHMcfAvI6SPk2tLWj8xGwQFeOC/OwDKEgZQVg6tHy1iCrexTouWXRURBf2/2/HgCEi mChLFLBzJ9+Elea3rbECgXabCS1OSmYcGSkzM9o5fPoxlwJV/qFOPm4KG7NOnk0ytBPdRtxMjfk XJJrMRnU/yAtn4rW/Cum3D6osdTyHghgev2BCsd15GpYgg0JEuRF//owHrb/suEqx6XGeXAc6g= = X-Google-Smtp-Source: AGHT+IG+Q7ETey3DHcFK/zDzagfdQYLljMhBG2tERwRVAfdQUk+3Quc5wqofahtbJqs8njjHW5A69w== X-Received: by 2002:a17:90b:3902:b0:2ee:5106:f565 with SMTP id 98e67ed59e1d1-2f728e6838fmr24369046a91.16.1737249177189; Sat, 18 Jan 2025 17:12:57 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.12.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:12:56 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 06/50] target/riscv: add shtvala Date: Sun, 19 Jan 2025 11:11:41 +1000 Message-ID: <20250119011225.11452-7-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1032.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Daniel Henrique Barboza shtvala is described in RVA22 as: "htval must be written with the faulting guest physical address in all circumstances permitted by the ISA." This is the case since commit 3067553993, so claim support for shtvala. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20241218114026.1652352-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + tests/data/acpi/riscv64/virt/RHCT | Bin 356 -> 364 bytes 2 files changed, 1 insertion(+) diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT index 15b82b5bb1..065f894010 100644 Binary files a/tests/data/acpi/riscv64/virt/RHCT and b/tests/data/acpi/riscv64/virt/RHCT differ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4f76efc298..fe5f7b572f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -184,6 +184,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), + ISA_EXT_DATA_ENTRY(shtvala, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(shvstvala, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), From patchwork Sun Jan 19 01:11:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944283 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DFF12C02187 for ; Sun, 19 Jan 2025 01:13:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJs9-00015J-MR; Sat, 18 Jan 2025 20:13:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJs8-00014q-3o for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:13:04 -0500 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJs6-0003AJ-IR for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:13:03 -0500 Received: by mail-pj1-x102a.google.com with SMTP id 98e67ed59e1d1-2ee8aa26415so5809535a91.1 for ; Sat, 18 Jan 2025 17:13:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249181; x=1737853981; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6HWWsLugXEr9up/g4/JxXJKxCn4PeYas5O5GPDoslqE=; b=kfcmbw36Eeu9o85ET1Hw3LyDLBhX9Cp+aZdumoED40vgJRRNQAL0JQRtgOzVz0fuLE JayVAC2p+qYoKt3fqV/VFYk0jlLrqdLDzDPUTWrkFykxB9LIoNLlmfxCiiFw9dA5igZ7 CFQstsXU8fDPoutsETSsYZFAwchXc9BarYSuBOzQ/1bJq/k7bPiSyXQgLbLvY3zrnRcp /71SnT4TKsAZ1cmrtxFZX8p0q23mJ+9PrnMNTjwpeBFJbYjC+8R+OVg0l6wE9QNutedL RE0S7PwGm3rRL/Jjh3FILf7f2LWK7vS4uuzADUcALQXuy4KYJy3E7siK/7ruuc+2/vua LRuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249181; x=1737853981; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6HWWsLugXEr9up/g4/JxXJKxCn4PeYas5O5GPDoslqE=; b=wNTb13hb8aufTh69pLcAirk5wCbCGEPfmT44cPj5+6znzaj9I4ZdHWLjmFq83v2d8C U4veZ/dxcmzYan2vGm7Yyw/6aEZckWCz/F/Cx/LlfV3XlXA6SBeiU0x0G2DFdyLxilUk k/+uyDMUKe2reyIzIaSYlB18v5J/Lo19Cu6EJLM1mczTq16RFJdgAD/3vBdhbcO67i+N W4G02Z1VdkB5K3sWtkIrAdEW3SQl5r1+kSK2+DB9FyQmmUhWT/CdEnnPavZirI3wZkmz cybuS8Al9z+l91XpVzxYOKTKaCWMfDpIZSmwcDe/jBm0ik8/JlmH+6i2wtilxeLvfApg xieg== X-Gm-Message-State: AOJu0YwJbsvQk64Z7g355iVi6zBwiolVMfVkTHZDkvK5U5AVsyHSqWnI e4EASZKfv4aev57BTPvZglqdMh0mDyHa1KcHmnFvNo5U/lrgIkxCsPO8GFry X-Gm-Gg: ASbGncuy+efV2U5AdOqM28BWjn4SPH+OJxbJM4tCjUXyOO7VunIM/9vknB6aApx0qlp rB237S7udA4YdoIMvXEJFzFeec9d4cMJfdncpbyIP9MituJ5S3wQexL267K3GD7hC4tQ8gIsMDt aoiQ5L3ehzLntfflLWYgKWodnOc76FrpHqdB+cC93qkCKGQspL8NxCyREjA8OpPNMIRzsS1y1wR qHEeYVaAPWs2y20Frk9TsUpiDidHG7ohAjcGBDAJ9QO5tRVeXT4AIus21DaA2w+1UvaBeM2mzOg 48V9L0eP/rzKIHtKqltQv3o0p27Wo0PKo0phKl2V42ZWm8PAK5y9Y4UWwKKaeAGWqJwuzb2Qug= = X-Google-Smtp-Source: AGHT+IE4iImaV41IMPTC64WaEg9Ifi9JRKwJ4AfIvYYtGH7XcgEIgovlesJYGVgrd2/h/R00vYz5ow== X-Received: by 2002:a17:90b:2c83:b0:2ee:c918:cd42 with SMTP id 98e67ed59e1d1-2f782d4eea7mr10296300a91.22.1737249180863; Sat, 18 Jan 2025 17:13:00 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.12.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:13:00 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 07/50] target/riscv: add shvstvecd Date: Sun, 19 Jan 2025 11:11:42 +1000 Message-ID: <20250119011225.11452-8-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Daniel Henrique Barboza shvstvecd is defined in RVA22 as: "vstvec.MODE must be capable of holding the value 0 (Direct). When vstvec.MODE=Direct, vstvec.BASE must be capable of holding any valid four-byte-aligned address." This is always true for TCG so let's claim support for it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20241218114026.1652352-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + tests/data/acpi/riscv64/virt/RHCT | Bin 364 -> 374 bytes 2 files changed, 1 insertion(+) diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT index 065f894010..2c7dc6c9ab 100644 Binary files a/tests/data/acpi/riscv64/virt/RHCT and b/tests/data/acpi/riscv64/virt/RHCT differ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fe5f7b572f..20cbb6b2f4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -186,6 +186,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(shtvala, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(shvstvala, PRIV_VERSION_1_12_0, has_priv_1_12), + ISA_EXT_DATA_ENTRY(shvstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), From patchwork Sun Jan 19 01:11:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 86AFFC02185 for ; Sun, 19 Jan 2025 01:14:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJsD-0001Ag-1C; Sat, 18 Jan 2025 20:13:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJsB-00017m-8C for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:13:07 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJs9-0003Aj-PN for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:13:06 -0500 Received: by mail-pj1-x102c.google.com with SMTP id 98e67ed59e1d1-2ef760a1001so5877643a91.0 for ; Sat, 18 Jan 2025 17:13:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249184; x=1737853984; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8DOhQ+RXBVevo1zbAu7m7gJRKhDeUWa02zeKmgIvRqw=; b=bo6cmvci3CnaxMiCmXjcV4VEgVi4XKqCH02tstfNZXZT3zey/gDEuayVBZuR+0AZzk OcrCeG2R+InOKucne1d1VTn4CNyrfp/NV44dS6r2/jlzMuPzRxkqME0QdfiJok5si46u 1eO7qP0w4uI4ggicyeu8tOoZDSg8Nu53rQ6UdajOcNVzaRb9vhB07di5QJy2QoYTZxkA SHEZstQ9KwBEcM+ZWu2JMZ6EeYPdf7NxlOSohsXvCDiqXhdMLzURx052PbRrzJqFrh8M FF5Av5kfPqA69bKtXLSDqsH4glJGaZpiBYPXkXjWsy7OIrXrcjYtQ5X230do1ejL35sx jthw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249184; x=1737853984; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8DOhQ+RXBVevo1zbAu7m7gJRKhDeUWa02zeKmgIvRqw=; b=oOuheACqvcpZfqf1r/B2CuIBP2oS9n1gvoMM9Q3x/8RPXdGXGNh3oyiMgCbzZN2/l9 8cUIogNrDwd2RQEdHFS1AbIISQdkeaWh4L+Bzficnhnjfn58Tc2uznN6p+XZRwqplYf7 ttwmF2ImC52d6TkQ1Z65L6SacNc83Bbu8H0ytAWR9SKcE6nfBkAKgYsaXeqThktI9z18 zU4dO1e3ECV+trulFgck9Mx4oCqc2LxcwSzI70Hj5ak/srC53lv7sgD4ECE29pcjdRrr pKod/gwe7a8Az8j5oUNpcMmAk/uvm2p8+fZinNvMWcJCmGHY437IbLGagOTRaxujr4nN iWDw== X-Gm-Message-State: AOJu0YwQ6poSHFYW6DpX8KfR4F0MDd0BnrwSyCOZtG6eUSpNI6+YheMS I3g8H9m6gjqkA6P+eYVm5GuxhHU4V49I8Cy1xwclx9RVxs8rW6DrgiLJjB7f X-Gm-Gg: ASbGncsLSYYp2ehy2Y1ULXZb432/1215OoItYzOWPPmBo5/lYm+KKzrOWbDDzpIBmZu S3AXimk1B+bJCm2GfaQJb5/4D+Bksm+z+6sRZr27w4T4m2yQTw9Arqc7oIgdX76GINTsYJ7es8g uJ/0Xz7xQAlUpJzTPNH9EuZ2tN5aCrGcBgZ8+RrxOPcFStp8CBbmnPg8oLJJdapNqUIhIK5GNTd 9jPIab45Nm5EtBk8Xgdn21OxrQrnh3wfpzFBZBWVPor18070f2Ev4NywxqmdqUVS8GWaIPddXaa mJN78+lRyDPap3pF+MlKSGYYo6R60S7RGYJWygFn5MqHveQCa9udsknk71KLtwuIazTfbxyeHQ= = X-Google-Smtp-Source: AGHT+IGuuT+yyZhp4Nv6LSb8zXuUepsck96krlomKMIUv5JWG1CuvEkCAMHIdPl86b5/kMswyaCdGw== X-Received: by 2002:a17:90b:1f8f:b0:2ea:bf1c:1e3a with SMTP id 98e67ed59e1d1-2f782c71e64mr13880188a91.12.1737249184173; Sat, 18 Jan 2025 17:13:04 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.13.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:13:03 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 08/50] target/riscv: add shvsatpa Date: Sun, 19 Jan 2025 11:11:43 +1000 Message-ID: <20250119011225.11452-9-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Daniel Henrique Barboza shvsatpa is defined in RVA22 as: "All translation modes supported in satp must be supported in vsatp." This is always true in TCG so let's claim support for it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20241218114026.1652352-8-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + tests/data/acpi/riscv64/virt/RHCT | Bin 374 -> 382 bytes 2 files changed, 1 insertion(+) diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT index 2c7dc6c9ab..fcd9c95a6a 100644 Binary files a/tests/data/acpi/riscv64/virt/RHCT and b/tests/data/acpi/riscv64/virt/RHCT differ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 20cbb6b2f4..2f58eeb689 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -185,6 +185,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(shtvala, PRIV_VERSION_1_12_0, has_priv_1_12), + ISA_EXT_DATA_ENTRY(shvsatpa, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(shvstvala, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(shvstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), From patchwork Sun Jan 19 01:11:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944313 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1C4C1C02187 for ; Sun, 19 Jan 2025 01:17:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJsQ-0001Eg-I1; Sat, 18 Jan 2025 20:13:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJsF-0001C5-Fg for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:13:11 -0500 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJsD-0003BB-T3 for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:13:11 -0500 Received: by mail-pj1-x102a.google.com with SMTP id 98e67ed59e1d1-2eed82ca5b4so5844090a91.2 for ; Sat, 18 Jan 2025 17:13:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249188; x=1737853988; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dxNb4rdhTbxXkgYxdIx2H3V9pCkfROl+Bmd9x0HWUXM=; b=ASGAV+RTqh+puf+3iArux3iNtiyPUpM6anvCo0iSXf2uiRPgZ53cTA65Z0LIlu+kYF EBsLiBdXGWC7XCeRiXBIkSSay9maIsyX4WnOkVly/2s0mcovHKP5JiGI72Q1F2cm+yp5 iJk9JBz8Jyf9YV7rarpbo2pspyemWWEoTYCoHgAE2TUL4/p/H9q3zReJlj0HaivjRpHs 72SCgLG7ORkFwA5hxSr05pvWTccjq0+azqSEk0ol6hBa0/01X5hWZ+tlL7e9l57iBlEU m7b1KJPDteq3efYrqGuTO0/DZLdt9SlF+y1BeEGz0hNe1XLvouSszdPdN5sCM5LNWbCd Zvmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249188; x=1737853988; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dxNb4rdhTbxXkgYxdIx2H3V9pCkfROl+Bmd9x0HWUXM=; b=XqtHBAkyADBvgwba55QrvUOPAnFu8aCLwUI6BUeaog+ZLOVX1SKq2SGVgGJBle3rK6 jrx7YwGipCiL78h69OY9DSMEgaT8w3hg20WRS1cn6apynTsN9x/6OJU5bOEm9BvgycX8 LKTZtJO23gZYBPKJUboGtgmbrOqEFN4EIKtSCR+SK8vFJDSOtoBxR5lAvk8AHK1UqIZn oQaZP2V+VBfMNBqO0LXD+wMef2yKvB7/0TmIKwvBsrqIVzWCimSCUH/KU547fAfKi5pN 3x9raSvar4b5OgOUbGruf0bFxEUnpOpMiuc4aZZtoKWacACmCOHTPMV5aX2olrTQ4RtX GdHw== X-Gm-Message-State: AOJu0YwI38rW9qNNGv+l72yWkK2BVt8Hs4r1aSLcvmXWSfah5ZJJHXcx s9Tc0M9S4yviRYvoKjgJGx74z4aCn2ssd4BH+9RxjWULaLseZeyFriMab+tN X-Gm-Gg: ASbGnctlX5raVA9TcEWfQjP2Jnz78Cmkoo4SQrnY8MVReM7fpCreyp7k5WdyYFgggGg ad6nKXfcRHXQqyo6ygYIUkQvuLL6jRcW7NEViaKlrBn2O9JZw//vh4Cni8QSrY4J9XximnMexdb +uMarQ8Ds6uXLQkh+Yj/0L4nUM5k7avNNcfC4FKyuBNJc366qO2hROAtFuEZ4nP8QRU+pxscezF 8t7tJijeCVxDcZ0AEhNLkBPS07ub7+XxiIup1NSbwRBjQys7O9HD75iV53++PNCV6uiifNTj6X6 5uczApGu5QOd8c/V7xWdi7I9jljROOLQf/xvWIEudSv9KOkGVty3MXk4CAhfsEG3bBFVpF0eqA= = X-Google-Smtp-Source: AGHT+IE50j2EzlpfEnQu79zzpAAAlFq7+ahwCqY1/HlO9TtgR3HSn9+bccRovNB2Un0ekoLNY63Fww== X-Received: by 2002:a17:90b:2dc2:b0:2ee:6db1:21d3 with SMTP id 98e67ed59e1d1-2f782d323a6mr11378444a91.25.1737249188429; Sat, 18 Jan 2025 17:13:08 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.13.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:13:07 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 09/50] target/riscv: add shgatpa Date: Sun, 19 Jan 2025 11:11:44 +1000 Message-ID: <20250119011225.11452-10-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Daniel Henrique Barboza shgatpa is defined in RVA22 as: "For each supported virtual memory scheme SvNN supported in satp, the corresponding hgatp SvNNx4 mode must be supported. The hgatp mode Bare must also be supported." Claim support for shgatpa since this is always true for TCG. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20241218114026.1652352-9-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + tests/data/acpi/riscv64/virt/RHCT | Bin 382 -> 390 bytes 2 files changed, 1 insertion(+) diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT index fcd9c95a6a..695022d56c 100644 Binary files a/tests/data/acpi/riscv64/virt/RHCT and b/tests/data/acpi/riscv64/virt/RHCT differ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2f58eeb689..3e138572d4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -184,6 +184,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), + ISA_EXT_DATA_ENTRY(shgatpa, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(shtvala, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(shvsatpa, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(shvstvala, PRIV_VERSION_1_12_0, has_priv_1_12), From patchwork Sun Jan 19 01:11:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944308 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3C740C02187 for ; Sun, 19 Jan 2025 01:17:22 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJsU-0001Pv-QL; Sat, 18 Jan 2025 20:13:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJsO-0001EN-Bi for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:13:20 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJsL-0003BX-3U for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:13:20 -0500 Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-2ee86a1a92dso4713893a91.1 for ; Sat, 18 Jan 2025 17:13:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249191; x=1737853991; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v87WTdDQC8DDzGlvKqDnGwAE9sgIictuWkNEBi5lUJ4=; b=Ib26ORRAFkVXqBfjCsO59i5DBiX699lsoJId6+vWeUFZ2w0juOqMCwwcDs/NEs9dPj yj1fkHMZ48cKNsQfsaYpYbDRse4oHaCEW5zL6Xjn8skooy4D/YXfw/2Uk2L35Gqm7yIk tZRuKab9/jtvIuhXwyKvAwunrrPMt1JXbT/RPLodSL6jvHrVZN2/uHubiWH/JFoS4nxv b4l1uWNVPWqr3IPfuGZRnKFsPvBeIE44HtgAGcptS5bOkbFD8P/eKvfMc7Ac3Nrx6HyF Kzd/2xxUrxjJSkI2mSvTjl1OKkmixYdNiUz5HZGtZ7YgKrHHf8E6X1qaihA09lvOfpu4 BSPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249191; x=1737853991; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v87WTdDQC8DDzGlvKqDnGwAE9sgIictuWkNEBi5lUJ4=; b=f37BqHx7MZUlfphHI3e1b/A37FIcKoMMRtGyyICKbxYOReNs+ev8MiLbS5/8x6mfgp Kp7DF6zTP69YyliNXnkHaojD/ku8gqTeX4Pcg9i2gtpe6u0n/GHEV0doLkjI28n+mWuq mNQuRtOt+4k2qekh1EH219JeVa+GlhBMsth6MiN88lv7WTIuc3lHNVfZF2EcvpkjLpYP ol5sB2lo+1sKP3t4XjQlZnr0fhWkyyKKAhrJ0R828iMtEBbWHJdZBfBqg3KqM1qzTL7a WSneneqydFOzI0X2HUbl9u7A2e/UZNP3pK77G03YatYBd1Q6bzT42H9wYBtHYa5FA8LB x9JA== X-Gm-Message-State: AOJu0YzZoWV97xaKIHZQEu2Tui11N3c1afWEBa6iMe7Jet9VDM91ij8f wvH8qcMy+U5D8S56LmX/jHNLY2Mw95NQotfhYvg3BcRzjmTRSjUgUVcEbur1 X-Gm-Gg: ASbGncvcNnIvn8/cFvvLWYMSEVjbq6FrTuAXmpjUAYnTARIkmhs0DaIhxpPyiEqceZo CJp60rtUra0gQud2wMIKb7R1JIKavhMUfE2LOtMwgW2T2ofBKO0K+vgj4NRYfDgP7jB/4qV2e7v aVpNbf47xM6Py6ARSbv0uRXGJwSROKtgbX38AQ5ZlZjDDUd7eKks2MraXNDar8IixtOrCkCOXi/ MUIoF+NnieuInFv3EESQ5jDf4fV1+VO6iwkGjns+KpNX5T9D8haRFNi+p9N6bqyQqvz4ZbEs9pQ TmUJdoYWj0+cwojdWi0nax4MPerV0ClYgxgrWSHGT/rJeEiBgt2EnG6Gzvh2KPuhawoFw3VsgQ= = X-Google-Smtp-Source: AGHT+IHyNodN6VQLXrJZ2GQInNzspBuYKOUudc6JI+1WotfXgnfFWCSXTr0K4oV9Stl8gvKcdljfpw== X-Received: by 2002:a17:90b:2e41:b0:2ee:f19b:86e5 with SMTP id 98e67ed59e1d1-2f782c71ec7mr13086094a91.14.1737249191512; Sat, 18 Jan 2025 17:13:11 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.13.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:13:11 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 10/50] target/riscv/tcg: add sha Date: Sun, 19 Jan 2025 11:11:45 +1000 Message-ID: <20250119011225.11452-11-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Daniel Henrique Barboza 'sha' is the augmented hypervisor extension, defined in RVA22 as a set of the following extensions: - RVH - Ssstateen - Shcounterenw (always present) - Shvstvala (always present) - Shtvala (always present) - Shvstvecd (always present) - Shvsatpa (always present) - Shgatpa (always present) We can claim support for 'sha' by checking if we have RVH and ssstateen. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20241218114026.1652352-10-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + target/riscv/cpu.c | 2 ++ target/riscv/tcg/tcg-cpu.c | 8 ++++++++ 3 files changed, 11 insertions(+) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index a1457ab4f4..fe0c4173d2 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -141,6 +141,7 @@ struct RISCVCPUConfig { bool ext_svade; bool ext_zic64b; bool ext_ssstateen; + bool ext_sha; /* * Always 'true' booleans for named features diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3e138572d4..954425081d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -184,6 +184,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), + ISA_EXT_DATA_ENTRY(sha, PRIV_VERSION_1_12_0, ext_sha), ISA_EXT_DATA_ENTRY(shgatpa, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(shtvala, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(shvsatpa, PRIV_VERSION_1_12_0, has_priv_1_12), @@ -1714,6 +1715,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = { MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true), MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true), + MULTI_EXT_CFG_BOOL("sha", ext_sha, true), { }, }; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 8b89c99c0f..e03b409248 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -212,6 +212,11 @@ static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset) cpu->cfg.cbop_blocksize = 64; cpu->cfg.cboz_blocksize = 64; break; + case CPU_CFG_OFFSET(ext_sha): + if (!cpu_misa_ext_is_user_set(RVH)) { + riscv_cpu_write_misa_bit(cpu, RVH, true); + } + /* fallthrough */ case CPU_CFG_OFFSET(ext_ssstateen): cpu->cfg.ext_smstateen = true; break; @@ -352,6 +357,9 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu) cpu->cfg.cboz_blocksize == 64; cpu->cfg.ext_ssstateen = cpu->cfg.ext_smstateen; + + cpu->cfg.ext_sha = riscv_has_ext(&cpu->env, RVH) && + cpu->cfg.ext_ssstateen; } static void riscv_cpu_validate_g(RISCVCPU *cpu) From patchwork Sun Jan 19 01:11:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944301 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 61480C02187 for ; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.13.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:13:14 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= Subject: [PULL v2 11/50] target/riscv: use RISCVException enum in exception helpers Date: Sun, 19 Jan 2025 11:11:46 +1000 Message-ID: <20250119011225.11452-12-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Daniel Henrique Barboza Do a cosmetic change in riscv_raise_exception() to change 'exception' type from uint32_t to RISCVException, making it a bit clear that the arg is directly correlated to the RISCVException enum. As a side effect, change 'excp' type from int to RISCVException in generate_exception() to guarantee that all callers of riscv_raise_exception() will use the enum. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250106173734.412353-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 ++- target/riscv/op_helper.c | 3 ++- target/riscv/translate.c | 2 +- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 252fdb8672..3d9c404254 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -606,7 +606,8 @@ void riscv_translate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc); G_NORETURN void riscv_raise_exception(CPURISCVState *env, - uint32_t exception, uintptr_t pc); + RISCVException exception, + uintptr_t pc); target_ulong riscv_cpu_get_fflags(CPURISCVState *env); void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index eddedacf4b..29c104bc23 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -27,7 +27,8 @@ /* Exceptions processing helpers */ G_NORETURN void riscv_raise_exception(CPURISCVState *env, - uint32_t exception, uintptr_t pc) + RISCVException exception, + uintptr_t pc) { CPUState *cs = env_cpu(env); cs->exception_index = exception; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a992d4f3c6..f46d76c785 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -245,7 +245,7 @@ static void gen_update_pc(DisasContext *ctx, target_long diff) ctx->pc_save = ctx->base.pc_next + diff; } -static void generate_exception(DisasContext *ctx, int excp) +static void generate_exception(DisasContext *ctx, RISCVException excp) { gen_update_pc(ctx, 0); gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp)); From patchwork Sun Jan 19 01:11:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D60CC02187 for ; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.13.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:13:17 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 12/50] target/riscv: add trace in riscv_raise_exception() Date: Sun, 19 Jan 2025 11:11:47 +1000 Message-ID: <20250119011225.11452-13-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Daniel Henrique Barboza When using system mode we can get the CPU traps being taken via the 'riscv_trap' trace or the "-d int" qemu log. User mode does not a way of logging/showing exceptions to users. Add a trace in riscv_raise_exception() to allow qemu-riscv(32/64) users to check all exceptions being thrown. This is particularly useful to help identifying insns that are throwing SIGILLs. As it is today we need to debug their binaries to identify where the illegal insns are: $ ~/work/qemu/build/qemu-riscv64 -cpu rv64 ./foo.out Illegal instruction (core dumped) After this change users can capture the trace and use EPC to pinpoint the insn: $ ~/work/qemu/build/qemu-riscv64 -cpu rv64 -trace riscv_exception ./foo.out riscv_exception 8 (user_ecall) on epc 0x17cd2 riscv_exception 8 (user_ecall) on epc 0x17cda riscv_exception 8 (user_ecall) on epc 0x17622 (...) riscv_exception 2 (illegal_instruction) on epc 0x1053a Illegal instruction (core dumped) Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250106173734.412353-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/op_helper.c | 6 ++++++ target/riscv/trace-events | 3 +++ 2 files changed, 9 insertions(+) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 29c104bc23..29de8eb43d 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" +#include "trace.h" /* Exceptions processing helpers */ G_NORETURN void riscv_raise_exception(CPURISCVState *env, @@ -31,6 +32,11 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env, uintptr_t pc) { CPUState *cs = env_cpu(env); + + trace_riscv_exception(exception, + riscv_cpu_get_trap_name(exception, false), + env->pc); + cs->exception_index = exception; cpu_loop_exit_restore(cs, pc); } diff --git a/target/riscv/trace-events b/target/riscv/trace-events index 49ec4d3b7d..93837f82a1 100644 --- a/target/riscv/trace-events +++ b/target/riscv/trace-events @@ -9,3 +9,6 @@ pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" mseccfg_csr_read(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": read mseccfg, val: 0x%" PRIx64 mseccfg_csr_write(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": write mseccfg, val: 0x%" PRIx64 + +# op_helper.c +riscv_exception(uint32_t exception, const char *desc, uint64_t epc) "%u (%s) on epc 0x%"PRIx64"" From patchwork Sun Jan 19 01:11:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944299 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 85818C02185 for ; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.13.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:13:20 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alexey Baturo , Alistair Francis Subject: [PULL v2 13/50] target/riscv: Remove obsolete pointer masking extension code. Date: Sun, 19 Jan 2025 11:11:48 +1000 Message-ID: <20250119011225.11452-14-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1029.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Alexey Baturo Zjpm extension is finally ratified. And it's much simplier compared to the experimental one. The newer version doesn't allow to specify custom mask or base for pointer masking. Instead it allows only certain options for masking top bits. Signed-off-by: Alexey Baturo Acked-by: Alistair Francis Message-ID: <20250106102346.1100149-2-baturo.alexey@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 33 +--- target/riscv/cpu_bits.h | 87 ---------- target/riscv/cpu.c | 13 +- target/riscv/cpu_helper.c | 52 ------ target/riscv/csr.c | 326 ----------------------------------- target/riscv/machine.c | 17 +- target/riscv/tcg/tcg-cpu.c | 5 +- target/riscv/translate.c | 28 +-- target/riscv/vector_helper.c | 2 +- 9 files changed, 19 insertions(+), 544 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3d9c404254..c78e97af50 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -71,7 +71,6 @@ typedef struct CPUArchState CPURISCVState; #define RVS RV('S') #define RVU RV('U') #define RVH RV('H') -#define RVJ RV('J') #define RVG RV('G') #define RVB RV('B') @@ -451,24 +450,11 @@ struct CPUArchState { /* True if in debugger mode. */ bool debugger; - /* - * CSRs for PointerMasking extension - */ - target_ulong mmte; - target_ulong mpmmask; - target_ulong mpmbase; - target_ulong spmmask; - target_ulong spmbase; - target_ulong upmmask; - target_ulong upmbase; - uint64_t mstateen[SMSTATEEN_MAX_COUNT]; uint64_t hstateen[SMSTATEEN_MAX_COUNT]; uint64_t sstateen[SMSTATEEN_MAX_COUNT]; uint64_t henvcfg; #endif - target_ulong cur_pmmask; - target_ulong cur_pmbase; /* Fields from here on are preserved across CPU reset. */ QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ @@ -628,19 +614,19 @@ FIELD(TB_FLAGS, XL, 16, 2) /* If PointerMasking should be applied */ FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) -FIELD(TB_FLAGS, VTA, 20, 1) -FIELD(TB_FLAGS, VMA, 21, 1) +FIELD(TB_FLAGS, VTA, 18, 1) +FIELD(TB_FLAGS, VMA, 19, 1) /* Native debug itrigger */ -FIELD(TB_FLAGS, ITRIGGER, 22, 1) +FIELD(TB_FLAGS, ITRIGGER, 20, 1) /* Virtual mode enabled */ -FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) -FIELD(TB_FLAGS, PRIV, 24, 2) -FIELD(TB_FLAGS, AXL, 26, 2) +FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1) +FIELD(TB_FLAGS, PRIV, 22, 2) +FIELD(TB_FLAGS, AXL, 24, 2) /* zicfilp needs a TB flag to track indirect branches */ -FIELD(TB_FLAGS, FCFI_ENABLED, 28, 1) -FIELD(TB_FLAGS, FCFI_LP_EXPECTED, 29, 1) +FIELD(TB_FLAGS, FCFI_ENABLED, 26, 1) +FIELD(TB_FLAGS, FCFI_LP_EXPECTED, 27, 1) /* zicfiss needs a TB flag so that correct TB is located based on tb flags */ -FIELD(TB_FLAGS, BCFI_ENABLED, 30, 1) +FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) @@ -776,7 +762,6 @@ static inline uint32_t vext_get_vlmax(uint32_t vlenb, uint32_t vsew, void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflags); -void riscv_cpu_update_mask(CPURISCVState *env); bool riscv_cpu_is_32bit(RISCVCPU *cpu); RISCVException riscv_csrr(CPURISCVState *env, int csrno, diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index fe4e34c64a..c5b3de6469 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -497,37 +497,6 @@ #define CSR_MHPMCOUNTER30H 0xb9e #define CSR_MHPMCOUNTER31H 0xb9f -/* - * User PointerMasking registers - * NB: actual CSR numbers might be changed in future - */ -#define CSR_UMTE 0x4c0 -#define CSR_UPMMASK 0x4c1 -#define CSR_UPMBASE 0x4c2 - -/* - * Machine PointerMasking registers - * NB: actual CSR numbers might be changed in future - */ -#define CSR_MMTE 0x3c0 -#define CSR_MPMMASK 0x3c1 -#define CSR_MPMBASE 0x3c2 - -/* - * Supervisor PointerMaster registers - * NB: actual CSR numbers might be changed in future - */ -#define CSR_SMTE 0x1c0 -#define CSR_SPMMASK 0x1c1 -#define CSR_SPMBASE 0x1c2 - -/* - * Hypervisor PointerMaster registers - * NB: actual CSR numbers might be changed in future - */ -#define CSR_VSMTE 0x2c0 -#define CSR_VSPMMASK 0x2c1 -#define CSR_VSPMBASE 0x2c2 #define CSR_SCOUNTOVF 0xda0 /* Crypto Extension */ @@ -759,11 +728,6 @@ typedef enum RISCVException { #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS)) -/* General PointerMasking CSR bits */ -#define PM_ENABLE 0x00000001ULL -#define PM_CURRENT 0x00000002ULL -#define PM_INSN 0x00000004ULL - /* Execution environment configuration bits */ #define MENVCFG_FIOM BIT(0) #define MENVCFG_LPE BIT(2) /* zicfilp */ @@ -803,57 +767,6 @@ typedef enum RISCVException { #define HENVCFGH_PBMTE MENVCFGH_PBMTE #define HENVCFGH_STCE MENVCFGH_STCE -/* Offsets for every pair of control bits per each priv level */ -#define XS_OFFSET 0ULL -#define U_OFFSET 2ULL -#define S_OFFSET 5ULL -#define M_OFFSET 8ULL - -#define PM_XS_BITS (EXT_STATUS_MASK << XS_OFFSET) -#define U_PM_ENABLE (PM_ENABLE << U_OFFSET) -#define U_PM_CURRENT (PM_CURRENT << U_OFFSET) -#define U_PM_INSN (PM_INSN << U_OFFSET) -#define S_PM_ENABLE (PM_ENABLE << S_OFFSET) -#define S_PM_CURRENT (PM_CURRENT << S_OFFSET) -#define S_PM_INSN (PM_INSN << S_OFFSET) -#define M_PM_ENABLE (PM_ENABLE << M_OFFSET) -#define M_PM_CURRENT (PM_CURRENT << M_OFFSET) -#define M_PM_INSN (PM_INSN << M_OFFSET) - -/* mmte CSR bits */ -#define MMTE_PM_XS_BITS PM_XS_BITS -#define MMTE_U_PM_ENABLE U_PM_ENABLE -#define MMTE_U_PM_CURRENT U_PM_CURRENT -#define MMTE_U_PM_INSN U_PM_INSN -#define MMTE_S_PM_ENABLE S_PM_ENABLE -#define MMTE_S_PM_CURRENT S_PM_CURRENT -#define MMTE_S_PM_INSN S_PM_INSN -#define MMTE_M_PM_ENABLE M_PM_ENABLE -#define MMTE_M_PM_CURRENT M_PM_CURRENT -#define MMTE_M_PM_INSN M_PM_INSN -#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INSN | \ - MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INSN | \ - MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INSN | \ - MMTE_PM_XS_BITS) - -/* (v)smte CSR bits */ -#define SMTE_PM_XS_BITS PM_XS_BITS -#define SMTE_U_PM_ENABLE U_PM_ENABLE -#define SMTE_U_PM_CURRENT U_PM_CURRENT -#define SMTE_U_PM_INSN U_PM_INSN -#define SMTE_S_PM_ENABLE S_PM_ENABLE -#define SMTE_S_PM_CURRENT S_PM_CURRENT -#define SMTE_S_PM_INSN S_PM_INSN -#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INSN | \ - SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INSN | \ - SMTE_PM_XS_BITS) - -/* umte CSR bits */ -#define UMTE_U_PM_ENABLE U_PM_ENABLE -#define UMTE_U_PM_CURRENT U_PM_CURRENT -#define UMTE_U_PM_INSN U_PM_INSN -#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN) - /* MISELECT, SISELECT, and VSISELECT bits (AIA) */ #define ISELECT_IPRIO0 0x30 #define ISELECT_IPRIO15 0x3f diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 954425081d..99588e219e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -42,7 +42,7 @@ /* RISC-V CPU definitions */ static const char riscv_single_letter_exts[] = "IEMAFDQCBPVH"; const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV, - RVC, RVS, RVU, RVH, RVJ, RVG, RVB, 0}; + RVC, RVS, RVU, RVH, RVG, RVB, 0}; /* * From vector_helper.c @@ -896,13 +896,6 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) CSR_MSCRATCH, CSR_SSCRATCH, CSR_SATP, - CSR_MMTE, - CSR_UPMBASE, - CSR_UPMMASK, - CSR_SPMBASE, - CSR_SPMMASK, - CSR_MPMBASE, - CSR_MPMMASK, }; for (i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { @@ -1088,8 +1081,6 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) } i++; } - /* mmte is supposed to have pm.current hardwired to 1 */ - env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT); /* * Bits 10, 6, 2 and 12 of mideleg are read only 1 when the Hypervisor @@ -1121,7 +1112,6 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) env->ssp = 0; env->xl = riscv_cpu_mxl(env); - riscv_cpu_update_mask(env); cs->exception_index = RISCV_EXCP_NONE; env->load_res = -1; set_default_nan_mode(1, &env->fp_status); @@ -1511,7 +1501,6 @@ static const MISAExtInfo misa_ext_info_arr[] = { MISA_EXT_INFO(RVS, "s", "Supervisor-level instructions"), MISA_EXT_INFO(RVU, "u", "User-level instructions"), MISA_EXT_INFO(RVH, "h", "Hypervisor"), - MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"), MISA_EXT_INFO(RVV, "v", "Vector operations"), MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"), MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)") diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f62b21e182..8c1969294f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -210,61 +210,10 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); - if (env->cur_pmmask != 0) { - flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); - } - if (env->cur_pmbase != 0) { - flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); - } *pflags = flags; } -void riscv_cpu_update_mask(CPURISCVState *env) -{ - target_ulong mask = 0, base = 0; - RISCVMXL xl = env->xl; - /* - * TODO: Current RVJ spec does not specify - * how the extension interacts with XLEN. - */ -#ifndef CONFIG_USER_ONLY - int mode = cpu_address_mode(env); - xl = cpu_get_xl(env, mode); - if (riscv_has_ext(env, RVJ)) { - switch (mode) { - case PRV_M: - if (env->mmte & M_PM_ENABLE) { - mask = env->mpmmask; - base = env->mpmbase; - } - break; - case PRV_S: - if (env->mmte & S_PM_ENABLE) { - mask = env->spmmask; - base = env->spmbase; - } - break; - case PRV_U: - if (env->mmte & U_PM_ENABLE) { - mask = env->upmmask; - base = env->upmbase; - } - break; - default: - g_assert_not_reached(); - } - } -#endif - if (xl == MXL_RV32) { - env->cur_pmmask = mask & UINT32_MAX; - env->cur_pmbase = base & UINT32_MAX; - } else { - env->cur_pmmask = mask; - env->cur_pmbase = base; - } -} - #ifndef CONFIG_USER_ONLY /* @@ -786,7 +735,6 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool virt_en) /* tlb_flush is unnecessary as mode is contained in mmu_idx */ env->priv = newpriv; env->xl = cpu_recompute_xl(env); - riscv_cpu_update_mask(env); /* * Clear the load reservation - otherwise a reservation placed in one diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 381cda81f8..48abcab487 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -531,16 +531,6 @@ static RISCVException hgatp(CPURISCVState *env, int csrno) return hmode(env, csrno); } -/* Checks if PointerMasking registers could be accessed */ -static RISCVException pointer_masking(CPURISCVState *env, int csrno) -{ - /* Check if j-ext is present */ - if (riscv_has_ext(env, RVJ)) { - return RISCV_EXCP_NONE; - } - return RISCV_EXCP_ILLEGAL_INST; -} - static RISCVException aia_hmode(CPURISCVState *env, int csrno) { if (!riscv_cpu_cfg(env)->ext_ssaia) { @@ -1648,7 +1638,6 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, env->xl = cpu_recompute_xl(env); } - riscv_cpu_update_mask(env); return RISCV_EXCP_NONE; } @@ -4358,302 +4347,6 @@ static RISCVException write_mcontext(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -/* - * Functions to access Pointer Masking feature registers - * We have to check if current priv lvl could modify - * csr in given mode - */ -static bool check_pm_current_disabled(CPURISCVState *env, int csrno) -{ - int csr_priv = get_field(csrno, 0x300); - int pm_current; - - if (env->debugger) { - return false; - } - /* - * If priv lvls differ that means we're accessing csr from higher priv lvl, - * so allow the access - */ - if (env->priv != csr_priv) { - return false; - } - switch (env->priv) { - case PRV_M: - pm_current = get_field(env->mmte, M_PM_CURRENT); - break; - case PRV_S: - pm_current = get_field(env->mmte, S_PM_CURRENT); - break; - case PRV_U: - pm_current = get_field(env->mmte, U_PM_CURRENT); - break; - default: - g_assert_not_reached(); - } - /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */ - return !pm_current; -} - -static RISCVException read_mmte(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val = env->mmte & MMTE_MASK; - return RISCV_EXCP_NONE; -} - -static RISCVException write_mmte(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - target_ulong wpri_val = val & MMTE_MASK; - - if (val != wpri_val) { - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" - TARGET_FMT_lx "\n", "MMTE: WPRI violation written 0x", - val, "vs expected 0x", wpri_val); - } - /* for machine mode pm.current is hardwired to 1 */ - wpri_val |= MMTE_M_PM_CURRENT; - - /* hardwiring pm.instruction bit to 0, since it's not supported yet */ - wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); - env->mmte = wpri_val | EXT_STATUS_DIRTY; - riscv_cpu_update_mask(env); - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus = env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_smte(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val = env->mmte & SMTE_MASK; - return RISCV_EXCP_NONE; -} - -static RISCVException write_smte(CPURISCVState *env, int csrno, - target_ulong val) -{ - target_ulong wpri_val = val & SMTE_MASK; - - if (val != wpri_val) { - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" - TARGET_FMT_lx "\n", "SMTE: WPRI violation written 0x", - val, "vs expected 0x", wpri_val); - } - - /* if pm.current==0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - - wpri_val |= (env->mmte & ~SMTE_MASK); - write_mmte(env, csrno, wpri_val); - return RISCV_EXCP_NONE; -} - -static RISCVException read_umte(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val = env->mmte & UMTE_MASK; - return RISCV_EXCP_NONE; -} - -static RISCVException write_umte(CPURISCVState *env, int csrno, - target_ulong val) -{ - target_ulong wpri_val = val & UMTE_MASK; - - if (val != wpri_val) { - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" - TARGET_FMT_lx "\n", "UMTE: WPRI violation written 0x", - val, "vs expected 0x", wpri_val); - } - - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - - wpri_val |= (env->mmte & ~UMTE_MASK); - write_mmte(env, csrno, wpri_val); - return RISCV_EXCP_NONE; -} - -static RISCVException read_mpmmask(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val = env->mpmmask; - return RISCV_EXCP_NONE; -} - -static RISCVException write_mpmmask(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - env->mpmmask = val; - if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) { - env->cur_pmmask = val; - } - env->mmte |= EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus = env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_spmmask(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val = env->spmmask; - return RISCV_EXCP_NONE; -} - -static RISCVException write_spmmask(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - /* if pm.current==0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - env->spmmask = val; - if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) { - env->cur_pmmask = val; - if (cpu_get_xl(env, PRV_S) == MXL_RV32) { - env->cur_pmmask &= UINT32_MAX; - } - } - env->mmte |= EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus = env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_upmmask(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val = env->upmmask; - return RISCV_EXCP_NONE; -} - -static RISCVException write_upmmask(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - /* if pm.current==0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - env->upmmask = val; - if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) { - env->cur_pmmask = val; - if (cpu_get_xl(env, PRV_U) == MXL_RV32) { - env->cur_pmmask &= UINT32_MAX; - } - } - env->mmte |= EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus = env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_mpmbase(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val = env->mpmbase; - return RISCV_EXCP_NONE; -} - -static RISCVException write_mpmbase(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - env->mpmbase = val; - if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) { - env->cur_pmbase = val; - } - env->mmte |= EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus = env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_spmbase(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val = env->spmbase; - return RISCV_EXCP_NONE; -} - -static RISCVException write_spmbase(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - /* if pm.current==0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - env->spmbase = val; - if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) { - env->cur_pmbase = val; - if (cpu_get_xl(env, PRV_S) == MXL_RV32) { - env->cur_pmbase &= UINT32_MAX; - } - } - env->mmte |= EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus = env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_upmbase(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val = env->upmbase; - return RISCV_EXCP_NONE; -} - -static RISCVException write_upmbase(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - /* if pm.current==0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - env->upmbase = val; - if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) { - env->cur_pmbase = val; - if (cpu_get_xl(env, PRV_U) == MXL_RV32) { - env->cur_pmbase &= UINT32_MAX; - } - } - env->mmte |= EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus = env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - #endif /* Crypto Extension */ @@ -5323,25 +5016,6 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_TINFO] = { "tinfo", debug, read_tinfo, write_ignore }, [CSR_MCONTEXT] = { "mcontext", debug, read_mcontext, write_mcontext }, - /* User Pointer Masking */ - [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, - [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, - write_upmmask }, - [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, - write_upmbase }, - /* Machine Pointer Masking */ - [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte }, - [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, - write_mpmmask }, - [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, - write_mpmbase }, - /* Supervisor Pointer Masking */ - [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte }, - [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, - write_spmmask }, - [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, - write_spmbase }, - /* Performance Counters */ [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_hpmcounter }, [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_hpmcounter }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index b2e1f2503c..d81621010d 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -152,25 +152,15 @@ static const VMStateDescription vmstate_vector = { static bool pointermasking_needed(void *opaque) { - RISCVCPU *cpu = opaque; - CPURISCVState *env = &cpu->env; - - return riscv_has_ext(env, RVJ); + return false; } static const VMStateDescription vmstate_pointermasking = { .name = "cpu/pointer_masking", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .needed = pointermasking_needed, .fields = (const VMStateField[]) { - VMSTATE_UINTTL(env.mmte, RISCVCPU), - VMSTATE_UINTTL(env.mpmmask, RISCVCPU), - VMSTATE_UINTTL(env.mpmbase, RISCVCPU), - VMSTATE_UINTTL(env.spmmask, RISCVCPU), - VMSTATE_UINTTL(env.spmbase, RISCVCPU), - VMSTATE_UINTTL(env.upmmask, RISCVCPU), - VMSTATE_UINTTL(env.upmbase, RISCVCPU), VMSTATE_END_OF_LIST() } @@ -266,7 +256,6 @@ static int riscv_cpu_post_load(void *opaque, int version_id) CPURISCVState *env = &cpu->env; env->xl = cpu_recompute_xl(env); - riscv_cpu_update_mask(env); return 0; } diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index e03b409248..7f7283d52a 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1115,7 +1115,6 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { MISA_CFG(RVS, true), MISA_CFG(RVU, true), MISA_CFG(RVH, true), - MISA_CFG(RVJ, false), MISA_CFG(RVV, false), MISA_CFG(RVG, false), MISA_CFG(RVB, false), @@ -1402,8 +1401,8 @@ static void riscv_init_max_cpu_extensions(Object *obj) CPURISCVState *env = &cpu->env; const RISCVCPUMultiExtConfig *prop; - /* Enable RVG, RVJ and RVV that are disabled by default */ - riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV); + /* Enable RVG and RVV that are disabled by default */ + riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVV); for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { isa_ext_update_enabled(cpu, prop->offset, true); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f46d76c785..7406a43b9f 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -42,9 +42,6 @@ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ static TCGv load_res; static TCGv load_val; -/* globals for PM CSRs */ -static TCGv pm_mask; -static TCGv pm_base; /* * If an operation is being performed on less than TARGET_LONG_BITS, @@ -106,9 +103,6 @@ typedef struct DisasContext { bool vl_eq_vlmax; CPUState *cs; TCGv zero; - /* PointerMasking extension */ - bool pm_mask_enabled; - bool pm_base_enabled; /* Ztso */ bool ztso; /* Use icount trigger for native debug */ @@ -592,14 +586,9 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm) TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); tcg_gen_addi_tl(addr, src1, imm); - if (ctx->pm_mask_enabled) { - tcg_gen_andc_tl(addr, addr, pm_mask); - } else if (get_address_xl(ctx) == MXL_RV32) { + if (get_address_xl(ctx) == MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } - if (ctx->pm_base_enabled) { - tcg_gen_or_tl(addr, addr, pm_base); - } return addr; } @@ -611,14 +600,10 @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); tcg_gen_add_tl(addr, src1, offs); - if (ctx->pm_mask_enabled) { - tcg_gen_andc_tl(addr, addr, pm_mask); - } else if (get_xl(ctx) == MXL_RV32) { + if (get_xl(ctx) == MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } - if (ctx->pm_base_enabled) { - tcg_gen_or_tl(addr, addr, pm_base); - } + return addr; } @@ -1246,8 +1231,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs = cs; - ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); - ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); ctx->ztso = cpu->cfg.ext_ztso; ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->bcfi_enabled = FIELD_EX32(tb_flags, TB_FLAGS, BCFI_ENABLED); @@ -1386,9 +1369,4 @@ void riscv_translate_init(void) "load_res"); load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val), "load_val"); - /* Assign PM CSRs to tcg globals */ - pm_mask = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmmask), - "pmmask"); - pm_base = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmbase), - "pmbase"); } diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index ead3ec5194..cf5dd7f2e1 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -107,7 +107,7 @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz) static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr) { - return (addr & ~env->cur_pmmask) | env->cur_pmbase; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.13.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:13:24 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alexey Baturo , Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 14/50] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0 Date: Sun, 19 Jan 2025 11:11:49 +1000 Message-ID: <20250119011225.11452-15-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250106102346.1100149-3-baturo.alexey@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 8 ++++++++ target/riscv/cpu_bits.h | 4 ++++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/pmp.h | 1 + target/riscv/csr.c | 33 +++++++++++++++++++++++++++++++-- target/riscv/pmp.c | 14 +++++++++++--- 6 files changed, 58 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c78e97af50..ad33e96ddf 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -128,6 +128,14 @@ typedef enum { EXT_STATUS_DIRTY, } RISCVExtStatus; +/* Enum holds PMM field values for Zjpm v1.0 extension */ +typedef enum { + PMM_FIELD_DISABLED = 0, + PMM_FIELD_RESERVED = 1, + PMM_FIELD_PMLEN7 = 2, + PMM_FIELD_PMLEN16 = 3, +} RISCVPmPmm; + typedef struct riscv_cpu_implied_exts_rule { #ifndef CONFIG_USER_ONLY /* diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index c5b3de6469..797dd6985b 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -575,6 +575,7 @@ typedef enum { #define HSTATUS_VTSR 0x00400000 #define HSTATUS_HUKTE 0x01000000 #define HSTATUS_VSXL 0x300000000 +#define HSTATUS_HUPMM 0x3000000000000 #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL @@ -735,6 +736,7 @@ typedef enum RISCVException { #define MENVCFG_CBIE (3UL << 4) #define MENVCFG_CBCFE BIT(6) #define MENVCFG_CBZE BIT(7) +#define MENVCFG_PMM (3ULL << 32) #define MENVCFG_ADUE (1ULL << 61) #define MENVCFG_PBMTE (1ULL << 62) #define MENVCFG_STCE (1ULL << 63) @@ -751,6 +753,7 @@ typedef enum RISCVException { #define SENVCFG_CBCFE MENVCFG_CBCFE #define SENVCFG_CBZE MENVCFG_CBZE #define SENVCFG_UKTE BIT(8) +#define SENVCFG_PMM MENVCFG_PMM #define HENVCFG_FIOM MENVCFG_FIOM #define HENVCFG_LPE MENVCFG_LPE @@ -758,6 +761,7 @@ typedef enum RISCVException { #define HENVCFG_CBIE MENVCFG_CBIE #define HENVCFG_CBCFE MENVCFG_CBCFE #define HENVCFG_CBZE MENVCFG_CBZE +#define HENVCFG_PMM MENVCFG_PMM #define HENVCFG_ADUE MENVCFG_ADUE #define HENVCFG_PBMTE MENVCFG_PBMTE #define HENVCFG_STCE MENVCFG_STCE diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index fe0c4173d2..a36d3fada3 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -129,6 +129,9 @@ struct RISCVCPUConfig { bool ext_ssaia; bool ext_sscofpmf; bool ext_smepmp; + bool ext_ssnpm; + bool ext_smnpm; + bool ext_smmpm; bool rvv_ta_all_1s; bool rvv_ma_all_1s; bool rvv_vl_half_avl; diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h index e0530a17a3..271cf24169 100644 --- a/target/riscv/pmp.h +++ b/target/riscv/pmp.h @@ -46,6 +46,7 @@ typedef enum { MSECCFG_USEED = 1 << 8, MSECCFG_SSEED = 1 << 9, MSECCFG_MLPE = 1 << 10, + MSECCFG_PMM = 3ULL << 32, } mseccfg_field_t; typedef struct { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 48abcab487..6b8cef52fe 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -575,6 +575,9 @@ static RISCVException have_mseccfg(CPURISCVState *env, int csrno) if (riscv_cpu_cfg(env)->ext_zkr) { return RISCV_EXCP_NONE; } + if (riscv_cpu_cfg(env)->ext_smmpm) { + return RISCV_EXCP_NONE; + } return RISCV_EXCP_ILLEGAL_INST; } @@ -2379,6 +2382,12 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno, if (env_archcpu(env)->cfg.ext_zicfiss) { mask |= MENVCFG_SSE; } + + /* Update PMM field only if the value is valid according to Zjpm v1.0 */ + if (env_archcpu(env)->cfg.ext_smnpm && + get_field(val, MENVCFG_PMM) != PMM_FIELD_RESERVED) { + mask |= MENVCFG_PMM; + } } env->menvcfg = (env->menvcfg & ~mask) | (val & mask); @@ -2425,6 +2434,12 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno, { uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE; RISCVException ret; + /* Update PMM field only if the value is valid according to Zjpm v1.0 */ + if (env_archcpu(env)->cfg.ext_ssnpm && + riscv_cpu_mxl(env) == MXL_RV64 && + get_field(val, SENVCFG_PMM) != PMM_FIELD_RESERVED) { + mask |= SENVCFG_PMM; + } ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); if (ret != RISCV_EXCP_NONE) { @@ -2493,6 +2508,12 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno, get_field(env->menvcfg, MENVCFG_SSE)) { mask |= HENVCFG_SSE; } + + /* Update PMM field only if the value is valid according to Zjpm v1.0 */ + if (env_archcpu(env)->cfg.ext_ssnpm && + get_field(val, HENVCFG_PMM) != PMM_FIELD_RESERVED) { + mask |= HENVCFG_PMM; + } } env->henvcfg = (env->henvcfg & ~mask) | (val & mask); @@ -3529,10 +3550,18 @@ static RISCVException read_hstatus(CPURISCVState *env, int csrno, static RISCVException write_hstatus(CPURISCVState *env, int csrno, target_ulong val) { + uint64_t mask = (target_ulong)-1; if (!env_archcpu(env)->cfg.ext_svukte) { - val = val & (~HSTATUS_HUKTE); + mask &= ~HSTATUS_HUKTE; } - env->hstatus = val; + /* Update PMM field only if the value is valid according to Zjpm v1.0 */ + if (!env_archcpu(env)->cfg.ext_ssnpm || + riscv_cpu_mxl(env) != MXL_RV64 || + get_field(val, HSTATUS_HUPMM) == PMM_FIELD_RESERVED) { + mask &= ~HSTATUS_HUPMM; + } + env->hstatus = (env->hstatus & ~mask) | (val & mask); + if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index a1b36664fc..a185c246d6 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -575,6 +575,13 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index) void mseccfg_csr_write(CPURISCVState *env, target_ulong val) { int i; + uint64_t mask = MSECCFG_MMWP | MSECCFG_MML; + /* Update PMM field only if the value is valid according to Zjpm v1.0 */ + if (riscv_cpu_cfg(env)->ext_smmpm && + riscv_cpu_mxl(env) == MXL_RV64 && + get_field(val, MSECCFG_PMM) != PMM_FIELD_RESERVED) { + mask |= MSECCFG_PMM; + } trace_mseccfg_csr_write(env->mhartid, val); @@ -590,12 +597,13 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val) if (riscv_cpu_cfg(env)->ext_smepmp) { /* Sticky bits */ - val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML)); - if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) { + val |= (env->mseccfg & mask); + if ((val ^ env->mseccfg) & mask) { tlb_flush(env_cpu(env)); } } else { - val &= ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB); + mask |= MSECCFG_RLB; + val &= ~(mask); } /* M-mode forward cfi to be enabled if cfi extension is implemented */ From patchwork Sun Jan 19 01:11:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5F3A9C02187 for ; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.13.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:13:28 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alexey Baturo , Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 15/50] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking Date: Sun, 19 Jan 2025 11:11:50 +1000 Message-ID: <20250119011225.11452-16-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250106102346.1100149-4-baturo.alexey@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 5 +++ target/riscv/cpu_helper.c | 78 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 83 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ad33e96ddf..5c85e8b28d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -772,8 +772,13 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, bool riscv_cpu_is_32bit(RISCVCPU *cpu); +bool riscv_cpu_virt_mem_enabled(CPURISCVState *env); +RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env); +uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm); + RISCVException riscv_csrr(CPURISCVState *env, int csrno, target_ulong *ret_value); + RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8c1969294f..0e030d4ecb 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -214,6 +214,84 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, *pflags = flags; } +RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) +{ +#ifndef CONFIG_USER_ONLY + int priv_mode = cpu_address_mode(env); + + if (get_field(env->mstatus, MSTATUS_MPRV) && + get_field(env->mstatus, MSTATUS_MXR)) { + return PMM_FIELD_DISABLED; + } + + /* Get current PMM field */ + switch (priv_mode) { + case PRV_M: + if (riscv_cpu_cfg(env)->ext_smmpm) { + return get_field(env->mseccfg, MSECCFG_PMM); + } + break; + case PRV_S: + if (riscv_cpu_cfg(env)->ext_smnpm) { + if (get_field(env->mstatus, MSTATUS_MPV)) { + return get_field(env->henvcfg, HENVCFG_PMM); + } else { + return get_field(env->menvcfg, MENVCFG_PMM); + } + } + break; + case PRV_U: + if (riscv_has_ext(env, RVS)) { + if (riscv_cpu_cfg(env)->ext_ssnpm) { + return get_field(env->senvcfg, SENVCFG_PMM); + } + } else { + if (riscv_cpu_cfg(env)->ext_smnpm) { + return get_field(env->menvcfg, MENVCFG_PMM); + } + } + break; + default: + g_assert_not_reached(); + } + return PMM_FIELD_DISABLED; +#else + return PMM_FIELD_DISABLED; +#endif +} + +bool riscv_cpu_virt_mem_enabled(CPURISCVState *env) +{ +#ifndef CONFIG_USER_ONLY + int satp_mode = 0; + int priv_mode = cpu_address_mode(env); + + if (riscv_cpu_mxl(env) == MXL_RV32) { + satp_mode = get_field(env->satp, SATP32_MODE); + } else { + satp_mode = get_field(env->satp, SATP64_MODE); + } + + return ((satp_mode != VM_1_10_MBARE) && (priv_mode != PRV_M)); +#else + return false; +#endif +} + +uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm) +{ + switch (pmm) { + case PMM_FIELD_DISABLED: + return 0; + case PMM_FIELD_PMLEN7: + return 7; + case PMM_FIELD_PMLEN16: + return 16; + default: + g_assert_not_reached(); + } +} + #ifndef CONFIG_USER_ONLY /* From patchwork Sun Jan 19 01:11:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944298 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3509C02187 for ; Sun, 19 Jan 2025 01:15:24 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJsf-0001vn-Ai; Sat, 18 Jan 2025 20:13:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJse-0001px-3U for qemu-devel@nongnu.org; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.13.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:13:32 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alexey Baturo , Richard Henderson , Alistair Francis , LIU Zhiwei Subject: [PULL v2 16/50] target/riscv: Add pointer masking tb flags Date: Sun, 19 Jan 2025 11:11:51 +1000 Message-ID: <20250119011225.11452-17-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Message-ID: <20250106102346.1100149-5-baturo.alexey@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 +++ target/riscv/cpu_helper.c | 3 +++ target/riscv/translate.c | 5 +++++ 3 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5c85e8b28d..f22e43c662 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -635,6 +635,9 @@ FIELD(TB_FLAGS, FCFI_ENABLED, 26, 1) FIELD(TB_FLAGS, FCFI_LP_EXPECTED, 27, 1) /* zicfiss needs a TB flag so that correct TB is located based on tb flags */ FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1) +/* If pointer masking should be applied and address sign extended */ +FIELD(TB_FLAGS, PM_PMM, 29, 2) +FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0e030d4ecb..8728541b99 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -126,6 +126,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, RISCVCPU *cpu = env_archcpu(env); RISCVExtStatus fs, vs; uint32_t flags = 0; + bool pm_signext = riscv_cpu_virt_mem_enabled(env); *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; *cs_base = 0; @@ -210,6 +211,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); + flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); + flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); *pflags = flags; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 7406a43b9f..26350b2826 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -103,6 +103,9 @@ typedef struct DisasContext { bool vl_eq_vlmax; CPUState *cs; TCGv zero; + /* actual address width */ + uint8_t addr_xl; + bool addr_signed; /* Ztso */ bool ztso; /* Use icount trigger for native debug */ @@ -1231,6 +1234,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs = cs; + ctx->addr_xl = 0; + ctx->addr_signed = false; ctx->ztso = cpu->cfg.ext_ztso; ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->bcfi_enabled = FIELD_EX32(tb_flags, TB_FLAGS, BCFI_ENABLED); From patchwork Sun Jan 19 01:11:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944287 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 352CAC02185 for ; Sun, 19 Jan 2025 01:14:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJsk-0002N1-TT; Sat, 18 Jan 2025 20:13:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJsh-00029M-GX for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:13:39 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJsf-0003EV-Mi for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:13:39 -0500 Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-2ee786b3277so4380304a91.1 for ; Sat, 18 Jan 2025 17:13:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249216; x=1737854016; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E7JlPx7ehQjMtsapu7OSc3TgFYoGt3fWe7/SxgEC/fk=; b=nFUPS6DCrxbSDONC2ccQ7MYjtdqWUCUbo7w9uTZVpWr61+lrRcHY0+8pSfsMf5BAzZ jCLeiozkdxEQMluM4NefDEBiW/cttN/p5PK4pnVjYTft41+p6J+2IXHKNP8RvPBdJNLE mqgwke633m3gCMgRcxP863I7QgPWKWxrdOz+hkuD5pklzQd8AS15fzMqUDi3aN9pRJI5 6wKRhfTlRoKPo1xEH1q7mzYEHAHp6l3ErxOb+8wIGsGy0GvsiZ5ITrri2Ncua15nt0Of n35iX3uhL1JvTg2HwgUfR3SyR6kGBUoco4MkBfYkbHeTGK0O7CAQXr/nCaSZiIiYV4Od 43cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249216; x=1737854016; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E7JlPx7ehQjMtsapu7OSc3TgFYoGt3fWe7/SxgEC/fk=; b=f/CyXBsvAiddcR6TZSdIqCZkCPILIMbdsSkiQ/sSSs0ZgPKf6gCweFrcr9ODIIRsd5 8kKUgBlfs2cKrKPtoSULn17uCEztbpQSZyRgjlb+KBPMmjp6orjgXNHQxa5KqC4t57rN r4SmAQsXVxt8AFQHMwtR+3XBk+B3wZCS1wj7EhTK+SZUZFxWZuZQdmjr8S/tz9q/O4sC m/P65DO3s8kx50yPIQ24YEK1grzv9/xrDIqNsAV1zARVXreYbJjA0B5678debcWZlIQ5 vsEBJ0tDRJjiI3acnm8ILTT91zdE3xkom7ehITcOoElPyOIURRLZlqGWeuUAKIypJwFw 4rLQ== X-Gm-Message-State: AOJu0YzHCcfELcg/a1HtS6+8nuzlBOlygtz2VXAjF9MM00AYdw4WtGmt o46JzKwAP368xRXzPOX5aMrnswTKIDoBk+amCOlU1dpQwzVXw+viR18fKlmj X-Gm-Gg: ASbGnctuvmAzyZKxlDckfdAWZ8dBw4ViEPDGMSa4hwjJqxWWNjSdoUGitRq65f3Tr7+ 1zvqOgNPP8wf3d0AzjCkIm3zfETDhaWJ6YFLcBCFNRJrmcUGjXba9iAL2i6HiC62EFCY+q4J+Ht xbU3iUOkCUO5fi24U/vIPTUREVitzr2xc2pDdKt5GM1ukb9DD6vbswAi3iNIn/8tAzBz3DKofNn zI+y9/l0gsok1cFwVp3UbZ2iJYOE5ss/POWCe1T7k7v9XhVdepD4er6q9upHQdxVruLJZHTERPl dnvSCzGLYoZNDTLPwDyfz+DRaXI04UvBqVpMJ89TV/39WCRyidHVdCmAHrr0jtBS0O1tXcP0FA= = X-Google-Smtp-Source: AGHT+IEJqgvMc7wU/ClJj/UdmeTsjn4tMV0BCUkEpHZ+JwFQBgRhvOgKHaLc3n40m+fd/9J1sxXdCA== X-Received: by 2002:a17:90b:2748:b0:2ea:59e3:2d2e with SMTP id 98e67ed59e1d1-2f782c73b7fmr12338777a91.10.1737249215894; Sat, 18 Jan 2025 17:13:35 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.13.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:13:35 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alexey Baturo , Richard Henderson , Alistair Francis Subject: [PULL v2 17/50] target/riscv: Update address modify functions to take into account pointer masking Date: Sun, 19 Jan 2025 11:11:52 +1000 Message-ID: <20250119011225.11452-18-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1030.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-ID: <20250106102346.1100149-6-baturo.alexey@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/translate.c | 22 ++++++++++++++++------ target/riscv/vector_helper.c | 16 ++++++++++++++++ 2 files changed, 32 insertions(+), 6 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 26350b2826..698b74f7a8 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -589,8 +589,10 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm) TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); tcg_gen_addi_tl(addr, src1, imm); - if (get_address_xl(ctx) == MXL_RV32) { - tcg_gen_ext32u_tl(addr, addr); + if (ctx->addr_signed) { + tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_xl); + } else { + tcg_gen_extract_tl(addr, addr, 0, ctx->addr_xl); } return addr; @@ -603,8 +605,10 @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); tcg_gen_add_tl(addr, src1, offs); - if (get_xl(ctx) == MXL_RV32) { - tcg_gen_ext32u_tl(addr, addr); + if (ctx->addr_signed) { + tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_xl); + } else { + tcg_gen_extract_tl(addr, addr, 0, ctx->addr_xl); } return addr; @@ -1234,8 +1238,14 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs = cs; - ctx->addr_xl = 0; - ctx->addr_signed = false; + if (get_xl(ctx) == MXL_RV32) { + ctx->addr_xl = 32; + ctx->addr_signed = false; + } else { + int pm_pmm = FIELD_EX32(tb_flags, TB_FLAGS, PM_PMM); + ctx->addr_xl = 64 - riscv_pm_get_pmlen(pm_pmm); + ctx->addr_signed = FIELD_EX32(tb_flags, TB_FLAGS, PM_SIGNEXTEND); + } ctx->ztso = cpu->cfg.ext_ztso; ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->bcfi_enabled = FIELD_EX32(tb_flags, TB_FLAGS, BCFI_ENABLED); diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index cf5dd7f2e1..0eea124b66 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -107,6 +107,22 @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz) static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr) { + if (riscv_cpu_mxl(env) == MXL_RV32) { + return addr; + } + RISCVPmPmm pmm = riscv_pm_get_pmm(env); + if (pmm == PMM_FIELD_DISABLED) { + return addr; + } + int pmlen = riscv_pm_get_pmlen(pmm); + bool signext = riscv_cpu_virt_mem_enabled(env); + addr = addr << pmlen; + /* sign/zero extend masked address by N-1 bit */ + if (signext) { + addr = (target_long)addr >> pmlen; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.13.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:13:38 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alexey Baturo , Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 18/50] target/riscv: Apply pointer masking for virtualized memory accesses Date: Sun, 19 Jan 2025 11:11:53 +1000 Message-ID: <20250119011225.11452-19-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250106102346.1100149-7-baturo.alexey@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/internals.h | 54 ++++++++++++++++++++++++++++++++++++ target/riscv/cpu_helper.c | 19 +++++++++++++ target/riscv/op_helper.c | 16 +++++------ target/riscv/vector_helper.c | 21 -------------- 5 files changed, 82 insertions(+), 29 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f22e43c662..5e7152200f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -777,6 +777,7 @@ bool riscv_cpu_is_32bit(RISCVCPU *cpu); bool riscv_cpu_virt_mem_enabled(CPURISCVState *env); RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env); +RISCVPmPmm riscv_pm_get_virt_pmm(CPURISCVState *env); uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm); RISCVException riscv_csrr(CPURISCVState *env, int csrno, diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 76934eaa7b..67291933f8 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -145,4 +145,58 @@ static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f) /* Our implementation of CPUClass::has_work */ bool riscv_cpu_has_work(CPUState *cs); +/* Zjpm addr masking routine */ +static inline target_ulong adjust_addr_body(CPURISCVState *env, + target_ulong addr, + bool is_virt_addr) +{ + RISCVPmPmm pmm = PMM_FIELD_DISABLED; + uint32_t pmlen = 0; + bool signext = false; + + /* do nothing for rv32 mode */ + if (riscv_cpu_mxl(env) == MXL_RV32) { + return addr; + } + + /* get pmm field depending on whether addr is */ + if (is_virt_addr) { + pmm = riscv_pm_get_virt_pmm(env); + } else { + pmm = riscv_pm_get_pmm(env); + } + + /* if pointer masking is disabled, return original addr */ + if (pmm == PMM_FIELD_DISABLED) { + return addr; + } + + if (!is_virt_addr) { + signext = riscv_cpu_virt_mem_enabled(env); + } + addr = addr << pmlen; + pmlen = riscv_pm_get_pmlen(pmm); + + /* sign/zero extend masked address by N-1 bit */ + if (signext) { + addr = (target_long)addr >> pmlen; + } else { + addr = addr >> pmlen; + } + + return addr; +} + +static inline target_ulong adjust_addr(CPURISCVState *env, + target_ulong addr) +{ + return adjust_addr_body(env, addr, false); +} + +static inline target_ulong adjust_addr_virt(CPURISCVState *env, + target_ulong addr) +{ + return adjust_addr_body(env, addr, true); +} + #endif diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8728541b99..2e307e4ea5 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -263,6 +263,25 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) #endif } +RISCVPmPmm riscv_pm_get_virt_pmm(CPURISCVState *env) +{ +#ifndef CONFIG_USER_ONLY + int priv_mode = cpu_address_mode(env); + + if (priv_mode == PRV_U) { + return get_field(env->hstatus, HSTATUS_HUPMM); + } else { + if (get_field(env->hstatus, HSTATUS_SPVP)) { + return get_field(env->henvcfg, HENVCFG_PMM); + } else { + return get_field(env->senvcfg, SENVCFG_PMM); + } + } +#else + return PMM_FIELD_DISABLED; +#endif +} + bool riscv_cpu_virt_mem_enabled(CPURISCVState *env) { #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 29de8eb43d..952ef8b3ec 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -479,7 +479,7 @@ target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr) int mmu_idx = check_access_hlsv(env, false, ra); MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); - return cpu_ldb_mmu(env, addr, oi, ra); + return cpu_ldb_mmu(env, adjust_addr_virt(env, addr), oi, ra); } target_ulong helper_hyp_hlv_hu(CPURISCVState *env, target_ulong addr) @@ -488,7 +488,7 @@ target_ulong helper_hyp_hlv_hu(CPURISCVState *env, target_ulong addr) int mmu_idx = check_access_hlsv(env, false, ra); MemOpIdx oi = make_memop_idx(MO_TEUW, mmu_idx); - return cpu_ldw_mmu(env, addr, oi, ra); + return cpu_ldw_mmu(env, adjust_addr_virt(env, addr), oi, ra); } target_ulong helper_hyp_hlv_wu(CPURISCVState *env, target_ulong addr) @@ -497,7 +497,7 @@ target_ulong helper_hyp_hlv_wu(CPURISCVState *env, target_ulong addr) int mmu_idx = check_access_hlsv(env, false, ra); MemOpIdx oi = make_memop_idx(MO_TEUL, mmu_idx); - return cpu_ldl_mmu(env, addr, oi, ra); + return cpu_ldl_mmu(env, adjust_addr_virt(env, addr), oi, ra); } target_ulong helper_hyp_hlv_d(CPURISCVState *env, target_ulong addr) @@ -506,7 +506,7 @@ target_ulong helper_hyp_hlv_d(CPURISCVState *env, target_ulong addr) int mmu_idx = check_access_hlsv(env, false, ra); MemOpIdx oi = make_memop_idx(MO_TEUQ, mmu_idx); - return cpu_ldq_mmu(env, addr, oi, ra); + return cpu_ldq_mmu(env, adjust_addr_virt(env, addr), oi, ra); } void helper_hyp_hsv_b(CPURISCVState *env, target_ulong addr, target_ulong val) @@ -515,7 +515,7 @@ void helper_hyp_hsv_b(CPURISCVState *env, target_ulong addr, target_ulong val) int mmu_idx = check_access_hlsv(env, false, ra); MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); - cpu_stb_mmu(env, addr, val, oi, ra); + cpu_stb_mmu(env, adjust_addr_virt(env, addr), val, oi, ra); } void helper_hyp_hsv_h(CPURISCVState *env, target_ulong addr, target_ulong val) @@ -524,7 +524,7 @@ void helper_hyp_hsv_h(CPURISCVState *env, target_ulong addr, target_ulong val) int mmu_idx = check_access_hlsv(env, false, ra); MemOpIdx oi = make_memop_idx(MO_TEUW, mmu_idx); - cpu_stw_mmu(env, addr, val, oi, ra); + cpu_stw_mmu(env, adjust_addr_virt(env, addr), val, oi, ra); } void helper_hyp_hsv_w(CPURISCVState *env, target_ulong addr, target_ulong val) @@ -533,7 +533,7 @@ void helper_hyp_hsv_w(CPURISCVState *env, target_ulong addr, target_ulong val) int mmu_idx = check_access_hlsv(env, false, ra); MemOpIdx oi = make_memop_idx(MO_TEUL, mmu_idx); - cpu_stl_mmu(env, addr, val, oi, ra); + cpu_stl_mmu(env, adjust_addr_virt(env, addr), val, oi, ra); } void helper_hyp_hsv_d(CPURISCVState *env, target_ulong addr, target_ulong val) @@ -542,7 +542,7 @@ void helper_hyp_hsv_d(CPURISCVState *env, target_ulong addr, target_ulong val) int mmu_idx = check_access_hlsv(env, false, ra); MemOpIdx oi = make_memop_idx(MO_TEUQ, mmu_idx); - cpu_stq_mmu(env, addr, val, oi, ra); + cpu_stq_mmu(env, adjust_addr_virt(env, addr), val, oi, ra); } /* diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 0eea124b66..5386e3b97c 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -105,27 +105,6 @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz) return scale < 0 ? vlenb >> -scale : vlenb << scale; } -static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr) -{ - if (riscv_cpu_mxl(env) == MXL_RV32) { - return addr; - } - RISCVPmPmm pmm = riscv_pm_get_pmm(env); - if (pmm == PMM_FIELD_DISABLED) { - return addr; - } - int pmlen = riscv_pm_get_pmlen(pmm); - bool signext = riscv_cpu_virt_mem_enabled(env); - addr = addr << pmlen; - /* sign/zero extend masked address by N-1 bit */ - if (signext) { - addr = (target_long)addr >> pmlen; - } else { - addr = addr >> pmlen; - } - return addr; -} - /* * This function checks watchpoint before real load operation. * From patchwork Sun Jan 19 01:11:54 2025 Content-Type: text/plain; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.13.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:13:42 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alexey Baturo , Alistair Francis Subject: [PULL v2 19/50] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension Date: Sun, 19 Jan 2025 11:11:54 +1000 Message-ID: <20250119011225.11452-20-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis Message-ID: <20250106102346.1100149-8-baturo.alexey@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 99588e219e..d9eb2c04c3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -193,11 +193,14 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), + ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_13_0, ext_smmpm), + ISA_EXT_DATA_ENTRY(smnpm, PRIV_VERSION_1_13_0, ext_smnpm), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), + ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_13_0, ext_ssnpm), ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12), @@ -1595,9 +1598,12 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false), MULTI_EXT_CFG_BOOL("zvfhmin", ext_zvfhmin, false), MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), + MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false), MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), + MULTI_EXT_CFG_BOOL("smmpm", ext_smmpm, false), + MULTI_EXT_CFG_BOOL("smnpm", ext_smnpm, false), MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), MULTI_EXT_CFG_BOOL("ssaia", ext_ssaia, false), MULTI_EXT_CFG_BOOL("svade", ext_svade, false), From patchwork Sun Jan 19 01:11:55 2025 Content-Type: text/plain; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.13.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:13:45 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Tommy Wu , Frank Chang , Alistair Francis Subject: [PULL v2 20/50] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig Date: Sun, 19 Jan 2025 11:11:55 +1000 Message-ID: <20250119011225.11452-21-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Tommy Wu The boolean variable 'ext_smrnmi' is used to determine whether the Smrnmi extension exists. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis Message-ID: <20250106054336.1878291-2-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index a36d3fada3..ee7c908710 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -129,6 +129,7 @@ struct RISCVCPUConfig { bool ext_ssaia; bool ext_sscofpmf; bool ext_smepmp; + bool ext_smrnmi; bool ext_ssnpm; bool ext_smnpm; bool ext_smmpm; From patchwork Sun Jan 19 01:11:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944286 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BB1BFC02188 for ; Sun, 19 Jan 2025 01:14:08 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJt0-0003cv-Mk; Sat, 18 Jan 2025 20:13:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJsw-0003I8-0Q for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:13:54 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJsu-0003Gu-1t for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:13:53 -0500 Received: by mail-pj1-x102d.google.com with SMTP id 98e67ed59e1d1-2ee46851b5eso4518181a91.1 for ; Sat, 18 Jan 2025 17:13:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249230; x=1737854030; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xeNptC+QWnpU+5NAPa8/GJLL6/97Pfg0ebpvg1NlFls=; b=h7/lkP2kJmeOFzxXVbSGiXqECDHye4SIQs288nNSzKkOiP8bFWeBJtcA++zcBLZTIk dOWOY8PNepzWxNPctx2Lq7KoEp4Hd2+a+mVzeHhRP1+vneX2mYSvT+HY2YrmC7fYoxVp oisdfcoA5nWR+E//NzAliKjiH1jAplTQU+0HaRau4bSCFY/q7UuynJXatx4ri3IVOb6c MJl0uXl4XGyf5t/euyqrxf0TMvy5an2eeqC/49tG+G8PA0tRQ8fdDm+3kCznVO/lQ0r3 YsWMMeootlAyX/tL8SVmIWJ5LlFigJPeSWctHpsjcIk8kx40P/yWyrgQA8nF5bnNTgLC ttbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249230; x=1737854030; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xeNptC+QWnpU+5NAPa8/GJLL6/97Pfg0ebpvg1NlFls=; b=YEE8ZA1PZEI/IF5wmpbLvHDQ/fVNJ7hIA2MY9aWiGtMooh1bygV68A8yhMAvcg8F/7 kQrhx+9NgMbCZsdcsDfqERGeIBnNMI3EyNLllsSdkE7u+hctBF7rnaVOSrd4rgnsjZNw 53QpvD5IehjTy0Ymttmr3NvWkZXTR6wunTlPLgjxFP32fGAPkkhMJWtNcb3rzVAYDVtY 5LsTBZVC93kHhiAUzsojRZ9qfDJGed3/8RdHFTomt0pDJh7erbqUmaJutwSExMBz/oyz jOrRvSIB+3YTkx42KYmwdhwY1iFnvyveG8/Armrg9FbcfMPNuPinLdXvmquYd6URS+U5 PQiQ== X-Gm-Message-State: AOJu0YwlK/nwEwsOgVGtREs56bd4Ng6HOu3sq0Vea3BuZtA2bKZkN/fA bAsaqn9ZCpXMNSQS9d6UOQSFcNlJ8UTSSFxyEo2rvT9bOJ1YSWS7TcGhNJnG X-Gm-Gg: ASbGncvXn65iUJqZCBWBLDHZgE6Uf1Wx9yevxMK7qlSzOrhhZ9ernfJfyW/OkXPFiEK Bv3LB8h+4EIf2g6J5ymbjSYKQ7mW8VXBC4NUxLPwv5LW+b0Ui/dYoKB7Yqukm+vi53yz1c947n3 Swy1MA7OPfzd5WtX2SCJ2KKgH/RZ3KdO6bIDHvq+A/jW1aqtl1pWLvNcLDvxJ97MBmb2/Hnar36 FqZK8zp4aTFnIB0MzqDsCy4H8HHhEjCZ3YgsuHt/N05lxpP5/ofxzpupfV0hKHkX+QZnq/AMnkJ DfzcB1jVXjOI1dB6ZjqVgflBCrr5J6bkMRUK6B5GemNxnDr52MZAO9AtsAyAQs/IrAc87j3uAw= = X-Google-Smtp-Source: AGHT+IExjd3f53bSIwkEIMRGPrxSadZgTf6p4E8yJxf3ePw52UOXQi13cHjXkzB7ImV5kWNNTxG0Jw== X-Received: by 2002:a17:90a:c2c5:b0:2ee:8008:b583 with SMTP id 98e67ed59e1d1-2f782c9c88fmr12756060a91.16.1737249230473; Sat, 18 Jan 2025 17:13:50 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.13.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:13:49 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Tommy Wu , Frank Chang , Alistair Francis Subject: [PULL v2 21/50] target/riscv: Add Smrnmi CSRs Date: Sun, 19 Jan 2025 11:11:56 +1000 Message-ID: <20250119011225.11452-22-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Tommy Wu The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause', 'mnstatus' CSRs. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis Message-ID: <20250106054336.1878291-3-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 7 ++++ target/riscv/cpu_bits.h | 11 ++++++ target/riscv/cpu.c | 5 +++ target/riscv/csr.c | 82 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 105 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5e7152200f..5eaf9da1f7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -480,6 +480,13 @@ struct CPUArchState { uint64_t kvm_timer_state; uint64_t kvm_timer_frequency; #endif /* CONFIG_KVM */ + + /* RNMI */ + target_ulong mnscratch; + target_ulong mnepc; + target_ulong mncause; /* mncause without bit XLEN-1 set to 1 */ + target_ulong mnstatus; + target_ulong rnmip; }; /* diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 797dd6985b..ba6fc546c4 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -353,6 +353,12 @@ #define CSR_PMPADDR14 0x3be #define CSR_PMPADDR15 0x3bf +/* RNMI */ +#define CSR_MNSCRATCH 0x740 +#define CSR_MNEPC 0x741 +#define CSR_MNCAUSE 0x742 +#define CSR_MNSTATUS 0x744 + /* Debug/Trace Registers (shared with Debug Mode) */ #define CSR_TSELECT 0x7a0 #define CSR_TDATA1 0x7a1 @@ -604,6 +610,11 @@ typedef enum { #define SATP64_ASID 0x0FFFF00000000000ULL #define SATP64_PPN 0x00000FFFFFFFFFFFULL +/* RNMI mnstatus CSR mask */ +#define MNSTATUS_NMIE 0x00000008 +#define MNSTATUS_MNPV 0x00000080 +#define MNSTATUS_MNPP 0x00001800 + /* VM modes (satp.mode) privileged ISA 1.10 */ #define VM_1_10_MBARE 0 #define VM_1_10_SV32 1 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d9eb2c04c3..66193cd2f6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1127,6 +1127,11 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) riscv_trigger_reset_hold(env); } + if (cpu->cfg.ext_smrnmi) { + env->rnmip = 0; + env->mnstatus = set_field(env->mnstatus, MNSTATUS_NMIE, false); + } + if (kvm_enabled()) { kvm_riscv_reset_vcpu(cpu); } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6b8cef52fe..af9766759a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -590,6 +590,17 @@ static RISCVException debug(CPURISCVState *env, int csrno) return RISCV_EXCP_ILLEGAL_INST; } + +static RISCVException rnmi(CPURISCVState *env, int csrno) +{ + RISCVCPU *cpu = env_archcpu(env); + + if (cpu->cfg.ext_smrnmi) { + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; +} #endif static RISCVException seed(CPURISCVState *env, int csrno) @@ -4376,6 +4387,67 @@ static RISCVException write_mcontext(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static RISCVException read_mnscratch(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->mnscratch; + return RISCV_EXCP_NONE; +} + +static int write_mnscratch(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mnscratch = val; + return RISCV_EXCP_NONE; +} + +static int read_mnepc(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->mnepc; + return RISCV_EXCP_NONE; +} + +static int write_mnepc(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mnepc = val; + return RISCV_EXCP_NONE; +} + +static int read_mncause(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->mncause; + return RISCV_EXCP_NONE; +} + +static int write_mncause(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mncause = val; + return RISCV_EXCP_NONE; +} + +static int read_mnstatus(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->mnstatus; + return RISCV_EXCP_NONE; +} + +static int write_mnstatus(CPURISCVState *env, int csrno, target_ulong val) +{ + target_ulong mask = (MNSTATUS_NMIE | MNSTATUS_MNPP); + + if (riscv_has_ext(env, RVH)) { + /* Flush tlb on mnstatus fields that affect VM. */ + if ((val ^ env->mnstatus) & MNSTATUS_MNPV) { + tlb_flush(env_cpu(env)); + } + + mask |= MNSTATUS_MNPV; + } + + /* mnstatus.mnie can only be cleared by hardware. */ + env->mnstatus = (env->mnstatus & MNSTATUS_NMIE) | (val & mask); + return RISCV_EXCP_NONE; +} + #endif /* Crypto Extension */ @@ -4883,6 +4955,16 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { write_sstateen_1_3, .min_priv_ver = PRIV_VERSION_1_12_0 }, + /* RNMI */ + [CSR_MNSCRATCH] = { "mnscratch", rnmi, read_mnscratch, write_mnscratch, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MNEPC] = { "mnepc", rnmi, read_mnepc, write_mnepc, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MNCAUSE] = { "mncause", rnmi, read_mncause, write_mncause, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MNSTATUS] = { "mnstatus", rnmi, read_mnstatus, write_mnstatus, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + /* Supervisor Trap Setup */ [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, NULL, read_sstatus_i128 }, From patchwork Sun Jan 19 01:11:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944312 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AC2FAC02187 for ; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.13.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:13:53 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Tommy Wu , Frank Chang , Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 22/50] target/riscv: Handle Smrnmi interrupt and exception Date: Sun, 19 Jan 2025 11:11:57 +1000 Message-ID: <20250119011225.11452-23-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Tommy Wu Because the RNMI interrupt trap handler address is implementation defined. We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property of the harts. It’s very easy for users to set the address based on their expectation. This patch also adds the functionality to handle the RNMI signals. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250106054336.1878291-4-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- include/hw/riscv/riscv_hart.h | 4 ++ target/riscv/cpu.h | 3 ++ target/riscv/cpu_bits.h | 12 +++++ hw/riscv/riscv_hart.c | 41 ++++++++++++++++ target/riscv/cpu.c | 11 +++++ target/riscv/cpu_helper.c | 88 ++++++++++++++++++++++++++++++++--- 6 files changed, 152 insertions(+), 7 deletions(-) diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h index 912b4a2682..a6ed73a195 100644 --- a/include/hw/riscv/riscv_hart.h +++ b/include/hw/riscv/riscv_hart.h @@ -38,6 +38,10 @@ struct RISCVHartArrayState { uint32_t hartid_base; char *cpu_type; uint64_t resetvec; + uint32_t num_rnmi_irqvec; + uint64_t *rnmi_irqvec; + uint32_t num_rnmi_excpvec; + uint64_t *rnmi_excpvec; RISCVCPU *harts; }; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5eaf9da1f7..08215efb09 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -487,6 +487,8 @@ struct CPUArchState { target_ulong mncause; /* mncause without bit XLEN-1 set to 1 */ target_ulong mnstatus; target_ulong rnmip; + uint64_t rnmi_irqvec; + uint64_t rnmi_excpvec; }; /* @@ -585,6 +587,7 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, uint64_t value); +void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level); void riscv_cpu_interrupt(CPURISCVState *env); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index ba6fc546c4..32525f00d6 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -650,6 +650,12 @@ typedef enum { /* Default Reset Vector address */ #define DEFAULT_RSTVEC 0x1000 +/* Default RNMI Interrupt Vector address */ +#define DEFAULT_RNMI_IRQVEC 0x0 + +/* Default RNMI Exception Vector address */ +#define DEFAULT_RNMI_EXCPVEC 0x0 + /* Exception causes */ typedef enum RISCVException { RISCV_EXCP_NONE = -1, /* sentinel value */ @@ -704,6 +710,9 @@ typedef enum RISCVException { /* -1 is due to bit zero of hgeip and hgeie being ROZ. */ #define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) +/* RNMI causes */ +#define RNMI_MAX 16 + /* mip masks */ #define MIP_USIP (1 << IRQ_U_SOFT) #define MIP_SSIP (1 << IRQ_S_SOFT) @@ -889,6 +898,9 @@ typedef enum RISCVException { #define MHPMEVENT_IDX_MASK 0xFFFFF #define MHPMEVENT_SSCOF_RESVD 16 +/* RISC-V-specific interrupt pending bits. */ +#define CPU_INTERRUPT_RNMI CPU_INTERRUPT_TGT_EXT_0 + /* JVT CSR bits */ #define JVT_MODE 0x3F #define JVT_BASE (~0x3F) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index bc9ffdd2d4..62b7c44350 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -26,6 +26,7 @@ #include "target/riscv/cpu.h" #include "hw/qdev-properties.h" #include "hw/riscv/riscv_hart.h" +#include "qemu/error-report.h" static const Property riscv_harts_props[] = { DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1), @@ -33,6 +34,23 @@ static const Property riscv_harts_props[] = { DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type), DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec, DEFAULT_RSTVEC), + + /* + * Smrnmi implementation-defined interrupt and exception trap handlers. + * + * When an RNMI interrupt is detected, the hart then enters M-mode and + * jumps to the address defined by "rnmi-interrupt-vector". + * + * When the hart encounters an exception while executing in M-mode with + * the mnstatus.NMIE bit clear, the hart then jumps to the address + * defined by "rnmi-exception-vector". + */ + DEFINE_PROP_ARRAY("rnmi-interrupt-vector", RISCVHartArrayState, + num_rnmi_irqvec, rnmi_irqvec, qdev_prop_uint64, + uint64_t), + DEFINE_PROP_ARRAY("rnmi-exception-vector", RISCVHartArrayState, + num_rnmi_excpvec, rnmi_excpvec, qdev_prop_uint64, + uint64_t), }; static void riscv_harts_cpu_reset(void *opaque) @@ -46,6 +64,29 @@ static bool riscv_hart_realize(RISCVHartArrayState *s, int idx, { object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type); qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec); + + if (s->harts[idx].cfg.ext_smrnmi) { + if (idx < s->num_rnmi_irqvec) { + qdev_prop_set_uint64(DEVICE(&s->harts[idx]), + "rnmi-interrupt-vector", s->rnmi_irqvec[idx]); + } + + if (idx < s->num_rnmi_excpvec) { + qdev_prop_set_uint64(DEVICE(&s->harts[idx]), + "rnmi-exception-vector", s->rnmi_excpvec[idx]); + } + } else { + if (s->num_rnmi_irqvec > 0) { + warn_report_once("rnmi-interrupt-vector property is ignored " + "because Smrnmi extension is not enabled."); + } + + if (s->num_rnmi_excpvec > 0) { + warn_report_once("rnmi-exception-vector property is ignored " + "because Smrnmi extension is not enabled."); + } + } + s->harts[idx].env.mhartid = s->hartid_base + idx; qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 66193cd2f6..eb06d06628 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1412,6 +1412,11 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level) g_assert_not_reached(); } } + +static void riscv_cpu_set_nmi(void *opaque, int irq, int level) +{ + riscv_cpu_set_rnmi(RISCV_CPU(opaque), irq, level); +} #endif /* CONFIG_USER_ONLY */ static bool riscv_cpu_is_dynamic(Object *cpu_obj) @@ -1435,6 +1440,8 @@ static void riscv_cpu_init(Object *obj) #ifndef CONFIG_USER_ONLY qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); + qdev_init_gpio_in_named(DEVICE(cpu), riscv_cpu_set_nmi, + "riscv.cpu.rnmi", RNMI_MAX); #endif /* CONFIG_USER_ONLY */ general_user_opts = g_hash_table_new(g_str_hash, g_str_equal); @@ -2793,6 +2800,10 @@ static const Property riscv_cpu_properties[] = { #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), + DEFINE_PROP_UINT64("rnmi-interrupt-vector", RISCVCPU, env.rnmi_irqvec, + DEFAULT_RNMI_IRQVEC), + DEFINE_PROP_UINT64("rnmi-exception-vector", RISCVCPU, env.rnmi_excpvec, + DEFAULT_RNMI_EXCPVEC), #endif DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 2e307e4ea5..4c70db6def 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -554,6 +554,18 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) uint64_t vsbits, irq_delegated; int virq; + /* Priority: RNMI > Other interrupt. */ + if (riscv_cpu_cfg(env)->ext_smrnmi) { + /* If mnstatus.NMIE == 0, all interrupts are disabled. */ + if (!get_field(env->mnstatus, MNSTATUS_NMIE)) { + return RISCV_EXCP_NONE; + } + + if (env->rnmip) { + return ctz64(env->rnmip); /* since non-zero */ + } + } + /* Determine interrupt enable state of all privilege modes */ if (env->virt_enabled) { mie = 1; @@ -616,7 +628,9 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - if (interrupt_request & CPU_INTERRUPT_HARD) { + uint32_t mask = CPU_INTERRUPT_HARD | CPU_INTERRUPT_RNMI; + + if (interrupt_request & mask) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; int interruptno = riscv_cpu_local_irq_pending(env); @@ -748,6 +762,30 @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) env->geilen = geilen; } +void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level) +{ + CPURISCVState *env = &cpu->env; + CPUState *cs = CPU(cpu); + bool release_lock = false; + + if (!bql_locked()) { + release_lock = true; + bql_lock(); + } + + if (level) { + env->rnmip |= 1 << irq; + cpu_interrupt(cs, CPU_INTERRUPT_RNMI); + } else { + env->rnmip &= ~(1 << irq); + cpu_reset_interrupt(cs, CPU_INTERRUPT_RNMI); + } + + if (release_lock) { + bql_unlock(); + } +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) { CPURISCVState *env = &cpu->env; @@ -1897,6 +1935,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool write_gva = false; bool always_storeamo = (env->excp_uw2 & RISCV_UW2_ALWAYS_STORE_AMO); uint64_t s; + int mode; /* * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide @@ -1914,7 +1953,24 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong htval = 0; target_ulong mtval2 = 0; int sxlen = 0; - int mxlen = 0; + int mxlen = 16 << riscv_cpu_mxl(env); + bool nnmi_excep = false; + + if (cpu->cfg.ext_smrnmi && env->rnmip && async) { + env->mnstatus = set_field(env->mnstatus, MNSTATUS_NMIE, false); + env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPV, + env->virt_enabled); + env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPP, + env->priv); + env->mncause = cause | ((target_ulong)1U << (mxlen - 1)); + env->mnepc = env->pc; + env->pc = env->rnmi_irqvec; + + /* Trapping to M mode, virt is disabled */ + riscv_cpu_set_mode(env, PRV_M, false); + + return; + } if (!async) { /* set tval to badaddr for traps with address information */ @@ -2008,8 +2064,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) __func__, env->mhartid, async, cause, env->pc, tval, riscv_cpu_get_trap_name(cause, async)); - if (env->priv <= PRV_S && cause < 64 && - (((deleg >> cause) & 1) || s_injected || vs_injected)) { + mode = env->priv <= PRV_S && cause < 64 && + (((deleg >> cause) & 1) || s_injected || vs_injected) ? PRV_S : PRV_M; + + if (mode == PRV_S) { /* handle the trap in S-mode */ /* save elp status */ if (cpu_get_fcfien(env)) { @@ -2064,6 +2122,14 @@ void riscv_cpu_do_interrupt(CPUState *cs) ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_S, virt); } else { + /* + * If the hart encounters an exception while executing in M-mode + * with the mnstatus.NMIE bit clear, the exception is an RNMI exception. + */ + nnmi_excep = cpu->cfg.ext_smrnmi && + !get_field(env->mnstatus, MNSTATUS_NMIE) && + !async; + /* handle the trap in M-mode */ /* save elp status */ if (cpu_get_fcfien(env)) { @@ -2091,14 +2157,22 @@ void riscv_cpu_do_interrupt(CPUState *cs) s = set_field(s, MSTATUS_MPP, env->priv); s = set_field(s, MSTATUS_MIE, 0); env->mstatus = s; - mxlen = 16 << riscv_cpu_mxl(env); env->mcause = cause | ((target_ulong)async << (mxlen - 1)); env->mepc = env->pc; env->mtval = tval; env->mtval2 = mtval2; env->mtinst = tinst; - env->pc = (env->mtvec >> 2 << 2) + - ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); + + /* + * For RNMI exception, program counter is set to the RNMI exception + * trap handler address. + */ + if (nnmi_excep) { + env->pc = env->rnmi_excpvec; + } else { + env->pc = (env->mtvec >> 2 << 2) + + ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); + } riscv_cpu_set_mode(env, PRV_M, virt); } From patchwork Sun Jan 19 01:11:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944294 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8258BC02187 for ; Sun, 19 Jan 2025 01:14:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJt7-0004LS-IQ; Sat, 18 Jan 2025 20:14:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJt5-00048x-9C for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:14:03 -0500 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJt1-0003Hx-RO for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:14:02 -0500 Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-2ee74291415so4504306a91.3 for ; Sat, 18 Jan 2025 17:13:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249238; x=1737854038; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=88uejHTxMUfNWO2ZqFUoG+1CMbM4VmsqYQ0Rsno50SI=; b=fsW/bh9+cnSv3KB9XJsjWX9vsfHQNGNXIbhfu6VVuYx44pTnRzVgHbQ1E3HgaKVsRF WdCfUOeFjp0hJcMpy3JYfPOhyQNqB4vBiUjueua+vkJUfamXNsm8st2CXPSGUFxSmyae PKjq0Dkizv1FPXKARaeejWozeJ0EUXZjgNnShSzikj6w/MHBrupfqHpH+cEh20FSNWS0 zOStz6pBDeEaCcAn+Z+yIMfMRRhIR8vIUKziaSd2qb81cqEieUgL2Xdb2RUgrFsbVSN1 cVGjUEMDJgzxxuI22v7BfPo8SwG5CGICuZ/7VSsCTvMWxxUz+AabgVCM2kDsL+ejSs1Y egcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249238; x=1737854038; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=88uejHTxMUfNWO2ZqFUoG+1CMbM4VmsqYQ0Rsno50SI=; b=NHZZAYvWt0BVWre+ylE6dzLw9z4IlCszCUjdHkA4Sd8vOCevaCkQpn79MhbagTroJE fh4RcXTDL64FT00Xv1uGW89npN45KyqJChgXajYsEh67U81vtVjkamqEWuOA+2AIVkZE 4phveifhqIXttnV+sfUqkGWdTYdoZEMGQBsQHosJbQLjqniR+rL9xnqjPfaDr3DcGNsI fWBH2ZqNh80R3BOPwUttkaYpjAkmDqmKWP/OdakOQeQnQhZnyXAl9q736m49A9yZlU2p P+9ObL21ph6GmfLm+eLBCir7jDXIiIlX8xlOtzmv0Ho0rDXRIMjs0ciS6fHqyjHIwowf Uoyw== X-Gm-Message-State: AOJu0YzfF5BhJZjW2a7V+18g1Oo287gRPTIalChr92/ntHceqkXyuvna ZOYMH+e7Ve4MCNvIhsWqDUjbWIRMaU6jMKGltQMdbGwEx0vecEN/PxIVi42s X-Gm-Gg: ASbGncsXXZuD/WSud+1npHUsSwTjjGjTKJN0cFeLvBmvIvEKhQVDRHWa/1FHcx7qF7r bt8gFiFMnqlfzYIgisMaIKBBb3bl3oan+4ywhv3sc2LvFOeChgqJKJ2zP5sN4YcJzSXS1jfh74j G+VhLLeyoq+KAimIjnsQ5NcezyedNKWCOM96uvbUEGz9c3Men2qIHmtcJci7fivlKUW50VcyhvX k6Md81aAy44b19dx6nY77bXOBCJ4kBmhvc23Nyz7MaSfEn1vuvfW7/Y2WVBUxB9palIJzPP/g7+ BZowqMX0uLDr5AiUFDesZExR48ZPjxvjHNuQUhWK9hHrhNW1KxKwfeXUAqAgMXlu11rrfSQRsg= = X-Google-Smtp-Source: AGHT+IH+UqLvfmNt5HPoAl4JsbueoWcv/0XpHLeMUfzvGtS6PKmXlLW2iu4l9HhxEJaUj3EOsyp0TQ== X-Received: by 2002:a17:90b:5145:b0:2ef:33a4:ae6e with SMTP id 98e67ed59e1d1-2f782c779edmr13959124a91.12.1737249238150; Sat, 18 Jan 2025 17:13:58 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.13.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:13:57 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Tommy Wu , Frank Chang , Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 23/50] target/riscv: Add Smrnmi mnret instruction Date: Sun, 19 Jan 2025 11:11:58 +1000 Message-ID: <20250119011225.11452-24-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1036.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Tommy Wu This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only instruction that uses the values in `mnepc` and `mnstatus` to return to the program counter, privilege mode, and virtualization mode of the interrupted context. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250106054336.1878291-5-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 3 ++ target/riscv/op_helper.c | 45 ++++++++++++++++--- .../riscv/insn_trans/trans_privileged.c.inc | 20 +++++++++ 4 files changed, 64 insertions(+), 5 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 451261ce5a..16ea240d26 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -131,6 +131,7 @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(sret, tl, env) DEF_HELPER_1(mret, tl, env) +DEF_HELPER_1(mnret, tl, env) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(wrs_nto, void, env) DEF_HELPER_1(tlb_flush, void, env) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e9139ec1b9..942c434c6e 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -121,6 +121,9 @@ wfi 0001000 00101 00000 000 00000 1110011 sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm +# *** NMI *** +mnret 0111000 00010 00000 000 00000 1110011 + # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u { diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 952ef8b3ec..bb022d89e2 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -328,24 +328,30 @@ target_ulong helper_sret(CPURISCVState *env) return retpc; } -target_ulong helper_mret(CPURISCVState *env) +static void check_ret_from_m_mode(CPURISCVState *env, target_ulong retpc, + target_ulong prev_priv) { if (!(env->priv >= PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } - target_ulong retpc = env->mepc; if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) { riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); } - uint64_t mstatus = env->mstatus; - target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP); - if (riscv_cpu_cfg(env)->pmp && !pmp_get_num_rules(env) && (prev_priv != PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC()); } +} + +target_ulong helper_mret(CPURISCVState *env) +{ + target_ulong retpc = env->mepc; + uint64_t mstatus = env->mstatus; + target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP); + + check_ret_from_m_mode(env, retpc, prev_priv); target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV) && (prev_priv != PRV_M); @@ -377,6 +383,35 @@ target_ulong helper_mret(CPURISCVState *env) return retpc; } +target_ulong helper_mnret(CPURISCVState *env) +{ + target_ulong retpc = env->mnepc; + target_ulong prev_priv = get_field(env->mnstatus, MNSTATUS_MNPP); + target_ulong prev_virt; + + check_ret_from_m_mode(env, retpc, prev_priv); + + prev_virt = get_field(env->mnstatus, MNSTATUS_MNPV) && + (prev_priv != PRV_M); + env->mnstatus = set_field(env->mnstatus, MNSTATUS_NMIE, true); + + /* + * If MNRET changes the privilege mode to a mode + * less privileged than M, it also sets mstatus.MPRV to 0. + */ + if (prev_priv < PRV_M) { + env->mstatus = set_field(env->mstatus, MSTATUS_MPRV, false); + } + + if (riscv_has_ext(env, RVH) && prev_virt) { + riscv_cpu_swap_hypervisor_regs(env); + } + + riscv_cpu_set_mode(env, prev_priv, prev_virt); + + return retpc; +} + void helper_wfi(CPURISCVState *env) { CPUState *cs = env_cpu(env); diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc index ecd3b8b2c9..73f940d406 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -18,6 +18,12 @@ * this program. If not, see . */ +#define REQUIRE_SMRNMI(ctx) do { \ + if (!ctx->cfg_ptr->ext_smrnmi) { \ + return false; \ + } \ +} while (0) + static bool trans_ecall(DisasContext *ctx, arg_ecall *a) { /* always generates U-level ECALL, fixed in do_interrupt handler */ @@ -106,6 +112,20 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a) #endif } +static bool trans_mnret(DisasContext *ctx, arg_mnret *a) +{ +#ifndef CONFIG_USER_ONLY + REQUIRE_SMRNMI(ctx); + decode_save_opc(ctx, 0); + gen_helper_mnret(cpu_pc, tcg_env); + tcg_gen_exit_tb(NULL, 0); /* no chaining */ + ctx->base.is_jmp = DISAS_NORETURN; + return true; +#else + return false; +#endif +} + static bool trans_wfi(DisasContext *ctx, arg_wfi *a) { #ifndef CONFIG_USER_ONLY From patchwork Sun Jan 19 01:11:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944290 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46012C02185 for ; Sun, 19 Jan 2025 01:14:26 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJt9-0004d7-4c; Sat, 18 Jan 2025 20:14:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJt7-0004Ky-30 for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:14:05 -0500 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJt5-0003IU-9N for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:14:04 -0500 Received: by mail-pj1-x1033.google.com with SMTP id 98e67ed59e1d1-2ee989553c1so5841709a91.3 for ; Sat, 18 Jan 2025 17:14:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249242; x=1737854042; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ObjOg1jNkCKQgckMwlEXeZthhx4HB8cGtwe97jDNC3w=; b=WF6/EUjvvO+kbeNWHLvwC9SsWVNKXbtXVKod4wBEpkC/KQfrTpdzjVP8ahaOfSvcpo O9LOLi1jgaGwgU3tOfG034sdll2MeDAbjoIIdn88H7/SiAaYlhWCZtxm7BwpsWvxUWUb sK+peLwRoGau1848bgh7TSu/8xkeLppv+bYrFkVMVMH1Lyn2YdZiyc2xbFb8gFl6vLkQ P3sQddker6A/rHnKkSbUL4jDSR1R3WXH3PgZABCKJjMOedeMFZKz037UYTkihjpAxcTr Xh0Y67xy3MXDu0iJTk06BItZbTbWO9CRZCscINVV+jCJA2/Az1fzY7/6Q2Qmw+G2p0uY iG3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249242; x=1737854042; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ObjOg1jNkCKQgckMwlEXeZthhx4HB8cGtwe97jDNC3w=; b=RnDF3ItLLIkNXn1vaEzJlOgWxl1PJ81Y/h+Zizqcmx4mg7VGZ02nZKeVZOg75vcEOF tozw8ttk6me8JGbvDPHjh765pMq910XoCl8m3beZKHCCZ+c3xPIZmLYDNUwcVk+lZfk0 F/BhaLtFkDiHfiIvXFyahlkAZ8BB7MpycCY71h2fIqNQXeWj1oy50aVFwQfJT47/QXd9 GydsiEXhJ/hkWsViOBu4KR84cN/wVOfmCAPt37Tdu05Oc4srkUafn8FJIlXyKoWNuuFi lCprHWi03VsQKPEPC7JgJ1dvtTGLUgZ922jTOKCCTy0l63jKTlHYs9QZKhy2hxZUZ+9o hvjA== X-Gm-Message-State: AOJu0YwIOiDwoR+aEDC2YBFAbVkt1lW0yY6/VQ6NJYzqRb0UGXyOQl0D bnSzdYbrmOw+3g/zOd5o7J66sJSSNyAHfUT3pn4KZnflXpXEhXJKAw746jyV X-Gm-Gg: ASbGncvlnBt+2lwcJ1ZAyzzH53/XMYf3WWeLe7Uh8Nv0vqOM8BEAAzEq6+j3qqvY5r5 B7d5zjJTAJUJEoLfednpIVoqS8tWks13or8Ez7HOQjHjcaiyhBaQ6RgBw7nj3vFNqRS4QE+lvcW JMPTmYdoutPXnCmxsG/auLZ6L5LJwKV95CQhlYAIoPGch9isQU5+AwERVQCJSEzcB5D6glOrqaX /QQ2Yh0YU7E7K1c8c9Juf/S/H47OjmhYSDfwZ77EMuiybnFP5uyIO9urX7zhK6kmH7kzMx3mBm+ y3iwBP3pg1CZ6eKriUW553YusH4qLAvqeQO8SqbZxbXuEh5ZKwVXiLERGxnjAgaVsSt6NwRp3w= = X-Google-Smtp-Source: AGHT+IGPq4jJF/fdsUOx7ScQ4yHlTcmnMlTIz+6TGYHPqNPWi2G5koVVSXIaeCDXXDrEUowsRjkVug== X-Received: by 2002:a17:90b:4a48:b0:2ee:863e:9fff with SMTP id 98e67ed59e1d1-2f782c701cfmr12562301a91.10.1737249241684; Sat, 18 Jan 2025 17:14:01 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.13.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:14:01 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Tommy Wu , Frank Chang , Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 24/50] target/riscv: Add Smrnmi cpu extension Date: Sun, 19 Jan 2025 11:11:59 +1000 Message-ID: <20250119011225.11452-25-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Tommy Wu This adds the properties for ISA extension Smrnmi. Also, when Smrnmi is present, the firmware (e.g., OpenSBI) must set mnstatus.NMIE to 1 before enabling any interrupts. Otherwise, all interrupts will be disabled. Since our current OpenSBI does not support Smrnmi yet, let's disable Smrnmi for the 'max' type CPU for now. We can re-enable it once OpenSBI includes proper support for it. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Signed-off-by: Daniel Henrique Barboza Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250106054336.1878291-6-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ target/riscv/tcg/tcg-cpu.c | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index eb06d06628..dace670e5e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -193,6 +193,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), + ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi), ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_13_0, ext_smmpm), ISA_EXT_DATA_ENTRY(smnpm, PRIV_VERSION_1_13_0, ext_smnpm), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), @@ -1614,6 +1615,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), + MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false), MULTI_EXT_CFG_BOOL("smmpm", ext_smmpm, false), MULTI_EXT_CFG_BOOL("smnpm", ext_smnpm, false), MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 7f7283d52a..f94aa9f29e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1430,6 +1430,15 @@ static void riscv_init_max_cpu_extensions(Object *obj) if (env->misa_mxl != MXL_RV32) { isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); } + + /* + * ext_smrnmi requires OpenSBI changes that our current + * image does not have. Disable it for now. + */ + if (cpu->cfg.ext_smrnmi) { + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false); + qemu_log("Smrnmi is disabled in the 'max' type CPU\n"); + } } static bool riscv_cpu_has_max_extensions(Object *cpu_obj) From patchwork Sun Jan 19 01:12:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944289 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BEA8EC0218A for ; Sun, 19 Jan 2025 01:14:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJtD-000513-6e; Sat, 18 Jan 2025 20:14:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJtA-0004oI-TI for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:14:09 -0500 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJt9-0003J8-60 for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:14:08 -0500 Received: by mail-pj1-x1034.google.com with SMTP id 98e67ed59e1d1-2eeb4d643a5so6087027a91.3 for ; Sat, 18 Jan 2025 17:14:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249246; x=1737854046; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G7TFB4wgLSjm+8sg62VV/jZBqX5r4K428u5pVR59C3c=; b=mKWj7lg81VcN01vPWyKuM6CtRoqwRuIazLxUuofvgKjEpRwt2j6VxUM/0tHo+ND0aG 3qTs0WqzGZmOkA2p9c9zh2B3la7c35dtkGhAjLjo70Tg7TNhcOotv2Ul+rBzGk4MV3E3 AN/6G+lhyRIVHrXDjD3jbnUwdSN8OXaZQLqxGRQAjm5cctnJfphMop89x+Ejtm2jCdZ9 ZRZ4TqgokH7QoSzWS8fpo9Oci0hv9kMaPJ3aFrT8NwZuZ77a2tN5EYwRu2qKRlyhFOMT xNVt8OYV4GyFnm80v7V6WI4ADE5LtvW9ziKBYqvf9snzwqcE+aLir3w5jPvUhAirvjRg wDcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249246; x=1737854046; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G7TFB4wgLSjm+8sg62VV/jZBqX5r4K428u5pVR59C3c=; b=DywLShR4Hqiw7hrK4KMVgs3D+T3xDl4Jmt2ZXOm9mXSDPuVjMVlLZapRoRFfuinV+c snJgf0tZ9V7ad6VEM6UIuXjnfGgNduy+m3clT9wg7BDWvuN1RpuTqcMuhN0OgeIVqHya L8toBOlwWETHdsn6nC91fU2CfIRvJnJGribdOogYEsUSaRRtln1uW+IwlAsqhDyw5gfE +/5oWIS8BmadWp5c54pFz8e99a5DMXMH1QndlHRdCwwqiXctm2m96/CkMkN133s9BYeU c/ZhkkmInN1IvZz3hwVOxyv/iM+XFSiDHg+2sx6vrcXKzHvFB4rgtjSJ1r9SWilMS+MK TGsA== X-Gm-Message-State: AOJu0Ywc4SqaYVvvo4DSbJam2Y24GJlr1Zk+HNffqT5Y4QBC1yjy0pNt yJU2DxY+XqIB8qZ7yc/FXKLptzTpLmcRuiJkVFb/3clBsd7PO0JcqHl3SLHr X-Gm-Gg: ASbGncubRcm7j7dfND9FlvujIwSv+xxT7U/oozs8y8HV7rVTmzjYY9DzEg+2ek6Bb3h JN2gh1CU6nxnKr9xLvglX0KnnBsQsC9vYfX9Kkz+VytBI7ntWafG9o1pUNKFrn/5y0xojoOZheI J8MJUyX6lrhC3DnYPIucUWts5Lx5BW3xzjgU8+ANO1I5EfGJlKXq3SwkT4BgOcttCuFNPTm9sWm nFMOAh2vVZ9XesjkYIdQIORSJVgo+Fjq6MfPYPMu9RxuYag4d6/aNK/3SaBfgr5sH7eSC4X8AFB 2MZNKImh6TePeVOFJ9W/ye6Q8tbcyBNigrcsmeQWjrAXHiOxyTmZMHDGSSgm//f+9eLIpyv7LQ= = X-Google-Smtp-Source: AGHT+IHa2wYDLqFcL+S178J+hwuJW93lRHr94MpAsx4W3zrsmQiuaNYkUr3+d4THaScsDK3uBGo6sg== X-Received: by 2002:a17:90b:2703:b0:2f4:f7f8:f70c with SMTP id 98e67ed59e1d1-2f782d4f17emr11818151a91.28.1737249245630; Sat, 18 Jan 2025 17:14:05 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.14.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:14:04 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Frank Chang , Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 25/50] target/riscv: Add Zicfilp support for Smrnmi Date: Sun, 19 Jan 2025 11:12:00 +1000 Message-ID: <20250119011225.11452-26-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Frank Chang Zicfilp extension introduces the MNPELP (bit 9) in mnstatus. The MNPELP field holds the previous ELP. When a RNMI trap is delivered, the MNPELP is set to ELP and ELP set to NO_LP_EXPECTED. Upon a mnret, if the mnstatus.MNPP holds the value y, then ELP is set to the value of MNPELP if yLPE is 1; otherwise, it is set to NO_LP_EXPECTED. Signed-off-by: Frank Chang Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250106054336.1878291-7-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 11 ++++++++++- target/riscv/op_helper.c | 9 +++++++++ 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 32525f00d6..d51f3d8cef 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -613,6 +613,7 @@ typedef enum { /* RNMI mnstatus CSR mask */ #define MNSTATUS_NMIE 0x00000008 #define MNSTATUS_MNPV 0x00000080 +#define MNSTATUS_MNPELP 0x00000200 #define MNSTATUS_MNPP 0x00001800 /* VM modes (satp.mode) privileged ISA 1.10 */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 4c70db6def..3318ce440d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1966,6 +1966,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mnepc = env->pc; env->pc = env->rnmi_irqvec; + if (cpu_get_fcfien(env)) { + env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPELP, env->elp); + } + /* Trapping to M mode, virt is disabled */ riscv_cpu_set_mode(env, PRV_M, false); @@ -2133,7 +2137,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) /* handle the trap in M-mode */ /* save elp status */ if (cpu_get_fcfien(env)) { - env->mstatus = set_field(env->mstatus, MSTATUS_MPELP, env->elp); + if (nnmi_excep) { + env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPELP, + env->elp); + } else { + env->mstatus = set_field(env->mstatus, MSTATUS_MPELP, env->elp); + } } if (riscv_has_ext(env, RVH)) { diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index bb022d89e2..c825336519 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -409,6 +409,15 @@ target_ulong helper_mnret(CPURISCVState *env) riscv_cpu_set_mode(env, prev_priv, prev_virt); + /* + * If forward cfi enabled for new priv, restore elp status + * and clear mnpelp in mnstatus + */ + if (cpu_get_fcfien(env)) { + env->elp = get_field(env->mnstatus, MNSTATUS_MNPELP); + } + env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPELP, 0); + return retpc; } From patchwork Sun Jan 19 01:12:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944292 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9C397C02185 for ; Sun, 19 Jan 2025 01:14:38 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJtG-0005Jp-Dj; Sat, 18 Jan 2025 20:14:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJtE-0005Am-4A for qemu-devel@nongnu.org; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.14.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:14:08 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL v2 26/50] target/riscv: Have kvm_riscv_get_timebase_frequency() take RISCVCPU cpu Date: Sun, 19 Jan 2025 11:12:01 +1000 Message-ID: <20250119011225.11452-27-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé Keep kvm_riscv_get_timebase_frequency() prototype aligned with the other ones declared in "kvm_riscv.h", have it take a RISCVCPU cpu as argument. Include "target/riscv/cpu-qom.h" which declares the RISCVCPU typedef. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-ID: <20250112231344.34632-2-philmd@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/kvm/kvm_riscv.h | 4 +++- hw/riscv/virt.c | 2 +- target/riscv/kvm/kvm-cpu.c | 4 ++-- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/kvm/kvm_riscv.h b/target/riscv/kvm/kvm_riscv.h index 5851898868..b2bcd1041f 100644 --- a/target/riscv/kvm/kvm_riscv.h +++ b/target/riscv/kvm/kvm_riscv.h @@ -19,6 +19,8 @@ #ifndef QEMU_KVM_RISCV_H #define QEMU_KVM_RISCV_H +#include "target/riscv/cpu-qom.h" + void kvm_riscv_reset_vcpu(RISCVCPU *cpu); void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, @@ -28,6 +30,6 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, void riscv_kvm_aplic_request(void *opaque, int irq, int level); int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state); void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp); -uint64_t kvm_riscv_get_timebase_frequency(CPUState *cs); +uint64_t kvm_riscv_get_timebase_frequency(RISCVCPU *cpu); #endif diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 2bc5a9dd98..9e8876be29 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -750,7 +750,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, qemu_fdt_add_subnode(ms->fdt, "/cpus"); qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", kvm_enabled() ? - kvm_riscv_get_timebase_frequency(first_cpu) : + kvm_riscv_get_timebase_frequency(RISCV_CPU(first_cpu)) : RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 11278ea778..23ce779359 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -758,11 +758,11 @@ static void kvm_riscv_put_regs_timer(CPUState *cs) env->kvm_timer_dirty = false; } -uint64_t kvm_riscv_get_timebase_frequency(CPUState *cs) +uint64_t kvm_riscv_get_timebase_frequency(RISCVCPU *cpu) { uint64_t reg; - KVM_RISCV_GET_TIMER(cs, frequency, reg); + KVM_RISCV_GET_TIMER(CPU(cpu), frequency, reg); return reg; } From patchwork Sun Jan 19 01:12:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944300 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1A622C02185 for ; Sun, 19 Jan 2025 01:15:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJtM-0005hz-5k; Sat, 18 Jan 2025 20:14:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJtJ-0005XX-2G for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:14:17 -0500 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJtF-0003KR-DN for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:14:16 -0500 Received: by mail-pj1-x102a.google.com with SMTP id 98e67ed59e1d1-2ee9a780de4so4366030a91.3 for ; Sat, 18 Jan 2025 17:14:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249252; x=1737854052; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NdLEaQfdnKEQEDdTsYjN/zThxqSlLF48asIv/trDC5U=; b=fy2Id470hVPQ19pNDsM9IWI4J1eKWLimkX3jPLNuLHbNPcqI4AqD3QjGG980t9ib2d TRkDV2eqIcu6yzlKfiSQ8mDyd9rMZkzsDty7UMosm/HL27pMIblgVJunyNeda1U/kepW rf0FjHyzbgtLM2bULCHfX7Cjp723bovRzlMOKJmKdumOKSG4j6HePrSAZtEwFEyTyqNt F9ryAz+IDIUZ+R0QtBSDEeKlnQVn2dbPja5UHt5jRtduCDsuCWGX1aZpUP4otwvI1eHZ SznN6dpxn7wrP0ajlMEbWzSR5ep6XjuGbjxM6VfMciVpTqphG0KsKOqLJtwcGyRpc8A7 2pSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249252; x=1737854052; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NdLEaQfdnKEQEDdTsYjN/zThxqSlLF48asIv/trDC5U=; b=j9SQWy7TKVX3nnW0lH9+xVJbVL/1XjtjdBMkV8YJ03wB2u2zRw0OpLWeNnFx0EMkHe CyXN38LKeQ7/0f8W+EXc/7O/iWBiF7h9ko3IDKn0BHpCV0htCXk2tuYoHluJKJaLgwAi MxHVla4fOPZvky7yiZ3XInxHCGAG/7RTOqJLOlpJjxrSH/3VEGkpLnm1Gq2203UAMMqb Rmwlmp82Cc09bMS1U1CrRTvH5cnTAwjzmmQamNDnASHVdHvK3/o5tTgtzHOxH7NXstAQ S2E5tfcy0RgJ5D5vSEJpBNHOqqhSNc1q6gbXN8NaxRgAZ7GTvszdr9XyZkI+cVL9KzwJ XrRA== X-Gm-Message-State: AOJu0YzMobIm0iXGEf1/dLl8AoStsK+puLfdRc/dHuMGe7wQBYJ0GmqT buCrAs1NB/7n73HLNmgwq4oFuoPmfWIcWP1kAiYKX4yUZ/hZNtMtvBdRq+mB X-Gm-Gg: ASbGncsXbEFeEXQ0lbQBD9bL8bQ9zQ8b4RlcmQbMzXsOMjDscXqFmIvbX+B781z3F+l dw1E7HlwkU+apmoujZ2rhT0HesK2izg11uOARmWfp/vmFtLy2wbtFAZNjGsxf3br6ZCBVlurgN0 CXOvz+zKoaw+tFokbjS/pdYa7JyIu14ki1prtO/VI4BJlzcI/ET1iGx6rj1WP/K5Vht3dovfdaN RLp3HJhrngqi14dmn/LoqJk6wIaV2e1JnF+Tv7JhlKEWmAi5bScR0b4YCl3mcG20syKqnkRAaLu pX9MPayjxKu5NHLvN2EuEY6V8W4HKQsN3pvCzskF860edkaqG7AVLMy3m/e4FN4zkfl2If+Jow= = X-Google-Smtp-Source: AGHT+IEWpacPsKaadIgjRuh4J84ePW6xg7qrmEo6HagbmOpRRFBHbIVc6mF5WFZD+X6XqFp2nGJA+w== X-Received: by 2002:a17:90a:c883:b0:2ee:b2be:f390 with SMTP id 98e67ed59e1d1-2f782d37d55mr11524979a91.28.1737249251797; Sat, 18 Jan 2025 17:14:11 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.14.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:14:11 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL v2 27/50] hw/riscv/virt: Remove unnecessary use of &first_cpu Date: Sun, 19 Jan 2025 11:12:02 +1000 Message-ID: <20250119011225.11452-28-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé virt_machine_init() creates the HARTs vCPUs, then later virt_machine_done() calls create_fdt_sockets(), so the latter has access to the first vCPU via: RISCVVirtState { RISCVHartArrayState { RISCVCPU *harts; ... } soc[VIRT_SOCKETS_MAX]; ... } s; Directly use that instead of the &first_cpu global. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-ID: <20250112231344.34632-3-philmd@linaro.org> Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 9e8876be29..241389d72f 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -750,7 +750,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, qemu_fdt_add_subnode(ms->fdt, "/cpus"); qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", kvm_enabled() ? - kvm_riscv_get_timebase_frequency(RISCV_CPU(first_cpu)) : + kvm_riscv_get_timebase_frequency(&s->soc->harts[0]) : RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); From patchwork Sun Jan 19 01:12:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944305 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A52A2C02185 for ; Sun, 19 Jan 2025 01:17:10 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJtM-0005io-73; Sat, 18 Jan 2025 20:14:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJtK-0005e1-Lg for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:14:18 -0500 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJtJ-0003Ks-00 for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:14:18 -0500 Received: by mail-pj1-x1034.google.com with SMTP id 98e67ed59e1d1-2ef70c7efa5so4702222a91.2 for ; Sat, 18 Jan 2025 17:14:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249255; x=1737854055; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2LHXMBF6i1q7RRjNkT6ZcWgA0CuRJJd6cB+bhUvNlRg=; b=eZJXade34d3vyLrJrLYM/XHMt7J4za1yjs2jKFqqL7JaeUzUrSKKujY6xbwDTMPRSD BPyq/XBGhKTDKHssIdWJT4ofr/oXmRC1BIdSt1n/fl/s2ggB6QLs/eW9D+o4iz8p27gQ 7KhWC0HNao5c42+XPhyfGkIh/rN2K7wfONP5DaHGu94kxezuM5iyantOftOIx8nJHri1 hhUS7la3M4+SsGImj43cLQNrEEU83e2SKMNP7hQmhbFbdH0TWBI2aY10WHE68hrwkVLc dvA9gj/oOssUybJ+rQ33jY/UWuW+gtyJmPoaCvgGgy7YDcSU2fdXMSDDPXfmtfkU+do7 O6bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249255; x=1737854055; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2LHXMBF6i1q7RRjNkT6ZcWgA0CuRJJd6cB+bhUvNlRg=; b=Ip0wUjaqgDbi2okaZUNXE3iEc7Zc7n0aKc5NVM8Avw7c5sIXPG0DJTk1p3i1GsuP/J ogoLzV4OCNe7YEtUi0OGlFCds1g1iVus4Q1d5+q1Peorn2DE0lQ70jgFiqtcLI1vxtnU ck303mFPcraFSkC2JOSAUBCj2mLmGC94bdGNqlLYbM9s9/So9XuJrLWGrl790cskHMbY xyL9XUtA/1b5HdWFFZ548vGH5dZEwBJUOgpR3w22XmtGjrWGwIcdshcxX541v5OI2qpM 8F1NPiQUuFlYUNwcLjYHZbLcv6mKtLQyp4WI/q2SNJ0O/MxfL/hH+hfMI+0iu7X2kUx/ PItw== X-Gm-Message-State: AOJu0YzqwXjJfpJB3hud8pCj8ymccJpGdjkZaBZ63wrQKCOyehc0bD8n H4uiojQYSk/LLFEbb0tGrCpY2xvWI6VmLh4cUZQFtYvqQKEuEUvCj+T0x4Hp X-Gm-Gg: ASbGncvDtov4EHDUeAXoVr+lV9RvbHSztXMXOqWOVBnSSsUcqP9IrLsOlelPHPiyBWF 4NlggLn/AVHZW4l9R/KDQWdi7LYW579RUNaJH4v5GYLTyUBKst9DatGKLPwOk5O2c9GkE22hJsA 5V+G2AbyWS2aVcHEuL7TydzNcFrU/Hwyd2LTmNBHN0wdZvjWTghWXgOvsiUpRh+en98+6B4n9/3 +g4Dr1hl9Znb9J2/7C55Bj+B/QM9x/NNmgkuvaKf7V2sUXjdH86d9XuHbpAGEtN3/eoRtAEvCrl XAElrl23DZsTnPYUqUyoEwW9ufbvStGK4zRFUxyvpsubl//0ge7bvhwvJIFzytVz9QhWYl6org= = X-Google-Smtp-Source: AGHT+IEssHuh6zF3OwrMK4BngBUfA8Pi6Ix9k8LcgORQLRcvNZPV0DrEY3B1j2PKzF0lQ02BgukG1w== X-Received: by 2002:a17:90b:2dc9:b0:2f6:be57:49cd with SMTP id 98e67ed59e1d1-2f782d306f5mr11166568a91.25.1737249255538; Sat, 18 Jan 2025 17:14:15 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.14.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:14:15 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Kaiwen Xue , Daniel Henrique Barboza , Alistair Francis , Atish Patra Subject: [PULL v2 28/50] target/riscv: Add properties for Indirect CSR Access extension Date: Sun, 19 Jan 2025 11:12:03 +1000 Message-ID: <20250119011225.11452-29-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Kaiwen Xue This adds the properties for sxcsrind. Definitions of new registers and implementations will come with future patches. Signed-off-by: Kaiwen Xue Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-1-e83d797ae294@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 2 ++ target/riscv/cpu.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index ee7c908710..4fe2144ec7 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -79,6 +79,8 @@ struct RISCVCPUConfig { bool ext_smstateen; bool ext_sstc; bool ext_smcntrpmf; + bool ext_smcsrind; + bool ext_sscsrind; bool ext_svadu; bool ext_svinval; bool ext_svnapot; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index dace670e5e..4f5772ae5b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -192,6 +192,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(shvstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), + ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_13_0, ext_smcsrind), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi), ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_13_0, ext_smmpm), @@ -201,6 +202,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), + ISA_EXT_DATA_ENTRY(sscsrind, PRIV_VERSION_1_12_0, ext_sscsrind), ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_13_0, ext_ssnpm), ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), From patchwork Sun Jan 19 01:12:04 2025 Content-Type: text/plain; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.14.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:14:18 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Kaiwen Xue , Alistair Francis , Atish Patra Subject: [PULL v2 29/50] target/riscv: Decouple AIA processing from xiselect and xireg Date: Sun, 19 Jan 2025 11:12:04 +1000 Message-ID: <20250119011225.11452-30-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1029.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Kaiwen Xue Since xiselect and xireg also will be of use in sxcsrind, AIA should have its own separated interface when those CSRs are accessed. Signed-off-by: Kaiwen Xue Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-2-e83d797ae294@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 165 ++++++++++++++++++++++++++++++++++++++------- 1 file changed, 139 insertions(+), 26 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index af9766759a..123e9fd2bd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -29,6 +29,7 @@ #include "system/cpu-timers.h" #include "qemu/guest-random.h" #include "qapi/error.h" +#include /* CSR function table public API */ void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) @@ -305,6 +306,15 @@ static RISCVException aia_any32(CPURISCVState *env, int csrno) return any32(env, csrno); } +static RISCVException csrind_or_aia_any(CPURISCVState *env, int csrno) +{ + if (!riscv_cpu_cfg(env)->ext_smaia && !riscv_cpu_cfg(env)->ext_smcsrind) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return any(env, csrno); +} + static RISCVException smode(CPURISCVState *env, int csrno) { if (riscv_has_ext(env, RVS)) { @@ -341,6 +351,30 @@ static RISCVException aia_smode32(CPURISCVState *env, int csrno) return smode32(env, csrno); } +static bool csrind_extensions_present(CPURISCVState *env) +{ + return riscv_cpu_cfg(env)->ext_smcsrind || riscv_cpu_cfg(env)->ext_sscsrind; +} + +static bool aia_extensions_present(CPURISCVState *env) +{ + return riscv_cpu_cfg(env)->ext_smaia || riscv_cpu_cfg(env)->ext_ssaia; +} + +static bool csrind_or_aia_extensions_present(CPURISCVState *env) +{ + return csrind_extensions_present(env) || aia_extensions_present(env); +} + +static RISCVException csrind_or_aia_smode(CPURISCVState *env, int csrno) +{ + if (!csrind_or_aia_extensions_present(env)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return smode(env, csrno); +} + static RISCVException hmode(CPURISCVState *env, int csrno) { if (riscv_has_ext(env, RVH)) { @@ -360,6 +394,15 @@ static RISCVException hmode32(CPURISCVState *env, int csrno) } +static RISCVException csrind_or_aia_hmode(CPURISCVState *env, int csrno) +{ + if (!csrind_or_aia_extensions_present(env)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return hmode(env, csrno); +} + static RISCVException umode(CPURISCVState *env, int csrno) { if (riscv_has_ext(env, RVU)) { @@ -1969,6 +2012,22 @@ static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno) }; } +static int csrind_xlate_vs_csrno(CPURISCVState *env, int csrno) +{ + if (!env->virt_enabled) { + return csrno; + } + + switch (csrno) { + case CSR_SISELECT: + return CSR_VSISELECT; + case CSR_SIREG: + return CSR_VSIREG; + default: + return csrno; + }; +} + static RISCVException rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *val, target_ulong new_val, target_ulong wr_mask) @@ -1976,7 +2035,7 @@ static RISCVException rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *iselect; /* Translate CSR number for VS-mode */ - csrno = aia_xlate_vs_csrno(env, csrno); + csrno = csrind_xlate_vs_csrno(env, csrno); /* Find the iselect CSR based on CSR number */ switch (csrno) { @@ -2005,6 +2064,12 @@ static RISCVException rmw_xiselect(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static bool xiselect_aia_range(target_ulong isel) +{ + return (ISELECT_IPRIO0 <= isel && isel <= ISELECT_IPRIO15) || + (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST); +} + static int rmw_iprio(target_ulong xlen, target_ulong iselect, uint8_t *iprio, target_ulong *val, target_ulong new_val, @@ -2050,45 +2115,44 @@ static int rmw_iprio(target_ulong xlen, return 0; } -static RISCVException rmw_xireg(CPURISCVState *env, int csrno, - target_ulong *val, target_ulong new_val, - target_ulong wr_mask) +static RISCVException rmw_xireg_aia(CPURISCVState *env, int csrno, + target_ulong isel, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) { - bool virt, isel_reserved; - uint8_t *iprio; + bool virt = false, isel_reserved = false; int ret = -EINVAL; - target_ulong priv, isel, vgein; - - /* Translate CSR number for VS-mode */ - csrno = aia_xlate_vs_csrno(env, csrno); + uint8_t *iprio; + target_ulong priv, vgein; - /* Decode register details from CSR number */ - virt = false; - isel_reserved = false; + /* VS-mode CSR number passed in has already been translated */ switch (csrno) { case CSR_MIREG: + if (!riscv_cpu_cfg(env)->ext_smaia) { + goto done; + } iprio = env->miprio; - isel = env->miselect; priv = PRV_M; break; case CSR_SIREG: - if (env->priv == PRV_S && env->mvien & MIP_SEIP && + if (!riscv_cpu_cfg(env)->ext_ssaia || + (env->priv == PRV_S && env->mvien & MIP_SEIP && env->siselect >= ISELECT_IMSIC_EIDELIVERY && - env->siselect <= ISELECT_IMSIC_EIE63) { + env->siselect <= ISELECT_IMSIC_EIE63)) { goto done; } iprio = env->siprio; - isel = env->siselect; priv = PRV_S; break; case CSR_VSIREG: + if (!riscv_cpu_cfg(env)->ext_ssaia) { + goto done; + } iprio = env->hviprio; - isel = env->vsiselect; priv = PRV_S; virt = true; break; default: - goto done; + goto done; }; /* Find the selected guest interrupt file */ @@ -2119,10 +2183,54 @@ static RISCVException rmw_xireg(CPURISCVState *env, int csrno, } done: + /* + * If AIA is not enabled, illegal instruction exception is always + * returned regardless of whether we are in VS-mode or not + */ if (ret) { return (env->virt_enabled && virt && !isel_reserved) ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; } + + return RISCV_EXCP_NONE; +} + +static RISCVException rmw_xireg(CPURISCVState *env, int csrno, + target_ulong *val, target_ulong new_val, + target_ulong wr_mask) +{ + bool virt = false; + int ret = -EINVAL; + target_ulong isel; + + /* Translate CSR number for VS-mode */ + csrno = csrind_xlate_vs_csrno(env, csrno); + + /* Decode register details from CSR number */ + switch (csrno) { + case CSR_MIREG: + isel = env->miselect; + break; + case CSR_SIREG: + isel = env->siselect; + break; + case CSR_VSIREG: + isel = env->vsiselect; + virt = true; + break; + default: + goto done; + }; + + if (xiselect_aia_range(isel)) { + return rmw_xireg_aia(env, csrno, isel, val, new_val, wr_mask); + } + +done: + if (ret) { + return (env->virt_enabled && virt) ? + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; + } return RISCV_EXCP_NONE; } @@ -4866,8 +4974,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ - [CSR_MISELECT] = { "miselect", aia_any, NULL, NULL, rmw_xiselect }, - [CSR_MIREG] = { "mireg", aia_any, NULL, NULL, rmw_xireg }, + [CSR_MISELECT] = { "miselect", csrind_or_aia_any, NULL, NULL, + rmw_xiselect }, + [CSR_MIREG] = { "mireg", csrind_or_aia_any, NULL, NULL, + rmw_xireg }, /* Machine-Level Interrupts (AIA) */ [CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, @@ -4995,8 +5105,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_SATP] = { "satp", satp, read_satp, write_satp }, /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ - [CSR_SISELECT] = { "siselect", aia_smode, NULL, NULL, rmw_xiselect }, - [CSR_SIREG] = { "sireg", aia_smode, NULL, NULL, rmw_xireg }, + [CSR_SISELECT] = { "siselect", csrind_or_aia_smode, NULL, NULL, + rmw_xiselect }, + [CSR_SIREG] = { "sireg", csrind_or_aia_smode, NULL, NULL, + rmw_xireg }, /* Supervisor-Level Interrupts (AIA) */ [CSR_STOPEI] = { "stopei", aia_smode, NULL, NULL, rmw_xtopei }, @@ -5075,9 +5187,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { /* * VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */ - [CSR_VSISELECT] = { "vsiselect", aia_hmode, NULL, NULL, - rmw_xiselect }, - [CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg }, + [CSR_VSISELECT] = { "vsiselect", csrind_or_aia_hmode, NULL, NULL, + rmw_xiselect }, + [CSR_VSIREG] = { "vsireg", csrind_or_aia_hmode, NULL, NULL, + rmw_xireg }, /* VS-Level Interrupts (H-extension with AIA) */ [CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei }, From patchwork Sun Jan 19 01:12:05 2025 Content-Type: text/plain; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.14.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:14:21 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Atish Patra , Alistair Francis Subject: [PULL v2 30/50] target/riscv: Enable S*stateen bits for AIA Date: Sun, 19 Jan 2025 11:12:05 +1000 Message-ID: <20250119011225.11452-31-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Atish Patra As per the ratified AIA spec v1.0, three stateen bits control AIA CSR access. Bit 60 controls the indirect CSRs Bit 59 controls the most AIA CSR state Bit 58 controls the IMSIC state such as stopei and vstopei Enable the corresponding bits in [m|h]stateen and enable corresponding checks in the CSR accessor functions. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-3-e83d797ae294@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 85 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 84 insertions(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 123e9fd2bd..7f4348fe86 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -335,19 +335,42 @@ static RISCVException smode32(CPURISCVState *env, int csrno) static RISCVException aia_smode(CPURISCVState *env, int csrno) { + int ret; + if (!riscv_cpu_cfg(env)->ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } + if (csrno == CSR_STOPEI) { + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_IMSIC); + } else { + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); + } + + if (ret != RISCV_EXCP_NONE) { + return ret; + } + return smode(env, csrno); } static RISCVException aia_smode32(CPURISCVState *env, int csrno) { + int ret; + if (!riscv_cpu_cfg(env)->ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + + if (ret != RISCV_EXCP_NONE) { + return ret; + } + return smode32(env, csrno); } @@ -576,15 +599,38 @@ static RISCVException hgatp(CPURISCVState *env, int csrno) static RISCVException aia_hmode(CPURISCVState *env, int csrno) { + int ret; + if (!riscv_cpu_cfg(env)->ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } - return hmode(env, csrno); + if (csrno == CSR_VSTOPEI) { + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_IMSIC); + } else { + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); + } + + if (ret != RISCV_EXCP_NONE) { + return ret; + } + + return hmode(env, csrno); } static RISCVException aia_hmode32(CPURISCVState *env, int csrno) { + int ret; + + if (!riscv_cpu_cfg(env)->ext_ssaia) { + return RISCV_EXCP_ILLEGAL_INST; + } + + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + if (!riscv_cpu_cfg(env)->ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } @@ -2033,6 +2079,12 @@ static RISCVException rmw_xiselect(CPURISCVState *env, int csrno, target_ulong wr_mask) { target_ulong *iselect; + int ret; + + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); + if (ret != RISCV_EXCP_NONE) { + return ret; + } /* Translate CSR number for VS-mode */ csrno = csrind_xlate_vs_csrno(env, csrno); @@ -2203,6 +2255,11 @@ static RISCVException rmw_xireg(CPURISCVState *env, int csrno, int ret = -EINVAL; target_ulong isel; + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + /* Translate CSR number for VS-mode */ csrno = csrind_xlate_vs_csrno(env, csrno); @@ -2703,6 +2760,19 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno, wr_mask |= SMSTATEEN0_P1P13; } + if (riscv_cpu_cfg(env)->ext_smaia) { + wr_mask |= SMSTATEEN0_SVSLCT; + } + + /* + * As per the AIA specification, SMSTATEEN0_IMSIC is valid only if IMSIC is + * implemented. However, that information is with MachineState and we can't + * figure that out in csr.c. Just enable if Smaia is available. + */ + if (riscv_cpu_cfg(env)->ext_smaia) { + wr_mask |= (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC); + } + return write_mstateen(env, csrno, wr_mask, new_val); } @@ -2783,6 +2853,19 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno, wr_mask |= SMSTATEEN0_FCSR; } + if (riscv_cpu_cfg(env)->ext_ssaia) { + wr_mask |= SMSTATEEN0_SVSLCT; + } + + /* + * As per the AIA specification, SMSTATEEN0_IMSIC is valid only if IMSIC is + * implemented. However, that information is with MachineState and we can't + * figure that out in csr.c. Just enable if Ssaia is available. + */ + if (riscv_cpu_cfg(env)->ext_ssaia) { + wr_mask |= (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC); + } + return write_hstateen(env, csrno, wr_mask, new_val); } From patchwork Sun Jan 19 01:12:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D15C8C02185 for ; Sun, 19 Jan 2025 01:18:11 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJtY-00078j-Rw; Sat, 18 Jan 2025 20:14:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJtW-0006qn-V2 for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:14:30 -0500 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJtU-0003MY-EU for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:14:30 -0500 Received: by mail-pj1-x102a.google.com with SMTP id 98e67ed59e1d1-2ee74291415so4504498a91.3 for ; Sat, 18 Jan 2025 17:14:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249267; x=1737854067; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q55Z6JAFa4QpEJ8TsmFf/6pKyZUDknBgvusG+66LWAY=; b=X1anMRtet68AQr/o8iQbj5O4S0f87XDDtK/w+0PnM6LUrA1/y2fCCRynpZbFPQ2Skr aFGa3oitIupRN6unSQbvAfyVdYTrXJ23n/BniXKd5ds3tU1LTaU9137jOhqJJNLeecvm SRqfYJZZjGVgabyfqYseyWUV2FXlYlmocsfRY/slJWtCaeN9RF/fWG1PhJEyswZ2KY9d ZKRXDOp4gxcPACQkBRTLeUVvIJv1LFsasDHO07JwSPDYGeOTcN5kunfMON8VBm/QGhSO 2LvwDkaZanLWdMM5eFuxfxk4tX2aakbLQpiZt/XrlNYpXoINt5VkwgcysFxhHMF5GeA9 R2sQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249267; x=1737854067; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q55Z6JAFa4QpEJ8TsmFf/6pKyZUDknBgvusG+66LWAY=; b=mZoUBhmRSTv93WrMxE3WHO6rjSlIyrBcSumLvGQp5ywkHRHJN6jLsnlx6PB6oBLLHn GCPFAGeW4dSTRLNjC7bd4evOzkcTdiJGaga8NjFEBVNV8aOWbiJ0uiutACEoI4AKPsW8 ogdjr4y+TOcqz7Gl/TjakP3CjNKu0FIbRiSVxKheLU9DiM1J/scrvR9KVd9bESMGaZPR kzBH4O8QHgicf6IF0tPOfUseKmv/CfSj7/0chWaDpE2s8Y88ylyiWYk+pwUJc9bXGk+O liKMGYdEId3fk1rYJLLwFpSTaQPZB4a7ewDW/+QT42oMKeyI3LVJxGwWKQmo7XP7yte9 WB4g== X-Gm-Message-State: AOJu0Yzg/YLVM9pNHN+OdMGoKm3UX7D8dme/V53KsXsvKdahyNACwysd irv8W8yYdiovxEbBHXZs8rki1b6A7xYM3KMQbjLPURqnWLkF1cln0Ass8h1t X-Gm-Gg: ASbGncvUKdyxzvfWSx8+pXGNnH8KJUp4ChOoWqVNR4rE1XvVUdHfhfgxLJYvGQmzXRN nF5iODCTuY8PE+GDFVuzPXI9eE/UfKOaJmYTofvJaS5iDiLmScYE7SSuxZOL3V1h8qUIZoCDrEp QunfubjpwI6XQpMUWglzVX7KQFwtGQjZ9Q/sXhyxDhTg2F2cR3HTW+YJQzEDWRekm2FBzRZn5xj fo2/ngv6w/u3GzsNAaDvEHr25xMzlIldYGUvVuf9bT6s1hNivLFPP8QV1MxvwkofgL7GuJrMVar g1wxD3ynPn0Rte7d8+J9HgEFLT/9NqukJw0AVNTW3l5BVOqlqTz7E5TWrRf9YHiBG4o+meGjyA= = X-Google-Smtp-Source: AGHT+IFqA5l8vu+XFmY2lG7jrhHVbjjACqw5FjsbIKcyqMuZ/95KrnbwMC2cB42ie1ugcLJ4RgsQQg== X-Received: by 2002:a17:90a:c2c5:b0:2ee:8008:b583 with SMTP id 98e67ed59e1d1-2f782c9c88fmr12758167a91.16.1737249266783; Sat, 18 Jan 2025 17:14:26 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.14.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:14:25 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Kaiwen Xue , Atish Patra , Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 31/50] target/riscv: Support generic CSR indirect access Date: Sun, 19 Jan 2025 11:12:06 +1000 Message-ID: <20250119011225.11452-32-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Kaiwen Xue This adds the indirect access registers required by sscsrind/smcsrind and the operations on them. Note that xiselect and xireg are used for both AIA and sxcsrind, and the behavior of accessing them depends on whether each extension is enabled and the value stored in xiselect. Co-developed-by: Atish Patra Signed-off-by: Kaiwen Xue Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-4-e83d797ae294@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 28 +++++++- target/riscv/csr.c | 144 ++++++++++++++++++++++++++++++++++++++-- 2 files changed, 166 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index d51f3d8cef..6b1446fb7e 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -173,6 +173,13 @@ #define CSR_MISELECT 0x350 #define CSR_MIREG 0x351 +/* Machine Indirect Register Alias */ +#define CSR_MIREG2 0x352 +#define CSR_MIREG3 0x353 +#define CSR_MIREG4 0x355 +#define CSR_MIREG5 0x356 +#define CSR_MIREG6 0x357 + /* Machine-Level Interrupts (AIA) */ #define CSR_MTOPEI 0x35c #define CSR_MTOPI 0xfb0 @@ -222,6 +229,13 @@ #define CSR_SISELECT 0x150 #define CSR_SIREG 0x151 +/* Supervisor Indirect Register Alias */ +#define CSR_SIREG2 0x152 +#define CSR_SIREG3 0x153 +#define CSR_SIREG4 0x155 +#define CSR_SIREG5 0x156 +#define CSR_SIREG6 0x157 + /* Supervisor-Level Interrupts (AIA) */ #define CSR_STOPEI 0x15c #define CSR_STOPI 0xdb0 @@ -288,6 +302,13 @@ #define CSR_VSISELECT 0x250 #define CSR_VSIREG 0x251 +/* Virtual Supervisor Indirect Alias */ +#define CSR_VSIREG2 0x252 +#define CSR_VSIREG3 0x253 +#define CSR_VSIREG4 0x255 +#define CSR_VSIREG5 0x256 +#define CSR_VSIREG6 0x257 + /* VS-Level Interrupts (H-extension with AIA) */ #define CSR_VSTOPEI 0x25c #define CSR_VSTOPI 0xeb0 @@ -803,10 +824,13 @@ typedef enum RISCVException { #define ISELECT_IMSIC_EIE63 0xff #define ISELECT_IMSIC_FIRST ISELECT_IMSIC_EIDELIVERY #define ISELECT_IMSIC_LAST ISELECT_IMSIC_EIE63 -#define ISELECT_MASK 0x1ff +#define ISELECT_MASK_AIA 0x1ff + +/* MISELECT, SISELECT, and VSISELECT bits (AIA) */ +#define ISELECT_MASK_SXCSRIND 0xfff /* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */ -#define ISELECT_IMSIC_TOPEI (ISELECT_MASK + 1) +#define ISELECT_IMSIC_TOPEI (ISELECT_MASK_AIA + 1) /* IMSIC bits (AIA) */ #define IMSIC_TOPEI_IID_SHIFT 16 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 7f4348fe86..49648ddc95 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -306,6 +306,15 @@ static RISCVException aia_any32(CPURISCVState *env, int csrno) return any32(env, csrno); } +static RISCVException csrind_any(CPURISCVState *env, int csrno) +{ + if (!riscv_cpu_cfg(env)->ext_smcsrind) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return RISCV_EXCP_NONE; +} + static RISCVException csrind_or_aia_any(CPURISCVState *env, int csrno) { if (!riscv_cpu_cfg(env)->ext_smaia && !riscv_cpu_cfg(env)->ext_smcsrind) { @@ -389,6 +398,15 @@ static bool csrind_or_aia_extensions_present(CPURISCVState *env) return csrind_extensions_present(env) || aia_extensions_present(env); } +static RISCVException csrind_smode(CPURISCVState *env, int csrno) +{ + if (!csrind_extensions_present(env)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return smode(env, csrno); +} + static RISCVException csrind_or_aia_smode(CPURISCVState *env, int csrno) { if (!csrind_or_aia_extensions_present(env)) { @@ -417,6 +435,15 @@ static RISCVException hmode32(CPURISCVState *env, int csrno) } +static RISCVException csrind_hmode(CPURISCVState *env, int csrno) +{ + if (!csrind_extensions_present(env)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return hmode(env, csrno); +} + static RISCVException csrind_or_aia_hmode(CPURISCVState *env, int csrno) { if (!csrind_or_aia_extensions_present(env)) { @@ -2068,7 +2095,12 @@ static int csrind_xlate_vs_csrno(CPURISCVState *env, int csrno) case CSR_SISELECT: return CSR_VSISELECT; case CSR_SIREG: - return CSR_VSIREG; + case CSR_SIREG2: + case CSR_SIREG3: + case CSR_SIREG4: + case CSR_SIREG5: + case CSR_SIREG6: + return CSR_VSIREG + (csrno - CSR_SIREG); default: return csrno; }; @@ -2108,7 +2140,12 @@ static RISCVException rmw_xiselect(CPURISCVState *env, int csrno, *val = *iselect; } - wr_mask &= ISELECT_MASK; + if (riscv_cpu_cfg(env)->ext_smcsrind || riscv_cpu_cfg(env)->ext_sscsrind) { + wr_mask &= ISELECT_MASK_SXCSRIND; + } else { + wr_mask &= ISELECT_MASK_AIA; + } + if (wr_mask) { *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask); } @@ -2247,6 +2284,56 @@ done: return RISCV_EXCP_NONE; } +/* + * rmw_xireg_csrind: Perform indirect access to xireg and xireg2-xireg6 + * + * Perform indirect access to xireg and xireg2-xireg6. + * This is a generic interface for all xireg CSRs. Apart from AIA, all other + * extension using csrind should be implemented here. + */ +static int rmw_xireg_csrind(CPURISCVState *env, int csrno, + target_ulong isel, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) +{ + return -EINVAL; +} + +static int rmw_xiregi(CPURISCVState *env, int csrno, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) +{ + bool virt = false; + int ret = -EINVAL; + target_ulong isel; + + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + + /* Translate CSR number for VS-mode */ + csrno = csrind_xlate_vs_csrno(env, csrno); + + if (CSR_MIREG <= csrno && csrno <= CSR_MIREG6 && + csrno != CSR_MIREG4 - 1) { + isel = env->miselect; + } else if (CSR_SIREG <= csrno && csrno <= CSR_SIREG6 && + csrno != CSR_SIREG4 - 1) { + isel = env->siselect; + } else if (CSR_VSIREG <= csrno && csrno <= CSR_VSIREG6 && + csrno != CSR_VSIREG4 - 1) { + isel = env->vsiselect; + virt = true; + } else { + goto done; + } + + return rmw_xireg_csrind(env, csrno, isel, val, new_val, wr_mask); + +done: + return (env->virt_enabled && virt) ? + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; +} + static RISCVException rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val, target_ulong new_val, target_ulong wr_mask) @@ -2279,8 +2366,21 @@ static RISCVException rmw_xireg(CPURISCVState *env, int csrno, goto done; }; + /* + * Use the xiselect range to determine actual op on xireg. + * + * Since we only checked the existence of AIA or Indirect Access in the + * predicate, we should check the existence of the exact extension when + * we get to a specific range and return illegal instruction exception even + * in VS-mode. + */ if (xiselect_aia_range(isel)) { return rmw_xireg_aia(env, csrno, isel, val, new_val, wr_mask); + } else if (riscv_cpu_cfg(env)->ext_smcsrind || + riscv_cpu_cfg(env)->ext_sscsrind) { + return rmw_xireg_csrind(env, csrno, isel, val, new_val, wr_mask); + } else { + return RISCV_EXCP_ILLEGAL_INST; } done: @@ -2760,7 +2860,7 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno, wr_mask |= SMSTATEEN0_P1P13; } - if (riscv_cpu_cfg(env)->ext_smaia) { + if (riscv_cpu_cfg(env)->ext_smaia || riscv_cpu_cfg(env)->ext_smcsrind) { wr_mask |= SMSTATEEN0_SVSLCT; } @@ -2853,7 +2953,7 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno, wr_mask |= SMSTATEEN0_FCSR; } - if (riscv_cpu_cfg(env)->ext_ssaia) { + if (riscv_cpu_cfg(env)->ext_ssaia || riscv_cpu_cfg(env)->ext_sscsrind) { wr_mask |= SMSTATEEN0_SVSLCT; } @@ -5062,6 +5162,18 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MIREG] = { "mireg", csrind_or_aia_any, NULL, NULL, rmw_xireg }, + /* Machine Indirect Register Alias */ + [CSR_MIREG2] = { "mireg2", csrind_any, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MIREG3] = { "mireg3", csrind_any, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MIREG4] = { "mireg4", csrind_any, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MIREG5] = { "mireg5", csrind_any, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MIREG6] = { "mireg6", csrind_any, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + /* Machine-Level Interrupts (AIA) */ [CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, [CSR_MTOPI] = { "mtopi", aia_any, read_mtopi }, @@ -5193,6 +5305,18 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_SIREG] = { "sireg", csrind_or_aia_smode, NULL, NULL, rmw_xireg }, + /* Supervisor Indirect Register Alias */ + [CSR_SIREG2] = { "sireg2", csrind_smode, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_SIREG3] = { "sireg3", csrind_smode, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_SIREG4] = { "sireg4", csrind_smode, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_SIREG5] = { "sireg5", csrind_smode, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_SIREG6] = { "sireg6", csrind_smode, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + /* Supervisor-Level Interrupts (AIA) */ [CSR_STOPEI] = { "stopei", aia_smode, NULL, NULL, rmw_xtopei }, [CSR_STOPI] = { "stopi", aia_smode, read_stopi }, @@ -5275,6 +5399,18 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_VSIREG] = { "vsireg", csrind_or_aia_hmode, NULL, NULL, rmw_xireg }, + /* Virtual Supervisor Indirect Alias */ + [CSR_VSIREG2] = { "vsireg2", csrind_hmode, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSIREG3] = { "vsireg3", csrind_hmode, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSIREG4] = { "vsireg4", csrind_hmode, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSIREG5] = { "vsireg5", csrind_hmode, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSIREG6] = { "vsireg6", csrind_hmode, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + /* VS-Level Interrupts (H-extension with AIA) */ [CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei }, [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi }, From patchwork Sun Jan 19 01:12:07 2025 Content-Type: text/plain; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.14.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:14:29 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Atish Patra , Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 32/50] target/riscv: Add properties for counter delegation ISA extensions Date: Sun, 19 Jan 2025 11:12:07 +1000 Message-ID: <20250119011225.11452-33-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Atish Patra This adds the properties for counter delegation ISA extensions (Smcdeleg/Ssccfg). Definitions of new registers and and implementation will come in the next set of patches. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-5-e83d797ae294@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 2 ++ target/riscv/cpu.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 4fe2144ec7..561f5119b6 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -78,6 +78,8 @@ struct RISCVCPUConfig { bool ext_ztso; bool ext_smstateen; bool ext_sstc; + bool ext_smcdeleg; + bool ext_ssccfg; bool ext_smcntrpmf; bool ext_smcsrind; bool ext_sscsrind; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4f5772ae5b..da40f68715 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -191,6 +191,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(shvstvala, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(shvstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), + ISA_EXT_DATA_ENTRY(smcdeleg, PRIV_VERSION_1_13_0, ext_smcdeleg), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_13_0, ext_smcsrind), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), @@ -199,6 +200,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(smnpm, PRIV_VERSION_1_13_0, ext_smnpm), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), + ISA_EXT_DATA_ENTRY(ssccfg, PRIV_VERSION_1_13_0, ext_ssccfg), ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), From patchwork Sun Jan 19 01:12:08 2025 Content-Type: text/plain; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.14.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:14:33 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Kaiwen Xue , Alistair Francis , Atish Patra Subject: [PULL v2 33/50] target/riscv: Add counter delegation definitions Date: Sun, 19 Jan 2025 11:12:08 +1000 Message-ID: <20250119011225.11452-34-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Kaiwen Xue This adds definitions for counter delegation, including the new scountinhibit register and the mstateen.CD bit. Signed-off-by: Kaiwen Xue Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-6-e83d797ae294@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 8 +++++++- target/riscv/machine.c | 1 + 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 08215efb09..a936300103 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -392,6 +392,7 @@ struct CPUArchState { uint32_t scounteren; uint32_t mcounteren; + uint32_t scountinhibit; uint32_t mcountinhibit; /* PMU cycle & instret privilege mode filtering */ diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 6b1446fb7e..73f7d37d80 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -210,6 +210,9 @@ #define CSR_SSTATEEN2 0x10E #define CSR_SSTATEEN3 0x10F +/* Supervisor Counter Delegation */ +#define CSR_SCOUNTINHIBIT 0x120 + /* Supervisor Trap Handling */ #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 @@ -779,6 +782,7 @@ typedef enum RISCVException { #define MENVCFG_CBCFE BIT(6) #define MENVCFG_CBZE BIT(7) #define MENVCFG_PMM (3ULL << 32) +#define MENVCFG_CDE (1ULL << 60) #define MENVCFG_ADUE (1ULL << 61) #define MENVCFG_PBMTE (1ULL << 62) #define MENVCFG_STCE (1ULL << 63) @@ -826,7 +830,9 @@ typedef enum RISCVException { #define ISELECT_IMSIC_LAST ISELECT_IMSIC_EIE63 #define ISELECT_MASK_AIA 0x1ff -/* MISELECT, SISELECT, and VSISELECT bits (AIA) */ +/* [M|S|VS]SELCT value for Indirect CSR Access Extension */ +#define ISELECT_CD_FIRST 0x40 +#define ISELECT_CD_LAST 0x5f #define ISELECT_MASK_SXCSRIND 0xfff /* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */ diff --git a/target/riscv/machine.c b/target/riscv/machine.c index d81621010d..d8445244ab 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -423,6 +423,7 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINTTL(env.siselect, RISCVCPU), VMSTATE_UINT32(env.scounteren, RISCVCPU), VMSTATE_UINT32(env.mcounteren, RISCVCPU), + VMSTATE_UINT32(env.scountinhibit, RISCVCPU), VMSTATE_UINT32(env.mcountinhibit, RISCVCPU), VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0, vmstate_pmu_ctr_state, PMUCTRState), From patchwork Sun Jan 19 01:12:09 2025 Content-Type: text/plain; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.14.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:14:37 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Kaiwen Xue , Atish Patra , Alistair Francis Subject: [PULL v2 34/50] target/riscv: Add select value range check for counter delegation Date: Sun, 19 Jan 2025 11:12:09 +1000 Message-ID: <20250119011225.11452-35-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Kaiwen Xue This adds checks in ops performed on xireg and xireg2-xireg6 so that the counter delegation function will receive a valid xiselect value with the proper extensions enabled. Co-developed-by: Atish Patra Signed-off-by: Kaiwen Xue Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-7-e83d797ae294@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 49648ddc95..df748dffa3 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2159,6 +2159,11 @@ static bool xiselect_aia_range(target_ulong isel) (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST); } +static bool xiselect_cd_range(target_ulong isel) +{ + return (ISELECT_CD_FIRST <= isel && isel <= ISELECT_CD_LAST); +} + static int rmw_iprio(target_ulong xlen, target_ulong iselect, uint8_t *iprio, target_ulong *val, target_ulong new_val, @@ -2284,6 +2289,17 @@ done: return RISCV_EXCP_NONE; } +static int rmw_xireg_cd(CPURISCVState *env, int csrno, + target_ulong isel, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) +{ + if (!riscv_cpu_cfg(env)->ext_smcdeleg) { + return RISCV_EXCP_ILLEGAL_INST; + } + /* TODO: Implement the functionality later */ + return RISCV_EXCP_NONE; +} + /* * rmw_xireg_csrind: Perform indirect access to xireg and xireg2-xireg6 * @@ -2295,7 +2311,25 @@ static int rmw_xireg_csrind(CPURISCVState *env, int csrno, target_ulong isel, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { - return -EINVAL; + int ret = -EINVAL; + bool virt = csrno == CSR_VSIREG ? true : false; + + if (xiselect_cd_range(isel)) { + ret = rmw_xireg_cd(env, csrno, isel, val, new_val, wr_mask); + } else { + /* + * As per the specification, access to unimplented region is undefined + * but recommendation is to raise illegal instruction exception. + */ + return RISCV_EXCP_ILLEGAL_INST; + } + + if (ret) { + return (env->virt_enabled && virt) ? + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; + } + + return RISCV_EXCP_NONE; } static int rmw_xiregi(CPURISCVState *env, int csrno, target_ulong *val, From patchwork Sun Jan 19 01:12:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944324 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72518C02187 for ; Sun, 19 Jan 2025 01:18:52 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJtq-0000Lf-B1; Sat, 18 Jan 2025 20:14:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJtm-0008VC-KT for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:14:46 -0500 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJtj-0003Om-R9 for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:14:46 -0500 Received: by mail-pj1-x102f.google.com with SMTP id 98e67ed59e1d1-2efd81c7ca4so4507385a91.2 for ; Sat, 18 Jan 2025 17:14:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249282; x=1737854082; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YbQ2GKWxA4aqDx/5bcHhQQIo5ehgVzih+lXxpGtXsbQ=; b=mWdShhD4S7nEh1RnBfDiUzSFBmGh0+lhCzAaG52k/tarNhXv/qfFytQ6gMDopvpX0v 9FfJpssvB3bX2hl+5KCOd6RdGuoGeRRxLa6hW6K2zsdDBEnVtfR239YvF85W1nf6kP76 +dUeaT6i1MtEh6xKMr4arLwSzTWmX6WaVmfhVy7AV3BGNnMLGK0t+2QhwXsvT8jxC3RX hnarqOhuv68MIg52UKlSkj37HBYZYeiR3Bdd2GVaQZD452BbtdYpCld4LtdHDFMej7mw UEAzu+hztOrQ+huzgbyHoCzb0R23ntAFG0UzP40rJeAqMzGflbN/63e8rwVo73iuZGcn MuaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249282; x=1737854082; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YbQ2GKWxA4aqDx/5bcHhQQIo5ehgVzih+lXxpGtXsbQ=; b=V8SOoRStqByLygwrCmNTbykw234w8pUNkrsxtc3Kk6rltMQOrAQ3sG8Go6qoRuOhne TtuksQkNlXSSTuFxlEoenPX9SO1uJ4rToQv6IiRJW/kyNTc70DhuHj4VSSMKPL16vDxM +T8NPROSfkFfVQRb83PcA1eHaVkCqg3fGZZJiR6vRFUz+TQvFpG9A0H0YQNVQ2NjZ/f0 d9wjz78BZ8QkJZ/dsJ1djED1LRx71obAeaZl0YFk6YigCHg239i4KuShJSZiPQfjDm2a lLL9OcCegT1W2dnukvNcVIuUHFR1HiVkkhNejW3LlzuJJzpmxHaojeRrbJO1TCwk/J9Z 4SKg== X-Gm-Message-State: AOJu0YxkiJuD49ixiemOhhBA+pCz7H0GMe+lagjmugHWArZTn2jMY4po jZaePxB2GNLdEKUSchLvzxGPuA/fxHHWUx4UGIk+tYV/M/unNj48VNyVgVQr X-Gm-Gg: ASbGncs9XMKUy1cOKHSDKSfovkEve3QjEQxCm35A+5VEZMn6lQSp87TC2tlLa+gQ/NK vydS4M9P4zTNbrLj+O3CqhngfmlAUM7okn2xZwwOq+dc0OaXq3mJ7+83Mo+2exRvv4sIf/Cw6w/ eSaOYc7noz9Ikc5+xqLhIesJULKCNq96UX7vOk+LrXsgGC4wG9DMVJftA1+w780mWFnvC091Vhy OqeEjGmG+hddYeUmvm5e+feD8GAaiIxSJE4ORvkbFPQqTs3/OI9zLHLwP4WxGscNkjVuX8Qgh44 O2M/RF8cY4Lt0VFMvMyF/nGnuqKyRFYjdxoIdMifVUWzQnWDaUTDgvueSo8cONvONSdd2I9i6A= = X-Google-Smtp-Source: AGHT+IFj9B3qnqoP3SkXOvdc9ETqBeXe8UrSL1VnvX8k/zEBv9q9dO41pq52zYcwN/4qzji3al4KZw== X-Received: by 2002:a17:90a:c888:b0:2ee:f687:6ad5 with SMTP id 98e67ed59e1d1-2f782c5174emr12530066a91.2.1737249282054; Sat, 18 Jan 2025 17:14:42 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.14.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:14:41 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Kaiwen Xue , Atish Patra , Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 35/50] target/riscv: Add counter delegation/configuration support Date: Sun, 19 Jan 2025 11:12:10 +1000 Message-ID: <20250119011225.11452-36-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Kaiwen Xue The Smcdeleg/Ssccfg adds the support for counter delegation via S*indcsr and Ssccfg. It also adds a new shadow CSR scountinhibit and menvcfg enable bit (CDE) to enable this extension and scountovf virtualization. Signed-off-by: Kaiwen Xue Co-developed-by: Atish Patra Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-8-e83d797ae294@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 304 +++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 292 insertions(+), 12 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index df748dffa3..eddcf5a5d0 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -383,6 +383,21 @@ static RISCVException aia_smode32(CPURISCVState *env, int csrno) return smode32(env, csrno); } +static RISCVException scountinhibit_pred(CPURISCVState *env, int csrno) +{ + RISCVCPU *cpu = env_archcpu(env); + + if (!cpu->cfg.ext_ssccfg || !cpu->cfg.ext_smcdeleg) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (env->virt_enabled) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + + return smode(env, csrno); +} + static bool csrind_extensions_present(CPURISCVState *env) { return riscv_cpu_cfg(env)->ext_smcsrind || riscv_cpu_cfg(env)->ext_sscsrind; @@ -1224,10 +1239,9 @@ done: return result; } -static RISCVException write_mhpmcounter(CPURISCVState *env, int csrno, - target_ulong val) +static RISCVException riscv_pmu_write_ctr(CPURISCVState *env, target_ulong val, + uint32_t ctr_idx) { - int ctr_idx = csrno - CSR_MCYCLE; PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; uint64_t mhpmctr_val = val; @@ -1252,10 +1266,9 @@ static RISCVException write_mhpmcounter(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static RISCVException write_mhpmcounterh(CPURISCVState *env, int csrno, - target_ulong val) +static RISCVException riscv_pmu_write_ctrh(CPURISCVState *env, target_ulong val, + uint32_t ctr_idx) { - int ctr_idx = csrno - CSR_MCYCLEH; PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; uint64_t mhpmctr_val = counter->mhpmcounter_val; uint64_t mhpmctrh_val = val; @@ -1277,6 +1290,20 @@ static RISCVException write_mhpmcounterh(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong val) +{ + int ctr_idx = csrno - CSR_MCYCLE; + + return riscv_pmu_write_ctr(env, val, ctr_idx); +} + +static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong val) +{ + int ctr_idx = csrno - CSR_MCYCLEH; + + return riscv_pmu_write_ctrh(env, val, ctr_idx); +} + RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val, bool upper_half, uint32_t ctr_idx) { @@ -1342,6 +1369,167 @@ static RISCVException read_hpmcounterh(CPURISCVState *env, int csrno, return riscv_pmu_read_ctr(env, val, true, ctr_index); } +static int rmw_cd_mhpmcounter(CPURISCVState *env, int ctr_idx, + target_ulong *val, target_ulong new_val, + target_ulong wr_mask) +{ + if (wr_mask != 0 && wr_mask != -1) { + return -EINVAL; + } + + if (!wr_mask && val) { + riscv_pmu_read_ctr(env, val, false, ctr_idx); + } else if (wr_mask) { + riscv_pmu_write_ctr(env, new_val, ctr_idx); + } else { + return -EINVAL; + } + + return 0; +} + +static int rmw_cd_mhpmcounterh(CPURISCVState *env, int ctr_idx, + target_ulong *val, target_ulong new_val, + target_ulong wr_mask) +{ + if (wr_mask != 0 && wr_mask != -1) { + return -EINVAL; + } + + if (!wr_mask && val) { + riscv_pmu_read_ctr(env, val, true, ctr_idx); + } else if (wr_mask) { + riscv_pmu_write_ctrh(env, new_val, ctr_idx); + } else { + return -EINVAL; + } + + return 0; +} + +static int rmw_cd_mhpmevent(CPURISCVState *env, int evt_index, + target_ulong *val, target_ulong new_val, + target_ulong wr_mask) +{ + uint64_t mhpmevt_val = new_val; + + if (wr_mask != 0 && wr_mask != -1) { + return -EINVAL; + } + + if (!wr_mask && val) { + *val = env->mhpmevent_val[evt_index]; + if (riscv_cpu_cfg(env)->ext_sscofpmf) { + *val &= ~MHPMEVENT_BIT_MINH; + } + } else if (wr_mask) { + wr_mask &= ~MHPMEVENT_BIT_MINH; + mhpmevt_val = (new_val & wr_mask) | + (env->mhpmevent_val[evt_index] & ~wr_mask); + if (riscv_cpu_mxl(env) == MXL_RV32) { + mhpmevt_val = mhpmevt_val | + ((uint64_t)env->mhpmeventh_val[evt_index] << 32); + } + env->mhpmevent_val[evt_index] = mhpmevt_val; + riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); + } else { + return -EINVAL; + } + + return 0; +} + +static int rmw_cd_mhpmeventh(CPURISCVState *env, int evt_index, + target_ulong *val, target_ulong new_val, + target_ulong wr_mask) +{ + uint64_t mhpmevth_val; + uint64_t mhpmevt_val = env->mhpmevent_val[evt_index]; + + if (wr_mask != 0 && wr_mask != -1) { + return -EINVAL; + } + + if (!wr_mask && val) { + *val = env->mhpmeventh_val[evt_index]; + if (riscv_cpu_cfg(env)->ext_sscofpmf) { + *val &= ~MHPMEVENTH_BIT_MINH; + } + } else if (wr_mask) { + wr_mask &= ~MHPMEVENTH_BIT_MINH; + env->mhpmeventh_val[evt_index] = + (new_val & wr_mask) | (env->mhpmeventh_val[evt_index] & ~wr_mask); + mhpmevth_val = env->mhpmeventh_val[evt_index]; + mhpmevt_val = mhpmevt_val | (mhpmevth_val << 32); + riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); + } else { + return -EINVAL; + } + + return 0; +} + +static int rmw_cd_ctr_cfg(CPURISCVState *env, int cfg_index, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) +{ + switch (cfg_index) { + case 0: /* CYCLECFG */ + if (wr_mask) { + wr_mask &= ~MCYCLECFG_BIT_MINH; + env->mcyclecfg = (new_val & wr_mask) | (env->mcyclecfg & ~wr_mask); + } else { + *val = env->mcyclecfg &= ~MHPMEVENTH_BIT_MINH; + } + break; + case 2: /* INSTRETCFG */ + if (wr_mask) { + wr_mask &= ~MINSTRETCFG_BIT_MINH; + env->minstretcfg = (new_val & wr_mask) | + (env->minstretcfg & ~wr_mask); + } else { + *val = env->minstretcfg &= ~MHPMEVENTH_BIT_MINH; + } + break; + default: + return -EINVAL; + } + return 0; +} + +static int rmw_cd_ctr_cfgh(CPURISCVState *env, int cfg_index, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) +{ + + if (riscv_cpu_mxl(env) != MXL_RV32) { + return RISCV_EXCP_ILLEGAL_INST; + } + + switch (cfg_index) { + case 0: /* CYCLECFGH */ + if (wr_mask) { + wr_mask &= ~MCYCLECFGH_BIT_MINH; + env->mcyclecfgh = (new_val & wr_mask) | + (env->mcyclecfgh & ~wr_mask); + } else { + *val = env->mcyclecfgh; + } + break; + case 2: /* INSTRETCFGH */ + if (wr_mask) { + wr_mask &= ~MINSTRETCFGH_BIT_MINH; + env->minstretcfgh = (new_val & wr_mask) | + (env->minstretcfgh & ~wr_mask); + } else { + *val = env->minstretcfgh; + } + break; + default: + return -EINVAL; + } + return 0; +} + + static RISCVException read_scountovf(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1351,6 +1539,14 @@ static RISCVException read_scountovf(CPURISCVState *env, int csrno, target_ulong *mhpm_evt_val; uint64_t of_bit_mask; + /* Virtualize scountovf for counter delegation */ + if (riscv_cpu_cfg(env)->ext_sscofpmf && + riscv_cpu_cfg(env)->ext_ssccfg && + get_field(env->menvcfg, MENVCFG_CDE) && + env->virt_enabled) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + if (riscv_cpu_mxl(env) == MXL_RV32) { mhpm_evt_val = env->mhpmeventh_val; of_bit_mask = MHPMEVENTH_BIT_OF; @@ -2293,11 +2489,72 @@ static int rmw_xireg_cd(CPURISCVState *env, int csrno, target_ulong isel, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { - if (!riscv_cpu_cfg(env)->ext_smcdeleg) { - return RISCV_EXCP_ILLEGAL_INST; + int ret = -EINVAL; + int ctr_index = isel - ISELECT_CD_FIRST; + int isel_hpm_start = ISELECT_CD_FIRST + 3; + + if (!riscv_cpu_cfg(env)->ext_smcdeleg || !riscv_cpu_cfg(env)->ext_ssccfg) { + ret = RISCV_EXCP_ILLEGAL_INST; + goto done; } - /* TODO: Implement the functionality later */ - return RISCV_EXCP_NONE; + + /* Invalid siselect value for reserved */ + if (ctr_index == 1) { + goto done; + } + + /* sireg4 and sireg5 provides access RV32 only CSRs */ + if (((csrno == CSR_SIREG5) || (csrno == CSR_SIREG4)) && + (riscv_cpu_mxl(env) != MXL_RV32)) { + ret = RISCV_EXCP_ILLEGAL_INST; + goto done; + } + + /* Check Sscofpmf dependancy */ + if (!riscv_cpu_cfg(env)->ext_sscofpmf && csrno == CSR_SIREG5 && + (isel_hpm_start <= isel && isel <= ISELECT_CD_LAST)) { + goto done; + } + + /* Check smcntrpmf dependancy */ + if (!riscv_cpu_cfg(env)->ext_smcntrpmf && + (csrno == CSR_SIREG2 || csrno == CSR_SIREG5) && + (ISELECT_CD_FIRST <= isel && isel < isel_hpm_start)) { + goto done; + } + + if (!get_field(env->mcounteren, BIT(ctr_index)) || + !get_field(env->menvcfg, MENVCFG_CDE)) { + goto done; + } + + switch (csrno) { + case CSR_SIREG: + ret = rmw_cd_mhpmcounter(env, ctr_index, val, new_val, wr_mask); + break; + case CSR_SIREG4: + ret = rmw_cd_mhpmcounterh(env, ctr_index, val, new_val, wr_mask); + break; + case CSR_SIREG2: + if (ctr_index <= 2) { + ret = rmw_cd_ctr_cfg(env, ctr_index, val, new_val, wr_mask); + } else { + ret = rmw_cd_mhpmevent(env, ctr_index, val, new_val, wr_mask); + } + break; + case CSR_SIREG5: + if (ctr_index <= 2) { + ret = rmw_cd_ctr_cfgh(env, ctr_index, val, new_val, wr_mask); + } else { + ret = rmw_cd_mhpmeventh(env, ctr_index, val, new_val, wr_mask); + } + break; + default: + goto done; + } + +done: + return ret; } /* @@ -2576,6 +2833,21 @@ static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static RISCVException read_scountinhibit(CPURISCVState *env, int csrno, + target_ulong *val) +{ + /* S-mode can only access the bits delegated by M-mode */ + *val = env->mcountinhibit & env->mcounteren; + return RISCV_EXCP_NONE; +} + +static RISCVException write_scountinhibit(CPURISCVState *env, int csrno, + target_ulong val) +{ + write_mcountinhibit(env, csrno, val & env->mcounteren); + return RISCV_EXCP_NONE; +} + static RISCVException read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val) { @@ -2678,11 +2950,13 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno, target_ulong val) { const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); - uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE; + uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | + MENVCFG_CBZE | MENVCFG_CDE; if (riscv_cpu_mxl(env) == MXL_RV64) { mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | + (cfg->ext_smcdeleg ? MENVCFG_CDE : 0) | (cfg->ext_svadu ? MENVCFG_ADUE : 0); if (env_archcpu(env)->cfg.ext_zicfilp) { @@ -2717,7 +2991,8 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | - (cfg->ext_svadu ? MENVCFG_ADUE : 0); + (cfg->ext_svadu ? MENVCFG_ADUE : 0) | + (cfg->ext_smcdeleg ? MENVCFG_CDE : 0); uint64_t valh = (uint64_t)val << 32; env->menvcfg = (env->menvcfg & ~mask) | (valh & mask); @@ -5304,6 +5579,11 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MNSTATUS] = { "mnstatus", rnmi, read_mnstatus, write_mnstatus, .min_priv_ver = PRIV_VERSION_1_12_0 }, + /* Supervisor Counter Delegation */ + [CSR_SCOUNTINHIBIT] = {"scountinhibit", scountinhibit_pred, + read_scountinhibit, write_scountinhibit, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + /* Supervisor Trap Setup */ [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, NULL, read_sstatus_i128 }, From patchwork Sun Jan 19 01:12:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944329 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 85D7EC02185 for ; Sun, 19 Jan 2025 01:19:42 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJts-0000ba-2c; Sat, 18 Jan 2025 20:14:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJtp-0000LA-8U for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:14:49 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJtn-0003PU-C7 for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:14:48 -0500 Received: by mail-pj1-x1031.google.com with SMTP id 98e67ed59e1d1-2f43da61ba9so4501234a91.2 for ; Sat, 18 Jan 2025 17:14:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249285; x=1737854085; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tBdLRF0uol7FqBm4EOyL0TOCyZ3ye1dx/esQnUs6Ug0=; b=FdnrPXpcHPtFkJCcU+xzcMiVmdNcARHb9QaMSPjxTtFTErPUi9WR7FcmW/R4V0wAal i94fVNkYuI4mV3WREVtaom4gp4+tMov1z7AlkeeFTVwD9bBvUJF8U9Fagcm+x+4odjIr bBATkKjDPWkuezkFINYOH/espA7yPY8p0NFhBfbUJXWrhkgHRJIumu924rrNyM7bCkXI Mn+KZL/bENWafyDRoPcZkhk7hQV5Re0826UaC3+NaFjfzI2vdWPFLE4k7ddG2ZWpqabY XyB5Sb+dbIgoLcSBXyV+TDpH90pml0kM7+SC/sSk0nQZpiRj44OtAa8sn10oKJODjUQZ VBJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249285; x=1737854085; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tBdLRF0uol7FqBm4EOyL0TOCyZ3ye1dx/esQnUs6Ug0=; b=vpqOIl6QMzPoTK3SZraMRmhRVvkTRdvz+cIrbYwkkKu/BbpzDuJVYGS+zxfodd0lwF pV0Img5y0b529uevChGWqt7E7lr/gMHd0MAZB3QcaDSwKoGL4pHvs4IvNsmP4ad50eB1 nrM6Ls7rvisR2XArQ5YSCES758gamSrLW7hQe60wYVqeu95Mfit7OETSfkNBQsuMJfts dYQy+k3CjUZm8WgQY/bKpybWeYwncdoQCD9gGJz/+G+CP4Fr0P6DNQ2PdAWB/LYFXpap PrZ77DY2SZJNfmJ5EFTV4X7lR6INhlO+njyspjbtAkRaHChaUl+OFjLCuIEZAJKQGyUT w57A== X-Gm-Message-State: AOJu0YzGWP3qS/tfYSymuT2bCqlrxBQsxymqA8QgJNFQ4ax24UEwcQis WXXAsokMZgwMRSbz152TfcyLa5nk1HQFQJiWtaT/TROQQMk0gX7N8k6NhkJp X-Gm-Gg: ASbGncs7Ve6WnjkIt1mEDhE8zgWpBGvuWEHjfoGXM8Po6Jc8EnCZ7h4aKMsKEsYfOS3 8b7b356u5u8uEyjE+DjnOiDrUsmB1hc3nI1IrOYnmS9CObsvBrx06ojXyCwata4q6WWx0T3TPKT P1BK0JfsIV/tXLBl5kyEm24PB4nvkgGcXhtXnF0TfiNEAlY+l8ok/vKxuezYVlY/qsbdw+Vd+6T 9EjjtSGQAEgWIX5F1a/KXCSyhBfmlYWty4aMQXZORjqHlpd5jYYmDHT7GfXgR+KuFSMu0Ma8R8S TaCS8Pn3rvajOsjvNYjGsKmslFJUHmvT7I5v0SzpKlaQBfiJvlSSJHNpLfxlWWV8mTNAhgHXiw= = X-Google-Smtp-Source: AGHT+IEWOT1KSj31fkWKAt7f7vcncsB9UzhvONskoP6hc7GcpVCrU+ncPIkzvpVAv3yOc5muAzXm2w== X-Received: by 2002:a17:90b:5146:b0:2ee:c04a:4281 with SMTP id 98e67ed59e1d1-2f782c6579dmr10503573a91.6.1737249285257; Sat, 18 Jan 2025 17:14:45 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.14.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:14:44 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Atish Patra , Alistair Francis Subject: [PULL v2 36/50] target/riscv: Invoke pmu init after feature enable Date: Sun, 19 Jan 2025 11:12:11 +1000 Message-ID: <20250119011225.11452-37-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Atish Patra The dependant ISA features are enabled at the end of cpu_realize in finalize_features. Thus, PMU init should be invoked after that only. Move the init invocation to riscv_tcg_cpu_finalize_features. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-9-e83d797ae294@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f94aa9f29e..48be24bbbe 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -963,6 +963,20 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) error_propagate(errp, local_err); return; } +#ifndef CONFIG_USER_ONLY + if (cpu->cfg.pmu_mask) { + riscv_pmu_init(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + + if (cpu->cfg.ext_sscofpmf) { + cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, + riscv_pmu_timer_cb, cpu); + } + } +#endif } void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu) @@ -1010,7 +1024,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) #ifndef CONFIG_USER_ONLY CPURISCVState *env = &cpu->env; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.14.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:14:48 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Atish Patra , Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 37/50] target/riscv: Add implied rule for counter delegation extensions Date: Sun, 19 Jan 2025 11:12:12 +1000 Message-ID: <20250119011225.11452-38-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1030.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Atish Patra The counter delegation/configuration extensions depend on the following extensions. 1. Smcdeleg - To enable counter delegation from M to S 2. S[m|s]csrind - To enable indirect access CSRs Add an implied rule so that these extensions are enabled by default if the sscfg extension is enabled. Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-10-e83d797ae294@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index da40f68715..671fc3d1c1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2760,6 +2760,16 @@ static RISCVCPUImpliedExtsRule ZVKSG_IMPLIED = { }, }; +static RISCVCPUImpliedExtsRule SSCFG_IMPLIED = { + .ext = CPU_CFG_OFFSET(ext_ssccfg), + .implied_multi_exts = { + CPU_CFG_OFFSET(ext_smcsrind), CPU_CFG_OFFSET(ext_sscsrind), + CPU_CFG_OFFSET(ext_smcdeleg), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = { &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED, &RVM_IMPLIED, &RVV_IMPLIED, NULL @@ -2777,7 +2787,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = { &ZVE64X_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED, &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED, &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED, - &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, + &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SSCFG_IMPLIED, NULL }; From patchwork Sun Jan 19 01:12:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944325 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 24D39C02185 for ; Sun, 19 Jan 2025 01:18:53 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJu6-0001dv-Qa; Sat, 18 Jan 2025 20:15:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJtw-0001Hg-3i for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:14:56 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJtu-0003Qz-8k for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:14:55 -0500 Received: by mail-pj1-x1031.google.com with SMTP id 98e67ed59e1d1-2f78a4ca5deso2184682a91.0 for ; Sat, 18 Jan 2025 17:14:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249293; x=1737854093; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=t14AYRuGs2SL7RwFjkxmv907YPXKPHoDqrHxeht7Kdk=; b=GLx/lNV23Z01ITYcOioH00L7Dbtbms8R6fmwwcg73ytHytxMd5VavXvyGiqspF9zME t0mDej/MdAABV5/of7ydOwQFKnwj14cN0ciz7OGDZodhhG5QKgaCoynp5Xdy5nII1T50 SxKcCxunjyeEZqfmo/po/3zsD8D82XPegybi4C9fGar+o6WQ0fnIST8jTithGR83ARrR ilnf/y/jLPJEr80ZmWxjrhpPu9zijZX4oSP8jOKZfMSvtUSg+T6H1EIlQ1rbdFLur2ce MTtHaHzrt9e1H3NT4oq3yGb6+oas+qtbWAkhh/YLSAvuIfidHOmsgvanPFORTokKOuvJ HSRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249293; x=1737854093; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=t14AYRuGs2SL7RwFjkxmv907YPXKPHoDqrHxeht7Kdk=; b=Q7oDUvdHgrdSigTyWhd3Z/lAdc1kJEJt+4pEtetlIxWcHKqrv7V5ziNh/o0InhD/7e gctcIY4nBhiuHLRvYLrE2iiZ0k/v3gc7PHwPfv4w0RveN+W8TXQLvSp4RmgkHEzgghXS 4Bi9xPrWkvbUHEvGPQuvyrXsvQQs7JiQ5vBGKfA3S6TVpoBSCnPd3ztpYrXkJYLFTrdL Tm3HGnaPuorWCjD/qvGZZpv38+Ltx8YttE0wmX0mSy4kkyfo5ES+9CRKlrZh4byUjeSD m2ChZZns7sdVU2oQn3vlnam3J1gDHSWKF/SyWnG6BeZTG/76lQiHw7iAii/i7CqZn1hj v2Jw== X-Gm-Message-State: AOJu0YyUZhkqkD45xdXSyOeSg2kpKGX7foyvpxym2mXdnak8Soo61cII X/GZ7zYH7ym1uOe7pzvRUm/+MvEKB1/WzvZuV+Gpc5XXZhP/98xDLhnW+xCM X-Gm-Gg: ASbGncvz2wsrkaCYazAosls43/9Q+kcJVTaWwVUhAyRxkxRASlydTreBguX4mi/cV2W VgZLIVdgBm8WpTTVhFtkPFfrNt+3VbevEydrTLVM4efjRMJPNopd7Bb2Xn34RzMf0HDrQ2DKWI4 5vl8ZBdvAS/WSPEf6siSgjsAc7txTgna8ozPEqQeZaUiOJFOXpLM5rmVA+zsaLGsmr5pmvmQyH8 SChgHigla+1Kr1CRUJRDyZlOfgW0QURmQza/VtUo7rrbDXUQ+1idw+5/t88+bU7z7XZLb3gL4+E 6HAA8LlXwb+CVLwsaVjALULbu1ZA594lkYGVUZNN5TFJtisZEPp+gC7me/oCsfiq1ecNLZxcRg= = X-Google-Smtp-Source: AGHT+IEV70DFh59o4QWzZrSB41B8RlQz1Vy1n60J83eNdnG4CoPeSl2tqYekOCvgqW9AvzIzKonN3A== X-Received: by 2002:a17:90b:2652:b0:2ee:599e:f411 with SMTP id 98e67ed59e1d1-2f782d8cf56mr10084011a91.34.1737249292666; Sat, 18 Jan 2025 17:14:52 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.14.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:14:52 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Atish Patra , Alistair Francis , Daniel Henrique Barboza Subject: [PULL v2 38/50] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg Date: Sun, 19 Jan 2025 11:12:13 +1000 Message-ID: <20250119011225.11452-39-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Atish Patra Add configuration options so that they can be enabled/disabld from qemu commandline. Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-11-e83d797ae294@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 671fc3d1c1..fe470f646d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1587,6 +1587,10 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { /* Defaults for standard extensions */ MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false), + MULTI_EXT_CFG_BOOL("smcsrind", ext_smcsrind, false), + MULTI_EXT_CFG_BOOL("smcdeleg", ext_smcdeleg, false), + MULTI_EXT_CFG_BOOL("sscsrind", ext_sscsrind, false), + MULTI_EXT_CFG_BOOL("ssccfg", ext_ssccfg, false), MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), MULTI_EXT_CFG_BOOL("zicfilp", ext_zicfilp, false), MULTI_EXT_CFG_BOOL("zicfiss", ext_zicfiss, false), From patchwork Sun Jan 19 01:12:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944303 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 14A28C02185 for ; Sun, 19 Jan 2025 01:17:04 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJuG-000265-Sr; Sat, 18 Jan 2025 20:15:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJu0-0001eh-3X for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:15:03 -0500 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJty-0003Rj-Am for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:14:59 -0500 Received: by mail-pj1-x1034.google.com with SMTP id 98e67ed59e1d1-2ee8aa26415so5810846a91.1 for ; Sat, 18 Jan 2025 17:14:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249297; x=1737854097; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q+JZitJ5X0eLTwWV1TxpFzX8qirOhwdqWIWi206MQik=; b=RG4NcCfNqnWUydRWrr2xehJhCST/ofaVTexPLfbegz+BMN6ptH44U6eqSq5aumVgTl 6VkRe9NvEbzIgCEmZYpf1cG4VvsNQcY7AhizvOQCFi7/SzTjvjM8mcUxhTxwlQPqUQht ERuajTl2i5JOtbnkH2+ySi61J8WHp6Es2eRaC4MKQyoT/VLr4AtjYmV9slyvhU71hyXP YGENaHyGSKxamdVb8wDe97dv6LuT3f/IAbHTmer5iCiDUL9FGXI6pb1MUJ+/9623LfZo eJVY2MJ4BBFDfdG4ygq6dx5GhRbDdwXRXeZ2Fg/gf+xJgUXzVlAMGkF7CRbm3l4yIAQO rfOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249297; x=1737854097; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q+JZitJ5X0eLTwWV1TxpFzX8qirOhwdqWIWi206MQik=; b=ZUqS99SswSKZwXsKSpYNH3dxNyv9gi/V7EuYX68GelsH1eFVdOQSjarRpabgdqSWWo ZFxG77IkJ0Sc6y5wx7jSbRh+waI6CpvPBqu39TXelDsg40bByEuYGO+U/G2a96yl1pAM O7rOp/AbM/FI8fCyS+YtVqso2OzC8QiS+tgm9Lie1VMwgZMFr/rUNU5n8U5SKaIxXmB8 oTgassbdLRde8u0nCmIiRmN01+Dc854J1sTJGCdvAF6cyDw2Wsc04ZatmcOq6WbvOXuQ NYm1Ysd+8FF4GydpNQXfhe2tH5+m0NDdV2naM0hp1Yv7afY7ATpj1izJKGFl4Wd6U7if r//w== X-Gm-Message-State: AOJu0Yxyg/zZULxegg8nG0ZLtY1S3U+nRdxJn/D32tzK/nr1i4ggaPkd Z/WF0Rs9g5AYJyC+tKEL85vL6wmWZrLCqVMAoQtZsEOY7cfGhM1CYFzpo9Rn X-Gm-Gg: ASbGncsiZrAxopoG710XrmHvbw+kC7JGxpahOFpqBDBW+pnqyZbnoftBTMGhTuFLrLW rbe3K2qMaL1AKfxMaIugWeTSiw3VebHw4bnbhjduox+aeiEZ6050C9m8T2S2Cy0ETrtQU0xDGui 1/NGgjCBNbz+txa5Jj8Y4WhkhSORtTzIGOPZqV2T3URrdzeShZv/0FR3JO2mtbGOXPvYnE9v9Za cyzmRij8qDi/7d1kUe/M8G20LciMYKfJYyBcQDZlUW7A2d81W2fNmW3klr8hMn46QUcE4TrWNG7 3AfwqFVPZ/xYFBNoBJvAxsrjiaxGNeWBRy82iTS5nKNoN3S/fix58ja9BzCTAiQ0z6/s33CQVA= = X-Google-Smtp-Source: AGHT+IFtMqr1mtyE1U7fPUbZXhd7fPiQ7D3LpDIBFCrGUXrCmYd09bWVUdy68GXer75rhFkiGwse+A== X-Received: by 2002:a17:90b:2cc3:b0:2ee:d193:f3d5 with SMTP id 98e67ed59e1d1-2f782c628ddmr12912778a91.7.1737249296746; Sat, 18 Jan 2025 17:14:56 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.14.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:14:56 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 39/50] target/riscv: Fix henvcfg potentially containing stale bits Date: Sun, 19 Jan 2025 11:12:14 +1000 Message-ID: <20250119011225.11452-40-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Clément Léger With the current implementation, if we had the following scenario: - Set bit x in menvcfg - Set bit x in henvcfg - Clear bit x in menvcfg then, the internal variable env->henvcfg would still contain bit x due to both a wrong menvcfg mask used in write_henvcfg() as well as a missing update of henvcfg upon menvcfg update. This can lead to some wrong interpretation of the context. In order to update henvcfg upon menvcfg writing, call write_henvcfg() after writing menvcfg. Clearing henvcfg upon writing the new value is also needed in write_henvcfg() as well as clearing henvcfg upper part when writing it with write_henvcfgh(). Signed-off-by: Clément Léger Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-2-cleger@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index eddcf5a5d0..279293b86d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2946,6 +2946,8 @@ static RISCVException read_menvcfg(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static RISCVException write_henvcfg(CPURISCVState *env, int csrno, + target_ulong val); static RISCVException write_menvcfg(CPURISCVState *env, int csrno, target_ulong val) { @@ -2974,6 +2976,7 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno, } } env->menvcfg = (env->menvcfg & ~mask) | (val & mask); + write_henvcfg(env, CSR_HENVCFG, env->henvcfg); return RISCV_EXCP_NONE; } @@ -2985,6 +2988,8 @@ static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.14.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:14:59 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 40/50] target/riscv: Add Ssdbltrp CSRs handling Date: Sun, 19 Jan 2025 11:12:15 +1000 Message-ID: <20250119011225.11452-41-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Clément Léger Add ext_ssdbltrp in RISCVCPUConfig and implement MSTATUS.SDT, {H|M}ENVCFG.DTE and modify the availability of MTVAL2 based on the presence of the Ssdbltrp ISA extension. Signed-off-by: Clément Léger Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-3-cleger@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 6 ++++ target/riscv/cpu_cfg.h | 1 + target/riscv/cpu_helper.c | 17 ++++++++++ target/riscv/csr.c | 71 ++++++++++++++++++++++++++++++++------- 5 files changed, 84 insertions(+), 12 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a936300103..97713681cb 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -564,6 +564,7 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); bool cpu_get_fcfien(CPURISCVState *env); bool cpu_get_bcfien(CPURISCVState *env); +bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 73f7d37d80..0a56163d73 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -555,6 +555,7 @@ #define MSTATUS_TW 0x00200000 /* since: priv-1.10 */ #define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */ #define MSTATUS_SPELP 0x00800000 /* zicfilp */ +#define MSTATUS_SDT 0x01000000 #define MSTATUS_MPELP 0x020000000000 /* zicfilp */ #define MSTATUS_GVA 0x4000000000ULL #define MSTATUS_MPV 0x8000000000ULL @@ -587,6 +588,7 @@ typedef enum { #define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */ #define SSTATUS_MXR 0x00080000 #define SSTATUS_SPELP MSTATUS_SPELP /* zicfilp */ +#define SSTATUS_SDT MSTATUS_SDT #define SSTATUS64_UXL 0x0000000300000000ULL @@ -782,12 +784,14 @@ typedef enum RISCVException { #define MENVCFG_CBCFE BIT(6) #define MENVCFG_CBZE BIT(7) #define MENVCFG_PMM (3ULL << 32) +#define MENVCFG_DTE (1ULL << 59) #define MENVCFG_CDE (1ULL << 60) #define MENVCFG_ADUE (1ULL << 61) #define MENVCFG_PBMTE (1ULL << 62) #define MENVCFG_STCE (1ULL << 63) /* For RV32 */ +#define MENVCFGH_DTE BIT(27) #define MENVCFGH_ADUE BIT(29) #define MENVCFGH_PBMTE BIT(30) #define MENVCFGH_STCE BIT(31) @@ -808,11 +812,13 @@ typedef enum RISCVException { #define HENVCFG_CBCFE MENVCFG_CBCFE #define HENVCFG_CBZE MENVCFG_CBZE #define HENVCFG_PMM MENVCFG_PMM +#define HENVCFG_DTE MENVCFG_DTE #define HENVCFG_ADUE MENVCFG_ADUE #define HENVCFG_PBMTE MENVCFG_PBMTE #define HENVCFG_STCE MENVCFG_STCE /* For RV32 */ +#define HENVCFGH_DTE MENVCFGH_DTE #define HENVCFGH_ADUE MENVCFGH_ADUE #define HENVCFGH_PBMTE MENVCFGH_PBMTE #define HENVCFGH_STCE MENVCFGH_STCE diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 561f5119b6..20e11a5bdd 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -83,6 +83,7 @@ struct RISCVCPUConfig { bool ext_smcntrpmf; bool ext_smcsrind; bool ext_sscsrind; + bool ext_ssdbltrp; bool ext_svadu; bool ext_svinval; bool ext_svnapot; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 3318ce440d..1eac0a0062 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -120,6 +120,19 @@ bool cpu_get_bcfien(CPURISCVState *env) } } +bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt) +{ +#ifdef CONFIG_USER_ONLY + return false; +#else + if (virt) { + return (env->henvcfg & HENVCFG_DTE) != 0; + } else { + return (env->menvcfg & MENVCFG_DTE) != 0; + } +#endif +} + void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflags) { @@ -691,6 +704,10 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) g_assert(riscv_has_ext(env, RVH)); + if (riscv_env_smode_dbltrp_enabled(env, current_virt)) { + mstatus_mask |= MSTATUS_SDT; + } + if (current_virt) { /* Current V=1 and we are about to change to V=0 */ env->vsstatus = env->mstatus & mstatus_mask; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 279293b86d..4aded3f00c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -680,6 +680,15 @@ static RISCVException aia_hmode32(CPURISCVState *env, int csrno) return hmode32(env, csrno); } +static RISCVException dbltrp_hmode(CPURISCVState *env, int csrno) +{ + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + return RISCV_EXCP_NONE; + } + + return hmode(env, csrno); +} + static RISCVException pmp(CPURISCVState *env, int csrno) { if (riscv_cpu_cfg(env)->pmp) { @@ -1938,6 +1947,13 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, mask |= MSTATUS_VS; } + if (riscv_env_smode_dbltrp_enabled(env, env->virt_enabled)) { + mask |= MSTATUS_SDT; + if ((val & MSTATUS_SDT) != 0) { + val &= ~MSTATUS_SIE; + } + } + if (xl != MXL_RV32 || env->debugger) { if (riscv_has_ext(env, RVH)) { mask |= MSTATUS_MPV | MSTATUS_GVA; @@ -2959,7 +2975,8 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno, mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | (cfg->ext_smcdeleg ? MENVCFG_CDE : 0) | - (cfg->ext_svadu ? MENVCFG_ADUE : 0); + (cfg->ext_svadu ? MENVCFG_ADUE : 0) | + (cfg->ext_ssdbltrp ? MENVCFG_DTE : 0); if (env_archcpu(env)->cfg.ext_zicfilp) { mask |= MENVCFG_LPE; @@ -2973,6 +2990,10 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno, if (env_archcpu(env)->cfg.ext_smnpm && get_field(val, MENVCFG_PMM) != PMM_FIELD_RESERVED) { mask |= MENVCFG_PMM; + } + + if ((val & MENVCFG_DTE) == 0) { + env->mstatus &= ~MSTATUS_SDT; } } env->menvcfg = (env->menvcfg & ~mask) | (val & mask); @@ -2997,9 +3018,14 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | (cfg->ext_svadu ? MENVCFG_ADUE : 0) | - (cfg->ext_smcdeleg ? MENVCFG_CDE : 0); + (cfg->ext_smcdeleg ? MENVCFG_CDE : 0) | + (cfg->ext_ssdbltrp ? MENVCFG_DTE : 0); uint64_t valh = (uint64_t)val << 32; + if ((valh & MENVCFG_DTE) == 0) { + env->mstatus &= ~MSTATUS_SDT; + } + env->menvcfg = (env->menvcfg & ~mask) | (valh & mask); write_henvcfgh(env, CSR_HENVCFGH, env->henvcfg >> 32); @@ -3070,9 +3096,10 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno, * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0 * henvcfg.stce is read_only 0 when menvcfg.stce = 0 * henvcfg.adue is read_only 0 when menvcfg.adue = 0 + * henvcfg.dte is read_only 0 when menvcfg.dte = 0 */ - *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | - env->menvcfg); + *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE | + HENVCFG_DTE) | env->menvcfg); return RISCV_EXCP_NONE; } @@ -3088,7 +3115,8 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno, } if (riscv_cpu_mxl(env) == MXL_RV64) { - mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE); + mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE | + HENVCFG_DTE); if (env_archcpu(env)->cfg.ext_zicfilp) { mask |= HENVCFG_LPE; @@ -3108,6 +3136,9 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno, } env->henvcfg = val & mask; + if ((env->henvcfg & HENVCFG_DTE) == 0) { + env->vsstatus &= ~MSTATUS_SDT; + } return RISCV_EXCP_NONE; } @@ -3122,8 +3153,8 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, return ret; } - *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | - env->menvcfg)) >> 32; + *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE | + HENVCFG_DTE) | env->menvcfg)) >> 32; return RISCV_EXCP_NONE; } @@ -3131,7 +3162,7 @@ static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, target_ulong val) { uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | - HENVCFG_ADUE); + HENVCFG_ADUE | HENVCFG_DTE); uint64_t valh = (uint64_t)val << 32; RISCVException ret; @@ -3139,8 +3170,10 @@ static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, if (ret != RISCV_EXCP_NONE) { return ret; } - env->henvcfg = (env->henvcfg & 0xFFFFFFFF) | (valh & mask); + if ((env->henvcfg & HENVCFG_DTE) == 0) { + env->vsstatus &= ~MSTATUS_SDT; + } return RISCV_EXCP_NONE; } @@ -3594,6 +3627,9 @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno, if (env->xl != MXL_RV32 || env->debugger) { mask |= SSTATUS64_UXL; } + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + mask |= SSTATUS_SDT; + } if (env_archcpu(env)->cfg.ext_zicfilp) { mask |= SSTATUS_SPELP; @@ -3614,7 +3650,9 @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno, if (env_archcpu(env)->cfg.ext_zicfilp) { mask |= SSTATUS_SPELP; } - + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + mask |= SSTATUS_SDT; + } /* TODO: Use SXL not MXL. */ *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); return RISCV_EXCP_NONE; @@ -3634,7 +3672,9 @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno, if (env_archcpu(env)->cfg.ext_zicfilp) { mask |= SSTATUS_SPELP; } - + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + mask |= SSTATUS_SDT; + } target_ulong newval = (env->mstatus & ~mask) | (val & mask); return write_mstatus(env, CSR_MSTATUS, newval); } @@ -4751,6 +4791,13 @@ static RISCVException write_vsstatus(CPURISCVState *env, int csrno, if ((val & VSSTATUS64_UXL) == 0) { mask &= ~VSSTATUS64_UXL; } + if ((env->henvcfg & HENVCFG_DTE)) { + if ((val & SSTATUS_SDT) != 0) { + val &= ~SSTATUS_SIE; + } + } else { + val &= ~SSTATUS_SDT; + } env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; return RISCV_EXCP_NONE; } @@ -5698,7 +5745,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2, + [CSR_MTVAL2] = { "mtval2", dbltrp_hmode, read_mtval2, write_mtval2, .min_priv_ver = PRIV_VERSION_1_12_0 }, [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst, .min_priv_ver = PRIV_VERSION_1_12_0 }, From patchwork Sun Jan 19 01:12:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944316 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB7E8C02188 for ; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.15.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:15:02 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Alistair Francis Subject: [PULL v2 41/50] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior Date: Sun, 19 Jan 2025 11:12:16 +1000 Message-ID: <20250119011225.11452-42-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Clément Léger When the Ssdbltrp extension is enabled, SSTATUS.SDT field is cleared when executing sret. When executing mret/mnret, SSTATUS.SDT is cleared when returning to U, VS or VU and VSSTATUS.SDT is cleared when returning to VU from HS. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-4-cleger@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/op_helper.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index c825336519..59c4bf28ed 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -294,6 +294,18 @@ target_ulong helper_sret(CPURISCVState *env) get_field(mstatus, MSTATUS_SPIE)); mstatus = set_field(mstatus, MSTATUS_SPIE, 1); mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U); + + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + if (riscv_has_ext(env, RVH)) { + target_ulong prev_vu = get_field(env->hstatus, HSTATUS_SPV) && + prev_priv == PRV_U; + /* Returning to VU from HS, vsstatus.sdt = 0 */ + if (!env->virt_enabled && prev_vu) { + env->vsstatus = set_field(env->vsstatus, MSTATUS_SDT, 0); + } + } + mstatus = set_field(mstatus, MSTATUS_SDT, 0); + } if (env->priv_ver >= PRIV_VERSION_1_12_0) { mstatus = set_field(mstatus, MSTATUS_MPRV, 0); } @@ -304,7 +316,6 @@ target_ulong helper_sret(CPURISCVState *env) target_ulong hstatus = env->hstatus; prev_virt = get_field(hstatus, HSTATUS_SPV); - hstatus = set_field(hstatus, HSTATUS_SPV, 0); env->hstatus = hstatus; @@ -344,6 +355,22 @@ static void check_ret_from_m_mode(CPURISCVState *env, target_ulong retpc, riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC()); } } +static target_ulong ssdbltrp_mxret(CPURISCVState *env, target_ulong mstatus, + target_ulong prev_priv, + target_ulong prev_virt) +{ + /* If returning to U, VS or VU, sstatus.sdt = 0 */ + if (prev_priv == PRV_U || (prev_virt && + (prev_priv == PRV_S || prev_priv == PRV_U))) { + mstatus = set_field(mstatus, MSTATUS_SDT, 0); + /* If returning to VU, vsstatus.sdt = 0 */ + if (prev_virt && prev_priv == PRV_U) { + env->vsstatus = set_field(env->vsstatus, MSTATUS_SDT, 0); + } + } + + return mstatus; +} target_ulong helper_mret(CPURISCVState *env) { @@ -361,6 +388,9 @@ target_ulong helper_mret(CPURISCVState *env) mstatus = set_field(mstatus, MSTATUS_MPP, riscv_has_ext(env, RVU) ? PRV_U : PRV_M); mstatus = set_field(mstatus, MSTATUS_MPV, 0); + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + mstatus = ssdbltrp_mxret(env, mstatus, prev_priv, prev_virt); + } if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) { mstatus = set_field(mstatus, MSTATUS_MPRV, 0); } @@ -402,6 +432,9 @@ target_ulong helper_mnret(CPURISCVState *env) if (prev_priv < PRV_M) { env->mstatus = set_field(env->mstatus, MSTATUS_MPRV, false); } + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + env->mstatus = ssdbltrp_mxret(env, env->mstatus, prev_priv, prev_virt); + } if (riscv_has_ext(env, RVH) && prev_virt) { riscv_cpu_swap_hypervisor_regs(env); From patchwork Sun Jan 19 01:12:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944302 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 68E95C02185 for ; Sun, 19 Jan 2025 01:16:39 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJum-0003du-Eo; Sat, 18 Jan 2025 20:15:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJuC-0001qa-ND for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:15:12 -0500 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJu8-0003es-VJ for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:15:12 -0500 Received: by mail-pj1-x1034.google.com with SMTP id 98e67ed59e1d1-2ef760a1001so5879167a91.0 for ; Sat, 18 Jan 2025 17:15:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249306; x=1737854106; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gf4FLsfTMGpl/kEVYpdgLrPyFPxMp7ICmBJwS+O0aYM=; b=R9GVwJ9O7+FJnGBj/l23tOLyhColNdXQRWPFVK5QvbaCpSWHbbQtxG6g6EOwdYvqKH sINUsJeHJHAWxHslAT9Bss1YZxhBYlIHk6W43dY176TFf+wqb1RC0vZXeGMNtrlMWx5d UueGxR0yxZpZ780FgWSROxmgNmDvILzJ6CDkAapydtFc9ribrDSh1yW6it24fgNUR8QL cs0efK9+SK1wlGdW8ExX/bYC3Q7R9J+rNzCAjVIkdZpKQ9ZZO2HJyR2GZa7BSvJ3yOac OGgriD0u5QL3jv0w3kigjJKtWvdJmnXWLDhymaE7VykNFUFnOgQXUT7RPKMMcvqNDzuF TPGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249306; x=1737854106; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gf4FLsfTMGpl/kEVYpdgLrPyFPxMp7ICmBJwS+O0aYM=; b=Lp1na5e0rxkko4XGmF7GuBwRqdOip3ubFDWZ9G/B9RjeTUTNRiY0NgHW69SNT+goH3 yIqE0pUr+q1PlFQdEnNCc5fSgz5ZqB6IWJZ42O1mIt1FVq5BmM+/YPfS2jaMOcnzNQo1 eWRnAkftHaR7+lEIjm8BIb8OQIRHGImgVGqC2pa5+tALBrEDpraDPajLMTIOD4W9mo2w bNOnn+nt7/2JD9+Qx3Wl8d+Sluc3B9MZUw9/M9MYwu8blNeJ0zK+kR/HtnHPB9EOK3i5 Y/4x9dA8SApSgfAp751jtC6OJKvkTcQj8UnboDfw+x1CzDqRXWHJ3l2MHUMXdGF3vz1r 8Vww== X-Gm-Message-State: AOJu0Yw21IwIIEdUrTQ5Qx2IG1NK/qxi+T/01/9EnbLmBH8vH15lgpio SaVTdBLfJws2f3+IXZhKy4DadsDBmQq2noUZVJai8ZBf6fpzS26k/4gEx5X7 X-Gm-Gg: ASbGncu6bRxAaETEgYs39K3HlsU3FhPZ9gscpRM44qviadvssv+uXI3Z76yvkR5nwu7 nK5xqKawyl2io9oS1tc9TNt+14zyXkzsHcm5KG9HS5BMOmvOj4GAA8Z8UodI4WqbBH1ZnhNE+Mg VnoVmcVsxCUsmO6z+g7f5lMafFRF1N9Jfkzwei+2cRFOs8RFGNB2EyHvGWUBe/13t0dOjHo4w+u 6jukX+Y/DTDQJ8S2a6oOvA+lvJyvmpDqikA0//EUyDJscNtkH5uRjauap7uRYAogklEQO+oPDu8 yijdA3OffZ5l1oO/I/YHzUYY3mLWnkAeTs5SRV8F/g4lTtbSO6UFKlj2QItKg9LJ+D3oD6taPA= = X-Google-Smtp-Source: AGHT+IGXOPgY5B2dZvnRcET33xSKIoGsRVz0kms2Gg9Avb7coib35ac03Ik07OKVyyaGtDNkOqig1Q== X-Received: by 2002:a17:90b:520d:b0:2ee:7411:ca99 with SMTP id 98e67ed59e1d1-2f782c4cb23mr10708829a91.1.1737249306494; Sat, 18 Jan 2025 17:15:06 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.15.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:15:06 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Alistair Francis Subject: [PULL v2 42/50] target/riscv: Implement Ssdbltrp exception handling Date: Sun, 19 Jan 2025 11:12:17 +1000 Message-ID: <20250119011225.11452-43-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Clément Léger When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode while SSTATUS.SDT isn't cleared, generate a double trap exception to M-mode. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-5-cleger@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 42 ++++++++++++++++++++++++++++++++++----- 3 files changed, 39 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 0a56163d73..a3acda4bc8 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -701,6 +701,7 @@ typedef enum RISCVException { RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */ RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */ RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */ + RISCV_EXCP_DOUBLE_TRAP = 0x10, RISCV_EXCP_SW_CHECK = 0x12, /* since: priv-1.13.0 */ RISCV_EXCP_HW_ERR = 0x13, /* since: priv-1.13.0 */ RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14, diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fe470f646d..5540eb7f63 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -303,7 +303,7 @@ static const char * const riscv_excp_names[] = { "load_page_fault", "reserved", "store_page_fault", - "reserved", + "double_trap", "reserved", "reserved", "reserved", diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 1eac0a0062..539ba327e7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1951,6 +1951,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool virt = env->virt_enabled; bool write_gva = false; bool always_storeamo = (env->excp_uw2 & RISCV_UW2_ALWAYS_STORE_AMO); + bool vsmode_exc; uint64_t s; int mode; @@ -1965,6 +1966,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) !(env->mip & (1ULL << cause)); bool vs_injected = env->hvip & (1ULL << cause) & env->hvien && !(env->mip & (1ULL << cause)); + bool smode_double_trap = false; + uint64_t hdeleg = async ? env->hideleg : env->hedeleg; target_ulong tval = 0; target_ulong tinst = 0; target_ulong htval = 0; @@ -2088,6 +2091,30 @@ void riscv_cpu_do_interrupt(CPUState *cs) mode = env->priv <= PRV_S && cause < 64 && (((deleg >> cause) & 1) || s_injected || vs_injected) ? PRV_S : PRV_M; + vsmode_exc = env->virt_enabled && (((hdeleg >> cause) & 1) || vs_injected); + /* + * Check double trap condition only if already in S-mode and targeting + * S-mode + */ + if (cpu->cfg.ext_ssdbltrp && env->priv == PRV_S && mode == PRV_S) { + bool dte = (env->menvcfg & MENVCFG_DTE) != 0; + bool sdt = (env->mstatus & MSTATUS_SDT) != 0; + /* In VS or HS */ + if (riscv_has_ext(env, RVH)) { + if (vsmode_exc) { + /* VS -> VS, use henvcfg instead of menvcfg*/ + dte = (env->henvcfg & HENVCFG_DTE) != 0; + } else if (env->virt_enabled) { + /* VS -> HS, use mstatus_hs */ + sdt = (env->mstatus_hs & MSTATUS_SDT) != 0; + } + } + smode_double_trap = dte && sdt; + if (smode_double_trap) { + mode = PRV_M; + } + } + if (mode == PRV_S) { /* handle the trap in S-mode */ /* save elp status */ @@ -2096,10 +2123,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) } if (riscv_has_ext(env, RVH)) { - uint64_t hdeleg = async ? env->hideleg : env->hedeleg; - - if (env->virt_enabled && - (((hdeleg >> cause) & 1) || vs_injected)) { + if (vsmode_exc) { /* Trap to VS mode */ /* * See if we need to adjust cause. Yes if its VS mode interrupt @@ -2132,6 +2156,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); s = set_field(s, MSTATUS_SPP, env->priv); s = set_field(s, MSTATUS_SIE, 0); + if (riscv_env_smode_dbltrp_enabled(env, virt)) { + s = set_field(s, MSTATUS_SDT, 1); + } env->mstatus = s; sxlen = 16 << riscv_cpu_sxl(env); env->scause = cause | ((target_ulong)async << (sxlen - 1)); @@ -2184,9 +2211,14 @@ void riscv_cpu_do_interrupt(CPUState *cs) s = set_field(s, MSTATUS_MIE, 0); env->mstatus = s; env->mcause = cause | ((target_ulong)async << (mxlen - 1)); + if (smode_double_trap) { + env->mtval2 = env->mcause; + env->mcause = RISCV_EXCP_DOUBLE_TRAP; + } else { + env->mtval2 = mtval2; + } env->mepc = env->pc; env->mtval = tval; - env->mtval2 = mtval2; env->mtinst = tinst; /* From patchwork Sun Jan 19 01:12:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944326 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8822C02185 for ; Sun, 19 Jan 2025 01:19:38 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJuy-0003tg-OJ; Sat, 18 Jan 2025 20:16:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJuE-0001zQ-9N for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:15:15 -0500 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJuC-0003fL-43 for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:15:13 -0500 Received: by mail-pj1-x102a.google.com with SMTP id 98e67ed59e1d1-2f4409fc8fdso5244421a91.1 for ; Sat, 18 Jan 2025 17:15:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249309; x=1737854109; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OwEyXlo5Rvtc+kl5EB4TVm2Xy+p29wGWgR0S30rNC/g=; b=g9+7rIF3XaZtR/fmmhoJKlZX/fFRPf0xilSowbI+yYzdR7T/IIf57FdBlJyiH8TACP zH6LZ42PAscrj+TLRsrltrK/Te8FG3nocJ+ra/ulZPxiwvnOsY34nhyFpWO8Rl8WnJno UFg+ngsQQ9Hz2TtuLBO4ZiKl+LyOQ2rFEPRFIiJWJ+toUUKm6Hg29nNRcZ+mnmL9SnjA ad6OSZjBDg0t0pM15GIwP31t/qbisE4M0tgD6LZR8sNyqH4a3vKNe1fYvbnFopCZ8ApK cJAh5UsYZ0cETozhxrMGvYPEEXtXUHZVO37UUcVQPiwvBD2tnKnE1VQzcN5dm3xsGt/V Hs7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249309; x=1737854109; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OwEyXlo5Rvtc+kl5EB4TVm2Xy+p29wGWgR0S30rNC/g=; b=Ps8/4wdPyci9/ZhdakyztR4ah2XZpY6NlSwLthjUhxQ7CuC3eAKfAxqXdMA2JPxife qiGqxOm5nMzW9m5bLu6kBDwmX73eobpW4xlpPGUszhGGxwIRWR8vJo7CpfN0OHwd8GkV AxJt88jYh7zzrKxUUIObzrHcqrG5n1A/HK6iw7I5dHXMMTWExCYf/ylWlLErzg+VvitA 4rTX1ax3NBSpaFgNCkZaJ4/ucn8x28t8MUWjoZozLc90/KcWwZtfaHjV5M4xZT9Gw0yE EFgP45q7eZyJV1alhal+uSFOR6p0t8wdhEmxhsL2eJEXpahJCyeTFIT6OfrmxLvbQIf8 qd3g== X-Gm-Message-State: AOJu0Yy3HfVgdFSWOfxTwT7jRTMwFECX8D3/HDbxjJjWxMTRGOoApXqP Dud496yYlMXfQaGgMVk22r6moPE0xvL7WMPCykItMz/bvCdbub9x44t9UDux X-Gm-Gg: ASbGncv0H3jHNxM5G7Kd59fDXAV0MWlw/zGEVgeUN92qUIeyLTxCpQPV38FFftscIyw dg+CzwpL0JHG2X+jSMqzWHCW4K0JggqoRgrrnRM5E/ztPiHOim8SmscAMgAPTiYeH7p4Bs0HWj5 OxA7zjeqdZVsOJEan7TxBhYFzXZRMHMfCgPJvQdCI77oUqUxBS3P+UPo92dvuZ72Pbgos7lAmH8 uWR49bYM884gtnoNb8rXvWyXTaXIhpLmE9H0ET/yXVLDkFieyoeIO4yXuUD6B5+hWimDZ7mrctq MXr37fQZSAXnFyoHek26v0UJ7FjX3DnHyuKZCT8kXMXG3TGQpIOSImN1A6baMwngn7aT8A5BuQ= = X-Google-Smtp-Source: AGHT+IF1RaktCwLsT12ERsF9lwkS0iw4E6OD4RcFB8l31tI0CfrSm9jr7ZPHxqVy4I+LzpcKRSZLjg== X-Received: by 2002:a17:90b:2e44:b0:2f7:4c7a:b5f with SMTP id 98e67ed59e1d1-2f74c7a0c32mr19816223a91.2.1737249309564; Sat, 18 Jan 2025 17:15:09 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.15.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:15:09 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Alistair Francis Subject: [PULL v2 43/50] target/riscv: Add Ssdbltrp ISA extension enable switch Date: Sun, 19 Jan 2025 11:12:18 +1000 Message-ID: <20250119011225.11452-44-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Clément Léger Add the switch to enable the Ssdbltrp ISA extension. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-6-cleger@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5540eb7f63..9e1ce0e1f1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -205,6 +205,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(sscsrind, PRIV_VERSION_1_12_0, ext_sscsrind), + ISA_EXT_DATA_ENTRY(ssdbltrp, PRIV_VERSION_1_13_0, ext_ssdbltrp), ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_13_0, ext_ssnpm), ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), @@ -1628,6 +1629,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("smnpm", ext_smnpm, false), MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), MULTI_EXT_CFG_BOOL("ssaia", ext_ssaia, false), + MULTI_EXT_CFG_BOOL("ssdbltrp", ext_ssdbltrp, false), MULTI_EXT_CFG_BOOL("svade", ext_svade, false), MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true), MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false), From patchwork Sun Jan 19 01:12:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944310 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6043CC02185 for ; Sun, 19 Jan 2025 01:17:28 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJuM-0002g1-K4; Sat, 18 Jan 2025 20:15:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJuI-0002MU-8z for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:15:18 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJuF-0003gS-3w for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:15:17 -0500 Received: by mail-pj1-x1031.google.com with SMTP id 98e67ed59e1d1-2efb17478adso5859576a91.1 for ; Sat, 18 Jan 2025 17:15:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249313; x=1737854113; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BzfXtdeXTxj7aTbAzBirn5FPQKv+kTN3iTkNh9s4tgA=; b=KTjhITOaQeZrSsavEr7nE7CN4zx6i6SStmsnSrQWG5uOr87ONcYUMknPiGhxquhAvY cK350AbsHKfScnAprjPoNe9Mr8I4uDQKo0GmofWJ1GurbYx04/uog+te8ruOl69AbCje fxjiBRSCWjovGmLFsymGqqAFro833+GEGxDIJrcQBxQ9GYXVyPz4BPnCrix+uC7gdUPa N3kGiAbK58f8JQC1Miydg3Bjd55ROgJH/WIZqixxcuryD2D9CgNIZdeVX1mBiDj5PMG6 4LMvp1cizcMBurLn7XzEaX4UvIDPaU5nsQ5BevVRKp988FsSEyT/lI2pNJ+TDTE+IuGK MGNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249313; x=1737854113; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BzfXtdeXTxj7aTbAzBirn5FPQKv+kTN3iTkNh9s4tgA=; b=UjeNkxGQYzG+3z7J2QSN/WnOK6rj3bekWFQW1lJ9TvRbJQl+7Io+jqA0DozGR0FC1R +x3fWA7iq4myb69wgaLErRgYEdcr2JS8koNbFos5cHG8Hvqedc8g12vfuaR8W8c8S3MY D/9424SPFQqeiKnRtYi87jyJN0+BTGnXoaYXJM86fouy23TUoiI6WaVMgdH+P/uKtbiP VV44oR/f4SyhUB3+cFKJHZcr+nr9KLfUUSk/EkPdl+FojYB0VoRshkyT3LI21n+jzSrp NaLQWRBMWStu2OBxinSeTrLR8KXGABO/eP4ZzwwUGoQEDyDJC5ZhuRoKhZ0CZE0jjbiU hOQw== X-Gm-Message-State: AOJu0YxCF6PKtvLJutfwtuIKMiSNLeYb6PR37Buv91x0qUdRyH1jkBG2 nE3Fu8nVrZ65xJlwsn/msj34XzTr/1rhscEl+V7amgkzvOW5bxEBCHlzobjY X-Gm-Gg: ASbGncsAT2G/CoqC3zQVCth11dllgD3kUa31e1+pc2N4BgUJob17y/bGSU3USexivsD 0twAku5aFp7Kj9dUtoFiJRTu7367ikswVFu0urvHbVIoWb2sxdYtJnQG4ETJ/RMno5M+cwbxuEs 31QupOZUn363zUQ990KOrEz3HBFbS6axShEhk+6IjnhiWN58Q16lQ4Z7x4ePxrJPrx3LbMrJAhB DhUldukd1nH7PXkEv7fp/ih2o1XqwUd3v3kspoMqqWl+4VgrGo+8vLx2fT7IwXQhib+FNdcv6Vc nUjsQXSQMNQB+ad9VTt6cEj3ixxTtT0B3mYTBqc4c5IBvbZKplah3UEnGQldJJ//rgf66PjbeQ= = X-Google-Smtp-Source: AGHT+IGYZZnjhmL71CCFCjdBgYBw2Uev+rwgEBjj6Ph0MjMt0EOUVrqBOXLulB5LThTt++1g1CJbdQ== X-Received: by 2002:a17:90b:2703:b0:2ee:d63f:d71 with SMTP id 98e67ed59e1d1-2f782c7252dmr13256054a91.14.1737249313128; Sat, 18 Jan 2025 17:15:13 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.15.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:15:12 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Alistair Francis Subject: [PULL v2 44/50] target/riscv: Add Smdbltrp CSRs handling Date: Sun, 19 Jan 2025 11:12:19 +1000 Message-ID: <20250119011225.11452-45-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Clément Léger Add `ext_smdbltrp`in RISCVCPUConfig and implement MSTATUS.MDT behavior. Also set MDT to 1 at reset according to the specification. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-7-cleger@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_cfg.h | 1 + target/riscv/cpu.c | 3 +++ target/riscv/csr.c | 13 +++++++++++++ 4 files changed, 18 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index a3acda4bc8..f97c48a394 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -559,6 +559,7 @@ #define MSTATUS_MPELP 0x020000000000 /* zicfilp */ #define MSTATUS_GVA 0x4000000000ULL #define MSTATUS_MPV 0x8000000000ULL +#define MSTATUS_MDT 0x40000000000ULL /* Smdbltrp extension */ #define MSTATUS64_UXL 0x0000000300000000ULL #define MSTATUS64_SXL 0x0000000C00000000ULL diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 20e11a5bdd..aef896ba00 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -84,6 +84,7 @@ struct RISCVCPUConfig { bool ext_smcsrind; bool ext_sscsrind; bool ext_ssdbltrp; + bool ext_smdbltrp; bool ext_svadu; bool ext_svinval; bool ext_svnapot; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9e1ce0e1f1..e3ed11b0fd 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1064,6 +1064,9 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) env->mstatus_hs = set_field(env->mstatus_hs, MSTATUS64_UXL, env->misa_mxl); } + if (riscv_cpu_cfg(env)->ext_smdbltrp) { + env->mstatus = set_field(env->mstatus, MSTATUS_MDT, 1); + } } env->mcause = 0; env->miclaim = MIP_SGEIP; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4aded3f00c..afb7544f07 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1954,6 +1954,13 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, } } + if (riscv_cpu_cfg(env)->ext_smdbltrp) { + mask |= MSTATUS_MDT; + if ((val & MSTATUS_MDT) != 0) { + val &= ~MSTATUS_MIE; + } + } + if (xl != MXL_RV32 || env->debugger) { if (riscv_has_ext(env, RVH)) { mask |= MSTATUS_MPV | MSTATUS_GVA; @@ -1996,6 +2003,12 @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno, uint64_t valh = (uint64_t)val << 32; uint64_t mask = riscv_has_ext(env, RVH) ? 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.15.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:15:15 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Alistair Francis Subject: [PULL v2 45/50] target/riscv: Implement Smdbltrp sret, mret and mnret behavior Date: Sun, 19 Jan 2025 11:12:20 +1000 Message-ID: <20250119011225.11452-46-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Clément Léger When the Ssdbltrp extension is enabled, SSTATUS.MDT field is cleared when executing sret if executed in M-mode. When executing mret/mnret, SSTATUS.MDT is cleared. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-8-cleger@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/op_helper.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 59c4bf28ed..ce1256f439 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -306,6 +306,9 @@ target_ulong helper_sret(CPURISCVState *env) } mstatus = set_field(mstatus, MSTATUS_SDT, 0); } + if (riscv_cpu_cfg(env)->ext_smdbltrp && env->priv >= PRV_M) { + mstatus = set_field(mstatus, MSTATUS_MDT, 0); + } if (env->priv_ver >= PRIV_VERSION_1_12_0) { mstatus = set_field(mstatus, MSTATUS_MPRV, 0); } @@ -391,6 +394,9 @@ target_ulong helper_mret(CPURISCVState *env) if (riscv_cpu_cfg(env)->ext_ssdbltrp) { mstatus = ssdbltrp_mxret(env, mstatus, prev_priv, prev_virt); } + if (riscv_cpu_cfg(env)->ext_smdbltrp) { + mstatus = set_field(mstatus, MSTATUS_MDT, 0); + } if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) { mstatus = set_field(mstatus, MSTATUS_MPRV, 0); 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.15.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:15:18 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Alistair Francis Subject: [PULL v2 46/50] target/riscv: Implement Smdbltrp behavior Date: Sun, 19 Jan 2025 11:12:21 +1000 Message-ID: <20250119011225.11452-47-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Clément Léger When the Smsdbltrp ISA extension is enabled, if a trap happens while MSTATUS.MDT is already set, it will trigger an abort or an NMI is the Smrnmi extension is available. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-9-cleger@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 57 ++++++++++++++++++++++++++++----------- 1 file changed, 41 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 539ba327e7..e1dfc4ecbf 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1938,6 +1938,24 @@ static target_ulong promote_load_fault(target_ulong orig_cause) /* if no promotion, return original cause */ return orig_cause; } + +static void riscv_do_nmi(CPURISCVState *env, target_ulong cause, bool virt) +{ + env->mnstatus = set_field(env->mnstatus, MNSTATUS_NMIE, false); + env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPV, virt); + env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPP, env->priv); + env->mncause = cause; + env->mnepc = env->pc; + env->pc = env->rnmi_irqvec; + + if (cpu_get_fcfien(env)) { + env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPELP, env->elp); + } + + /* Trapping to M mode, virt is disabled */ + riscv_cpu_set_mode(env, PRV_M, false); +} + /* * Handle Traps * @@ -1977,22 +1995,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool nnmi_excep = false; if (cpu->cfg.ext_smrnmi && env->rnmip && async) { - env->mnstatus = set_field(env->mnstatus, MNSTATUS_NMIE, false); - env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPV, - env->virt_enabled); - env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPP, - env->priv); - env->mncause = cause | ((target_ulong)1U << (mxlen - 1)); - env->mnepc = env->pc; - env->pc = env->rnmi_irqvec; - - if (cpu_get_fcfien(env)) { - env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPELP, env->elp); - } - - /* Trapping to M mode, virt is disabled */ - riscv_cpu_set_mode(env, PRV_M, false); - + riscv_do_nmi(env, cause | ((target_ulong)1U << (mxlen - 1)), + env->virt_enabled); return; } @@ -2204,11 +2208,32 @@ void riscv_cpu_do_interrupt(CPUState *cs) /* Trapping to M mode, virt is disabled */ virt = false; } + /* + * If the hart encounters an exception while executing in M-mode, + * with the mnstatus.NMIE bit clear, the program counter is set to + * the RNMI exception trap handler address. + */ + nnmi_excep = cpu->cfg.ext_smrnmi && + !get_field(env->mnstatus, MNSTATUS_NMIE) && + !async; s = env->mstatus; s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); s = set_field(s, MSTATUS_MPP, env->priv); s = set_field(s, MSTATUS_MIE, 0); + if (cpu->cfg.ext_smdbltrp) { + if (env->mstatus & MSTATUS_MDT) { + assert(env->priv == PRV_M); + if (!cpu->cfg.ext_smrnmi || nnmi_excep) { + cpu_abort(CPU(cpu), "M-mode double trap\n"); + } else { + riscv_do_nmi(env, cause, false); + return; + } + } + + s = set_field(s, MSTATUS_MDT, 1); + } env->mstatus = s; env->mcause = cause | ((target_ulong)async << (mxlen - 1)); if (smode_double_trap) { From patchwork Sun Jan 19 01:12:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944321 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4555CC02188 for ; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.15.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:15:22 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 47/50] target/riscv: Add Smdbltrp ISA extension enable switch Date: Sun, 19 Jan 2025 11:12:22 +1000 Message-ID: <20250119011225.11452-48-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Clément Léger Add the switch to enable the Smdbltrp ISA extension and disable it for the max cpu. Indeed, OpenSBI when Smdbltrp is present, M-mode double trap is enabled by default and MSTATUS.MDT needs to be cleared to avoid taking a double trap. OpenSBI does not currently support it so disable it for the max cpu to avoid breaking regression tests. Signed-off-by: Clément Léger Reviewed-by: Daniel Henrique Barboza Message-ID: <20250116131539.2475785-1-cleger@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ target/riscv/tcg/tcg-cpu.c | 10 ++++++++++ 2 files changed, 12 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e3ed11b0fd..bddf1ba75e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -194,6 +194,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(smcdeleg, PRIV_VERSION_1_13_0, ext_smcdeleg), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_13_0, ext_smcsrind), + ISA_EXT_DATA_ENTRY(smdbltrp, PRIV_VERSION_1_13_0, ext_smdbltrp), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi), ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_13_0, ext_smmpm), @@ -1626,6 +1627,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false), MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), + MULTI_EXT_CFG_BOOL("smdbltrp", ext_smdbltrp, false), MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false), MULTI_EXT_CFG_BOOL("smmpm", ext_smmpm, false), diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 48be24bbbe..0a137281de 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1439,6 +1439,16 @@ static void riscv_init_max_cpu_extensions(Object *obj) isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false); qemu_log("Smrnmi is disabled in the 'max' type CPU\n"); } + + /* + * ext_smdbltrp requires the firmware to clear MSTATUS.MDT on startup to + * avoid generating a double trap. OpenSBI does not currently support it, + * disable it for now. + */ + if (cpu->cfg.ext_smdbltrp) { + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smdbltrp), false); + qemu_log("Smdbltrp is disabled in the 'max' type CPU\n"); + } } static bool riscv_cpu_has_max_extensions(Object *cpu_obj) From patchwork Sun Jan 19 01:12:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944309 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8CA87C0218A for ; Sun, 19 Jan 2025 01:17:22 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tZJuo-0003hB-RX; Sat, 18 Jan 2025 20:15:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tZJuU-000393-5w for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:15:31 -0500 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tZJuR-0003jo-U6 for qemu-devel@nongnu.org; Sat, 18 Jan 2025 20:15:29 -0500 Received: by mail-pj1-x1034.google.com with SMTP id 98e67ed59e1d1-2ee50ffcf14so7034255a91.0 for ; Sat, 18 Jan 2025 17:15:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249326; x=1737854126; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LOzDdutfjUChqV9nQci53MRyMfPW93kG5/B+G7+D6ZM=; b=CsognJUKB1NGzOebkLd1IH/anmWnu4kFg0d5Bh5qfJ9vlJnFFb7IzOZsCIuPUY9b+Q w0E+QiCYXa+ntiNYGtxJrnhtcLpyTo5vTgWc32Y1gdGWL32xQC0InIPLJvqHZlP+eXvV B3CVa2/lFGtdDT88lCWYmdW+NYYAg7Wa9VxkhAL7e8psYA7at91Vnkxq6X8X7LKtIq+o SCBYxx6uL8zFm2lihZJY8sMIiQmUABbSuxP18tlmwKuT8FbEj/kq9NMDVq87ZuEj1z4F uaI9Gqu1ov3k6GxcSueRg96gEsPRq+er3WEycflUHFZiQuejVnr5KPuxQXI22pRy17Qo qQ0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249326; x=1737854126; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LOzDdutfjUChqV9nQci53MRyMfPW93kG5/B+G7+D6ZM=; b=UhgO8OpK/GVX5B80LINPDp8h57soivpjJ8ne0Q2ZdvjHj4VA8ihEWVqPMm1H95rVzL 9LRWZz4e0OKkDzH1bPhaJ1XkOT4qq+rEuwEZjpOgDAPgDql3teNHWVRjGiW6f7EkpQ6+ QbFY+LbWSGwYooYkPBSM89oVtzJFv8GCkhfgxVIk5o1wcYKL/tsIZSgazQWSgnOvx2ks p2XplDMGqTAutOPJxz09rfjvSmPKnwFHA00+WOhkrEbXpf6A7E6+kLTuYIYDUlVxOESf yaNqFNx+LDw3uLI2mFZgk/RVfQeg58Ao5E/BO3QZYPjtXQw0NlHiLAmclYWeaCOH7Tjg ngsg== X-Gm-Message-State: AOJu0Ywy1VEBIVgl86rAAdwYHekEn2UHQ51YFa3xBhGUbc35rEl5L4Cp 9g4gAblara4b1q16JZp+QXhfOxG2TXteCRqrNxmckWOoXgZGuJvcfrLR32mc X-Gm-Gg: ASbGncvHfs4YgZAFIe90lOMlV+hgiUARBixUW7gAUeS22wZM9ZgVh0agDD+XJ/3yv9L POq9Gc2PZd9LBOSGMZ35aaIIVXIGmZpmKsfVyOcaqVtgJmqMrT19LokhYYa0RPWVjl0AkG94qUz RDS2awSTJk++pbOX1Vbh19lVQ56aG4I6lzZB4uYXyHsTbV9nBA3ABS7n0lQ9rFFgr5y+wCit1Ls KbXkqLzyqqh0KnivptV2SzgR2/NGbfzGETXFKVwNM1bRw86l2Izj2d1O4NxcfUTTwU19lrOBwLA gotoJ67Not6SDdgbAuq+RdYR0kWuUUWV+JjlLoD6e5YiR8RXEk4waICqbClqeJmeMkkt1UwU/g= = X-Google-Smtp-Source: AGHT+IFgMNzN8TSTGIUyOX0FcHUOU2z8a4ztmUCX//FjDl5i5+MVVLjE4f3npB2fcfxby9XL3dmG8A== X-Received: by 2002:a17:90b:2808:b0:2f6:e47c:1750 with SMTP id 98e67ed59e1d1-2f782d026fcmr12124650a91.13.1737249326303; Sat, 18 Jan 2025 17:15:26 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.15.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:15:25 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Jason Chien , Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 48/50] hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache Date: Sun, 19 Jan 2025 11:12:23 +1000 Message-ID: <20250119011225.11452-49-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Jason Chien This commit introduces a translation tag to avoid invalidating an entry that should not be invalidated when IOMMU executes invalidation commands. E.g. IOTINVAL.VMA with GV=0, AV=0, PSCV=1 invalidates both a mapping of single stage translation and a mapping of nested translation with the same PSCID, but only the former one should be invalidated. Signed-off-by: Jason Chien Reviewed-by: Daniel Henrique Barboza Message-ID: <20241108110147.11178-1-jason.chien@sifive.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu.c | 205 ++++++++++++++++++++++++++++++----------- 1 file changed, 153 insertions(+), 52 deletions(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index 8bf920deab..e7568ca227 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -64,8 +64,16 @@ struct RISCVIOMMUContext { uint64_t msiptp; /* MSI redirection page table pointer */ }; +typedef enum RISCVIOMMUTransTag { + RISCV_IOMMU_TRANS_TAG_BY, /* Bypass */ + RISCV_IOMMU_TRANS_TAG_SS, /* Single Stage */ + RISCV_IOMMU_TRANS_TAG_VG, /* G-stage only */ + RISCV_IOMMU_TRANS_TAG_VN, /* Nested translation */ +} RISCVIOMMUTransTag; + /* Address translation cache entry */ struct RISCVIOMMUEntry { + RISCVIOMMUTransTag tag; /* Translation Tag */ uint64_t iova:44; /* IOVA Page Number */ uint64_t pscid:20; /* Process Soft-Context identifier */ uint64_t phys:44; /* Physical Page Number */ @@ -1227,7 +1235,7 @@ static gboolean riscv_iommu_iot_equal(gconstpointer v1, gconstpointer v2) RISCVIOMMUEntry *t1 = (RISCVIOMMUEntry *) v1; RISCVIOMMUEntry *t2 = (RISCVIOMMUEntry *) v2; return t1->gscid == t2->gscid && t1->pscid == t2->pscid && - t1->iova == t2->iova; + t1->iova == t2->iova && t1->tag == t2->tag; } static guint riscv_iommu_iot_hash(gconstpointer v) @@ -1236,67 +1244,115 @@ static guint riscv_iommu_iot_hash(gconstpointer v) return (guint)t->iova; } -/* GV: 1 PSCV: 1 AV: 1 */ +/* GV: 0 AV: 0 PSCV: 0 GVMA: 0 */ +/* GV: 0 AV: 0 GVMA: 1 */ +static +void riscv_iommu_iot_inval_all(gpointer key, gpointer value, gpointer data) +{ + RISCVIOMMUEntry *iot = (RISCVIOMMUEntry *) value; + RISCVIOMMUEntry *arg = (RISCVIOMMUEntry *) data; + if (iot->tag == arg->tag) { + iot->perm = IOMMU_NONE; + } +} + +/* GV: 0 AV: 0 PSCV: 1 GVMA: 0 */ +static +void riscv_iommu_iot_inval_pscid(gpointer key, gpointer value, gpointer data) +{ + RISCVIOMMUEntry *iot = (RISCVIOMMUEntry *) value; + RISCVIOMMUEntry *arg = (RISCVIOMMUEntry *) data; + if (iot->tag == arg->tag && + iot->pscid == arg->pscid) { + iot->perm = IOMMU_NONE; + } +} + +/* GV: 0 AV: 1 PSCV: 0 GVMA: 0 */ +static +void riscv_iommu_iot_inval_iova(gpointer key, gpointer value, gpointer data) +{ + RISCVIOMMUEntry *iot = (RISCVIOMMUEntry *) value; + RISCVIOMMUEntry *arg = (RISCVIOMMUEntry *) data; + if (iot->tag == arg->tag && + iot->iova == arg->iova) { + iot->perm = IOMMU_NONE; + } +} + +/* GV: 0 AV: 1 PSCV: 1 GVMA: 0 */ static void riscv_iommu_iot_inval_pscid_iova(gpointer key, gpointer value, gpointer data) { RISCVIOMMUEntry *iot = (RISCVIOMMUEntry *) value; RISCVIOMMUEntry *arg = (RISCVIOMMUEntry *) data; - if (iot->gscid == arg->gscid && + if (iot->tag == arg->tag && iot->pscid == arg->pscid && iot->iova == arg->iova) { iot->perm = IOMMU_NONE; } } -/* GV: 1 PSCV: 1 AV: 0 */ -static void riscv_iommu_iot_inval_pscid(gpointer key, gpointer value, - gpointer data) +/* GV: 1 AV: 0 PSCV: 0 GVMA: 0 */ +/* GV: 1 AV: 0 GVMA: 1 */ +static +void riscv_iommu_iot_inval_gscid(gpointer key, gpointer value, gpointer data) { RISCVIOMMUEntry *iot = (RISCVIOMMUEntry *) value; RISCVIOMMUEntry *arg = (RISCVIOMMUEntry *) data; - if (iot->gscid == arg->gscid && - iot->pscid == arg->pscid) { + if (iot->tag == arg->tag && + iot->gscid == arg->gscid) { iot->perm = IOMMU_NONE; } } -/* GV: 1 GVMA: 1 */ -static void riscv_iommu_iot_inval_gscid_gpa(gpointer key, gpointer value, - gpointer data) +/* GV: 1 AV: 0 PSCV: 1 GVMA: 0 */ +static void riscv_iommu_iot_inval_gscid_pscid(gpointer key, gpointer value, + gpointer data) { RISCVIOMMUEntry *iot = (RISCVIOMMUEntry *) value; RISCVIOMMUEntry *arg = (RISCVIOMMUEntry *) data; - if (iot->gscid == arg->gscid) { - /* simplified cache, no GPA matching */ + if (iot->tag == arg->tag && + iot->gscid == arg->gscid && + iot->pscid == arg->pscid) { iot->perm = IOMMU_NONE; } } -/* GV: 1 GVMA: 0 */ -static void riscv_iommu_iot_inval_gscid(gpointer key, gpointer value, - gpointer data) +/* GV: 1 AV: 1 PSCV: 0 GVMA: 0 */ +/* GV: 1 AV: 1 GVMA: 1 */ +static void riscv_iommu_iot_inval_gscid_iova(gpointer key, gpointer value, + gpointer data) { RISCVIOMMUEntry *iot = (RISCVIOMMUEntry *) value; RISCVIOMMUEntry *arg = (RISCVIOMMUEntry *) data; - if (iot->gscid == arg->gscid) { + if (iot->tag == arg->tag && + iot->gscid == arg->gscid && + iot->iova == arg->iova) { iot->perm = IOMMU_NONE; } } -/* GV: 0 */ -static void riscv_iommu_iot_inval_all(gpointer key, gpointer value, - gpointer data) +/* GV: 1 AV: 1 PSCV: 1 GVMA: 0 */ +static void riscv_iommu_iot_inval_gscid_pscid_iova(gpointer key, gpointer value, + gpointer data) { RISCVIOMMUEntry *iot = (RISCVIOMMUEntry *) value; - iot->perm = IOMMU_NONE; + RISCVIOMMUEntry *arg = (RISCVIOMMUEntry *) data; + if (iot->tag == arg->tag && + iot->gscid == arg->gscid && + iot->pscid == arg->pscid && + iot->iova == arg->iova) { + iot->perm = IOMMU_NONE; + } } /* caller should keep ref-count for iot_cache object */ static RISCVIOMMUEntry *riscv_iommu_iot_lookup(RISCVIOMMUContext *ctx, - GHashTable *iot_cache, hwaddr iova) + GHashTable *iot_cache, hwaddr iova, RISCVIOMMUTransTag transtag) { RISCVIOMMUEntry key = { + .tag = transtag, .gscid = get_field(ctx->gatp, RISCV_IOMMU_DC_IOHGATP_GSCID), .pscid = get_field(ctx->ta, RISCV_IOMMU_DC_TA_PSCID), .iova = PPN_DOWN(iova), @@ -1322,10 +1378,11 @@ static void riscv_iommu_iot_update(RISCVIOMMUState *s, } static void riscv_iommu_iot_inval(RISCVIOMMUState *s, GHFunc func, - uint32_t gscid, uint32_t pscid, hwaddr iova) + uint32_t gscid, uint32_t pscid, hwaddr iova, RISCVIOMMUTransTag transtag) { GHashTable *iot_cache; RISCVIOMMUEntry key = { + .tag = transtag, .gscid = gscid, .pscid = pscid, .iova = PPN_DOWN(iova), @@ -1336,9 +1393,24 @@ static void riscv_iommu_iot_inval(RISCVIOMMUState *s, GHFunc func, g_hash_table_unref(iot_cache); } +static RISCVIOMMUTransTag riscv_iommu_get_transtag(RISCVIOMMUContext *ctx) +{ + uint64_t satp = get_field(ctx->satp, RISCV_IOMMU_ATP_MODE_FIELD); + uint64_t gatp = get_field(ctx->gatp, RISCV_IOMMU_ATP_MODE_FIELD); + + if (satp == RISCV_IOMMU_DC_FSC_MODE_BARE) { + return (gatp == RISCV_IOMMU_DC_IOHGATP_MODE_BARE) ? + RISCV_IOMMU_TRANS_TAG_BY : RISCV_IOMMU_TRANS_TAG_VG; + } else { + return (gatp == RISCV_IOMMU_DC_IOHGATP_MODE_BARE) ? + RISCV_IOMMU_TRANS_TAG_SS : RISCV_IOMMU_TRANS_TAG_VN; + } +} + static int riscv_iommu_translate(RISCVIOMMUState *s, RISCVIOMMUContext *ctx, IOMMUTLBEntry *iotlb, bool enable_cache) { + RISCVIOMMUTransTag transtag = riscv_iommu_get_transtag(ctx); RISCVIOMMUEntry *iot; IOMMUAccessFlags perm; bool enable_pid; @@ -1364,7 +1436,7 @@ static int riscv_iommu_translate(RISCVIOMMUState *s, RISCVIOMMUContext *ctx, } } - iot = riscv_iommu_iot_lookup(ctx, iot_cache, iotlb->iova); + iot = riscv_iommu_iot_lookup(ctx, iot_cache, iotlb->iova, transtag); perm = iot ? iot->perm : IOMMU_NONE; if (perm != IOMMU_NONE) { iotlb->translated_addr = PPN_PHYS(iot->phys); @@ -1395,6 +1467,7 @@ static int riscv_iommu_translate(RISCVIOMMUState *s, RISCVIOMMUContext *ctx, iot->gscid = get_field(ctx->gatp, RISCV_IOMMU_DC_IOHGATP_GSCID); iot->pscid = get_field(ctx->ta, RISCV_IOMMU_DC_TA_PSCID); iot->perm = iotlb->perm; + iot->tag = transtag; riscv_iommu_iot_update(s, iot_cache, iot); } @@ -1602,44 +1675,72 @@ static void riscv_iommu_process_cq_tail(RISCVIOMMUState *s) case RISCV_IOMMU_CMD(RISCV_IOMMU_CMD_IOTINVAL_FUNC_GVMA, RISCV_IOMMU_CMD_IOTINVAL_OPCODE): - if (cmd.dword0 & RISCV_IOMMU_CMD_IOTINVAL_PSCV) { + { + bool gv = !!(cmd.dword0 & RISCV_IOMMU_CMD_IOTINVAL_GV); + bool av = !!(cmd.dword0 & RISCV_IOMMU_CMD_IOTINVAL_AV); + bool pscv = !!(cmd.dword0 & RISCV_IOMMU_CMD_IOTINVAL_PSCV); + uint32_t gscid = get_field(cmd.dword0, + RISCV_IOMMU_CMD_IOTINVAL_GSCID); + uint32_t pscid = get_field(cmd.dword0, + RISCV_IOMMU_CMD_IOTINVAL_PSCID); + hwaddr iova = (cmd.dword1 << 2) & TARGET_PAGE_MASK; + + if (pscv) { /* illegal command arguments IOTINVAL.GVMA & PSCV == 1 */ goto cmd_ill; - } else if (!(cmd.dword0 & RISCV_IOMMU_CMD_IOTINVAL_GV)) { - /* invalidate all cache mappings */ - func = riscv_iommu_iot_inval_all; - } else if (!(cmd.dword0 & RISCV_IOMMU_CMD_IOTINVAL_AV)) { - /* invalidate cache matching GSCID */ - func = riscv_iommu_iot_inval_gscid; - } else { - /* invalidate cache matching GSCID and ADDR (GPA) */ - func = riscv_iommu_iot_inval_gscid_gpa; } - riscv_iommu_iot_inval(s, func, - get_field(cmd.dword0, RISCV_IOMMU_CMD_IOTINVAL_GSCID), 0, - cmd.dword1 << 2 & TARGET_PAGE_MASK); + + func = riscv_iommu_iot_inval_all; + + if (gv) { + func = (av) ? riscv_iommu_iot_inval_gscid_iova : + riscv_iommu_iot_inval_gscid; + } + + riscv_iommu_iot_inval( + s, func, gscid, pscid, iova, RISCV_IOMMU_TRANS_TAG_VG); + + riscv_iommu_iot_inval( + s, func, gscid, pscid, iova, RISCV_IOMMU_TRANS_TAG_VN); break; + } case RISCV_IOMMU_CMD(RISCV_IOMMU_CMD_IOTINVAL_FUNC_VMA, RISCV_IOMMU_CMD_IOTINVAL_OPCODE): - if (!(cmd.dword0 & RISCV_IOMMU_CMD_IOTINVAL_GV)) { - /* invalidate all cache mappings, simplified model */ - func = riscv_iommu_iot_inval_all; - } else if (!(cmd.dword0 & RISCV_IOMMU_CMD_IOTINVAL_PSCV)) { - /* invalidate cache matching GSCID, simplified model */ - func = riscv_iommu_iot_inval_gscid; - } else if (!(cmd.dword0 & RISCV_IOMMU_CMD_IOTINVAL_AV)) { - /* invalidate cache matching GSCID and PSCID */ - func = riscv_iommu_iot_inval_pscid; + { + bool gv = !!(cmd.dword0 & RISCV_IOMMU_CMD_IOTINVAL_GV); + bool av = !!(cmd.dword0 & RISCV_IOMMU_CMD_IOTINVAL_AV); + bool pscv = !!(cmd.dword0 & RISCV_IOMMU_CMD_IOTINVAL_PSCV); + uint32_t gscid = get_field(cmd.dword0, + RISCV_IOMMU_CMD_IOTINVAL_GSCID); + uint32_t pscid = get_field(cmd.dword0, + RISCV_IOMMU_CMD_IOTINVAL_PSCID); + hwaddr iova = (cmd.dword1 << 2) & TARGET_PAGE_MASK; + RISCVIOMMUTransTag transtag; + + if (gv) { + transtag = RISCV_IOMMU_TRANS_TAG_VN; + if (pscv) { + func = (av) ? riscv_iommu_iot_inval_gscid_pscid_iova : + riscv_iommu_iot_inval_gscid_pscid; + } else { + func = (av) ? riscv_iommu_iot_inval_gscid_iova : + riscv_iommu_iot_inval_gscid; + } } else { - /* invalidate cache matching GSCID and PSCID and ADDR (IOVA) */ - func = riscv_iommu_iot_inval_pscid_iova; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.15.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:15:29 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alexey Baturo , Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 49/50] target/riscv: Support Supm and Sspm as part of Zjpm v1.0 Date: Sun, 19 Jan 2025 11:12:24 +1000 Message-ID: <20250119011225.11452-50-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Alexey Baturo The Zjpm v1.0 spec states there should be Supm and Sspm extensions that are used in profile specification. Enabling Supm extension enables both Ssnpm and Smnpm, while Sspm enables only Smnpm. Signed-off-by: Alexey Baturo Reviewed-by: Daniel Henrique Barboza Message-ID: <20250113194410.1307494-1-baturo.alexey@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 2 ++ target/riscv/cpu.c | 23 +++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index aef896ba00..b410b1e603 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -139,6 +139,8 @@ struct RISCVCPUConfig { bool ext_ssnpm; bool ext_smnpm; bool ext_smmpm; + bool ext_sspm; + bool ext_supm; bool rvv_ta_all_1s; bool rvv_ma_all_1s; bool rvv_vl_half_avl; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index bddf1ba75e..3d4bd157d2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -208,10 +208,12 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(sscsrind, PRIV_VERSION_1_12_0, ext_sscsrind), ISA_EXT_DATA_ENTRY(ssdbltrp, PRIV_VERSION_1_13_0, ext_ssdbltrp), ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_13_0, ext_ssnpm), + ISA_EXT_DATA_ENTRY(sspm, PRIV_VERSION_1_13_0, ext_sspm), ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), + ISA_EXT_DATA_ENTRY(supm, PRIV_VERSION_1_13_0, ext_supm), ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade), ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), @@ -1625,6 +1627,8 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("zvfhmin", ext_zvfhmin, false), MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false), + MULTI_EXT_CFG_BOOL("sspm", ext_sspm, false), + MULTI_EXT_CFG_BOOL("supm", ext_supm, false), MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), MULTI_EXT_CFG_BOOL("smdbltrp", ext_smdbltrp, false), @@ -2781,6 +2785,24 @@ static RISCVCPUImpliedExtsRule SSCFG_IMPLIED = { }, }; +static RISCVCPUImpliedExtsRule SUPM_IMPLIED = { + .ext = CPU_CFG_OFFSET(ext_supm), + .implied_multi_exts = { + CPU_CFG_OFFSET(ext_ssnpm), CPU_CFG_OFFSET(ext_smnpm), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule SSPM_IMPLIED = { + .ext = CPU_CFG_OFFSET(ext_sspm), + .implied_multi_exts = { + CPU_CFG_OFFSET(ext_smnpm), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = { &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED, &RVM_IMPLIED, &RVV_IMPLIED, NULL @@ -2799,6 +2821,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = { &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED, &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED, &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SSCFG_IMPLIED, + &SUPM_IMPLIED, &SSPM_IMPLIED, NULL }; From patchwork Sun Jan 19 01:12:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13944315 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B81BC02185 for ; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.15.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:15:32 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL v2 50/50] hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events Date: Sun, 19 Jan 2025 11:12:25 +1000 Message-ID: <20250119011225.11452-51-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-ID: <20250116223609.81594-1-philmd@linaro.org> Signed-off-by: Alistair Francis --- hw/char/riscv_htif.c | 15 +++------------ hw/char/trace-events | 4 ++++ 2 files changed, 7 insertions(+), 12 deletions(-) diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index 11a0e1a7b7..ec5db5a597 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -32,14 +32,7 @@ #include "exec/tswap.h" #include "system/dma.h" #include "system/runstate.h" - -#define RISCV_DEBUG_HTIF 0 -#define HTIF_DEBUG(fmt, ...) \ - do { \ - if (RISCV_DEBUG_HTIF) { \ - qemu_log_mask(LOG_TRACE, "%s: " fmt "\n", __func__, ##__VA_ARGS__);\ - } \ - } while (0) +#include "trace.h" #define HTIF_DEV_SHIFT 56 #define HTIF_CMD_SHIFT 48 @@ -159,8 +152,7 @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written) uint64_t payload = val_written & 0xFFFFFFFFFFFFULL; int resp = 0; - HTIF_DEBUG("mtohost write: device: %d cmd: %d what: %02" PRIx64 - " -payload: %016" PRIx64 "\n", device, cmd, payload & 0xFF, payload); + trace_htif_uart_write_to_host(device, cmd, payload); /* * Currently, there is a fixed mapping of devices: @@ -251,8 +243,7 @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written) } } else { qemu_log("HTIF unknown device or command\n"); - HTIF_DEBUG("device: %d cmd: %d what: %02" PRIx64 - " payload: %016" PRIx64, device, cmd, payload & 0xFF, payload); + trace_htif_uart_unknown_device_command(device, cmd, payload); } /* * Latest bbl does not set fromhost to 0 if there is a value in tohost. diff --git a/hw/char/trace-events b/hw/char/trace-events index 3ee7cfcdff..b2e3d25ae3 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -136,3 +136,7 @@ stm32f2xx_usart_read(char *id, unsigned size, uint64_t ofs, uint64_t val) " %s s stm32f2xx_usart_write(char *id, unsigned size, uint64_t ofs, uint64_t val) "%s size %d ofs 0x%02" PRIx64 " <- 0x%02" PRIx64 stm32f2xx_usart_drop(char *id) " %s dropping the chars" stm32f2xx_usart_receive(char *id, uint8_t chr) " %s receiving '%c'" + +# riscv_htif.c +htif_uart_write_to_host(uint8_t device, uint8_t cmd, uint64_t payload) "device: %u cmd: %02u payload: %016" PRIx64 +htif_uart_unknown_device_command(uint8_t device, uint8_t cmd, uint64_t payload) "device: %u cmd: %02u payload: %016" PRIx64