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Sun, 19 Jan 2025 12:00:51 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 19 Jan 2025 04:00:48 -0800 From: Taniya Das Date: Sun, 19 Jan 2025 17:30:27 +0530 Subject: [PATCH v2 1/2] arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250119-qcs615-mm-v2-dt-nodes-v2-1-c46ab4080989@quicinc.com> References: <20250119-qcs615-mm-v2-dt-nodes-v2-0-c46ab4080989@quicinc.com> In-Reply-To: <20250119-qcs615-mm-v2-dt-nodes-v2-0-c46ab4080989@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: IOBc58Td_DZA77-36cZb9p-9i8FQt89c X-Proofpoint-ORIG-GUID: IOBc58Td_DZA77-36cZb9p-9i8FQt89c X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-18_10,2025-01-16_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 clxscore=1015 phishscore=0 adultscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 spamscore=0 mlxlogscore=998 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501190093 Add support for video, camera, display and gpu clock controller nodes for QCS615 platform. Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 51 ++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index f4abfad474ea62dea13d05eb874530947e1e8d3e..9d537019437c5202c4d398eecd0ce2a991083175 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -3,7 +3,11 @@ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ +#include +#include #include +#include +#include #include #include #include @@ -1418,6 +1422,18 @@ data-pins { }; }; + gpucc: clock-controller@5090000 { + compatible = "qcom,qcs615-gpucc"; + reg = <0 0x05090000 0 0x9000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GPLL0>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x06002000 0x0 0x1000>, @@ -3187,6 +3203,41 @@ gem_noc: interconnect@9680000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + videocc: clock-controller@ab00000 { + compatible = "qcom,qcs615-videocc"; + reg = <0 0x0ab00000 0 0x10000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + camcc: clock-controller@ad00000 { + compatible = "qcom,qcs615-camcc"; + reg = <0 0x0ad00000 0 0x10000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,qcs615-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,qcs615-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>, From patchwork Sun Jan 19 12:00:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taniya Das X-Patchwork-Id: 13944423 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FD731DED79; Sun, 19 Jan 2025 12:00:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; 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Sun, 19 Jan 2025 12:00:56 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50JC0tBt019138 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 19 Jan 2025 12:00:55 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 19 Jan 2025 04:00:52 -0800 From: Taniya Das Date: Sun, 19 Jan 2025 17:30:28 +0530 Subject: [PATCH v2 2/2] arm64: dts: qcom: qcs615: Add CPU scaling clock node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250119-qcs615-mm-v2-dt-nodes-v2-2-c46ab4080989@quicinc.com> References: <20250119-qcs615-mm-v2-dt-nodes-v2-0-c46ab4080989@quicinc.com> In-Reply-To: <20250119-qcs615-mm-v2-dt-nodes-v2-0-c46ab4080989@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 5PGpUGgMA10O8Vm_FAdd1_KjQNImdpVq X-Proofpoint-GUID: 5PGpUGgMA10O8Vm_FAdd1_KjQNImdpVq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-18_10,2025-01-16_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=803 bulkscore=0 mlxscore=0 suspectscore=0 phishscore=0 priorityscore=1501 clxscore=1015 lowpriorityscore=0 impostorscore=0 malwarescore=0 adultscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501190093 Add cpufreq-hw node to support CPU frequency scaling. Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index 9d537019437c5202c4d398eecd0ce2a991083175..b8b50d5a668e2464715ef5abf5393affd9976814 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -36,6 +36,8 @@ cpu0: cpu@0 { capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&l2_0>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; l2_0: l2-cache { @@ -56,6 +58,8 @@ cpu1: cpu@100 { capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&l2_100>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; l2_100: l2-cache { compatible = "cache"; @@ -75,6 +79,8 @@ cpu2: cpu@200 { capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&l2_200>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; l2_200: l2-cache { compatible = "cache"; @@ -94,6 +100,8 @@ cpu3: cpu@300 { capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&l2_300>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; l2_300: l2-cache { compatible = "cache"; @@ -113,6 +121,8 @@ cpu4: cpu@400 { capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&l2_400>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; l2_400: l2-cache { compatible = "cache"; @@ -132,6 +142,8 @@ cpu5: cpu@500 { capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&l2_500>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; l2_500: l2-cache { compatible = "cache"; @@ -151,6 +163,8 @@ cpu6: cpu@600 { capacity-dmips-mhz = <1740>; dynamic-power-coefficient = <404>; next-level-cache = <&l2_600>; + clocks = <&cpufreq_hw 1>; + qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; l2_600: l2-cache { @@ -171,6 +185,8 @@ cpu7: cpu@700 { capacity-dmips-mhz = <1740>; dynamic-power-coefficient = <404>; next-level-cache = <&l2_700>; + clocks = <&cpufreq_hw 1>; + qcom,freq-domain = <&cpufreq_hw 1>; l2_700: l2-cache { compatible = "cache"; @@ -3711,6 +3727,18 @@ usb_2_dwc3: usb@a800000 { }; }; + cpufreq_hw: cpufreq@18323000 { + compatible = "qcom,sc7180-cpufreq-hw", qcom,cpufreq-hw"; + reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + arch_timer: timer { compatible = "arm,armv8-timer"; interrupts = ,