From patchwork Sun Jan 19 18:34:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 13944569 Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47E6E1DF240 for ; Sun, 19 Jan 2025 18:44:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=84.16.241.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737312269; cv=none; b=TzFNu1DXTpF6SuPqxSdDC6khja4UNAlNNxBjYW9mIlgX3ofPTZdVQK74+fvMkbjJr0t3pcpNw5MtHDCOilGnNReTOMtyKi4umcHbL+a0Swp4+7+bEDuLNjo70BHT8ZJN5kil1A54CwmjKZVpVzY8Ols6tVXkQlRyU1BYRWa7Mho= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737312269; c=relaxed/simple; bh=O3RVgBDqQ8ty40MmzDVyKK/AosSilQoJ9Z3By213rPw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qxb8eAKxtmntjc2JQ0auLMkjTZ1ScBJWvic3zvyhJ9yKb7Mgh9swNcwLZHUF0hiFHAvmWnDrFv9lIib0plWyrMfJgeYblGdPOZL+rpW2FOnTDoBBsOr1XTzP4aDcYQlcJAuMNi+uayeDNmTiiAAZ4cMANrT7ahG4Xjbf5/I8Y4c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=svanheule.net; spf=pass smtp.mailfrom=svanheule.net; dkim=pass (2048-bit key) header.d=svanheule.net header.i=@svanheule.net header.b=CpCVz7gi; arc=none smtp.client-ip=84.16.241.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=svanheule.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=svanheule.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=svanheule.net header.i=@svanheule.net header.b="CpCVz7gi" Received: from terra.vega.svanheule.net (unknown [94.110.49.146]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id 09C385A7E4C; Sun, 19 Jan 2025 19:34:50 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1737311690; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kiaTltfe3TpwNCiKPtsYlqYsvoY4+IUaNYIQw82paTU=; b=CpCVz7giJzeehZYAXE5ub3tFDDN6vWbwVFpI75gp4OvOnWaC5gpFebPlq0I2UzxD7z/20F Whzf9VQ7ufWSNFOxA0GfrcEA3QCrZ8dkRWk8ek6uvqDSP3af6nvhQnb6hi67X97e6WcEuJ KLzWj3A/j/ZDoOGKHmLwhZVGd6XIIK4cGU9yxa5oFjNdADDPs+gKbWhSL7f0QnCNPisiKX WXya1NKuAUPJcDNAgtMi2cTkOmWVh0VfEwjN+dg3C1gPnBCq5cd3ycW7zJdQFT0PTahLoq jwfv8N7qaSchpaIcYBmAoIrPDdCwSmS+FO3LhNrF/aLND/y9SUtvqsYoUolBNQ== From: Sander Vanheule To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Chris Packham , devicetree@vger.kernel.org, linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sander Vanheule Subject: [PATCH 1/9] mips: dts: realtek: Decouple RTL930x base DTSI Date: Sun, 19 Jan 2025 19:34:16 +0100 Message-ID: <20250119183424.259353-2-sander@svanheule.net> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119183424.259353-1-sander@svanheule.net> References: <20250119183424.259353-1-sander@svanheule.net> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The RTL930x SoC series is sufficiently different to warrant its own base dtsi. This ensures no properties need to be deleted or overwritten, and prevents accidental inclusions of updates from rtl83xx.dtsi. Signed-off-by: Sander Vanheule Reviewed-by: Chris Packham Tested-by: Chris Packham # For RTL9302C --- arch/mips/boot/dts/realtek/rtl930x.dtsi | 133 +++++++++++++++--------- 1 file changed, 83 insertions(+), 50 deletions(-) diff --git a/arch/mips/boot/dts/realtek/rtl930x.dtsi b/arch/mips/boot/dts/realtek/rtl930x.dtsi index 17577457d159..67261d6fcaa7 100644 --- a/arch/mips/boot/dts/realtek/rtl930x.dtsi +++ b/arch/mips/boot/dts/realtek/rtl930x.dtsi @@ -1,10 +1,23 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause -#include "rtl83xx.dtsi" - / { compatible = "realtek,rtl9302-soc"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + cpuintc: cpuintc { + compatible = "mti,cpu-interrupt-controller"; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -58,64 +71,84 @@ i2c1: i2c@388 { status = "disabled"; }; }; -}; -&soc { - ranges = <0x0 0x18000000 0x20000>; + soc: soc@18000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000000 0x20000>; - intc: interrupt-controller@3000 { - compatible = "realtek,rtl9300-intc", "realtek,rtl-intc"; - reg = <0x3000 0x18>, <0x3018 0x18>; - interrupt-controller; - #interrupt-cells = <1>; + intc: interrupt-controller@3000 { + compatible = "realtek,rtl9300-intc", "realtek,rtl-intc"; + reg = <0x3000 0x18>, <0x3018 0x18>; + interrupt-controller; + #interrupt-cells = <1>; - interrupt-parent = <&cpuintc>; - interrupts = <2>, <3>, <4>, <5>, <6>, <7>; - }; + interrupt-parent = <&cpuintc>; + interrupts = <2>, <3>, <4>, <5>, <6>, <7>; + }; - spi0: spi@1200 { - compatible = "realtek,rtl8380-spi"; - reg = <0x1200 0x100>; + spi0: spi@1200 { + compatible = "realtek,rtl8380-spi"; + reg = <0x1200 0x100>; - #address-cells = <1>; - #size-cells = <0>; - }; + #address-cells = <1>; + #size-cells = <0>; + }; - timer0: timer@3200 { - compatible = "realtek,rtl9302-timer", "realtek,otto-timer"; - reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>, - <0x3230 0x10>, <0x3240 0x10>; + timer0: timer@3200 { + compatible = "realtek,rtl9302-timer", "realtek,otto-timer"; + reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>, + <0x3230 0x10>, <0x3240 0x10>; - interrupt-parent = <&intc>; - interrupts = <7>, <8>, <9>, <10>, <11>; - clocks = <&lx_clk>; - }; + interrupt-parent = <&intc>; + interrupts = <7>, <8>, <9>, <10>, <11>; + clocks = <&lx_clk>; + }; - snand: spi@1a400 { - compatible = "realtek,rtl9301-snand"; - reg = <0x1a400 0x44>; - interrupt-parent = <&intc>; - interrupts = <19>; - clocks = <&lx_clk>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; + snand: spi@1a400 { + compatible = "realtek,rtl9301-snand"; + reg = <0x1a400 0x44>; + interrupt-parent = <&intc>; + interrupts = <19>; + clocks = <&lx_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; -&uart0 { - /delete-property/ clock-frequency; - clocks = <&lx_clk>; + uart0: serial@2000 { + compatible = "ns16550a"; + reg = <0x2000 0x100>; - interrupt-parent = <&intc>; - interrupts = <30>; -}; + clocks = <&lx_clk>; -&uart1 { - /delete-property/ clock-frequency; - clocks = <&lx_clk>; + interrupt-parent = <&intc>; + interrupts = <30>; - interrupt-parent = <&intc>; - interrupts = <31>; -}; + reg-io-width = <1>; + reg-shift = <2>; + fifo-size = <1>; + no-loopback-test; + status = "disabled"; + }; + + uart1: serial@2100 { + compatible = "ns16550a"; + reg = <0x2100 0x100>; + + clocks = <&lx_clk>; + + interrupt-parent = <&intc>; + interrupts = <31>; + + reg-io-width = <1>; + reg-shift = <2>; + fifo-size = <1>; + no-loopback-test; + + status = "disabled"; + }; + }; +}; From patchwork Sun Jan 19 18:34:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 13944571 Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00BBB1DFD8F for ; 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arc=none smtp.client-ip=84.16.241.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=svanheule.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=svanheule.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=svanheule.net header.i=@svanheule.net header.b="oQmIvtBA" Received: from terra.vega.svanheule.net (unknown [94.110.49.146]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id 96FB75A7E4D; Sun, 19 Jan 2025 19:34:50 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1737311690; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=JmnlXKkw6WYoqwfymcm3ceL6H3zSYoIfS+V2I2wrFc8=; b=oQmIvtBAZQknoMlSpM1tlit8GrRhyvwkpb0/HBeSTjwI6O8uw0oERSjkrkVT07/vHCmYKb 7r7gS+OwWRTNqe+HWxDj0xiQDpGF7IJ1wBU+P6ZuV9WOM4iUHlOMKKdmy7DtulWafGWiDb YkFeAei+BCvLdVcItCUELpwnP33SuQu7ltIgr5ToKcVwSI4VMI56I6l9C48NoCi+NoT64o VFXS0/xMJ0ihGYSZqtM44X4liIVtzVcQ6l4xC81mK51LnTNMzxjcYUV0SyTnthlLvH8vTe WAkGQ3X0qJ4gekGfKP8ul4tqzmg8gEWMtEe9+kvUDdb2Chvx2v6HsjcoITcbmA== From: Sander Vanheule To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Chris Packham , devicetree@vger.kernel.org, linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sander Vanheule Subject: [PATCH 2/9] mips: dts: realtek: Clean up CPU clocks Date: Sun, 19 Jan 2025 19:34:17 +0100 Message-ID: <20250119183424.259353-3-sander@svanheule.net> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119183424.259353-1-sander@svanheule.net> References: <20250119183424.259353-1-sander@svanheule.net> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The referenced CPU clock does not require any additional #clock-cells, so drop the extraneous '0' in the referenced CPU clock. The binding for MIPS cpus also does not allow for the clock-names property, so just drop it. This resolves some error message from 'dtbs_check': cpu@0: clocks: [[4], [0]] is too long 'clock-names' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Sander Vanheule Reviewed-by: Chris Packham Tested-by: Chris Packham # For RTL9302C --- arch/mips/boot/dts/realtek/rtl838x.dtsi | 3 +-- arch/mips/boot/dts/realtek/rtl930x.dtsi | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/mips/boot/dts/realtek/rtl838x.dtsi b/arch/mips/boot/dts/realtek/rtl838x.dtsi index 722106e39194..d2c6baabb38c 100644 --- a/arch/mips/boot/dts/realtek/rtl838x.dtsi +++ b/arch/mips/boot/dts/realtek/rtl838x.dtsi @@ -9,8 +9,7 @@ cpu@0 { device_type = "cpu"; compatible = "mips,mips4KEc"; reg = <0>; - clocks = <&baseclk 0>; - clock-names = "cpu"; + clocks = <&baseclk>; }; }; diff --git a/arch/mips/boot/dts/realtek/rtl930x.dtsi b/arch/mips/boot/dts/realtek/rtl930x.dtsi index 67261d6fcaa7..f2e57ea3a60c 100644 --- a/arch/mips/boot/dts/realtek/rtl930x.dtsi +++ b/arch/mips/boot/dts/realtek/rtl930x.dtsi @@ -26,8 +26,7 @@ cpu@0 { device_type = "cpu"; compatible = "mips,mips34Kc"; reg = <0>; - clocks = <&baseclk 0>; - clock-names = "cpu"; + clocks = <&baseclk>; }; }; From patchwork Sun Jan 19 18:34:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 13944572 Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B9321DFD94 for ; Sun, 19 Jan 2025 18:44:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=84.16.241.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737312270; cv=none; b=Js6cnAQ/PvPMTVtAgguGCfJ1G9A9tD/vZpX2lBLZhxB4oWfRh83A5w8Jbmgj68tTlvgPB8uIQdXzsq6cLZy+pXYmIeyoA0zvgXaqcoceQstsuEHCe32+NLhVvieMR53Z7g2+CcQWIcomYAIHakr3268psXh91+6YeHhKhqzbKrA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737312270; c=relaxed/simple; bh=vBUI1WTwvwlq9hWbSW/h3vK5gits9GeBFSD50wq7OPY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aGPeTzWHismqJLiC2efNQJ5ReQaxqtPCWB1ahsvM1obUN9tVylbi/h41pSsDavZTZEhH9jBwgS2nQCHcj4KKDIiiNXCWvxwq6FpGduNMVOHHIgkX4kszhdoUqX28225vzMjw4eyBV+KcQU5tY2zsOlM1sj6b8kWOtUQMRJtqhtg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=svanheule.net; spf=pass smtp.mailfrom=svanheule.net; dkim=pass (2048-bit key) header.d=svanheule.net header.i=@svanheule.net header.b=QYGLCx39; arc=none smtp.client-ip=84.16.241.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=svanheule.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=svanheule.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=svanheule.net header.i=@svanheule.net header.b="QYGLCx39" Received: from terra.vega.svanheule.net (unknown [94.110.49.146]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id 11B855A7E4E; Sun, 19 Jan 2025 19:34:51 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1737311691; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6WJoRzWJ8gqvs1EYgx8tUmkbjMY4RQ2licgvVNYBIGw=; b=QYGLCx391dnjsLRTTXtb4dwrAWUL54EmMRBkASD6R9Yzy6yeN6SZ0wbfLbJppQ1/olHcT6 QM5rLg08C2NhCro0GL/hw47GcApOYzMxf6FZ6u//sqpbi4gL9xqxcOrgOb4Lg1TpkjRgDH UOq34J4ltZ3MRdkxE1rCozwnk7HJgtJ43Tfr47DKZdjUrLyBPRsdrJqAfEDhGgPFHYgooO WjYRyiLvzGs9Q3NNHndmN9AQwQDLyZtNhu7sasn2wrl4t5XuX5gC01XFXlIuTgdh1yVKl3 Zeuf2WvYWg3bD524AE7i3c+jcQD9BPhdzPSvmvEo/CVmytaHUc/UITQlywGstA== From: Sander Vanheule To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Chris Packham , devicetree@vger.kernel.org, linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sander Vanheule Subject: [PATCH 3/9] mips: dts: realtek: Add address to SoC node name Date: Sun, 19 Jan 2025 19:34:18 +0100 Message-ID: <20250119183424.259353-4-sander@svanheule.net> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119183424.259353-1-sander@svanheule.net> References: <20250119183424.259353-1-sander@svanheule.net> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Although not strictly required by the simple-bus binding, add the bus offset to the node name to be consistent with other nodes. Also drop the node label as it is not referenced anywhere. Signed-off-by: Sander Vanheule Reviewed-by: Chris Packham --- arch/mips/boot/dts/realtek/rtl83xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/boot/dts/realtek/rtl83xx.dtsi b/arch/mips/boot/dts/realtek/rtl83xx.dtsi index 03ddc61f7c9e..1039cb50c7da 100644 --- a/arch/mips/boot/dts/realtek/rtl83xx.dtsi +++ b/arch/mips/boot/dts/realtek/rtl83xx.dtsi @@ -16,7 +16,7 @@ cpuintc: cpuintc { interrupt-controller; }; - soc: soc { + soc@18000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; From patchwork Sun Jan 19 18:34:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 13944573 Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4F541DFD9E for ; Sun, 19 Jan 2025 18:44:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=84.16.241.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737312271; cv=none; b=STRzAb1jxfW35MVDvsdmmKi2fh94r0IIO8zNocaYMpzbWQS8HQFzN3Zf16fLqfRNpkTtFaOLZyXAqMmL+Q0NXPhpO6OWFZrpzJV/g1rFwfoaEMOP4JSoOtOSnmGMlqDGyHeI7bICWXGDN9w5qSAWHf7HkLfaZTHHAjvOK2NGoJg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737312271; c=relaxed/simple; bh=7s6X85dGKcKt5k7mqwpvUEVLA1joFbe4Mqz6Q3UURz0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NvsmGL5u8z5zcCJkjUsyrhcK38cQxQAjDfhMy4kWHA8p+m0HRRR+zEg/JMExjDzagCBbWjq0HE1gLSP3Y81kpJHs7tbXArtgr4ymC5CYmos13yUE0fGH3RHfezVQF/Yon0NoenDIMYOVj1bWZ4nw8UbSvWvuJY1HIDNhr/rYTAY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=svanheule.net; spf=pass smtp.mailfrom=svanheule.net; dkim=pass (2048-bit key) header.d=svanheule.net header.i=@svanheule.net header.b=MrXWG2BB; arc=none smtp.client-ip=84.16.241.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=svanheule.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=svanheule.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=svanheule.net header.i=@svanheule.net header.b="MrXWG2BB" Received: from terra.vega.svanheule.net (unknown [94.110.49.146]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id 9C29A5A7E4F; Sun, 19 Jan 2025 19:34:51 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1737311691; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AAtOPeGdFJYu13oCktZjkO7SD0htkFwt14XxJEDOn3U=; b=MrXWG2BB03kP3f7jqTD4qhtMaXJUsObRdgrDGCRvZvjcVjUFIBHiW4EFWO1ITVfGHDYkG9 Iu381a9x+cGs6ecKhCQOzdOyBEBrF4CgRi5EVFrUnm2QCNf1MFuVdkMnwrkhZgsUrpBdtk dGBjy8U6wHzqFxtQ4rSGrbcsNmz2d2FWZTbUYiixxHSL9Sigu9mjD13gnfC6LVfc0NPTs9 Q0zrCPvsadBsChS37FPSH+qtu01QoT49gXF/kIxuP99gC4l0NcwMnlnZvamL1N4hMVVKI9 MahNpH2ccVOYJYk5DbGZ1gBdwceOlkCxTod6kpQ1DZHvMuqabj7LqzeXopdV0g== From: Sander Vanheule To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Chris Packham , devicetree@vger.kernel.org, linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sander Vanheule Subject: [PATCH 4/9] mips: dts: realtek: Fold rtl83xx into rtl838x Date: Sun, 19 Jan 2025 19:34:19 +0100 Message-ID: <20250119183424.259353-5-sander@svanheule.net> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119183424.259353-1-sander@svanheule.net> References: <20250119183424.259353-1-sander@svanheule.net> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 rtl83xx.dtsi was once (presumably) created as a base for both RTL838x and RTL839x SoCs. Both SoCs have a different CPU and the peripherals require different compatibles. Fold rtl83xx.dtsi into rtl838x.dtsi, currently only supporting RTL838x SoCs, and create the RTL839x base include later when required. Signed-off-by: Sander Vanheule Reviewed-by: Chris Packham --- arch/mips/boot/dts/realtek/cisco_sg220-26.dts | 1 - arch/mips/boot/dts/realtek/rtl838x.dtsi | 56 ++++++++++++++++++ arch/mips/boot/dts/realtek/rtl83xx.dtsi | 59 ------------------- 3 files changed, 56 insertions(+), 60 deletions(-) delete mode 100644 arch/mips/boot/dts/realtek/rtl83xx.dtsi diff --git a/arch/mips/boot/dts/realtek/cisco_sg220-26.dts b/arch/mips/boot/dts/realtek/cisco_sg220-26.dts index 1cdbb09297ef..cb85d172a1d3 100644 --- a/arch/mips/boot/dts/realtek/cisco_sg220-26.dts +++ b/arch/mips/boot/dts/realtek/cisco_sg220-26.dts @@ -2,7 +2,6 @@ /dts-v1/; -#include "rtl83xx.dtsi" #include "rtl838x.dtsi" / { diff --git a/arch/mips/boot/dts/realtek/rtl838x.dtsi b/arch/mips/boot/dts/realtek/rtl838x.dtsi index d2c6baabb38c..907449094536 100644 --- a/arch/mips/boot/dts/realtek/rtl838x.dtsi +++ b/arch/mips/boot/dts/realtek/rtl838x.dtsi @@ -1,6 +1,14 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause / { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -18,4 +26,52 @@ baseclk: baseclk { #clock-cells = <0>; clock-frequency = <500000000>; }; + + cpuintc: cpuintc { + compatible = "mti,cpu-interrupt-controller"; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + + soc@18000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000000 0x10000>; + + uart0: serial@2000 { + compatible = "ns16550a"; + reg = <0x2000 0x100>; + + clock-frequency = <200000000>; + + interrupt-parent = <&cpuintc>; + interrupts = <31>; + + reg-io-width = <1>; + reg-shift = <2>; + fifo-size = <1>; + no-loopback-test; + + status = "disabled"; + }; + + uart1: serial@2100 { + compatible = "ns16550a"; + reg = <0x2100 0x100>; + + clock-frequency = <200000000>; + + interrupt-parent = <&cpuintc>; + interrupts = <30>; + + reg-io-width = <1>; + reg-shift = <2>; + fifo-size = <1>; + no-loopback-test; + + status = "disabled"; + }; + }; }; diff --git a/arch/mips/boot/dts/realtek/rtl83xx.dtsi b/arch/mips/boot/dts/realtek/rtl83xx.dtsi deleted file mode 100644 index 1039cb50c7da..000000000000 --- a/arch/mips/boot/dts/realtek/rtl83xx.dtsi +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - cpuintc: cpuintc { - compatible = "mti,cpu-interrupt-controller"; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - - soc@18000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x18000000 0x10000>; - - uart0: serial@2000 { - compatible = "ns16550a"; - reg = <0x2000 0x100>; - - clock-frequency = <200000000>; - - interrupt-parent = <&cpuintc>; - interrupts = <31>; - - reg-io-width = <1>; - reg-shift = <2>; - fifo-size = <1>; - no-loopback-test; - - status = "disabled"; - }; - - uart1: serial@2100 { - compatible = "ns16550a"; - reg = <0x2100 0x100>; - - clock-frequency = <200000000>; - - interrupt-parent = <&cpuintc>; - interrupts = <30>; - - reg-io-width = <1>; - reg-shift = <2>; - fifo-size = <1>; - no-loopback-test; - - status = "disabled"; - }; - }; -}; From patchwork Sun Jan 19 18:34:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 13944562 Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0250E3CF58 for ; Sun, 19 Jan 2025 18:34:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=84.16.241.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737311701; cv=none; b=SybHEPRFHSadCnaqIL669NshV0IPIZ9mrptP4UEmG3G24rC/hN1p7fkRV6Rc+zWdWcgifrdemnfxXsn6PBjYM4EKOk61FrCKhvsOkDWpHgxnA8tyP1nwhSuEH2mZZraSR5DRv6F2XOLoZHbdTaCjoFlreHtWHTNA5AQtzPElQNE= ARC-Message-Signature: i=1; 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Sun, 19 Jan 2025 19:34:52 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1737311692; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9btHGkf//kk288NthFQi5y2bA1UgkbfCEvqEoL+nsJI=; b=OmuIyI2Zmymp1dIVn9oF6C9buUlDlqRs+mPF/9qZ6qt90o+oUVedzTT1GTWTnlvFXStb0f 4sIfhC2oFPTTrfskifg8LE1zOJF+IHjWYzdXnDCKtr0CT4lF961HMzaHRBb5EvcZCCKnXW OD/Pl0CXjA5RbfZbA8mvSISfKe3Fs6kFr1sHbHwhxtGd0FdBZVwx5B0jTiNVdfnI53HzKE 9UoTR90EQe5JM9nLoI/DGWCdY2/XIc5Dx11QgMU1Kh+fGRKLfGhFA8baDYJI4auUFaMuBB dLit+mNzFbD+1BxFjEO1RxtesxSO2T4f3ia6w2fz91N2wYM0Rif/o65LiSYg2Q== From: Sander Vanheule To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Chris Packham , devicetree@vger.kernel.org, linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sander Vanheule Subject: [PATCH 5/9] mips: dts: realtek: Add SoC IRQ node for RTL838x Date: Sun, 19 Jan 2025 19:34:20 +0100 Message-ID: <20250119183424.259353-6-sander@svanheule.net> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119183424.259353-1-sander@svanheule.net> References: <20250119183424.259353-1-sander@svanheule.net> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the SoC interrupt controller so other components can link to it. Signed-off-by: Sander Vanheule --- arch/mips/boot/dts/realtek/rtl838x.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/mips/boot/dts/realtek/rtl838x.dtsi b/arch/mips/boot/dts/realtek/rtl838x.dtsi index 907449094536..21fb584e6383 100644 --- a/arch/mips/boot/dts/realtek/rtl838x.dtsi +++ b/arch/mips/boot/dts/realtek/rtl838x.dtsi @@ -73,5 +73,15 @@ uart1: serial@2100 { status = "disabled"; }; + + intc: interrupt-controller@3000 { + compatible = "realtek,rtl8380-intc", "realtek,rtl-intc"; + reg = <0x3000 0x20>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>, <3>, <4>, <5>, <6>; + }; }; }; From patchwork Sun Jan 19 18:34:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 13944563 Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26D2A1DF74E for ; Sun, 19 Jan 2025 18:35:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=84.16.241.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737311702; cv=none; b=pK/0fm7CFyyQgNBXVQSt809fBhSNo0jn/VF8Ka9iOMv8P0JTLYkAOe2FgDGve2UZFtFWATkE/T8km8vQoyP2chgqxDeBoNCYJcLtpcutyZqn3DCFNCEqnfPzDtQbMwYswW5ORIq2KiMgBcK0INJP+eM7YXWAbV1c+4el4qDOHQ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737311702; c=relaxed/simple; bh=W8gkY/oB2mZcEQ3l5zYkHT2kMm97aDKy3B5Vf1lOxtY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MndyDKMoPM6zRbLDLzGYzUQh/RA/MZdn0Sve+Fl8OWAMTm6G/ndjvvh6L9cCHeq7MOmKbYdlRKpJHrYzKNP7CxPijuaoH4Sm0yoJdLji0RMIifOcvuv6Tt0RYEK9N0mD/A/Oq97FwCcUJUGqLo824psBEZo2gsFemlwdTU7YJOg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=svanheule.net; spf=pass smtp.mailfrom=svanheule.net; dkim=pass (2048-bit key) header.d=svanheule.net header.i=@svanheule.net header.b=dS5Z4bQH; arc=none smtp.client-ip=84.16.241.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=svanheule.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=svanheule.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=svanheule.net header.i=@svanheule.net header.b="dS5Z4bQH" Received: from terra.vega.svanheule.net (unknown [94.110.49.146]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id 1BE145A7E52; Sun, 19 Jan 2025 19:34:53 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1737311693; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aTURxDbV63Zjs2S/DRfXH2c9HmUmHuIZtKJs8r7hlnU=; b=dS5Z4bQHMmNu8SU4Jcu7hPtJlds+Ez/lasBY1G2KkjKh37I6j2EG8sGndz3j11XesCYl8n d0Cu5W21392dOaEDwRLMZZ4FZijI1UkVZdY1BALLy2LKOhMFE8rWB5tU6bSzigCo4l6S2+ 7hFcIOTim8D0tTGYq192j05KM1fhVuhbcU8rmlBBQ9qw4ZXOKGjBpr7S3N3R8h82h5I0j0 IzZA7lTRec1UryBqgbIRXgZ+IDA70uAo4zlhv4TvVNlLEV4Qr4/4zuTy8uxL2LfDaF+tV9 O9FvDfpGmKmp/DxsZwQ28NYwtcMyWvCjKd0jspgQe+KKqdyhf3O9YBbCFHIT4g== From: Sander Vanheule To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Chris Packham , devicetree@vger.kernel.org, linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sander Vanheule Subject: [PATCH 6/9] mips: dts: realtek: Correct uart interrupt-parent Date: Sun, 19 Jan 2025 19:34:21 +0100 Message-ID: <20250119183424.259353-7-sander@svanheule.net> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119183424.259353-1-sander@svanheule.net> References: <20250119183424.259353-1-sander@svanheule.net> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The uart interrupts on RTL838x chips do not lead to the CPU's interrupt controller directly, but passes via the SoC interrupt controller. Update the interrupt-parent property to fix this. Signed-off-by: Sander Vanheule --- arch/mips/boot/dts/realtek/rtl838x.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/boot/dts/realtek/rtl838x.dtsi b/arch/mips/boot/dts/realtek/rtl838x.dtsi index 21fb584e6383..e3183a71765e 100644 --- a/arch/mips/boot/dts/realtek/rtl838x.dtsi +++ b/arch/mips/boot/dts/realtek/rtl838x.dtsi @@ -46,7 +46,7 @@ uart0: serial@2000 { clock-frequency = <200000000>; - interrupt-parent = <&cpuintc>; + interrupt-parent = <&intc>; interrupts = <31>; reg-io-width = <1>; @@ -63,7 +63,7 @@ uart1: serial@2100 { clock-frequency = <200000000>; - interrupt-parent = <&cpuintc>; + interrupt-parent = <&intc>; interrupts = <30>; reg-io-width = <1>; From patchwork Sun Jan 19 18:34:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 13944564 Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CDCD1DF756 for ; Sun, 19 Jan 2025 18:35:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=84.16.241.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737311702; cv=none; b=rloTU4UB3ze6L7PCiMH9NncfzHPRnmBx2znxSmzF7dxxI6TsjJCjh7SnsWa7ekHkMm8yF+b6A6eX6L6rsyUogUP7OJVE7to8aZJrbnBFyFqDtBjh7O2MYNopsLWouOgyR5v8nFoO2jF6sfqW1g62IPayxuNR7Bp6LKHLyaEeolA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737311702; c=relaxed/simple; bh=vgKqXw1GDVF1Qfw7XSC2NSzrDeBNZ6mBd2vy2WV2pU8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PY5X3ubYa9YFMgnmj9dte3BsucnT6LTNd9ZOVsFPXmiWQ/cSfntExT+QCfJ1uNufCNvH6HxckVTERKgwLq50xVaKhVInPLXCfrREZnVUBbuqoWulvYTQl2z0SAy0sA1ORDVwzHKMKhKHFJZ1hU2PfuYTZHpPcRQ29W5qb+qDgSs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=svanheule.net; spf=pass smtp.mailfrom=svanheule.net; dkim=pass (2048-bit key) header.d=svanheule.net header.i=@svanheule.net header.b=tLnnxtgr; arc=none smtp.client-ip=84.16.241.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=svanheule.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=svanheule.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=svanheule.net header.i=@svanheule.net header.b="tLnnxtgr" Received: from terra.vega.svanheule.net (unknown [94.110.49.146]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id 8B7FC5A7E53; Sun, 19 Jan 2025 19:34:53 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1737311693; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gM3VAja4azBv7tGCoJD/bZC70hqkrjzsEu4n8T1L1dU=; b=tLnnxtgrlm0BFF/nT4TZNDRbn6Uv8CiYo0+ldjpQwvE/U9x/Qg87NdSgPgsKXkTtRDsny5 av9O0A0IQu1A+ZT/QSxbdvvxUskHLUgu4cHwEbVLkgNVEtwDRDG4frhbrjYI0nof5I3oCS WOWlybpx+3lGlCEHGQvm0k2w4GZRorTmZiH4PmQYdC0WCHyBv6LybN3MZT66QZVhQsEfwA wbdNJVs0woqtk4bOnKqewmtU9+dX166U0wVUm/8BETL6oA/VIwfTTV0WdPEryOLz/WWJw+ dJ2TxwpRldzXQ7glAWNeWSFwPAnf0ZIyMN6ypyyS3OB4mXpxulvuWhyK0cndgg== From: Sander Vanheule To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Chris Packham , devicetree@vger.kernel.org, linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sander Vanheule Subject: [PATCH 7/9] mips: dts: realtek: Replace uart clock property Date: Sun, 19 Jan 2025 19:34:22 +0100 Message-ID: <20250119183424.259353-8-sander@svanheule.net> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119183424.259353-1-sander@svanheule.net> References: <20250119183424.259353-1-sander@svanheule.net> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add a fixed clock to define the clock frequency of the Lexra bus and use this for the two uart nodes instead of a separate clock-frequency property. Signed-off-by: Sander Vanheule --- arch/mips/boot/dts/realtek/rtl838x.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/mips/boot/dts/realtek/rtl838x.dtsi b/arch/mips/boot/dts/realtek/rtl838x.dtsi index e3183a71765e..246f4f607128 100644 --- a/arch/mips/boot/dts/realtek/rtl838x.dtsi +++ b/arch/mips/boot/dts/realtek/rtl838x.dtsi @@ -34,6 +34,12 @@ cpuintc: cpuintc { interrupt-controller; }; + lx_clk: clock-lexra { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + soc@18000000 { compatible = "simple-bus"; #address-cells = <1>; @@ -44,7 +50,7 @@ uart0: serial@2000 { compatible = "ns16550a"; reg = <0x2000 0x100>; - clock-frequency = <200000000>; + clocks = <&lx_clk>; interrupt-parent = <&intc>; interrupts = <31>; @@ -61,7 +67,7 @@ uart1: serial@2100 { compatible = "ns16550a"; reg = <0x2100 0x100>; - clock-frequency = <200000000>; + clocks = <&lx_clk>; interrupt-parent = <&intc>; interrupts = <30>; From patchwork Sun Jan 19 18:34:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 13944565 Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 139B13CF58 for ; Sun, 19 Jan 2025 18:35:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=84.16.241.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737311708; cv=none; b=Y83BA2jkUQSBsnqkGjoWh7Y8GrWsM5Uu6IkydhRwWj60hBttdkUwe7ChwEB8Bpx8CU27tA7L3zgW2kMbLpfg3xM4XjZ1iMSjq+nGh28dZh+pqdBU5wbPZJC/hqq03s9wEW0UtAK29TU6lKFanN5O4doFMT8qKTiiT4CUumpi+hg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737311708; c=relaxed/simple; bh=ujPlZqSf5aQadi3yA2LhUrX1DVPJPMfBX7D3Thc5OP4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nZQrRSLOioeJcvDtXIJGNHieSRMo4fWkzNMjn4IURUMjY81psPh+ys96uVmmugNeWgA1nO6xhC8vwpzHgKTtKDBrL6c5YMBOvObV6RFu8xGgaD7+Tos/JBHvtHpee6fxT+VZcAjsRefQigp6Ms+OY0VRM1gcibTQWD2V3sS++ZQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=svanheule.net; spf=pass smtp.mailfrom=svanheule.net; dkim=pass (2048-bit key) header.d=svanheule.net header.i=@svanheule.net header.b=uPfzVbkz; arc=none smtp.client-ip=84.16.241.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=svanheule.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=svanheule.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=svanheule.net header.i=@svanheule.net header.b="uPfzVbkz" Received: from terra.vega.svanheule.net (unknown [94.110.49.146]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id 017695A7E54; Sun, 19 Jan 2025 19:34:53 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1737311694; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XGeRpsWSaI43r0iXcM3eTZdyHwA9+Y4qH9XwLcGUe7Q=; b=uPfzVbkzgCkFQrDPNiv/mACIRzuW3YclsI3/gbl8PMTKa6sVDLtCHpLPlkkT93nX2sqUhd w6FdO2Nfrk4v7Hm12YteKuYQXoLDHbwGjfsk3U7DrjKvY8EE5pztoJ06LkX/UFbNbLNJjV xpOlS8Q1b9YRgkl9NakMIcDSQqaADjVqn5azaWI+byU/OmuEYMwBQR2Tl0ieEL/oUSky2v nTc8B+arZ5ZKdXcMjgNR2Gq6B54yW86SNFDWHthk0oAoHiDrx2Ig6HTyZ36YPIJtG/lh9T NXBbY7za4zz5osH1cT9X7v0TN9mYs2OYbT9KOD8Io/ZOrG6cbQEkPxyWrQ0gKA== From: Sander Vanheule To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Chris Packham , devicetree@vger.kernel.org, linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sander Vanheule Subject: [PATCH 8/9] mips: dts: realtek: Add RTL838x SoC peripherals Date: Sun, 19 Jan 2025 19:34:23 +0100 Message-ID: <20250119183424.259353-9-sander@svanheule.net> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119183424.259353-1-sander@svanheule.net> References: <20250119183424.259353-1-sander@svanheule.net> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add some of the SoC's CPU peripherals currently supported: - GPIO controller with support for 24 GPIO lines, although not all lines are brought out to pads on the SoC package. These lines can generate interrupts from external sources. - Watchdog which can be used to restart the SoC if no external restart logic is present. - SPI controller, primarily used to access NOR flash Signed-off-by: Sander Vanheule --- arch/mips/boot/dts/realtek/rtl838x.dtsi | 36 +++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/mips/boot/dts/realtek/rtl838x.dtsi b/arch/mips/boot/dts/realtek/rtl838x.dtsi index 246f4f607128..ce522a6af262 100644 --- a/arch/mips/boot/dts/realtek/rtl838x.dtsi +++ b/arch/mips/boot/dts/realtek/rtl838x.dtsi @@ -46,6 +46,14 @@ soc@18000000 { #size-cells = <1>; ranges = <0x0 0x18000000 0x10000>; + spi0: spi@1200 { + compatible = "realtek,rtl8380-spi"; + reg = <0x1200 0x100>; + + #address-cells = <1>; + #size-cells = <0>; + }; + uart0: serial@2000 { compatible = "ns16550a"; reg = <0x2000 0x100>; @@ -89,5 +97,33 @@ intc: interrupt-controller@3000 { interrupt-parent = <&cpuintc>; interrupts = <2>, <3>, <4>, <5>, <6>; }; + + watchdog: watchdog@3150 { + compatible = "realtek,rtl8380-wdt"; + reg = <0x3150 0xc>; + + realtek,reset-mode = "soc"; + + clocks = <&lx_clk>; + timeout-sec = <20>; + + interrupt-parent = <&intc>; + interrupt-names = "phase1", "phase2"; + interrupts = <19>, <18>; + }; + + gpio0: gpio@3500 { + compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio"; + reg = <0x3500 0x1c>; + + gpio-controller; + #gpio-cells = <2>; + ngpios = <24>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <23>; + }; }; }; From patchwork Sun Jan 19 18:34:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 13944566 Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4EBC61DFE0A for ; Sun, 19 Jan 2025 18:35:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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b=hs4KABI7N1wUR3okMIMq0VDD+UqBLQcXI4/QEGphBF/9ZfTbCXrsIuUsEPkPtpeblFLosk pqFsVbkxM+YsTeFTNIwGEHSJq0U7OLNykYZdyq5QI7PeeyNDtmtkh/YkOuMUd5MnTwY/fr cCwB3fURoTIXnFw5pFDBE0FIaPtC+hX9atZezPpPYOYoyp6qpo92E7/L6ts8y7P/fNlJXE jMjV8GK/rCpYxuNatPlnaFJvtKn0LpU0KZDOeVMJsQOTCvxT0yd4YNxg5dbqp0Fl1wIoCd BLk6WsCjLLnBubUm9jO+WNkyKE6eBkSgQtesplR7FbyGtOg2okXYCOdPBvg3bQ== From: Sander Vanheule To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Chris Packham , devicetree@vger.kernel.org, linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sander Vanheule Subject: [PATCH 9/9] mips: dts: realtek: Add restart to Cisco SG220-26P Date: Sun, 19 Jan 2025 19:34:24 +0100 Message-ID: <20250119183424.259353-10-sander@svanheule.net> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119183424.259353-1-sander@svanheule.net> References: <20250119183424.259353-1-sander@svanheule.net> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Define a gpio-restart node to the Cisco SG220-26P so the device can be rebooted using the SoC's hard reset pin. Set the priority to 192 so the gpio-restart method takes priority over the watchdog restart. Signed-off-by: Sander Vanheule --- arch/mips/boot/dts/realtek/cisco_sg220-26.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/mips/boot/dts/realtek/cisco_sg220-26.dts b/arch/mips/boot/dts/realtek/cisco_sg220-26.dts index cb85d172a1d3..fab3d552404d 100644 --- a/arch/mips/boot/dts/realtek/cisco_sg220-26.dts +++ b/arch/mips/boot/dts/realtek/cisco_sg220-26.dts @@ -4,6 +4,8 @@ #include "rtl838x.dtsi" +#include + / { model = "Cisco SG220-26"; compatible = "cisco,sg220-26", "realtek,rtl8382-soc"; @@ -17,6 +19,13 @@ memory@0 { device_type = "memory"; reg = <0x0 0x8000000>; }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + priority = <192>; + open-source; + }; }; &uart0 {