From patchwork Mon Jan 20 09:46:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13944914 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 488B019995A; Mon, 20 Jan 2025 09:47:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737366458; cv=none; b=jalcOMmcwBDbfAX1LKdjNtIEcYb9isNqd08/upBC6eHJobYBMLOOeCm5cIREi67dZUgyGC9hS1cwzDhd2glJOljkGLPm908LoCcd8Y3sqa5wTnpHbyO/VGurDEh+pcXSMsU9zQYAgJis1WBkDk/rrMzKrxSZFOduVQ3CvV5dSHg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737366458; c=relaxed/simple; bh=lCUbHBO7d3Iw4cq9xZiUoS5/7vmV1porHfB2d2Bz+ig=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=c7J8pdzt4plWTv+PeqyWPgr+wugLVNGWgniHzcUvKswNR4bf7J9yScEWKv1wO5phqtDVVhqKd10jjx9eXtdUp8mGj76lQBEQIkqnAZ40lz2f2RnVaL626WJ4vKR4Zc/RV8YKY8T2TG+Usm+NqpyuAm+yzi7S4xElfimRZ5nFagg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: dvKULJ3pSYS7rUED4Ltrmg== X-CSE-MsgGUID: B4TUQoTuQvagLa2Zm4d3vg== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 20 Jan 2025 18:47:29 +0900 Received: from localhost.localdomain (unknown [10.226.92.210]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id E75164019C5E; Mon, 20 Jan 2025 18:47:21 +0900 (JST) From: Biju Das To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , Fabrizio Castro , devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 01/11] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC Date: Mon, 20 Jan 2025 09:46:57 +0000 Message-ID: <20250120094715.25802-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250120094715.25802-1-biju.das.jz@bp.renesas.com> References: <20250120094715.25802-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document RZ/G3E (R9A09G047) ICU bindings. The ICU block on the RZ/G3E SoC is almost identical to the one found on the RZ/V2H SoC, with the following differences: - The TINT register offset is 0x830 compared to ox30 on RZ/V2H. - The number of supported GPIO interrupts for TINT selection is 141 instead of 86. - The pin index and TINT selection index are not in the 1:1 map - The number of TSSR registers is 15 instead of 8 - Each TSSR register can program 2 TINTs instead of 4 TINTs Hence new compatible string "renesas,r9a09g047-icu" is added for RZ/G3E SoC. Signed-off-by: Biju Das --- .../bindings/interrupt-controller/renesas,rzv2h-icu.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml index d7ef4f1323a7..3f99c8645767 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzv2h-icu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/V2H(P) Interrupt Control Unit +title: Renesas RZ/{G3E,V2H(P)} Interrupt Control Unit maintainers: - Fabrizio Castro @@ -20,7 +20,9 @@ description: properties: compatible: - const: renesas,r9a09g057-icu # RZ/V2H(P) + enum: + - renesas,r9a09g047-icu # RZ/G3E + - renesas,r9a09g057-icu # RZ/V2H(P) '#interrupt-cells': description: The first cell is the SPI number of the NMI or the From patchwork Mon Jan 20 09:46:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13944915 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 86C1318801A; Mon, 20 Jan 2025 09:47:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737366458; cv=none; b=YP3yi8A1ZpTTLrxNPwku0446CriJQ+r6wit/BPrY44XsvNFKKkuIlib/PGXX8EfgxajtfNIbTuPq1QzM5lteol0QPsjoGYWOD8MKmAI2aKR4mwXuo6bnrrE/eYexcSiX7TTMRbAmxQF/fAM6rPO+X42+VXNvzDa5LpbUX2o997I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737366458; c=relaxed/simple; bh=JrbtD0vBIbLl5U2RyhYOoEGtx0OzrIDMmcztLwqcstg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KgrOUO5XhmhEpk28vwBuYyl0qx+8k20j4A+6vg6aoIsAE5udSF9du4PPDPpP0yoRTWyGankkqOM1wkJcCJATvjKqpaJeyk2fBAvbixkrfAA2kNnUPfsk2NH1cWkrn501ttIROiM/HCvBg3VraaMWe0ftX68JEfGDAlA/IwUD9xQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: LQedulZPSLS9TD3QpIsG2A== X-CSE-MsgGUID: FdDv2ackRjGQ4Mz4IUg+fQ== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 20 Jan 2025 18:47:29 +0900 Received: from localhost.localdomain (unknown [10.226.92.210]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 045BB4017D72; Mon, 20 Jan 2025 18:47:25 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd Cc: Biju Das , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 02/11] clk: renesas: r9a09g047: Add ICU clock/reset Date: Mon, 20 Jan 2025 09:46:58 +0000 Message-ID: <20250120094715.25802-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250120094715.25802-1-biju.das.jz@bp.renesas.com> References: <20250120094715.25802-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add ICU clock and reset entries. Signed-off-by: Biju Das --- drivers/clk/renesas/r9a09g047-cpg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c index 1886eab9ef9e..1181e7b605e8 100644 --- a/drivers/clk/renesas/r9a09g047-cpg.c +++ b/drivers/clk/renesas/r9a09g047-cpg.c @@ -90,6 +90,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { }; static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { + DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5, + BUS_MSTOP_NONE), DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, BUS_MSTOP(3, BIT(5))), DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13, @@ -128,6 +130,7 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { static const struct rzv2h_reset r9a09g047_resets[] __initconst = { DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ + DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */ DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */ From patchwork Mon Jan 20 09:46:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13944916 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BFB4D19995A for ; Mon, 20 Jan 2025 09:47:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737366460; cv=none; b=aKnFoimBT/ekMlJjLdBlg0G9MVTwC7Upi6MDxpI0QrwCfvOQbIRIrHTGELLqFvM7taGdi6RKUciBr7ESLAka+xCj1Fhcc8Xfs2gOUseyncga46rL1WR/0FPKlQmaemg0C+Qi2wnRDqn4oqScoq1J5Fn9RmJHQtSwcxJCy7/T+Ko= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737366460; c=relaxed/simple; bh=Wuu9c3k+IOB/Ow59ytgsPCpF5UwW0GpG4eNZTd1LEd0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JzoeHNCEG5JtKSiJMrUwXQUIYJQBScohfOubbrCK0kPx4XBuv2EqwYJyJPvO2iho3qXtTRsEI3PMr6tdWPP/Tt/GOgb5h/4Txp/pIS5tX9/o+AF8p5a9TsRJcDt20m+bcnsS/3vtZ7slIg6r9E7ACJOK484d1++ydhtZ5nphJaM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: k3XZqeD1RNK4XpBaL1LsAA== X-CSE-MsgGUID: kaUOlJldTtKy6wg0ncfzdw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 20 Jan 2025 18:47:30 +0900 Received: from localhost.localdomain (unknown [10.226.92.210]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 003214021BAD; Mon, 20 Jan 2025 18:47:28 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH 03/11] irqchip/renesas-rzv2h: Drop irqchip from struct rzv2h_icu_priv Date: Mon, 20 Jan 2025 09:46:59 +0000 Message-ID: <20250120094715.25802-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250120094715.25802-1-biju.das.jz@bp.renesas.com> References: <20250120094715.25802-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use rzv2h_icu_chip directly on irq_domain_set_hwirq_and_chip() and drop the global variable irqchip from struct rzv2h_icu_priv. Signed-off-by: Biju Das --- drivers/irqchip/irq-renesas-rzv2h.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index fe2d29e91026..fd432b43506b 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -83,13 +83,11 @@ /** * struct rzv2h_icu_priv - Interrupt Control Unit controller private data structure. * @base: Controller's base address - * @irqchip: Pointer to struct irq_chip * @fwspec: IRQ firmware specific data * @lock: Lock to serialize access to hardware registers */ struct rzv2h_icu_priv { void __iomem *base; - const struct irq_chip *irqchip; struct irq_fwspec fwspec[ICU_NUM_IRQ]; raw_spinlock_t lock; }; @@ -390,7 +388,7 @@ static int rzv2h_icu_alloc(struct irq_domain *domain, unsigned int virq, unsigne if (hwirq > (ICU_NUM_IRQ - 1)) return -EINVAL; - ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, priv->irqchip, + ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &rzv2h_icu_chip, (void *)(uintptr_t)tint); if (ret) return ret; @@ -446,8 +444,6 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) goto put_dev; } - rzv2h_icu_data->irqchip = &rzv2h_icu_chip; - rzv2h_icu_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); if (IS_ERR(rzv2h_icu_data->base)) { ret = PTR_ERR(rzv2h_icu_data->base); From patchwork Mon Jan 20 09:47:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13944920 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 11D7418801A for ; Mon, 20 Jan 2025 09:47:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737366469; cv=none; b=Hq6evHokBMsG4aDBjBJ34zdcrcVd7qnvxzQlWMy0SMWQfByn1cLjDqvwFB2c55ZH6D8sZlLwiuC7SQokHitlqo7S3ulS1V4fYv09CYVS/ybgfSelyK317URFPL0DzdbjN8hzCGjAfS8zQMcvcaUq14sVFDr36iITz37ilFrPVms= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737366469; c=relaxed/simple; bh=ip9hWimIMhqxUlxyDdu0RZBGaVzHeR7Rl3IJxiuIEns=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EpJPLf+LEr6+eMWQEzGjPAtRZdQPFifkAz5CVj2XSYt5gX9XW4oEZVftgYs0JodU6Fv/repCblwNNDN2AP/fjwJXJxL6UizY6E/QwJqhAAbLB6+9m2jtNrE+ztfqyU8PCjJ48fjth0BB0rTXy1IfDkspALXHPeGv1OsCoHAWliU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: sf8iisVGRVSjXzeY2XsvLA== X-CSE-MsgGUID: uhEkJTbCSpuU5SJb52uVLA== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 20 Jan 2025 18:47:45 +0900 Received: from localhost.localdomain (unknown [10.226.92.210]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 73C09400F73B; Mon, 20 Jan 2025 18:47:31 +0900 (JST) From: Biju Das To: Thomas Gleixner , Philipp Zabel Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH 04/11] irqchip/renesas-rzv2h: Simplify rzv2h_icu_init() Date: Mon, 20 Jan 2025 09:47:00 +0000 Message-ID: <20250120094715.25802-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250120094715.25802-1-biju.das.jz@bp.renesas.com> References: <20250120094715.25802-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Simplify rzv2h_icu_init() by using newly added devm_* helpers. Signed-off-by: Biju Das --- drivers/irqchip/irq-renesas-rzv2h.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index fd432b43506b..a02d47529564 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -456,23 +456,23 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) goto put_dev; } - resetn = devm_reset_control_get_exclusive(&pdev->dev, NULL); + resetn = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, NULL); if (IS_ERR(resetn)) { ret = PTR_ERR(resetn); + dev_err(&pdev->dev, "failed to acquire deasserted reset: %d\n", ret); goto put_dev; } - ret = reset_control_deassert(resetn); - if (ret) { - dev_err(&pdev->dev, "failed to deassert resetn pin, %d\n", ret); + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "devm_pm_runtime_enable failed, %d\n", ret); goto put_dev; } - pm_runtime_enable(&pdev->dev); ret = pm_runtime_resume_and_get(&pdev->dev); if (ret < 0) { dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret); - goto pm_disable; + goto put_dev; } raw_spin_lock_init(&rzv2h_icu_data->lock); @@ -493,9 +493,6 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) pm_put: pm_runtime_put(&pdev->dev); -pm_disable: - pm_runtime_disable(&pdev->dev); - reset_control_assert(resetn); put_dev: put_device(&pdev->dev); From patchwork Mon Jan 20 09:47:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13944919 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5CF191A9B49 for ; Mon, 20 Jan 2025 09:47:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737366467; cv=none; b=RYfrh/lxlz5SKIr92RZLdQU1t+JzXI7xF8NZKgJ6BF5JbizXN5aMdsP2OWzJQUQP5/2GqWzyW2Z8YHuPm7ZbdQhpittaz8RLn5r2CAFph7b6ScjzYiK30ZsHZXofRcaUxZGAYskcdm7RhzhJrWtrBITyl/RC/LWUe+L13PL0u84= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737366467; c=relaxed/simple; bh=d0ryn+E4c37PmZNw277t3a1DIk3+dTx3wwMScf6EyvU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VzhrF2KK4UrBUODFji5UGJokeOLBcOKEwS5uPcDWodXgNoZtCxd8IXfaIvL61nLY3ND13Yls9wWykC3iTmmjmn2RT9mn5g+2wqx8ywdFI8d6b1Vs6LWpZaMywxI1eYlx0usNavkNJjEWtEjqkR5ETZFneGp6mZQ7qeNBL/E21tM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: zbN2QBUoQFenfX5RpCbuhA== X-CSE-MsgGUID: ApPIly7uS9u50bpD7jktOQ== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 20 Jan 2025 18:47:45 +0900 Received: from localhost.localdomain (unknown [10.226.92.210]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 30F3F401831B; Mon, 20 Jan 2025 18:47:33 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH 05/11] irqchip/renesas-rzv2h: Add struct rzv2h_hw_info with t_offs variable Date: Mon, 20 Jan 2025 09:47:01 +0000 Message-ID: <20250120094715.25802-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250120094715.25802-1-biju.das.jz@bp.renesas.com> References: <20250120094715.25802-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The ICU block on the RZ/G3E SoC is almost identical to the one found on the RZ/V2H SoC, with the following differences:  - The TINT register offset starts at 0x830 instead of 0x30.  - The number of GPIO interrupts for TINT selection is 141 instead of 86.  - The pin index and TINT selection index are not in the 1:1 map  - The number of TSSR registers is 15 instead of 8  - Each TSSR register can program 2 TINTs instead of 4 TINTs Introduce struct rzv2h_hw_info to handle these differences and add t_offs variable to take care of the TINT register offset difference between RZ/G3E and RZ/V2H. Refactor the code by moving rzv2h_icu_init() into rzv2h_icu_init_common() and pass the varable containing hw difference to support both these SoCs. Signed-off-by: Biju Das --- drivers/irqchip/irq-renesas-rzv2h.c | 46 +++++++++++++++++++++-------- 1 file changed, 34 insertions(+), 12 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index a02d47529564..195ce9c5e5b5 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -80,16 +80,26 @@ #define ICU_TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) #define ICU_PB5_TINT 0x55 +/** + * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure. + * @t_offs: TINT offset + */ +struct rzv2h_hw_info { + u16 t_offs; +}; + /** * struct rzv2h_icu_priv - Interrupt Control Unit controller private data structure. * @base: Controller's base address * @fwspec: IRQ firmware specific data * @lock: Lock to serialize access to hardware registers + * @info: Pointer to struct rzv2h_hw_info */ struct rzv2h_icu_priv { void __iomem *base; struct irq_fwspec fwspec[ICU_NUM_IRQ]; raw_spinlock_t lock; + const struct rzv2h_hw_info *info; }; static inline struct rzv2h_icu_priv *irq_data_to_priv(struct irq_data *data) @@ -109,7 +119,7 @@ static void rzv2h_icu_eoi(struct irq_data *d) tintirq_nr = hw_irq - ICU_TINT_START; bit = BIT(tintirq_nr); if (!irqd_is_level_type(d)) - writel_relaxed(bit, priv->base + ICU_TSCLR); + writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR); } else if (hw_irq >= ICU_IRQ_START) { tintirq_nr = hw_irq - ICU_IRQ_START; bit = BIT(tintirq_nr); @@ -137,12 +147,12 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable) tssel_n = ICU_TSSR_TSSEL_N(tint_nr); guard(raw_spinlock)(&priv->lock); - tssr = readl_relaxed(priv->base + ICU_TSSR(k)); + tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k)); if (enable) tssr |= ICU_TSSR_TIEN(tssel_n); else tssr &= ~ICU_TSSR_TIEN(tssel_n); - writel_relaxed(tssr, priv->base + ICU_TSSR(k)); + writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k)); } static void rzv2h_icu_irq_disable(struct irq_data *d) @@ -245,8 +255,8 @@ static void rzv2h_clear_tint_int(struct rzv2h_icu_priv *priv, unsigned int hwirq u32 bit = BIT(tint_nr); int k = tint_nr / 16; - tsctr = readl_relaxed(priv->base + ICU_TSCTR); - titsr = readl_relaxed(priv->base + ICU_TITSR(k)); + tsctr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSCTR); + titsr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(k)); titsel = ICU_TITSR_TITSEL_GET(titsr, titsel_n); /* @@ -255,7 +265,7 @@ static void rzv2h_clear_tint_int(struct rzv2h_icu_priv *priv, unsigned int hwirq */ if ((tsctr & bit) && ((titsel == ICU_TINT_EDGE_RISING) || (titsel == ICU_TINT_EDGE_FALLING))) - writel_relaxed(bit, priv->base + ICU_TSCLR); + writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR); } static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) @@ -306,21 +316,21 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) guard(raw_spinlock)(&priv->lock); - tssr = readl_relaxed(priv->base + ICU_TSSR(tssr_k)); + tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n) | tien); tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n); - writel_relaxed(tssr, priv->base + ICU_TSSR(tssr_k)); + writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); - titsr = readl_relaxed(priv->base + ICU_TITSR(titsr_k)); + titsr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(titsr_k)); titsr &= ~ICU_TITSR_TITSEL_MASK(titsel_n); titsr |= ICU_TITSR_TITSEL_PREP(sense, titsel_n); - writel_relaxed(titsr, priv->base + ICU_TITSR(titsr_k)); + writel_relaxed(titsr, priv->base + priv->info->t_offs + ICU_TITSR(titsr_k)); rzv2h_clear_tint_int(priv, hwirq); - writel_relaxed(tssr | tien, priv->base + ICU_TSSR(tssr_k)); + writel_relaxed(tssr | tien, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); return 0; } @@ -419,7 +429,8 @@ static int rzv2h_icu_parse_interrupts(struct rzv2h_icu_priv *priv, struct device return 0; } -static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) +static int rzv2h_icu_init_common(struct device_node *node, struct device_node *parent, + const struct rzv2h_hw_info *hw_info) { struct irq_domain *irq_domain, *parent_domain; struct rzv2h_icu_priv *rzv2h_icu_data; @@ -485,6 +496,8 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) goto pm_put; } + rzv2h_icu_data->info = hw_info; + /* * coccicheck complains about a missing put_device call before returning, but it's a false * positive. We still need &pdev->dev after successfully returning from this function. @@ -499,6 +512,15 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) return ret; } +static const struct rzv2h_hw_info rzv2h_hw_params = { + .t_offs = 0, +}; + +static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) +{ + return rzv2h_icu_init_common(node, parent, &rzv2h_hw_params); +} + IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu) IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_init) IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu) From patchwork Mon Jan 20 09:47:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13944918 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D7A951AF0C2 for ; Mon, 20 Jan 2025 09:47:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737366462; cv=none; b=uDeiiou/kWJzhBAeXPmXa80gHcqeXS0eslQFqdfhJ/UFt9P5WCHb3yI2xViwt7rS9BkZEl/z1uPeO08CRYFUNmFOmoJ9olfsovYVWYvLCg3uEHQfFMwZRokBGNGjMrX9SgCoB7Z0RGWpfczzdccI1u+dNaqgDs9zh/zNRViJShQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737366462; c=relaxed/simple; bh=TKDJ2/AbGZCnMJlQsJYEjgAQySxBCi4I9kE44xdqErM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bBQQd7VYA59d0jruTiE9MjNAqOARVBw0GBNle3sJ8VEL9dUMllmqOEhiGu1yt6TGwFeC3F2f+Ev7GI/264obZCPsDDX1hVZ7BrJx8TsT8WrE0ab/z8jyLXsy+2ox3RdingYGlOZFNLudA17Om+uLtP/O3P8TbZmf9avBNrIZm0E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: iP/hD6s3So6qzB9qi/XI+w== X-CSE-MsgGUID: nWN3OJFpQ9Ki8cCzT9AR7w== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 20 Jan 2025 18:47:38 +0900 Received: from localhost.localdomain (unknown [10.226.92.210]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id A1D63401A639; Mon, 20 Jan 2025 18:47:36 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH 06/11] irqchip/renesas-rzv2h: Add max_tssel variable to struct rzv2h_hw_info Date: Mon, 20 Jan 2025 09:47:02 +0000 Message-ID: <20250120094715.25802-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250120094715.25802-1-biju.das.jz@bp.renesas.com> References: <20250120094715.25802-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The number of GPIO interrupts on RZ/G3E for TINT selection is 141 compared to 86 on RZ/V2H. Add max_tssel variable to struct rzv2h_hw_info to handle this difference. Signed-off-by: Biju Das --- drivers/irqchip/irq-renesas-rzv2h.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index 195ce9c5e5b5..b244cd61cba4 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -78,14 +78,15 @@ #define ICU_TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) #define ICU_TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) -#define ICU_PB5_TINT 0x55 /** * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure. * @t_offs: TINT offset + * @max_tssel: TSSEL max value */ struct rzv2h_hw_info { u16 t_offs; + u8 max_tssel; }; /** @@ -298,13 +299,12 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) return -EINVAL; } + priv = irq_data_to_priv(d); tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d); - if (tint > ICU_PB5_TINT) + if (tint > priv->info->max_tssel) return -EINVAL; - priv = irq_data_to_priv(d); hwirq = irqd_to_hwirq(d); - tint_nr = hwirq - ICU_TINT_START; tssr_k = ICU_TSSR_K(tint_nr); @@ -514,6 +514,7 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p static const struct rzv2h_hw_info rzv2h_hw_params = { .t_offs = 0, + .max_tssel = 0x55, }; static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) From patchwork Mon Jan 20 09:47:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13944924 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E4C761AB6D8 for ; Mon, 20 Jan 2025 09:47:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737366475; cv=none; b=ZcPDwp0tkkDqViYaJb6O+vvRxXBFnKCOT50hhyKoKfkS78gk+CpONrfSbZVw3b+lO14JpeqyEk/htwHTpia3VywDgoA7vBgWGRALOdPwNzqYoxWJr3EFIY4zIV9d06dkZaGVgF7za1QgLU6so9cjEdwy9xpGMbrVRVyc9zJsDsY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737366475; c=relaxed/simple; bh=LjmqqFmkALN6vcrIr2GGvUFTdCZnwZWzv13X4yW0GoA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IdR976Hhs8UoVmtj5L3XGqDS4FGo+NMe+Hz0edUEzzBnwNaIaXVfDNOLpo38po0Io04UMihANFXQ5C+nQOSjxg28roIxGHYvh+c6mAlw+hTwiefqjGTHbBhfE7DXD7uNLfXA+7kwUOWU2HbRJgLly8R1pdq95PkrUWPlLq3wDqA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: eWYAklcDQaytO4poDgdSPw== X-CSE-MsgGUID: sX6TSmQMSDuAaSQ7dzS59Q== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 20 Jan 2025 18:47:53 +0900 Received: from localhost.localdomain (unknown [10.226.92.210]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 18BF8401A629; Mon, 20 Jan 2025 18:47:38 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH 07/11] irqchip/renesas-rzv2h: Add tssr_k variable to struct rzv2h_hw_info Date: Mon, 20 Jan 2025 09:47:03 +0000 Message-ID: <20250120094715.25802-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250120094715.25802-1-biju.das.jz@bp.renesas.com> References: <20250120094715.25802-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On RZ/G3E the number of TSSR registers is 15 compared to 8 on RZ/V2H and each TSSR register can program 2 TINTs compared to 4 on RZ/V2H. Add tssr_k variable to struct rzv2h_hw_info to handle this difference and drop the macros ICU_TSSR_K and ICU_TSSR_TSSEL_N. Signed-off-by: Biju Das --- drivers/irqchip/irq-renesas-rzv2h.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index b244cd61cba4..a9a9723ff4bb 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -64,8 +64,6 @@ #define ICU_TINT_LEVEL_HIGH 2 #define ICU_TINT_LEVEL_LOW 3 -#define ICU_TSSR_K(tint_nr) ((tint_nr) / 4) -#define ICU_TSSR_TSSEL_N(tint_nr) ((tint_nr) % 4) #define ICU_TSSR_TSSEL_PREP(tssel, n) ((tssel) << ((n) * 8)) #define ICU_TSSR_TSSEL_MASK(n) ICU_TSSR_TSSEL_PREP(0x7F, n) #define ICU_TSSR_TIEN(n) (BIT(7) << ((n) * 8)) @@ -83,10 +81,12 @@ * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure. * @t_offs: TINT offset * @max_tssel: TSSEL max value + * @tssr_k: TSSR index k */ struct rzv2h_hw_info { u16 t_offs; u8 max_tssel; + u8 tssr_k; }; /** @@ -144,8 +144,8 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable) return; tint_nr = hw_irq - ICU_TINT_START; - k = ICU_TSSR_K(tint_nr); - tssel_n = ICU_TSSR_TSSEL_N(tint_nr); + k = tint_nr / priv->info->tssr_k; + tssel_n = tint_nr % priv->info->tssr_k; guard(raw_spinlock)(&priv->lock); tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k)); @@ -307,8 +307,8 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) hwirq = irqd_to_hwirq(d); tint_nr = hwirq - ICU_TINT_START; - tssr_k = ICU_TSSR_K(tint_nr); - tssel_n = ICU_TSSR_TSSEL_N(tint_nr); + tssr_k = tint_nr / priv->info->tssr_k; + tssel_n = tint_nr % priv->info->tssr_k; titsr_k = ICU_TITSR_K(tint_nr); titsel_n = ICU_TITSR_TITSEL_N(tint_nr); @@ -515,6 +515,7 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p static const struct rzv2h_hw_info rzv2h_hw_params = { .t_offs = 0, .max_tssel = 0x55, + .tssr_k = 4, }; static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) From patchwork Mon Jan 20 09:47:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13944925 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8978818801A for ; Mon, 20 Jan 2025 09:47:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737366478; cv=none; b=lqKrfR/t9hDpTxYzAXZHYfT0lUjQXtbRN97QIsBgUafIjPcwPHXeBY/8H+RHWS310yksmVx/q+QFoiOAEiNcyuchQU4zlzppbTw8CaJt5g9m2zuGCGi2Jxf+dK3Y6+ubIokRuOPnCbMT7cohl472bJASqE+0eesRJHcAkhRHxgM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737366478; c=relaxed/simple; bh=MFtqXWPV5pxlTSmL1kzkfK/sKN8cbFLAwmXu2n2J/Rw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HbcH+Cs4MgmOzUdtHFjy0uUtIGaYl8yI0fomvWqMFuTmwdNjcWQecEpTZW9pcKTLNuwFwoiqByNbRfSViVduSYaRt8ldaz+qmKNYdWptIimKlBQtRO2/nJFxdOVr5Wrt+RyKVvBR533YV0uIekiqCM3yehDWsZaw79QXAJqn5no= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: 8zAZ2dkXRf+Dswbbn42LbA== X-CSE-MsgGUID: bJE+MDHvTuCmJV+EvIEpuw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 20 Jan 2025 18:47:55 +0900 Received: from localhost.localdomain (unknown [10.226.92.210]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 8407D401BEE9; Mon, 20 Jan 2025 18:47:41 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH 08/11] irqchip/renesas-rzv2h: Add tssel_mask and tssel_shift variables to struct rzv2h_hw_info Date: Mon, 20 Jan 2025 09:47:04 +0000 Message-ID: <20250120094715.25802-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250120094715.25802-1-biju.das.jz@bp.renesas.com> References: <20250120094715.25802-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On RZ/G3E each TSSR register can program 2 TINTs compared to 4 TINTs on RZ/V2H. Add tssel_mask and tssel_shift variables to struct rzv2h_hw_info to simplify the calculations when we add support for RZ/G3E and drop the macros ICU_TSSR_TSSEL_PREP and ICU_TSSR_TSSEL_MASK. Signed-off-by: Biju Das --- drivers/irqchip/irq-renesas-rzv2h.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index a9a9723ff4bb..5990dcf72ef0 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -64,8 +64,6 @@ #define ICU_TINT_LEVEL_HIGH 2 #define ICU_TINT_LEVEL_LOW 3 -#define ICU_TSSR_TSSEL_PREP(tssel, n) ((tssel) << ((n) * 8)) -#define ICU_TSSR_TSSEL_MASK(n) ICU_TSSR_TSSEL_PREP(0x7F, n) #define ICU_TSSR_TIEN(n) (BIT(7) << ((n) * 8)) #define ICU_TITSR_K(tint_nr) ((tint_nr) / 16) @@ -80,11 +78,15 @@ /** * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure. * @t_offs: TINT offset + * @tssel_mask: TSSEL mask + * @tssel_shift: TSSEL shift * @max_tssel: TSSEL max value * @tssr_k: TSSR index k */ struct rzv2h_hw_info { u16 t_offs; + u16 tssel_mask; + u8 tssel_shift; u8 max_tssel; u8 tssr_k; }; @@ -317,8 +319,8 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) guard(raw_spinlock)(&priv->lock); tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); - tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n) | tien); - tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n); + tssr &= ~((priv->info->tssel_mask << (tssel_n * priv->info->tssel_shift)) | tien); + tssr |= (tint << (tssel_n * priv->info->tssel_shift)); writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); @@ -515,6 +517,8 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p static const struct rzv2h_hw_info rzv2h_hw_params = { .t_offs = 0, .max_tssel = 0x55, + .tssel_mask = GENMASK(6, 0), + .tssel_shift = 8, .tssr_k = 4, }; From patchwork Mon Jan 20 09:47:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13944921 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AFC2019AD8D for ; Mon, 20 Jan 2025 09:47:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737366469; cv=none; b=bRRTzAH2SUSVAVlgY7iPeoOP6EOoH2xGTEaWBI1zHbpD2m4E0leT6ntnOQNCq8s5Nb+TgAHl/fJrCRHB9mMZigsAG6pT7vvYlQ4ome7PZ1fYFKJMc1UERzoY/+gOoKtxSVzPKxWymrTfs0LFp0Dbtw97/bm/yKiGLGqK3fmHuTM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737366469; c=relaxed/simple; bh=1rg0RpD08+POyxRlqh97SV+43C7zysXd0xAWZJUFxAc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pO3DdbfqBcJHP+uvC5j0Rb7jQi+F07rkziJ5hWOadFm/qQE4zYwai8bJqVdL91j/OxzmvYvRDEsgpzpF3Dwzr5XfSFknImjEXuqpBhpNABHL0IlNu3WX8pDwNusBpQOwowKLd2t6DakZvOflElu5kyk9QDl7mbrg1dLS3Xou+/o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: h+G5dP41SV+V0X0zeyW5Tg== X-CSE-MsgGUID: oBPVK0DhR+e1j+3mxw8acQ== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 20 Jan 2025 18:47:46 +0900 Received: from localhost.localdomain (unknown [10.226.92.210]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 1E1C4401BF0C; Mon, 20 Jan 2025 18:47:43 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH 09/11] irqchip/renesas-rzv2h: Add tien variable to struct rzv2h_hw_info Date: Mon, 20 Jan 2025 09:47:05 +0000 Message-ID: <20250120094715.25802-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250120094715.25802-1-biju.das.jz@bp.renesas.com> References: <20250120094715.25802-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The TINT enable position on RZ/G3E is BIT 15 compared to BIT 8 on RZ/V2H. Add tien variable to struct rzv2h_hw_info to simplify the calculations when we add support for RZ/G3E and drop the macro ICU_TSSR_TIEN. Signed-off-by: Biju Das --- drivers/irqchip/irq-renesas-rzv2h.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index 5990dcf72ef0..a1ca34d33c93 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -64,8 +64,6 @@ #define ICU_TINT_LEVEL_HIGH 2 #define ICU_TINT_LEVEL_LOW 3 -#define ICU_TSSR_TIEN(n) (BIT(7) << ((n) * 8)) - #define ICU_TITSR_K(tint_nr) ((tint_nr) / 16) #define ICU_TITSR_TITSEL_N(tint_nr) ((tint_nr) % 16) #define ICU_TITSR_TITSEL_PREP(titsel, n) ICU_IITSR_IITSEL_PREP(titsel, n) @@ -78,6 +76,7 @@ /** * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure. * @t_offs: TINT offset + * @tien: TIEN mask * @tssel_mask: TSSEL mask * @tssel_shift: TSSEL shift * @max_tssel: TSSEL max value @@ -85,6 +84,7 @@ */ struct rzv2h_hw_info { u16 t_offs; + u16 tien; u16 tssel_mask; u8 tssel_shift; u8 max_tssel; @@ -152,9 +152,9 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable) guard(raw_spinlock)(&priv->lock); tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k)); if (enable) - tssr |= ICU_TSSR_TIEN(tssel_n); + tssr |= priv->info->tien << (tssel_n * priv->info->tssel_shift); else - tssr &= ~ICU_TSSR_TIEN(tssel_n); + tssr &= ~(priv->info->tien << (tssel_n * priv->info->tssel_shift)); writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k)); } @@ -314,7 +314,7 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) titsr_k = ICU_TITSR_K(tint_nr); titsel_n = ICU_TITSR_TITSEL_N(tint_nr); - tien = ICU_TSSR_TIEN(titsel_n); + tien = priv->info->tien << (titsel_n * priv->info->tssel_shift); guard(raw_spinlock)(&priv->lock); @@ -517,6 +517,7 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p static const struct rzv2h_hw_info rzv2h_hw_params = { .t_offs = 0, .max_tssel = 0x55, + .tien = BIT(7), .tssel_mask = GENMASK(6, 0), .tssel_shift = 8, .tssr_k = 4, From patchwork Mon Jan 20 09:47:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13944922 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9F44D19AD8D for ; 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dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: ZmZtv86XRay4ZGaG3p/e4Q== X-CSE-MsgGUID: 2coP6KzIRViVuwHTyQ7vng== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 20 Jan 2025 18:47:48 +0900 Received: from localhost.localdomain (unknown [10.226.92.210]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id ACA3E400F73B; Mon, 20 Jan 2025 18:47:46 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH 10/11] irqchip/renesas-rzv2h: Add RZ/G3E support Date: Mon, 20 Jan 2025 09:47:06 +0000 Message-ID: <20250120094715.25802-11-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250120094715.25802-1-biju.das.jz@bp.renesas.com> References: <20250120094715.25802-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The ICU block on the RZ/G3E SoC is almost identical to the one found on the RZ/V2H SoC, with the following differences: - The TINT register offset starts at 0x830 instead of 0x30. - The number of GPIO interrupts for TINT selection is 141 instead of 86. - The pin index and TINT selection index are not in the 1:1 map - The number of TSSR registers is 15 instead of 8 - Each TSSR register can program 2 TINTs instead of 4 TINTs Add support for the RZ/G3E driver by filling the rzv2h_hw_info table and adding LUT for mapping between pin index and TINT selection index. Signed-off-by: Biju Das --- drivers/irqchip/irq-renesas-rzv2h.c | 47 +++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index a1ca34d33c93..a0d79b357379 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -75,6 +75,7 @@ /** * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure. + * @tssel_lut: TINT lookup table * @t_offs: TINT offset * @tien: TIEN mask * @tssel_mask: TSSEL mask @@ -83,6 +84,7 @@ * @tssr_k: TSSR index k */ struct rzv2h_hw_info { + const u8 *tssel_lut; u16 t_offs; u16 tien; u16 tssel_mask; @@ -306,6 +308,9 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) if (tint > priv->info->max_tssel) return -EINVAL; + if (priv->info->tssel_lut) + tint = priv->info->tssel_lut[tint & 0xff]; + hwirq = irqd_to_hwirq(d); tint_nr = hwirq - ICU_TINT_START; @@ -514,6 +519,42 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p return ret; } +/* Mapping based on port index on Table 4.2-6 and TSSEL bits on Table 4.6-4 */ +static const u8 rzg3e_tssel_lut[] = { + 81, 82, 83, 84, 85, 86, 87, 88, /* P00-P07 */ + 89, 90, 91, 92, 93, 94, 95, 96, /* P10-P17 */ + 111, 112, /* P20-P21 */ + 97, 98, 99, 100, 101, 102, 103, 104, /* P30-P37 */ + 105, 106, 107, 108, 109, 110, /* P40-P45 */ + 113, 114, 115, 116, 117, 118, 119, /* P50-P56 */ + 120, 121, 122, 123, 124, 125, 126, /* P60-P66 */ + 127, 128, 129, 130, 131, 132, 133, 134, /* P70-P77 */ + 135, 136, 137, 138, 139, 140, /* P80-P85 */ + 43, 44, 45, 46, 47, 48, 49, 50, /* PA0-PA7 */ + 51, 52, 53, 54, 55, 56, 57, 58, /* PB0-PB7 */ + 59, 60, 61, /* PC0-PC2 */ + 62, 63, 64, 65, 66, 67, 68, 69, /* PD0-PD7 */ + 70, 71, 72, 73, 74, 75, 76, 77, /* PE0-PE7 */ + 78, 79, 80, /* PF0-PF2 */ + 25, 26, 27, 28, 29, 30, 31, 32, /* PG0-PG7 */ + 33, 34, 35, 36, 37, 38, /* PH0-PH5 */ + 4, 5, 6, 7, 8, /* PJ0-PJ4 */ + 39, 40, 41, 42, /* PK0-PK3 */ + 9, 10, 11, 12, 21, 22, 23, 24, /* PL0-PL7 */ + 13, 14, 15, 16, 17, 18, 19, 20, /* PM0-PM7 */ + 0, 1, 2, 3 /* PS0-PS3 */ +}; + +static const struct rzv2h_hw_info rzg3e_hw_params = { + .tssel_lut = rzg3e_tssel_lut, + .t_offs = 0x800, + .max_tssel = 0x8c, + .tien = BIT(15), + .tssel_mask = GENMASK(7, 0), + .tssel_shift = 16, + .tssr_k = 2, +}; + static const struct rzv2h_hw_info rzv2h_hw_params = { .t_offs = 0, .max_tssel = 0x55, @@ -523,12 +564,18 @@ static const struct rzv2h_hw_info rzv2h_hw_params = { .tssr_k = 4, }; +static int rzg3e_icu_init(struct device_node *node, struct device_node *parent) +{ + return rzv2h_icu_init_common(node, parent, &rzg3e_hw_params); +} + static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) { return rzv2h_icu_init_common(node, parent, &rzv2h_hw_params); } IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu) +IRQCHIP_MATCH("renesas,r9a09g047-icu", rzg3e_icu_init) IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_init) IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu) MODULE_AUTHOR("Fabrizio Castro "); From patchwork Mon Jan 20 09:47:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13944923 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6437B1AF0B0; Mon, 20 Jan 2025 09:47:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737366474; cv=none; b=AuRnblRELSQY27FIV4+ayMQ3LzBaEKwxx7HcMSLUmaeBiyM7eUyetd946TOReoOX5E+dUjySqnAGipRT1ON/MC4pL7PBTsRMPnEsvV/NWi2feCaH+9R4p+W5cfhfnS8KDfd7YVARBqIQvO6g6MQiBcf3c8NMxfUJv3XoU7s2tI4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737366474; c=relaxed/simple; bh=/XHkEIQJnwHkkkuaC14utEhUSKISy8uMGWEQa4/+AS4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bGtIxLaWms8puoq91GJwRVC80OOwyRp5qjSc57UnRKv6zzoufEyRXBnDdJN7O47yIue3mN/2MdypVOlF2R97MSxBjG9iiyIxC61Qp4QvgQUH+KRcAA2DHQU5ZV1DiFD3sKtl4SWtnRQWEsqfIAY0Ehb5GFg2W0MIla3naXBLy+M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: DciW5PrJTqWbf9BbZhHHZg== X-CSE-MsgGUID: ohcz8RuSTR+R7dmmzqN7Kg== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 20 Jan 2025 18:47:52 +0900 Received: from localhost.localdomain (unknown [10.226.92.210]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 24A304001968; Mon, 20 Jan 2025 18:47:48 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 11/11] arm64: dts: renesas: r9a09g047: Add icu node Date: Mon, 20 Jan 2025 09:47:07 +0000 Message-ID: <20250120094715.25802-12-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250120094715.25802-1-biju.das.jz@bp.renesas.com> References: <20250120094715.25802-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add interrupt control node to RZ/G3E ("R9A09G047") SoC DTSI and add icu as interrupt-parent of pincontrol. Also, define the ICU IRQs for board DT users. Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 108 +++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 133aa3272d3a..0beac052f208 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -8,6 +8,24 @@ #include #include +#define RZG3E_NMI 0 +#define RZG3E_IRQ0 1 +#define RZG3E_IRQ1 2 +#define RZG3E_IRQ2 3 +#define RZG3E_IRQ3 4 +#define RZG3E_IRQ4 5 +#define RZG3E_IRQ5 6 +#define RZG3E_IRQ6 7 +#define RZG3E_IRQ7 8 +#define RZG3E_IRQ8 9 +#define RZG3E_IRQ9 10 +#define RZG3E_IRQ10 11 +#define RZG3E_IRQ11 12 +#define RZG3E_IRQ12 13 +#define RZG3E_IRQ13 14 +#define RZG3E_IRQ14 15 +#define RZG3E_IRQ15 16 + / { compatible = "renesas,r9a09g047"; #address-cells = <2>; @@ -131,6 +149,95 @@ soc: soc { #size-cells = <2>; ranges; + icu: interrupt-controller@10400000 { + compatible = "renesas,r9a09g047-icu"; + reg = <0 0x10400000 0 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "nmi", + "port_irq0", "port_irq1", "port_irq2", + "port_irq3", "port_irq4", "port_irq5", + "port_irq6", "port_irq7", "port_irq8", + "port_irq9", "port_irq10", "port_irq11", + "port_irq12", "port_irq13", "port_irq14", + "port_irq15", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "int-ca55-0", "int-ca55-1", + "int-ca55-2", "int-ca55-3", + "icu-error-ca55", + "gpt-u0-gtciada", "gpt-u0-gtciadb", + "gpt-u1-gtciada", "gpt-u1-gtciadb"; + clocks = <&cpg CPG_MOD 0x5>; + power-domains = <&cpg>; + resets = <&cpg 0x36>; + }; + pinctrl: pinctrl@10410000 { compatible = "renesas,r9a09g047-pinctrl"; reg = <0 0x10410000 0 0x10000>; @@ -140,6 +247,7 @@ pinctrl: pinctrl@10410000 { gpio-ranges = <&pinctrl 0 0 232>; #interrupt-cells = <2>; interrupt-controller; + interrupt-parent = <&icu>; power-domains = <&cpg>; resets = <&cpg 0xa5>, <&cpg 0xa6>; };