From patchwork Mon Jan 20 13:09:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13945078 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 776C61E0E13 for ; Mon, 20 Jan 2025 13:09:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737378585; cv=none; b=LdpX+eNBv3EWi9umExKA+ooJPvZ6U6IDnhy5anSmv08KKu7oCrPu63QVP6+v38rSDc2SUZrS7e6kkgHNpftIQXTYjDjIUutEVh33O1WFlKLNAE7LUnh50GuhcJ9xiT5OXf5x8JZ4rVPAYcwSyOM3DMVDrGmc8WXjluWgyuQ9kso= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737378585; c=relaxed/simple; bh=uct9U7IhGmLGks2dzIuQgZHdXFiBAwtQzHFSaHGw5ao=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QyB1w7/SRNg1LgYkFtLM1COPDi43s21WBXRvAKNeXcQBrgG8JsJ4erauGgk8Jm8GyzxUIH+0aipbbuFjGHMZmYP5fhTJDGG2vYde7A1fXxsKfF9jPuvGMPKn1xsxBL4zUIeeDfLBEIG1qyUgcp/I3x2nzbKWHTWQpiDUmyZaIyg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=A5rclq2a; arc=none smtp.client-ip=209.85.128.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="A5rclq2a" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-43625c4a50dso30687275e9.0 for ; Mon, 20 Jan 2025 05:09:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737378582; x=1737983382; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f6x24vOEL5/TJ8vXf0hNcJSgsC5eLh36a2PxWG5XS3Q=; b=A5rclq2aAaPsgiQLdXDrjLZ5tbiqvYLg+ba9RHu9YPDBrUuryNzfrqiqImCrFBbyGb nSwQh04H8o7XaWrH9kRR/ef0Q2HGyy23qolknvFih6eAHJhmNkuAj589GQcL/QXyZGyc 95uAabMEgP7rV95nxZM4l18VSlhg3OndDuHFYXoDVZ8JelwvL49x8/JmoXyUu3GL1KSl un2BIpyX33MkzWBoL39J7bd6PHKNg1wAFLX0ldl9CqK3YWGlzHqQwaz/JC2+eFxTH2W5 kXIysTatgOGkrlJVzuggTxSCjs7Z8VI4J/eczgerBw9UYQhD+f0Jo9Ua/7xqTIkH6z19 xFuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737378582; x=1737983382; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f6x24vOEL5/TJ8vXf0hNcJSgsC5eLh36a2PxWG5XS3Q=; b=NCH5HC/fBLWs1iCwr/pd/SkaWSlbuCkgEqNGhGylc2PL+DasbS9hY0/2FdYm/7CP7E ZN5a4fRA659EpmUmInwAlFXJuKwQRRoCZGslA1a0VKcvLdPu4Pw0dKhX//2cNElJOZ07 t8gV3B15G7u4FEjF04kkmyPG0qpt75en8lCsN/pq/dIM3Xr3I5VAIz7V7zYxNeTGCZ2S KUzgqp2aBgA12729aSDd+C6cloCN8wZkuhUy/PBHFd7a9UfKks+FScD2wiP28FvYS5xV dF/vTWN5E+W0Ztyydf1dP4Hv8cKMsqb5WDNR5h7mqp09lG31HuAOeyayNlb1oMKjhS5e FoTQ== X-Forwarded-Encrypted: i=1; AJvYcCU41fBYBhlWDpa7QMxrV6bWa/Hl/pxpHVX8xZHaU0N5juTVbHxbKXkdwQ0a1SM2C3OTIeeWw2V41JgvOduA1KxUdQ==@vger.kernel.org X-Gm-Message-State: AOJu0YygnNlsmTjusPEEoZkt016k8W06hQkX9SsBzJAUsmYakZ2G+4N4 Bt3totWF32CJ97/uYjIhNpmpk+0tBCQ8SRMSPky8Q3sG+gOBb7ndbZDpAqoovcQ= X-Gm-Gg: ASbGncumY0wxTfV163TVi6qAmpNHa+Ec6K36Gv2jg93tsajG/Rt+yGndYthApwwvUru Jiv2nWwlh1t7FhOT6fy4w6pGa2T3ArOQMfeeD+ixTWTvrD7e+P3qGvTNOQSoBEcsK+eHy9vmZ5Q Iarz6X+XB/pbL5Pte/0rh+yw7vVX1OBRgXWWUU5WZWadFwrgBdiNxRgoePYd2H0TJl64LGgzFW1 5tRFLmQJ76xQpi5GqHjXamra8XsSIXw1w0U+TBn/h3z2cfCADUtVnOcigMJ/xCNMabSY3YejMZJ wbz9UUeRYajwRVXu+Bxi16M= X-Google-Smtp-Source: AGHT+IGxlb5HA5FYguAsz6eUdlluzgj3rUbYoqrhqAKMsNvCOU1DkxKaDcLmK42gJnvVftsGSFzeeQ== X-Received: by 2002:a05:600c:3844:b0:434:ff08:202b with SMTP id 5b1f17b1804b1-438913dbc09mr122718855e9.12.1737378581607; Mon, 20 Jan 2025 05:09:41 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4389041f61bsm138001955e9.17.2025.01.20.05.09.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jan 2025 05:09:41 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, magnus.damm@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, p.zabel@pengutronix.de, claudiu.beznea.uj@bp.renesas.com, wsa+renesas@sang-engineering.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v4 1/4] serial: sh-sci: Update the suspend/resume support Date: Mon, 20 Jan 2025 15:09:33 +0200 Message-ID: <20250120130936.1080069-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250120130936.1080069-1-claudiu.beznea.uj@bp.renesas.com> References: <20250120130936.1080069-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The Renesas RZ/G3S supports a power saving mode where power to most of the SoC components is turned off. When returning from this power saving mode, SoC components need to be re-configured. The SCIFs on the Renesas RZ/G3S need to be re-configured as well when returning from this power saving mode. The sh-sci code already configures the SCIF clocks, power domain and registers by calling uart_resume_port() in sci_resume(). On suspend path the SCIF UART ports are suspended accordingly (by calling uart_suspend_port() in sci_suspend()). The only missing setting is the reset signal. For this assert/de-assert the reset signal on driver suspend/resume. In case the no_console_suspend is specified by the user, the registers need to be saved on suspend path and restore on resume path. To do this the sci_console_setup() function was added. There is no need to cache/restore the status or FIFO registers. Only the control registers. To differentiate b/w these, the struct sci_port_params::regs was updated with a new member that specifies if the register needs to be chached on suspend. Only the RZ_SCIFA instances were updated with this new support as the hardware for the rest of variants was missing for testing. Signed-off-by: Claudiu Beznea --- Changes in v4: - none Changes in v3: - none Changes in v2: - rebased on top of the update version of patch 2/8 from this series drivers/tty/serial/sh-sci.c | 53 ++++++++++++++++++++++++++++++------- 1 file changed, 44 insertions(+), 9 deletions(-) diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index b1ea48f38248..ae43237dd684 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -101,7 +101,7 @@ enum SCI_CLKS { if ((_port)->sampling_rate_mask & SCI_SR((_sr))) struct plat_sci_reg { - u8 offset, size; + u8 offset, size, suspend_cacheable; }; struct sci_port_params { @@ -134,6 +134,8 @@ struct sci_port { struct dma_chan *chan_tx; struct dma_chan *chan_rx; + struct reset_control *rstc; + #ifdef CONFIG_SERIAL_SH_SCI_DMA struct dma_chan *chan_tx_saved; struct dma_chan *chan_rx_saved; @@ -153,6 +155,7 @@ struct sci_port { int rx_trigger; struct timer_list rx_fifo_timer; int rx_fifo_timeout; + unsigned int console_cached_regs[SCIx_NR_REGS]; u16 hscif_tot; bool has_rtscts; @@ -300,17 +303,17 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { */ [SCIx_RZ_SCIFA_REGTYPE] = { .regs = { - [SCSMR] = { 0x00, 16 }, - [SCBRR] = { 0x02, 8 }, - [SCSCR] = { 0x04, 16 }, + [SCSMR] = { 0x00, 16, 1 }, + [SCBRR] = { 0x02, 8, 1 }, + [SCSCR] = { 0x04, 16, 1 }, [SCxTDR] = { 0x06, 8 }, [SCxSR] = { 0x08, 16 }, [SCxRDR] = { 0x0A, 8 }, - [SCFCR] = { 0x0C, 16 }, + [SCFCR] = { 0x0C, 16, 1 }, [SCFDR] = { 0x0E, 16 }, - [SCSPTR] = { 0x10, 16 }, + [SCSPTR] = { 0x10, 16, 1 }, [SCLSR] = { 0x12, 16 }, - [SEMR] = { 0x14, 8 }, + [SEMR] = { 0x14, 8, 1 }, }, .fifosize = 16, .overrun_reg = SCLSR, @@ -3374,6 +3377,7 @@ static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, } sp = &sci_ports[id]; + sp->rstc = rstc; *dev_id = id; p->type = SCI_OF_TYPE(data); @@ -3546,13 +3550,34 @@ static int sci_probe(struct platform_device *dev) return 0; } +static void sci_console_setup(struct sci_port *s, bool save) +{ + for (u16 i = 0; i < SCIx_NR_REGS; i++) { + struct uart_port *port = &s->port; + + if (!s->params->regs[i].suspend_cacheable) + continue; + + if (save) + s->console_cached_regs[i] = sci_serial_in(port, i); + else + sci_serial_out(port, i, s->console_cached_regs[i]); + } +} + static __maybe_unused int sci_suspend(struct device *dev) { struct sci_port *sport = dev_get_drvdata(dev); - if (sport) + if (sport) { uart_suspend_port(&sci_uart_driver, &sport->port); + if (!console_suspend_enabled && uart_console(&sport->port)) + sci_console_setup(sport, true); + else + return reset_control_assert(sport->rstc); + } + return 0; } @@ -3560,8 +3585,18 @@ static __maybe_unused int sci_resume(struct device *dev) { struct sci_port *sport = dev_get_drvdata(dev); - if (sport) + if (sport) { + if (!console_suspend_enabled && uart_console(&sport->port)) { + sci_console_setup(sport, false); + } else { + int ret = reset_control_deassert(sport->rstc); + + if (ret) + return ret; + } + uart_resume_port(&sci_uart_driver, &sport->port); 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([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4389041f61bsm138001955e9.17.2025.01.20.05.09.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jan 2025 05:09:42 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, magnus.damm@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, p.zabel@pengutronix.de, claudiu.beznea.uj@bp.renesas.com, wsa+renesas@sang-engineering.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v4 2/4] arm64: dts: renesas: rzg3s-smarc-switches: Add a header to describe different switches Date: Mon, 20 Jan 2025 15:09:34 +0200 Message-ID: <20250120130936.1080069-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250120130936.1080069-1-claudiu.beznea.uj@bp.renesas.com> References: <20250120130936.1080069-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea There are different switches available on both the RZ/G3S SMARC Module and RZ SMARC Carrier II boards. These switches are used to route different SoC signals to different parts available on board. These switches are described in device trees through macros. These macros are set accordingly such that the resulted compiled dtb to describe the on-board switches states. The SCIF1 depends on the state of the SW_CONFIG3 and SW_OPT_MUX4 switches. SCIF1 can be enabled through a device tree overlay. To manage all switches in a unified state and allow users to configure the output device tree, add a file that contains all switch definitions and states. Commit prepares the code to enable SCIF1 on the RZ/G3S overlay. Signed-off-by: Claudiu Beznea --- Changes in v4: - adjusted the patch description - used GPL-2.0-only OR BSD-2-Clause license - used proper description for SW_CONFIG3 Changes in v3: - none Changes in v2: - none .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 20 +----------- .../boot/dts/renesas/rzg3s-smarc-switches.h | 32 +++++++++++++++++++ 2 files changed, 33 insertions(+), 19 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index ef12c1c462a7..39845faec894 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -9,25 +9,7 @@ #include #include -/* - * On-board switches' states: - * @SW_OFF: switch's state is OFF - * @SW_ON: switch's state is ON - */ -#define SW_OFF 0 -#define SW_ON 1 - -/* - * SW_CONFIG[x] switches' states: - * @SW_CONFIG2: - * SW_OFF - SD0 is connected to eMMC - * SW_ON - SD0 is connected to uSD0 card - * @SW_CONFIG3: - * SW_OFF - SD2 is connected to SoC - * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC - */ -#define SW_CONFIG2 SW_OFF -#define SW_CONFIG3 SW_ON +#include "rzg3s-smarc-switches.h" / { compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h new file mode 100644 index 000000000000..514a8a6dc013 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * On-board switches for the Renesas RZ/G3S SMARC Module and RZ SMARC Carrier II + * boards. + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#ifndef __RZG3S_SMARC_SWITCHES__ +#define __RZG3S_SMARC_SWITCHES__ + +/* + * On-board switches' states: + * @SW_OFF: switch's state is OFF + * @SW_ON: switch's state is ON + */ +#define SW_OFF 0 +#define SW_ON 1 + +/* + * SW_CONFIG[x] switches' states: + * @SW_CONFIG2: + * SW_OFF - SD0 is connected to eMMC + * SW_ON - SD0 is connected to uSD0 card + * @SW_CONFIG3: + * SW_OFF - SD2 is connected to SoC + * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC + */ +#define SW_CONFIG2 SW_OFF +#define SW_CONFIG3 SW_ON + +#endif /* __RZG3S_SMARC_SWITCHES__ */ From patchwork Mon Jan 20 13:09:35 2025 Content-Type: text/plain; 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([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4389041f61bsm138001955e9.17.2025.01.20.05.09.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jan 2025 05:09:44 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, magnus.damm@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, p.zabel@pengutronix.de, claudiu.beznea.uj@bp.renesas.com, wsa+renesas@sang-engineering.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v4 3/4] arm64: dts: renesas: rzg3s-smarc: Enable SCIF3 Date: Mon, 20 Jan 2025 15:09:35 +0200 Message-ID: <20250120130936.1080069-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250120130936.1080069-1-claudiu.beznea.uj@bp.renesas.com> References: <20250120130936.1080069-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Enable SCIF3. It is routed on the RZ SMARC Carrier II board on SER1_UART interface. Signed-off-by: Claudiu Beznea --- Changes in v4: - dropped checking the SW_CONFIG3 - dropped the include of rzg3s-smarc-switches.h Changes in v3: - none Changes in v2: - none arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index 81b4ffd1417d..0851e0b7ed40 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -12,6 +12,7 @@ / { aliases { i2c0 = &i2c0; + serial1 = &scif3; serial3 = &scif0; mmc1 = &sdhi1; }; @@ -162,6 +163,11 @@ scif0_pins: scif0 { ; /* TXD */ }; + scif3_pins: scif3 { + pinmux = , /* RXD */ + ; /* TXD */ + }; + sdhi1_pins: sd1 { data { pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; @@ -208,6 +214,12 @@ &scif0 { status = "okay"; }; +&scif3 { + pinctrl-names = "default"; + pinctrl-0 = <&scif3_pins>; + status = "okay"; +}; + &sdhi1 { pinctrl-0 = <&sdhi1_pins>; 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([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4389041f61bsm138001955e9.17.2025.01.20.05.09.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jan 2025 05:09:46 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, magnus.damm@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, p.zabel@pengutronix.de, claudiu.beznea.uj@bp.renesas.com, wsa+renesas@sang-engineering.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v4 4/4] arm64: dts: renesas: r9a08g045s33-smarc-pmod: Add overlay for SCIF1 Date: Mon, 20 Jan 2025 15:09:36 +0200 Message-ID: <20250120130936.1080069-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250120130936.1080069-1-claudiu.beznea.uj@bp.renesas.com> References: <20250120130936.1080069-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add DT overlay for SCIF1 (of the Renesas RZ/G3S SoC) routed through the PMOD1_3A interface available on the Renesas RZ SMARC Carrier II board. Signed-off-by: Claudiu Beznea --- Changes in v4: - rename overlay name to r9a08g045s33-smarc-pmod1-type-3a - add note about the needed switches for SCIF1 - guard the scif1 node with #if SW_CONFIG3 == SW_ON && SW_OPT_MUX4 == SW_ON - dropped the alias section from the overlay file and move it the board file - document SW_OPT_MUX4 switch Changes in v3: - none Changes in v2: - none arch/arm64/boot/dts/renesas/Makefile | 3 ++ .../r9a08g045s33-smarc-pmod1-type-3a.dtso | 48 +++++++++++++++++++ .../boot/dts/renesas/rzg3s-smarc-switches.h | 8 ++++ arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 1 + 4 files changed, 60 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 928635f2e76b..ef7f7b55145d 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -143,6 +143,9 @@ r9a07g054l2-smarc-cru-csi-ov5645-dtbs := r9a07g054l2-smarc.dtb r9a07g054l2-smarc dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc-cru-csi-ov5645.dtb dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc.dtb +dtb-$(CONFIG_ARCH_R9A07G043) += r9a08g045s33-smarc-pmod1-type-3a.dtbo +r9a08g045s33-smarc-pmod1-type-3a-dtbs := r9a08g045s33-smarc.dtb r9a08g045s33-smarc-pmod1-type-3a.dtbo +dtb-$(CONFIG_ARCH_R9A07G043) += r9a08g045s33-smarc-pmod1-type-3a.dtb dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb diff --git a/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso b/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso new file mode 100644 index 000000000000..e4cb4449f190 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the RZ/G3S SMARC Carrier II EVK PMOD parts + * + * Copyright (C) 2024 Renesas Electronics Corp. + * + * + * [Connection] + * + * SMARC Carrier II EVK + * +--------------------------------------------+ + * |PMOD1_3A (PMOD1 PIN HEADER) | + * | SCIF1_CTS# (pin1) (pin7) PMOD1_GPIO10 | + * | SCIF1_TXD (pin2) (pin8) PMOD1_GPIO11 | + * | SCIF1_RXD (pin3) (pin9) PMOD1_GPIO12 | + * | SCIF1_RTS# (pin4) (pin10) PMOD1_GPIO13 | + * | GND (pin5) (pin11) GND | + * | PWR_PMOD1 (pin6) (pin12) GND | + * +--------------------------------------------+ + * + * The following switches should be set as follows for SCIF1: + * - SW_CONFIG2: ON + * - SW_OPT_MUX4: ON + */ + +/dts-v1/; +/plugin/; + +#include +#include "rzg3s-smarc-switches.h" + +&pinctrl { + scif1_pins: scif1-pins { + pinmux = , /* TXD */ + , /* RXD */ + , /* CTS */ + ; /* RTS */ + }; +}; + +#if SW_CONFIG3 == SW_ON && SW_OPT_MUX4 == SW_ON +&scif1 { + pinctrl-names = "default"; + pinctrl-0 = <&scif1_pins>; + uart-has-rtscts; + status = "okay"; +}; +#endif diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h index 514a8a6dc013..9766cea55dc6 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h @@ -29,4 +29,12 @@ #define SW_CONFIG2 SW_OFF #define SW_CONFIG3 SW_ON +/* + * SW_OPT_MUX[x] switches' states: + * @SW_OPT_MUX4: + * SW_OFF - The SMARC SER0 signals are routed to M.2 Key E UART + * SW_ON - The SMARC SER0 signals are routed to PMOD1 + */ +#define SW_OPT_MUX4 SW_ON + #endif /* __RZG3S_SMARC_SWITCHES__ */ diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index 0851e0b7ed40..5e044a4d0234 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -12,6 +12,7 @@ / { aliases { i2c0 = &i2c0; + serial0 = &scif1; serial1 = &scif3; serial3 = &scif0; mmc1 = &sdhi1;