From patchwork Mon Jan 20 14:41:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 13945162 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 081371E3DD0; Mon, 20 Jan 2025 14:42:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737384168; cv=none; b=mNlZUk2RgDcdDwfpNgkaUZQXx1yXctA9xt3dXtos5mNgr7pUGrBXJ5BWyGWTKZD89Lkoa26FdfT/GKmKgB2jzSgHfiInsjt0VTM8ISXezAOhl1Kw2OrFLRpK5EMjxIcip/niNWFaqKhb7AKjOpxm7DFOZ5+bCawikTO3w8oNNNo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737384168; c=relaxed/simple; bh=cCCt1z+IEVRiJ6ejCa09m6Lrq4Wa209py8lnf/4l9FA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=o1RMHk2Y+ID/raI2WjhrXqj5XtXxLIukrJoWG3pbQC3aGCRx/pKKXrlAV5BJena+aAxCawCJjoeGEzNActv2bsqNLoJ1AhsD/HXS3hJMyh8eJ8DDK0LWmDJkmSpb7cTjGn9tGDv7rk7XdsTtWlrUMBoXMyqPjcspSC4qp6gSzzk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Le4/dz2l; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Le4/dz2l" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A7628C4CEEE; Mon, 20 Jan 2025 14:42:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1737384167; bh=cCCt1z+IEVRiJ6ejCa09m6Lrq4Wa209py8lnf/4l9FA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Le4/dz2lKiWMpjyEdkCBAkbWxKiYkfgM7DKUMerpT3NDXHZPzf17MgFWLwwlUJACa uLDjqRETRIEsiMXV6QezyXrGesjhl+Os3d+RQui2zTae0BgP+v1fDqRVxRMi/pUZlW NuxdrN3nhilGdMW+TBBwwuPCFFAl/HH5lrzl1VNSeTp2TTdjiBihC9RtOL2A1ULKyC PbAPy+QkQNpVzNAjwSbzZ5SOSoT3ZPv2y45j83vX3pyNx5LLwKwmadZny9d54qoBTR BqjofOdiBkkqslTAQxVaKT7AwaYYYHfZkhcLc4x7IEGJ/7m+CCTVO3YC5+CwHUDzPQ vBnlvWdZCo/oA== Received: from johan by xi.lan with local (Exim 4.97.1) (envelope-from ) id 1tZszL-0000000037y-1AVS; Mon, 20 Jan 2025 15:42:51 +0100 From: Johan Hovold To: Alexandre Belloni , Bjorn Andersson Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Jonathan Marek , linux-arm-msm@vger.kernel.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH 1/7] dt-bindings: rtc: qcom-pm8xxx: add uefi-variable offset Date: Mon, 20 Jan 2025 15:41:46 +0100 Message-ID: <20250120144152.11949-2-johan+linaro@kernel.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250120144152.11949-1-johan+linaro@kernel.org> References: <20250120144152.11949-1-johan+linaro@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On many Qualcomm platforms the PMIC RTC control and time registers are read-only so that the RTC time can not be updated. Instead an offset needs be stored in some machine-specific non-volatile memory, which a driver can take into account. Add a 'qcom,uefi-rtc-info' boolean flag which indicates that the RTC offset is stored in a Qualcomm specific UEFI variable so that the RTC time can be updated on such platforms. The UEFI variable is 882f8c2b-9646-435f-8de5-f208ff80c1bd-RTCInfo and holds a 12-byte structure where the first four bytes is a GPS time offset in little-endian byte order. Signed-off-by: Johan Hovold --- Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml b/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml index d274bb7a534b..cdc56dfbfac3 100644 --- a/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml @@ -50,6 +50,12 @@ properties: items: - const: offset + qcom,uefi-rtc-info: + type: boolean + description: + RTC offset is stored as a four-byte GPS time offset in a 12-byte UEFI + variable 882f8c2b-9646-435f-8de5-f208ff80c1bd-RTCInfo + wakeup-source: true required: From patchwork Mon Jan 20 14:41:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 13945168 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C4B81E47A9; Mon, 20 Jan 2025 14:42:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737384168; cv=none; b=aD6p0JAymuWgejJs7Ab+wf/9i3NFUcVKEWRV4oVOQeDL4b6NTcXM67Ib9gvJB67PAgLjRm3RIC5quIQ7fLUNuSym0RHZxyMWvFqjl8WXpMC85q1O6FROL1LVrFkrdKc42/JqSWOwFZEPFzrW6JMKL6Pu/ChSo3POPGDtL/KVJKA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737384168; c=relaxed/simple; bh=g5B8wRzRuC7nVNYrPG6OJobEDMTyTs0Bs77db0cnHP0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jJaz6L0186dji1ze+vUGjfSBqLqMo0adGmxmHRIwd44jd1viEdy1MtPRbn10j5vFz/FW2HDwdvhlxBtP83VQIpq9e1HjEXy6hA+VDHEI2I1nmCPCh8cdGz/ZcH35ptdjOZFQciqQhuda0jV234TbKkMvjRWWHNjfhyrs9tZ6wHM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=njpLeZIF; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="njpLeZIF" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A8362C4CEEF; Mon, 20 Jan 2025 14:42:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1737384167; bh=g5B8wRzRuC7nVNYrPG6OJobEDMTyTs0Bs77db0cnHP0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=njpLeZIF07oARHvgJqP5MnDDJBOPXMlJyzQdQsqnQaqQQSkqYJk/cGLqSyq+NSaKs WUG/RO1YgX40wJ/NZWsXe0U/E8FDTBxO7p1ZuiDY3t0GFdoCXz90MNQ76oemWhUEvj 3kgCCFHcHmMG3psXbw83fcQnq44dd8i++fg6QUezKzmZGkS6pro9axfDlI0cmrA9D6 2vH5SEbXeeOCWtf8RVSqT7tazmLDytuEZB7N+iRUN7DwUCwv5WU7Ze1Va3CufzRWkJ q1D6Q7DZTedegahgNKwyL1s0Uo7K+n/ozY7nJSPDbvOHPks43Kw7dMpvOkhtixNmGt O5K5jjBve0dJw== Received: from johan by xi.lan with local (Exim 4.97.1) (envelope-from ) id 1tZszL-00000000380-1V5x; Mon, 20 Jan 2025 15:42:51 +0100 From: Johan Hovold To: Alexandre Belloni , Bjorn Andersson Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Jonathan Marek , linux-arm-msm@vger.kernel.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH 2/7] dt-bindings: rtc: qcom-pm8xxx: document qcom,no-alarm flag Date: Mon, 20 Jan 2025 15:41:47 +0100 Message-ID: <20250120144152.11949-3-johan+linaro@kernel.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250120144152.11949-1-johan+linaro@kernel.org> References: <20250120144152.11949-1-johan+linaro@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Jonathan Marek Qualcomm x1e80100 firmware sets the ownership of the RTC alarm to ADSP. Thus writing to RTC alarm registers and receiving alarm interrupts is not possible. Add a qcom,no-alarm flag to support RTC on this platform. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20241015004945.3676-3-jonathan@marek.ca [ johan: move vendor property; use boolean; reword description ] Signed-off-by: Johan Hovold --- Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml b/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml index cdc56dfbfac3..7497dc3ac5b2 100644 --- a/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml @@ -50,6 +50,11 @@ properties: items: - const: offset + qcom,no-alarm: + type: boolean + description: + RTC alarm is not owned by the OS + qcom,uefi-rtc-info: type: boolean description: From patchwork Mon Jan 20 14:41:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 13945166 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55C5B1E412A; Mon, 20 Jan 2025 14:42:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737384168; cv=none; b=JvUA6V7Dxx1+yNmJUu6zJFg3zNTyi2wvgOK481Zkcccn39s8f5luW2Iu5vLvRqvxh1EUClMc/U7eRe5qRul8bRc90LJU7OZQaEOBGjFfa/I1vkHIrsBgj7TxnhVR5arqjKpgq4n4YgbMl/+vXSgMn0SwaLLehg+4TyDeaXnVgWc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737384168; c=relaxed/simple; bh=oDHEmr3MKOjjBGmHv0Y6U3Cze/d5aTyiFNbzNcI+nXs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dXFu1jNDqvn5L7EGC1C+bPSxhw3y5eT2v16JbXKoyAKxMRMQTB20PjgFqt4ksG/h55LargEES7shnfmAmdRwk0OMthPWAR5zCrEuroK8n0bHRWEADV3OHE8IwKkn1e9Bo6E7O0ePt8/oXtQY4hECpG0eFRS2CCBckZuJNKyus1w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QJpfd4bm; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QJpfd4bm" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8B70FC4CEEC; Mon, 20 Jan 2025 14:42:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1737384167; bh=oDHEmr3MKOjjBGmHv0Y6U3Cze/d5aTyiFNbzNcI+nXs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QJpfd4bmw0DaXYs+5ZU3ZPDUNhKUp+M9tfQO68F0Wnn7z3amrUm6mpkJcyZvlRjWD ngtvaujTSWeYRGr1Waf93YeIxfI7EXaXOB3CdHGGF+PfvhqVAo7sXtsGoGZ6/UBnRJ RsSuIxzWPonU1luciDRzImm4elP0kb2OFCdPKNmuXlCDvHGodhngNCUNsPo7dyzicn CprYDKsBuKq6T/KXwQqOOikQr9sbkJ1dv4sQhwKbcpNQuv7/L0khPbd1AvGyA2BARV lut+b3Lbwo20O3xJ/iL/Eimt5Dip6G/3cxJqdwP7PbTDGOzBXgFPAS6IHXHAn+7cUg u2CGgR4I4a7eA== Received: from johan by xi.lan with local (Exim 4.97.1) (envelope-from ) id 1tZszL-00000000382-1r6n; Mon, 20 Jan 2025 15:42:51 +0100 From: Johan Hovold To: Alexandre Belloni , Bjorn Andersson Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Jonathan Marek , linux-arm-msm@vger.kernel.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH 3/7] rtc: pm8xxx: add support for uefi offset Date: Mon, 20 Jan 2025 15:41:48 +0100 Message-ID: <20250120144152.11949-4-johan+linaro@kernel.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250120144152.11949-1-johan+linaro@kernel.org> References: <20250120144152.11949-1-johan+linaro@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On many Qualcomm platforms the PMIC RTC control and time registers are read-only so that the RTC time can not be updated. Instead an offset needs be stored in some machine-specific non-volatile memory, which the driver can take into account. Add support for storing a 32-bit offset from the GPS time epoch in a UEFI variable so that the RTC time can be set on such platforms. The UEFI variable is 882f8c2b-9646-435f-8de5-f208ff80c1bd-RTCInfo and holds a 12-byte structure where the first four bytes is a GPS time offset in little-endian byte order. Note that this format is not arbitrary as the variable is shared with the UEFI firmware (and Windows). Signed-off-by: Johan Hovold --- drivers/rtc/rtc-pm8xxx.c | 125 +++++++++++++++++++++++++++++++++++++-- include/linux/rtc.h | 1 + 2 files changed, 121 insertions(+), 5 deletions(-) diff --git a/drivers/rtc/rtc-pm8xxx.c b/drivers/rtc/rtc-pm8xxx.c index 2f32187ecc8d..be1983bf35cd 100644 --- a/drivers/rtc/rtc-pm8xxx.c +++ b/drivers/rtc/rtc-pm8xxx.c @@ -5,6 +5,7 @@ * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. * Copyright (c) 2023, Linaro Limited */ +#include #include #include #include @@ -16,9 +17,10 @@ #include #include #include - #include +#include + /* RTC_CTRL register bit fields */ #define PM8xxx_RTC_ENABLE BIT(7) #define PM8xxx_RTC_ALARM_CLEAR BIT(0) @@ -46,14 +48,21 @@ struct pm8xxx_rtc_regs { unsigned int alarm_en; }; +struct qcom_uefi_rtc_info { + __le32 offset_gps; + u8 reserved[8]; +} __packed; + /** * struct pm8xxx_rtc - RTC driver internal structure * @rtc: RTC device * @regmap: regmap used to access registers * @allow_set_time: whether the time can be set + * @use_uefi: use UEFI variable as fallback for offset * @alarm_irq: alarm irq number * @regs: register description * @dev: device structure + * @rtc_info: qcom uefi rtc-info structure * @nvmem_cell: nvmem cell for offset * @offset: offset from epoch in seconds */ @@ -61,13 +70,101 @@ struct pm8xxx_rtc { struct rtc_device *rtc; struct regmap *regmap; bool allow_set_time; + bool use_uefi; int alarm_irq; const struct pm8xxx_rtc_regs *regs; struct device *dev; + struct qcom_uefi_rtc_info rtc_info; struct nvmem_cell *nvmem_cell; u32 offset; }; +#ifdef CONFIG_EFI + +MODULE_IMPORT_NS("EFIVAR"); + +#define QCOM_UEFI_NAME L"RTCInfo" +#define QCOM_UEFI_GUID EFI_GUID(0x882f8c2b, 0x9646, 0x435f, \ + 0x8d, 0xe5, 0xf2, 0x08, 0xff, 0x80, 0xc1, 0xbd) +#define QCOM_UEFI_ATTRS (EFI_VARIABLE_NON_VOLATILE | \ + EFI_VARIABLE_BOOTSERVICE_ACCESS | \ + EFI_VARIABLE_RUNTIME_ACCESS) + +static int pm8xxx_rtc_read_uefi_offset(struct pm8xxx_rtc *rtc_dd) +{ + struct qcom_uefi_rtc_info *rtc_info = &rtc_dd->rtc_info; + unsigned long size = sizeof(*rtc_info); + struct device *dev = rtc_dd->dev; + efi_status_t status; + u32 offset_gps; + int rc; + + rc = efivar_lock(); + if (rc) + return rc; + + status = efivar_get_variable(QCOM_UEFI_NAME, &QCOM_UEFI_GUID, NULL, + &size, rtc_info); + efivar_unlock(); + + if (status != EFI_SUCCESS) { + dev_dbg(dev, "failed to read UEFI offset: %lu\n", status); + return efi_status_to_err(status); + } + + if (size != sizeof(*rtc_info)) { + dev_dbg(dev, "unexpected UEFI structure size %lu\n", size); + return -EINVAL; + } + + dev_dbg(dev, "uefi_rtc_info = %*ph\n", (int)size, rtc_info); + + /* Convert from GPS to Unix time offset */ + offset_gps = le32_to_cpu(rtc_info->offset_gps); + rtc_dd->offset = offset_gps + (u32)RTC_TIMESTAMP_EPOCH_GPS; + + return 0; +} + +static int pm8xxx_rtc_write_uefi_offset(struct pm8xxx_rtc *rtc_dd, u32 offset) +{ + struct qcom_uefi_rtc_info *rtc_info = &rtc_dd->rtc_info; + unsigned long size = sizeof(*rtc_info); + struct device *dev = rtc_dd->dev; + efi_status_t status; + u32 offset_gps; + + /* Convert from Unix to GPS time offset */ + offset_gps = offset - (u32)RTC_TIMESTAMP_EPOCH_GPS; + + rtc_info->offset_gps = cpu_to_le32(offset_gps); + + dev_dbg(dev, "efi_rtc_info = %*ph\n", (int)size, rtc_info); + + status = efivar_set_variable(QCOM_UEFI_NAME, &QCOM_UEFI_GUID, + QCOM_UEFI_ATTRS, size, rtc_info); + if (status != EFI_SUCCESS) { + dev_dbg(dev, "failed to write UEFI offset: %lx\n", status); + return efi_status_to_err(status); + } + + return 0; +} + +#else /* CONFIG_EFI */ + +static int pm8xxx_rtc_read_uefi_offset(struct pm8xxx_rtc *rtc_dd) +{ + return -ENODEV; +} + +static int pm8xxx_rtc_write_uefi_offset(struct pm8xxx_rtc *rtc_dd, u32 offset) +{ + return -ENODEV; +} + +#endif /* CONFIG_EFI */ + static int pm8xxx_rtc_read_nvmem_offset(struct pm8xxx_rtc *rtc_dd) { size_t len; @@ -112,10 +209,13 @@ static int pm8xxx_rtc_write_nvmem_offset(struct pm8xxx_rtc *rtc_dd, u32 offset) static int pm8xxx_rtc_read_offset(struct pm8xxx_rtc *rtc_dd) { - if (!rtc_dd->nvmem_cell) + if (!rtc_dd->nvmem_cell && !rtc_dd->use_uefi) return 0; - return pm8xxx_rtc_read_nvmem_offset(rtc_dd); + if (rtc_dd->nvmem_cell) + return pm8xxx_rtc_read_nvmem_offset(rtc_dd); + else + return pm8xxx_rtc_read_uefi_offset(rtc_dd); } static int pm8xxx_rtc_read_raw(struct pm8xxx_rtc *rtc_dd, u32 *secs) @@ -155,7 +255,7 @@ static int pm8xxx_rtc_update_offset(struct pm8xxx_rtc *rtc_dd, u32 secs) u32 offset; int rc; - if (!rtc_dd->nvmem_cell) + if (!rtc_dd->nvmem_cell && !rtc_dd->use_uefi) return -ENODEV; rc = pm8xxx_rtc_read_raw(rtc_dd, &raw_secs); @@ -167,7 +267,11 @@ static int pm8xxx_rtc_update_offset(struct pm8xxx_rtc *rtc_dd, u32 secs) if (offset == rtc_dd->offset) return 0; - rc = pm8xxx_rtc_write_nvmem_offset(rtc_dd, offset); + if (rtc_dd->nvmem_cell) + rc = pm8xxx_rtc_write_nvmem_offset(rtc_dd, offset); + else + rc = pm8xxx_rtc_write_uefi_offset(rtc_dd, offset); + if (rc) return rc; @@ -486,6 +590,17 @@ static int pm8xxx_rtc_probe(struct platform_device *pdev) if (rc != -ENOENT) return rc; rtc_dd->nvmem_cell = NULL; + + /* Use UEFI storage as fallback if available */ + rtc_dd->use_uefi = of_property_read_bool(pdev->dev.of_node, + "qcom,uefi-rtc-info"); + } + + if (rtc_dd->use_uefi && !efivar_is_available()) { + if (IS_ENABLED(CONFIG_EFI)) + return -EPROBE_DEFER; + dev_warn(&pdev->dev, "efivars not available\n"); + rtc_dd->use_uefi = false; } rtc_dd->regs = match->data; diff --git a/include/linux/rtc.h b/include/linux/rtc.h index 3f4d315aaec9..95da051fb155 100644 --- a/include/linux/rtc.h +++ b/include/linux/rtc.h @@ -170,6 +170,7 @@ struct rtc_device { /* useful timestamps */ #define RTC_TIMESTAMP_BEGIN_0000 -62167219200ULL /* 0000-01-01 00:00:00 */ #define RTC_TIMESTAMP_BEGIN_1900 -2208988800LL /* 1900-01-01 00:00:00 */ +#define RTC_TIMESTAMP_EPOCH_GPS 315964800LL /* 1980-01-06 00:00:00 */ #define RTC_TIMESTAMP_BEGIN_2000 946684800LL /* 2000-01-01 00:00:00 */ #define RTC_TIMESTAMP_END_2063 2966371199LL /* 2063-12-31 23:59:59 */ #define RTC_TIMESTAMP_END_2079 3471292799LL /* 2079-12-31 23:59:59 */ From patchwork Mon Jan 20 14:41:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 13945165 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1BC6B1E3DD8; Mon, 20 Jan 2025 14:42:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737384168; cv=none; b=fUHkh0YXH8ajqX2cbx8ssuOEIRnCZpJxA7xtPI8TP6nYlwHIrz6IFGNSMxU2RV9grRMzItJj+iNzSvh4r0bAh0a6zRRoYbsxq4DrWvh8AoqUp+Y1yD3bDARDvNywEsJvecmRuLnnIR4d5QB8M49WYX1oz6D17CkrQ2kIKo++8ak= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737384168; c=relaxed/simple; bh=NNzYiy5Em2YV65MV6jlNuBC0jkhkjSG/VfToW3QsblU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GYM2m97NEYRTAsqF3mHD9CNVIIV7fEQaWK4frQ7W97Bvu5QUpbFL3R2VrhOIB5dv3oPIzlLcd7OoT5IPo3qZ0ytHmnHKr8LxzfkGZOXuXw7Lsg00fTYWQgZ/4n5T1TPhzzYXYJbUkNK+XT1hGizAalrDbjOLDQWfa3mPU0ENhLw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZoSaS0LZ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZoSaS0LZ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 871EEC4CEE9; Mon, 20 Jan 2025 14:42:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1737384167; bh=NNzYiy5Em2YV65MV6jlNuBC0jkhkjSG/VfToW3QsblU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZoSaS0LZllTIL05t3VJUFBMXRX8P20TpYmVkV0GxMCePT6K5YIbUEB7qR/WwU+n55 twmYG4r0z33QVCQLkBkNsEsk+qyKLPkVBknshSamt2wLGAXfXFr1+32pcQk4RGDym8 T0xT/4ViIA/QACI6kzE4fgSw6Yy8eaC6dZ4GW5AmmwQShtWb/gA81fkvYl/DvlZqp0 tQ8p1FacFFwWCqo0v+HhTseFPfOR6lI80yi51znhGJzUW5vhaAvjaeR/sml5JogYje z5Ll0e2Px4Rh8DrydP/OXZ6+7bRBPUzQOpn2IYNfi+FULUhBLhFVk9BP0giODi4E04 WorlwR68MEXxQ== Received: from johan by xi.lan with local (Exim 4.97.1) (envelope-from ) id 1tZszL-00000000384-2HHk; Mon, 20 Jan 2025 15:42:51 +0100 From: Johan Hovold To: Alexandre Belloni , Bjorn Andersson Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Jonathan Marek , linux-arm-msm@vger.kernel.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH 4/7] rtc: pm8xxx: mitigate flash wear Date: Mon, 20 Jan 2025 15:41:49 +0100 Message-ID: <20250120144152.11949-5-johan+linaro@kernel.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250120144152.11949-1-johan+linaro@kernel.org> References: <20250120144152.11949-1-johan+linaro@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On many Qualcomm platforms the PMIC RTC control and time registers are read-only so that the RTC time can not be updated. Instead an offset needs be stored in some machine-specific non-volatile memory, which the driver can take into account. On machines like the Lenovo ThinkPad X14s the PMIC RTC drifts about one second every 3.5 hours, something which leads to repeated updates of the offset when NTP synchronisation is enabled. Reduce wear of the underlying flash storage (used for UEFI variables) by deferring writes until shutdown in case they appear to be due to clock drift. As an example, allowing the on-flash offset to differ up to 30 s reduces the number of writes on the X13s during a ten day session with the machine not suspending for more than four days in a row from up to 68 writes (every 3.5 h) to at most two (boot and shutdown). Signed-off-by: Johan Hovold --- drivers/rtc/rtc-pm8xxx.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/rtc/rtc-pm8xxx.c b/drivers/rtc/rtc-pm8xxx.c index be1983bf35cd..049daa39c417 100644 --- a/drivers/rtc/rtc-pm8xxx.c +++ b/drivers/rtc/rtc-pm8xxx.c @@ -65,6 +65,7 @@ struct qcom_uefi_rtc_info { * @rtc_info: qcom uefi rtc-info structure * @nvmem_cell: nvmem cell for offset * @offset: offset from epoch in seconds + * @offset_dirty: offset needs to be stored on shutdown */ struct pm8xxx_rtc { struct rtc_device *rtc; @@ -77,6 +78,7 @@ struct pm8xxx_rtc { struct qcom_uefi_rtc_info rtc_info; struct nvmem_cell *nvmem_cell; u32 offset; + bool offset_dirty; }; #ifdef CONFIG_EFI @@ -267,6 +269,15 @@ static int pm8xxx_rtc_update_offset(struct pm8xxx_rtc *rtc_dd, u32 secs) if (offset == rtc_dd->offset) return 0; + /* + * Reduce flash wear by deferring updates due to clock drift until + * shutdown. + */ + if (abs_diff(offset, rtc_dd->offset) < 30) { + rtc_dd->offset_dirty = true; + goto out; + } + if (rtc_dd->nvmem_cell) rc = pm8xxx_rtc_write_nvmem_offset(rtc_dd, offset); else @@ -275,6 +286,8 @@ static int pm8xxx_rtc_update_offset(struct pm8xxx_rtc *rtc_dd, u32 secs) if (rc) return rc; + rtc_dd->offset_dirty = false; +out: rtc_dd->offset = offset; return 0; @@ -650,9 +663,22 @@ static void pm8xxx_remove(struct platform_device *pdev) dev_pm_clear_wake_irq(&pdev->dev); } +static void pm8xxx_shutdown(struct platform_device *pdev) +{ + struct pm8xxx_rtc *rtc_dd = platform_get_drvdata(pdev); + + if (rtc_dd->offset_dirty) { + if (rtc_dd->nvmem_cell) + pm8xxx_rtc_write_nvmem_offset(rtc_dd, rtc_dd->offset); + else + pm8xxx_rtc_write_uefi_offset(rtc_dd, rtc_dd->offset); + } +} + static struct platform_driver pm8xxx_rtc_driver = { .probe = pm8xxx_rtc_probe, .remove = pm8xxx_remove, + .shutdown = pm8xxx_shutdown, .driver = { .name = "rtc-pm8xxx", .of_match_table = pm8xxx_id_table, From patchwork Mon Jan 20 14:41:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 13945164 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1BC111E3DD3; Mon, 20 Jan 2025 14:42:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737384168; cv=none; b=eyfUrriL/WYfSyOkt103BJEMPv1r++ZTubB915yL4pnSTmRe9Nq5PPZagbyjl5QOZ52czlG3ik5j9y5vzun99BSTPkJZP6V3msO4ATTH5+7k96Ccubtb00E7G4Kuk7BEC8C/ZB6PP+GK9vYTQLkzeOSssQ+2vzUNyO4PccJh9vs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737384168; c=relaxed/simple; bh=j7bpGCPILW2v7fURMsfzd1GOrBdY+KXNxn4zV2jA7B4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CBZrpIu2fZ2BUBwGq6v8g3zeVuc2bmj3ZU5x7zAXE4Q0AGwGgaFy6/DIhNEIdJBDquKYFB9Sl+B3dZzHEe8Od56APwH68CBU1Ir18OicJdnk4o54h0XuT0vdBY1MURB9qIOWcIYtco0uUFDvj7wiBtMHnQ84oI65TZco6SW5PzM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tBUFr2tP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tBUFr2tP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9EF67C4CEEB; Mon, 20 Jan 2025 14:42:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1737384167; bh=j7bpGCPILW2v7fURMsfzd1GOrBdY+KXNxn4zV2jA7B4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tBUFr2tPGoR0lJG4rVUzov5i0KhzyUAjxU/2VQ8oiaKbu4juqlSJybdPazHq45aq/ phdr6Cb/n2yImgxaCFNVoQuargPe76isTCw9FrB9fOm7ZHjgE/7bWe2M5VYQiey0lF 6GYqiPb/nVBQ4RGxM3H9ibm1IZelS3mzrBOSmbTdk+MFaEwIp38h69TcfS0dxLAgGO cyeE5V0P/uiwO2DB+fSpB1M+ocn9Q6QUVIb81CJlyemhLbuvua4J0RbXlUc2xYLyNB 0rH3JYj6KBG/2Pi7OpiRqgIWjcWMnJuLJcyP8F0AzMJzP+1jy0dxJ0bvpvL2cMh4w4 vt+sHo9pxBUYA== Received: from johan by xi.lan with local (Exim 4.97.1) (envelope-from ) id 1tZszL-00000000388-2hAb; Mon, 20 Jan 2025 15:42:51 +0100 From: Johan Hovold To: Alexandre Belloni , Bjorn Andersson Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Jonathan Marek , linux-arm-msm@vger.kernel.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH 5/7] rtc: pm8xxx: implement qcom,no-alarm flag for non-HLOS owned alarm Date: Mon, 20 Jan 2025 15:41:50 +0100 Message-ID: <20250120144152.11949-6-johan+linaro@kernel.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250120144152.11949-1-johan+linaro@kernel.org> References: <20250120144152.11949-1-johan+linaro@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Jonathan Marek Qualcomm x1e80100 firmware sets the ownership of the RTC alarm to ADSP. Thus writing to RTC alarm registers and receiving alarm interrupts is not possible. Add a qcom,no-alarm flag to support RTC on this platform. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20241015004945.3676-2-jonathan@marek.ca [ johan: drop no_alarm flag and restructure probe() ] Signed-off-by: Johan Hovold --- drivers/rtc/rtc-pm8xxx.c | 43 ++++++++++++++++++++++------------------ 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/drivers/rtc/rtc-pm8xxx.c b/drivers/rtc/rtc-pm8xxx.c index 049daa39c417..f9755fb9eaa5 100644 --- a/drivers/rtc/rtc-pm8xxx.c +++ b/drivers/rtc/rtc-pm8xxx.c @@ -590,9 +590,11 @@ static int pm8xxx_rtc_probe(struct platform_device *pdev) if (!rtc_dd->regmap) return -ENXIO; - rtc_dd->alarm_irq = platform_get_irq(pdev, 0); - if (rtc_dd->alarm_irq < 0) - return -ENXIO; + if (!of_property_read_bool(pdev->dev.of_node, "qcom,no-alarm")) { + rtc_dd->alarm_irq = platform_get_irq(pdev, 0); + if (rtc_dd->alarm_irq < 0) + return -ENXIO; + } rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node, "allow-set-time"); @@ -631,8 +633,6 @@ static int pm8xxx_rtc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, rtc_dd); - device_init_wakeup(&pdev->dev, 1); - rtc_dd->rtc = devm_rtc_allocate_device(&pdev->dev); if (IS_ERR(rtc_dd->rtc)) return PTR_ERR(rtc_dd->rtc); @@ -640,27 +640,32 @@ static int pm8xxx_rtc_probe(struct platform_device *pdev) rtc_dd->rtc->ops = &pm8xxx_rtc_ops; rtc_dd->rtc->range_max = U32_MAX; - rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->alarm_irq, - pm8xxx_alarm_trigger, - IRQF_TRIGGER_RISING, - "pm8xxx_rtc_alarm", rtc_dd); - if (rc < 0) - return rc; + if (rtc_dd->alarm_irq) { + rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->alarm_irq, + pm8xxx_alarm_trigger, + IRQF_TRIGGER_RISING, + "pm8xxx_rtc_alarm", rtc_dd); + if (rc < 0) + return rc; - rc = devm_rtc_register_device(rtc_dd->rtc); - if (rc) - return rc; + rc = dev_pm_set_wake_irq(&pdev->dev, rtc_dd->alarm_irq); + if (rc) + return rc; - rc = dev_pm_set_wake_irq(&pdev->dev, rtc_dd->alarm_irq); - if (rc) - return rc; + device_init_wakeup(&pdev->dev, 1); + } else { + clear_bit(RTC_FEATURE_ALARM, rtc_dd->rtc->features); + } - return 0; + return devm_rtc_register_device(rtc_dd->rtc); } static void pm8xxx_remove(struct platform_device *pdev) { - dev_pm_clear_wake_irq(&pdev->dev); + struct pm8xxx_rtc *rtc_dd = platform_get_drvdata(pdev); + + if (rtc_dd->alarm_irq) + dev_pm_clear_wake_irq(&pdev->dev); } static void pm8xxx_shutdown(struct platform_device *pdev) From patchwork Mon Jan 20 14:41:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 13945169 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 881651E47CD; Mon, 20 Jan 2025 14:42:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737384168; cv=none; b=EFymcAqWMO/wnTNGUBxQf88RVyM831sl43uRmhoMbhhosqDYEOIqO3+q2UhtDHYGY4Qp78BOqqpNAw09NfwdmjkZ7RSxrnutAoWg35U8ato7mdsNJX2d4bW+5eaeaKWHlvnKN5Ol3VZZorU+51j0JrYYM9Ww+Z3B3epGHiui87c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737384168; c=relaxed/simple; bh=2xVFRHUWfE9PJ70s7RfpZCcofH/jA5B1CaqMtdHej8A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=e38n3fbnr9HcOXJf7du914TXp+BCN8Y3YP8Q1oiUNsghdrcBRQNR8n0027aApNOARjNCHoGPOM65V9dtPb8eg84psugbSzOOBtbJNBzqxNcg7n8ZyEe7NWlVg+ivUIagdeo1VxyVSvQA+VYfA/pBVSQMwiEzMiZbEO0NSoH8nG4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ivIfR5eb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ivIfR5eb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E46C6C19421; Mon, 20 Jan 2025 14:42:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1737384168; bh=2xVFRHUWfE9PJ70s7RfpZCcofH/jA5B1CaqMtdHej8A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ivIfR5ebGw3Nn0sH/Wh9cNZUnDFmXhBR/172Q/KZvHWsBlRxR7BTbQIarE4Id+eWn 3j9SrXbMT1b1nOsD9rZ/OK4HvhpcjYghlespXddADB/kzxWpa4MCPRkPdKGoUND4CZ qquwFQshBgnsNFE3r05OVWoUTpBg5ICL87zlFNOXXSlG5f71OXrIBLNdHfHD8GvK9r y9k1K3YiTh+JFR9yGucO+BsmelY03DoHiBNzU1frDYWKrxQbLLXlc1ifHFDeYXxEBf T0eKMXFPExDYp0tOvcOO1RDLiBlrLHaI+eJc0957dq/7mrXqUGiAI6N93fAE1B2Yr6 8K5aIlkOy6NqQ== Received: from johan by xi.lan with local (Exim 4.97.1) (envelope-from ) id 1tZszL-0000000038B-31RF; Mon, 20 Jan 2025 15:42:51 +0100 From: Johan Hovold To: Alexandre Belloni , Bjorn Andersson Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Jonathan Marek , linux-arm-msm@vger.kernel.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH 6/7] arm64: dts: qcom: sc8280xp-x13s: switch to uefi rtc offset Date: Mon, 20 Jan 2025 15:41:51 +0100 Message-ID: <20250120144152.11949-7-johan+linaro@kernel.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250120144152.11949-1-johan+linaro@kernel.org> References: <20250120144152.11949-1-johan+linaro@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On many Qualcomm platforms the PMIC RTC control and time registers are read-only so that the RTC time can not be updated. Instead an offset needs be stored in some machine-specific non-volatile memory, which a driver can take into account. Switch to using the Qualcomm specific UEFI variable that is used by the UEFI firmware (and Windows) to store the RTC offset. This specifically means that the RTC time will be synchronised between the UEFI firmware setup (or UEFI shell), Windows and Linux. Note however that Windows stores the RTC time in local time by default, while Linux typically uses UTC (i.e. as on X86). Signed-off-by: Johan Hovold Tested-by: Jens Glathe --- .../boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 38d911992475..66c39765225f 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -1090,20 +1090,11 @@ &pmk8280_pon_resin { }; &pmk8280_rtc { - nvmem-cells = <&rtc_offset>; - nvmem-cell-names = "offset"; + qcom,uefi-rtc-info; status = "okay"; }; -&pmk8280_sdam_6 { - status = "okay"; - - rtc_offset: rtc-offset@bc { - reg = <0xbc 0x4>; - }; -}; - &pmk8280_vadc { channel@144 { reg = ; From patchwork Mon Jan 20 14:41:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 13945167 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C1591E47A6; Mon, 20 Jan 2025 14:42:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737384168; cv=none; b=iKMEL8uQWGvOajzOl2c7AFYMkOUOmoxgvV2PzbHrZEY+2YuEJ6VHkRGU11HkPgjR1/mYfqur+a9SP+sd8PEyW+NUaaW+tes/QWnoYN+yrkpZ2BFT15nz4FlnPUI1MhrXu62nfHQnmhAnYA45Dw509aoqxM1I5foJVJ/AeyDkT4w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737384168; c=relaxed/simple; bh=KMK58D4C+h2UQiZzzkAGki7tuZnIjmfF8XJycNxg1+g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pIMVVVa1Xin+u+gjCmC9H+cJTPh56RukOXkW+vUpz2MTVdVmq9nW18WgGM8kh7A0ufNZUx+/3w6zp54N3Vms27D3kZcTIx+O4ryHf+uKxH2kSxPAmk0j9kxcjJjPn9NIFlydJGz1xKLgiOUIlIw+lhxmhwlCS1ABUVVsGwdlNVs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FtpLca7+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FtpLca7+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C7781C4AF09; Mon, 20 Jan 2025 14:42:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1737384167; bh=KMK58D4C+h2UQiZzzkAGki7tuZnIjmfF8XJycNxg1+g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FtpLca7+LJoU794TWx594cU3FiFgOVcZykF1TQizqJb4PM59yhkKZmfA2Ms9xDhwq Ro9kV30cAv4teX8aUDNGKHIPC+KnTmiRTTif4FcfdrtplEaj7cO9AmsXHeabhqQUTL /nf9ONJ2Z6M5NEmCAzl7X8Xb019V2zhPgTv5VNAI1SN2XkZONJfspyBaDc5E2yvCsl 5IRb+Fe0zLTMgtU+CpznROuVd95XZw0X3H0ahkefDQJp6eGhCiVvmd4eZAc9/lPdu6 Ul1R3sBZSNl4ACUMw7WAHtC7rWLu8MGeL8jesFu5O7B6mKwiRKPuW13R0TPQoOUpQI 1xRsXFvuVE5wA== Received: from johan by xi.lan with local (Exim 4.97.1) (envelope-from ) id 1tZszL-0000000038E-3MEn; Mon, 20 Jan 2025 15:42:51 +0100 From: Johan Hovold To: Alexandre Belloni , Bjorn Andersson Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Jonathan Marek , linux-arm-msm@vger.kernel.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH 7/7] arm64: dts: qcom: x1e80100: enable rtc Date: Mon, 20 Jan 2025 15:41:52 +0100 Message-ID: <20250120144152.11949-8-johan+linaro@kernel.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250120144152.11949-1-johan+linaro@kernel.org> References: <20250120144152.11949-1-johan+linaro@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On many Qualcomm platforms the PMIC RTC control and time registers are read-only so that the RTC time can not be updated. Instead an offset needs be stored in some machine-specific non-volatile memory, which a driver can take into account. On X1E based Windows on Arm machines the offset is stored in a Qualcomm specific UEFI variable. Unlike on previous platforms the alarm registers are also unaccessible on X1E as they are owned by the ADSP. Assume all X1E machines use similar firmware and enable the RTC in the PMIC dtsi for now. Based on a patch by Jonathan Marek. [1] Link: https://lore.kernel.org/r/20241015004945.3676-4-jonathan@marek.ca # [1] Signed-off-by: Johan Hovold Tested-by: Jens Glathe --- arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi index 5b54ee79f048..051fb3a304b9 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi @@ -223,8 +223,8 @@ pmk8550_rtc: rtc@6100 { reg = <0x6100>, <0x6200>; reg-names = "rtc", "alarm"; interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; - /* Not yet sure what blocks access */ - status = "reserved"; + qcom,no-alarm; /* alarm owned by ADSP */ + qcom,uefi-rtc-info; }; pmk8550_sdam_2: nvram@7100 {