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Mon, 20 Jan 2025 17:21:19 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC v3 01/18] dt-bindings: clock: Add VO subsystem clock controller support Date: Mon, 20 Jan 2025 18:20:54 +0100 Message-Id: <20250120172111.3492708-2-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250120172111.3492708-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Se0xTVxzHPffe3luaAZcK8wyIGxi2TDcee5iDPBRQc6bLdFucxmSRZtwU AxTTwjZEI6U8BNuKzsks8pwbb5nYMkpEtEMKc7KBAm6TR3hM6EDW8vBBhFFu3fzv+/39Puf3 /f2SIyTFP9KewoOyJE4uk8T70iKqoe3xr2+6ZWmlgeldPqi9r4xAhgUdg2qaOwlU3NopQAPd egLdmZum0cWx3xg03qykUG9FIYNUbXU0mtAN0MiqHhCg203naTSjaQWoYSaDRrWt/Qyqmysm UKnVQKELjU0AZeV8L0BdP29D/QPtFJq4rSZRls4VLV1pZNBi7yUKFTxoYZB+8pQAmWv3ooyW M9SWtXj6biaDJycmKPzT8VkGN8+XUNio62ew2vgLwPVVOTS+13uFxkUdH+LBE2YCX75wDGfU thH45NNAPH21h8ZafRXA3ao+Zrd4vyg0hos/+DknDwiPFsWmX1sSHPrT88uzTUoqDUx45AIn IWTfgbPt1UQuEAnFbAWAuSNDDG9mAVyYt5C8mQEw/1oN+ezJZc1XDqocQMviqIOaBPC+qhbY KZp9Cw6VFwvsDXc2k4KZN5TAbkj2PoANo+dpO7Wa3QtVep3ArinWDxYZtCsZzuxmaCu4SPN5 L8OW67dW6k7sFviwp5nhGTfYcW6UsmtymVEZClbWgGytCPYMnl5OEy6brXBsgePnrIYWs57h tTdcMhYTvE6EQwab47Yj0Kg2O3QIvNf5hLaPIdnXYV1TAF+OgHkFJ0h+ugu8O+XGb+ACTzfk O8rO8HiWmKdfhV+rNf+FdlY0OEIx7Bm3CvKAj+65W3TP3aL7P7cEkFVgDZesSJByiiAZ94W/ QpKgSJZJ/T9LTKgHy3/75qLZ1ggKLVZ/EyCEwASgkPR1d/b4Ry0VO8dIUg5z8sQD8uR4TmEC XkLKd41zWUumVMxKJUlcHMcd4uTPuoTQyTONiNDu6I7fr4k+ctPkmhyZ7yRLtb7XY0mX7IsO uxFRoA8c/iSo73qUdtuqt7GqZL3n7x7q0sPFhHflcH/lGwEfnfu4e7tryUmqMa7GFiwY0Wb7 T8nLBoerh27tyPGKjokMAqVDm+asm89Wz35XlDobbvp2o6G7nH08hfFwMJfw4saQv/dcrdke ht/dM5aEo0oGXzhKhISvioh7/+krD0/didzwaZRE+USp7bhUH/Gaqhzk+Xzj/0f0Mc1fZZbK Kp/QFP2uR8px77Cu1E3e5l1+Z0J3j7jtLJeYhNnZ7ujR1g3V+35waUvJMa71wg+8ucLsIL91 L/WlMbbg2MkD8wMfjPkc1fhSilhJ0HpSrpD8C9igPU9KBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKKsWRmVeSWpSXmKPExsVy+t/xu7oCbX3pBqfWSVmcuL6IyWLr71ns Fmv2nmOymH/kHKvFvUtbmCyufH3PZrHu6QV2ixd7G1ksrq2Yy27RfGw9m8XLWffYLD723GO1 uLxrDpvF594jjBbbPrewWaw9cpfdYv3X+UwWCz9uZbFYsmMXo0Vb5zJWi4unXC3u3jvBYvHy cg+zRdssfov/e3awW/y7tpHFYva7/ewWW95MZLU4vjbcomX/FBYHOY/3N1rZPd68fMnicbjj C7vH3m8LWDx2zrrL7tGz8wyjx6ZVnWwed67tYfOYdzLQ4373cSaPzUvqPVrWHmPy6P9r4PF+ 31U2j74tqxg9LjVfZw8QitKzKcovLUlVyMgvLrFVija0MNIztLTQMzKx1DM0No+1MjJV0rez SUnNySxLLdK3S9DLaDrwn7XgtlTFtF2NLA2ML0W7GDk5JARMJDb3TmYHsYUEljJKXPodCRGX kbjW/ZIFwhaW+HOti62LkQuo5hWjxJMNv1lBEmwCRhIPls8Hs0UEFrNI7N1XCVLELPCWUeL6 zI1g3cICoRKzH/1mBLFZBFQl5m3tYwaxeQXsJT7NXscGsUFeYv/Bs2BxTgEHie9X90JdZC9x 52o3I0S9oMTJmU/AZjID1Tdvnc08gVFgFpLULCSpBYxMqxhFUkuLc9Nzi430ihNzi0vz0vWS 83M3MQLTy7ZjP7fsYFz56qPeIUYmDsZDjBIczEoivKIfetKFeFMSK6tSi/Lji0pzUosPMZoC 3T2RWUo0OR+Y4PJK4g3NDEwNTcwsDUwtzYyVxHnZrpxPExJITyxJzU5NLUgtgulj4uCUamDq T5PyE2abqnhyr+qBi2a/eU7dvbZsiRSrf/wma7HvHMWnBc0rdfI6z71XkbG/let12d2Rbd3p LOEy+8l1y6/Vx1xZL6/D1tjxhuHrCzmjp5d4Q1SWN/LFfbvZ9HhDp/XFF1LV6wUfbdN7P33x DpvF5/QPf150eAVT0frG010i7TwnN3hMXN7T6vTnm8fy5VqP9M+fPMG46ER9xDLP3UVnDlc5 b1HZ5fJSKezIPwFfdvfSo5GGcqtF+tJFlm+vePuu/NVO1vAz9mdPrZipwba5bt3C95MKpDYf rY2MNWY2X2d+SjQr/Gm78g0W1q/v2s0/F4nETgj4L/91U9ceLuk/zysLfxvz67+WfLWtIPG4 EktxRqKhFnNRcSIAg8FS+7gDAAA= X-CMS-MailID: 20250120172120eucas1p23993cdbbe65e82054b9cb92fb704103b X-Msg-Generator: CA X-RootMTR: 20250120172120eucas1p23993cdbbe65e82054b9cb92fb704103b X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250120172120eucas1p23993cdbbe65e82054b9cb92fb704103b References: <20250120172111.3492708-1-m.wilczynski@samsung.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a separate compatible string "thead,th1520-clk-vo" to describe the Video Output (VO) subsystem clock controller in the T-Head TH1520 SoC. The VO subsystem configures the clock gates for HDMI, MIPI, and GPU components. Meanwhile, the existing AP sub-system clock controller remains responsible for the CPU, DPU, GMAC, and TEE PLLs. Signed-off-by: Michal Wilczynski --- .../bindings/clock/thead,th1520-clk-ap.yaml | 16 +++++++-- .../dt-bindings/clock/thead,th1520-clk-ap.h | 33 +++++++++++++++++++ 2 files changed, 46 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml index 0129bd0ba4b3..e9ee8152ed5a 100644 --- a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml +++ b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml @@ -8,7 +8,8 @@ title: T-HEAD TH1520 AP sub-system clock controller description: | The T-HEAD TH1520 AP sub-system clock controller configures the - CPU, DPU, GMAC and TEE PLLs. + CPU, DPU, GMAC and TEE PLLs. Additionally the VO subsystem configures + the clock gates for the HDMI, MIPI and the GPU. SoC reference manual https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf @@ -20,14 +21,16 @@ maintainers: properties: compatible: - const: thead,th1520-clk-ap + enum: + - thead,th1520-clk-ap + - thead,th1520-clk-vo reg: maxItems: 1 clocks: items: - - description: main oscillator (24MHz) + - description: main oscillator (24MHz) or CLK_VIDEO_PLL "#clock-cells": const: 1 @@ -51,3 +54,10 @@ examples: clocks = <&osc>; #clock-cells = <1>; }; + + clock-controller@ff010000 { + compatible = "thead,th1520-clk-vo"; + reg = <0xff010000 0x1000>; + clocks = <&clk CLK_VIDEO_PLL>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-bindings/clock/thead,th1520-clk-ap.h index a199784b3512..470fa34f9a9d 100644 --- a/include/dt-bindings/clock/thead,th1520-clk-ap.h +++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h @@ -93,4 +93,37 @@ #define CLK_SRAM3 83 #define CLK_PLL_GMAC_100M 84 #define CLK_UART_SCLK 85 + +/* VO clocks */ +#define CLK_AXI4_VO_ACLK 0 +#define CLK_GPU_CORE 1 +#define CLK_GPU_CFG_ACLK 2 +#define CLK_DPU_PIXELCLK0 3 +#define CLK_DPU_PIXELCLK1 4 +#define CLK_DPU_HCLK 5 +#define CLK_DPU_ACLK 6 +#define CLK_DPU_CCLK 7 +#define CLK_HDMI_SFR 8 +#define CLK_HDMI_PCLK 9 +#define CLK_HDMI_CEC 10 +#define CLK_MIPI_DSI0_PCLK 11 +#define CLK_MIPI_DSI1_PCLK 12 +#define CLK_MIPI_DSI0_CFG 13 +#define CLK_MIPI_DSI1_CFG 14 +#define CLK_MIPI_DSI0_REFCLK 15 +#define CLK_MIPI_DSI1_REFCLK 16 +#define CLK_HDMI_I2S 17 +#define CLK_X2H_DPU1_ACLK 18 +#define CLK_X2H_DPU_ACLK 19 +#define CLK_AXI4_VO_PCLK 20 +#define CLK_IOPMP_VOSYS_DPU_PCLK 21 +#define CLK_IOPMP_VOSYS_DPU1_PCLK 22 +#define CLK_IOPMP_VOSYS_GPU_PCLK 23 +#define CLK_IOPMP_DPU1_ACLK 24 +#define CLK_IOPMP_DPU_ACLK 25 +#define CLK_IOPMP_GPU_ACLK 26 +#define CLK_MIPIDSI0_PIXCLK 27 +#define CLK_MIPIDSI1_PIXCLK 28 +#define CLK_HDMI_PIXCLK 29 + #endif From patchwork Mon Jan 20 17:20:55 2025 Content-Type: text/plain; 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Mon, 20 Jan 2025 17:21:20 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC v3 02/18] clk: thead: Add clock support for VO subsystem in T-Head TH1520 SoC Date: Mon, 20 Jan 2025 18:20:55 +0100 Message-Id: <20250120172111.3492708-3-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250120172111.3492708-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02SfUxTZxTG9957ubd0K16rzlcxU2Ho2CY69vVmGIUE8ZLFTKcBpyGjmXfV 8VHSCkxnIlDAwkpFgqEUXFnnoOsEIpaOEigBocgmZQMtHQJlG4goUFlBp4gMuHXzv+ec8zt5 npMcHi78iVzLO5Z4nJUmiuL9SD5hsj7q2iLMVom3pU28ia716jBUO6uh0KVGG4a0rTYvNNht xNCNGReJqkZ+pdCdxnQC2fUXKCS3VpNoTDNIoinloBfqqS8lkTuvFSCTO5NEla0DFKqe0WLo 26laAl2sqwcoO6fcC/328y40MHiNQGM9Shxla5ah+YY6Cj21XyZQyWQThYzj57xQe2U0ymwq JEJfYVyOLIoZHxsjmKuKaYppfFBGMGbNAMUozdcBU2PIIZl+ewPJfNOxj3F+3Y4xVy6eZjIr rRhzdm4b47LcJBmV0QCYbnkvtVd4iL/9CBt/LIWVbt0Ryz96x+oikyYPfml0x6WBGx/mAm8e pN+Bs09+98oFfJ6Q1gNYobQQXDENYIemxDNxA+h4YiOerRj+0HmoCgBnzvwIuGIcwEvDKmqR IulgOFShXVpfSWcRMKstfYnC6VEATcOl5CK1go6BDkU+tqgJOgAqXFNLWkDvhGr7NMn5rYdN zZ34ovamQ+HDm40UxyyHHcXDS5nwBUZeW4IvGkD6Mh8qp8o8YcPho+46nNMr4N12I8XpdXDe rMU4LYFDtX97mFPQrGz36BDYb3u8EIK3YBAIq+u3cu0wWK8rX2pD2gc6JpZzEXxggakI59oC qMgWcvQmeF6Z95+pTW/ymDJwqLmAygcbNc8do3nuGM3/vmUAN4DVbLIsQczKghPZ1CCZKEGW nCgO+kySUAMWfvuXp+3TdaDi7lRQC8B4oAVAHu63UrDqvlIsFBwRnTjJSiWfSpPjWVkL8OUR fqsFuqYssZAWi46zcSybxEqfTTGe99o0LKUgcLRw3/0Q1Rhdqr3151cF1z8XzF6hseHAIf2E OPzVA3OpIf6TFZb1u0whUWczonTLLHOa04df2HTy9oXW/fwkp70vYre/ImDD+fE18pbcqJqR Il9N35n8vW2usJg4Jf/ew/nu1x7Iv2+Rhr03Itng/0XgrOT2YcGe/qLyx8aq8KGNn0jf3Zwq UIZa1NYPfF2dEboqtcIa2xwZZbWvyzxQqt7hEJPb85x5RHF02wm3eY0zwyYOSykWHtr5g/mj GFNGTYQ6MSc1+P0+n6vzL62yfCdTVd/6Z1RyLnnPy9Hpb0cWzntLNt+resP58eSpzi2Gg381 +AcYYnu6evdHarte1Gf4EbKjordex6Uy0b9ElNYcSgQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrCKsWRmVeSWpSXmKPExsVy+t/xu7qCbX3pBh3n9C1OXF/EZLH19yx2 izV7zzFZzD9yjtXi3qUtTBZXvr5ns1j39AK7xYu9jSwW11bMZbdoPraezeLlrHtsFh977rFa XN41h83ic+8RRottn1vYLNYeuctusf7rfCaLhR+3slgs2bGL0aKtcxmrxcVTrhZ3751gsXh5 uYfZom0Wv8X/PTvYLf5d28hiMfvdfnaLLW8mslocXxtu0bJ/CouDnMf7G63sHm9evmTxONzx hd1j77cFLB47Z91l9+jZeYbRY9OqTjaPO9f2sHnMOxnocb/7OJPH5iX1Hi1rjzF59P818Hi/ 7yqbR9+WVYwel5qvswcIRenZFOWXlqQqZOQXl9gqRRtaGOkZWlroGZlY6hkam8daGZkq6dvZ pKTmZJalFunbJehlvDj2nq3gXUTFls/ZDYxXvLsYOTkkBEwkVj1cxNLFyMUhJLCUUeLJuenM EAkZiWvdL1kgbGGJP9e62CCKXjFKrP93GSzBJmAk8WD5fFYQW0RgMYvE3n2VIEXMAm8ZJa7P 3AhUxMEhLBAt0bZUDaSGRUBVouP9RyYQm1fAXmLGtS9sEAvkJfYfPAu2mFPAQeL71b3sILYQ UM2dq92MEPWCEidnPgHbywxU37x1NvMERoFZSFKzkKQWMDKtYhRJLS3OTc8tNtIrTswtLs1L 10vOz93ECEwu24793LKDceWrj3qHGJk4GA8xSnAwK4nwin7oSRfiTUmsrEotyo8vKs1JLT7E aAp090RmKdHkfGB6yyuJNzQzMDU0MbM0MLU0M1YS52W7cj5NSCA9sSQ1OzW1ILUIpo+Jg1Oq gcl0u/dq9q9S29hYVKaxlWSVhsfN23Wo4ffq+j8fV4crsheos1VyZb04tunPzOv7Lhuwvao8 0fvpAJNq3L6ZITf5lu+oe3/tvdiuSaeWu951vcD7e++UkMsWGze+j5v1U8Uu/PnPjucbPkY5 bmBY33Xbg1M4j3Pv1ONv1Dw3yk68LfF6q05He3uYqcKChruzmXWMMsqvl3+wjihZE1VkG3dn wTLzudmMenpSa5M8V1iYmK37wzfJa/nRe37W2yYKOgadqLjY9ba/4g+72OUVq9IPuTMWnk/S +VbrzpxuGp82IWfdJmvf4DLrlCl9cnckvCTq5qc3m+mZXTZhX3P7wTfrB3JBa1dvnfbxRG3T vOdKLMUZiYZazEXFiQDbGQmgtwMAAA== X-CMS-MailID: 20250120172121eucas1p24ed47f684da5f1dcf0df7735e21f2b4c X-Msg-Generator: CA X-RootMTR: 20250120172121eucas1p24ed47f684da5f1dcf0df7735e21f2b4c X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250120172121eucas1p24ed47f684da5f1dcf0df7735e21f2b4c References: <20250120172111.3492708-1-m.wilczynski@samsung.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The T-Head TH1520 SoC integrates a variety of clocks for its subsystems, including the Application Processor (AP) and the Video Output (VO) [1]. Up until now, the T-Head clock driver only supported AP clocks. This commit extends the driver to provide clock functionality for the VO subsystem. At this stage, the focus is on implementing the VO clock gates, as these are currently the most relevant and required components for enabling and disabling the VO subsystem functionality. Future enhancements may introduce additional VO-related clocks as necessary. Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf [1] Signed-off-by: Michal Wilczynski --- drivers/clk/thead/clk-th1520-ap.c | 197 +++++++++++++++++++++++++----- 1 file changed, 169 insertions(+), 28 deletions(-) diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c index 1015fab95251..2897b732624b 100644 --- a/drivers/clk/thead/clk-th1520-ap.c +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -847,6 +847,67 @@ static CCU_GATE(CLK_SRAM1, sram1_clk, "sram1", axi_aclk_pd, 0x20c, BIT(3), 0); static CCU_GATE(CLK_SRAM2, sram2_clk, "sram2", axi_aclk_pd, 0x20c, BIT(2), 0); static CCU_GATE(CLK_SRAM3, sram3_clk, "sram3", axi_aclk_pd, 0x20c, BIT(1), 0); +static CCU_GATE(CLK_AXI4_VO_ACLK, axi4_vo_aclk, "axi4-vo-aclk", + video_pll_clk_pd, 0x0, BIT(0), 0); +static CCU_GATE(CLK_GPU_CORE, gpu_core_clk, "gpu-core-clk", video_pll_clk_pd, + 0x0, BIT(3), 0); +static CCU_GATE(CLK_GPU_CFG_ACLK, gpu_cfg_aclk, "gpu-cfg-aclk", + video_pll_clk_pd, 0x0, BIT(4), 0); +static CCU_GATE(CLK_DPU_PIXELCLK0, dpu0_pixelclk, "dpu0-pixelclk", + video_pll_clk_pd, 0x0, BIT(5), 0); +static CCU_GATE(CLK_DPU_PIXELCLK1, dpu1_pixelclk, "dpu1-pixelclk", + video_pll_clk_pd, 0x0, BIT(6), 0); +static CCU_GATE(CLK_DPU_HCLK, dpu_hclk, "dpu-hclk", video_pll_clk_pd, 0x0, + BIT(7), 0); +static CCU_GATE(CLK_DPU_ACLK, dpu_aclk, "dpu-aclk", video_pll_clk_pd, 0x0, + BIT(8), 0); +static CCU_GATE(CLK_DPU_CCLK, dpu_cclk, "dpu-cclk", video_pll_clk_pd, 0x0, + BIT(9), 0); +static CCU_GATE(CLK_HDMI_SFR, hdmi_sfr_clk, "hdmi-sfr-clk", video_pll_clk_pd, + 0x0, BIT(10), 0); +static CCU_GATE(CLK_HDMI_PCLK, hdmi_pclk, "hdmi-pclk", video_pll_clk_pd, 0x0, + BIT(11), 0); +static CCU_GATE(CLK_HDMI_CEC, hdmi_cec_clk, "hdmi-cec-clk", video_pll_clk_pd, + 0x0, BIT(12), 0); +static CCU_GATE(CLK_MIPI_DSI0_PCLK, mipi_dsi0_pclk, "mipi-dsi0-pclk", + video_pll_clk_pd, 0x0, BIT(13), 0); +static CCU_GATE(CLK_MIPI_DSI1_PCLK, mipi_dsi1_pclk, "mipi-dsi1-pclk", + video_pll_clk_pd, 0x0, BIT(14), 0); +static CCU_GATE(CLK_MIPI_DSI0_CFG, mipi_dsi0_cfg_clk, "mipi-dsi0-cfg-clk", + video_pll_clk_pd, 0x0, BIT(15), 0); +static CCU_GATE(CLK_MIPI_DSI1_CFG, mipi_dsi1_cfg_clk, "mipi-dsi1-cfg-clk", + video_pll_clk_pd, 0x0, BIT(16), 0); +static CCU_GATE(CLK_MIPI_DSI0_REFCLK, mipi_dsi0_refclk, "mipi-dsi0-refclk", + video_pll_clk_pd, 0x0, BIT(17), 0); +static CCU_GATE(CLK_MIPI_DSI1_REFCLK, mipi_dsi1_refclk, "mipi-dsi1-refclk", + video_pll_clk_pd, 0x0, BIT(18), 0); +static CCU_GATE(CLK_HDMI_I2S, hdmi_i2s_clk, "hdmi-i2s-clk", video_pll_clk_pd, + 0x0, BIT(19), 0); +static CCU_GATE(CLK_X2H_DPU1_ACLK, x2h_dpu1_aclk, "x2h-dpu1-aclk", + video_pll_clk_pd, 0x0, BIT(20), 0); +static CCU_GATE(CLK_X2H_DPU_ACLK, x2h_dpu_aclk, "x2h-dpu-aclk", + video_pll_clk_pd, 0x0, BIT(21), 0); +static CCU_GATE(CLK_AXI4_VO_PCLK, axi4_vo_pclk, "axi4-vo-pclk", + video_pll_clk_pd, 0x0, BIT(22), 0); +static CCU_GATE(CLK_IOPMP_VOSYS_DPU_PCLK, iopmp_vosys_dpu_pclk, + "iopmp-vosys-dpu-pclk", video_pll_clk_pd, 0x0, BIT(23), 0); +static CCU_GATE(CLK_IOPMP_VOSYS_DPU1_PCLK, iopmp_vosys_dpu1_pclk, + "iopmp-vosys-dpu1-pclk", video_pll_clk_pd, 0x0, BIT(24), 0); +static CCU_GATE(CLK_IOPMP_VOSYS_GPU_PCLK, iopmp_vosys_gpu_pclk, + "iopmp-vosys-gpu-pclk", video_pll_clk_pd, 0x0, BIT(25), 0); +static CCU_GATE(CLK_IOPMP_DPU1_ACLK, iopmp_dpu1_aclk, "iopmp-dpu1-aclk", + video_pll_clk_pd, 0x0, BIT(27), 0); +static CCU_GATE(CLK_IOPMP_DPU_ACLK, iopmp_dpu_aclk, "iopmp-dpu-aclk", + video_pll_clk_pd, 0x0, BIT(28), 0); +static CCU_GATE(CLK_IOPMP_GPU_ACLK, iopmp_gpu_aclk, "iopmp-gpu-aclk", + video_pll_clk_pd, 0x0, BIT(29), 0); +static CCU_GATE(CLK_MIPIDSI0_PIXCLK, mipi_dsi0_pixclk, "mipi-dsi0-pixclk", + video_pll_clk_pd, 0x0, BIT(30), 0); +static CCU_GATE(CLK_MIPIDSI1_PIXCLK, mipi_dsi1_pixclk, "mipi-dsi1-pixclk", + video_pll_clk_pd, 0x0, BIT(31), 0); +static CCU_GATE(CLK_HDMI_PIXCLK, hdmi_pixclk, "hdmi-pixclk", video_pll_clk_pd, + 0x4, BIT(0), 0); + static CLK_FIXED_FACTOR_HW(gmac_pll_clk_100m, "gmac-pll-clk-100m", &gmac_pll_clk.common.hw, 10, 1, 0); @@ -963,7 +1024,38 @@ static struct ccu_common *th1520_gate_clks[] = { &sram3_clk.common, }; -#define NR_CLKS (CLK_UART_SCLK + 1) +static struct ccu_common *th1520_vo_gate_clks[] = { + &axi4_vo_aclk.common, + &gpu_core_clk.common, + &gpu_cfg_aclk.common, + &dpu0_pixelclk.common, + &dpu1_pixelclk.common, + &dpu_hclk.common, + &dpu_aclk.common, + &dpu_cclk.common, + &hdmi_sfr_clk.common, + &hdmi_pclk.common, + &hdmi_cec_clk.common, + &mipi_dsi0_pclk.common, + &mipi_dsi1_pclk.common, + &mipi_dsi0_cfg_clk.common, + &mipi_dsi1_cfg_clk.common, + &mipi_dsi0_refclk.common, + &mipi_dsi1_refclk.common, + &hdmi_i2s_clk.common, + &x2h_dpu1_aclk.common, + &x2h_dpu_aclk.common, + &axi4_vo_pclk.common, + &iopmp_vosys_dpu_pclk.common, + &iopmp_vosys_dpu1_pclk.common, + &iopmp_vosys_gpu_pclk.common, + &iopmp_dpu1_aclk.common, + &iopmp_dpu_aclk.common, + &iopmp_gpu_aclk.common, + &mipi_dsi0_pixclk.common, + &mipi_dsi1_pixclk.common, + &hdmi_pixclk.common +}; static const struct regmap_config th1520_clk_regmap_config = { .reg_bits = 32, @@ -972,8 +1064,44 @@ static const struct regmap_config th1520_clk_regmap_config = { .fast_io = true, }; +struct th1520_plat_data { + struct ccu_common **th1520_pll_clks; + struct ccu_common **th1520_div_clks; + struct ccu_common **th1520_mux_clks; + struct ccu_common **th1520_gate_clks; + + int nr_clks; + int nr_pll_clks; + int nr_div_clks; + int nr_mux_clks; + int nr_gate_clks; +}; + +static const struct th1520_plat_data th1520_ap_platdata = { + .th1520_pll_clks = th1520_pll_clks, + .th1520_div_clks = th1520_div_clks, + .th1520_mux_clks = th1520_mux_clks, + .th1520_gate_clks = th1520_gate_clks, + + .nr_clks = CLK_UART_SCLK + 1, + + .nr_pll_clks = ARRAY_SIZE(th1520_pll_clks), + .nr_div_clks = ARRAY_SIZE(th1520_div_clks), + .nr_mux_clks = ARRAY_SIZE(th1520_mux_clks), + .nr_gate_clks = ARRAY_SIZE(th1520_gate_clks), +}; + +static const struct th1520_plat_data th1520_vo_platdata = { + .th1520_gate_clks = th1520_vo_gate_clks, + + .nr_clks = CLK_HDMI_PIXCLK + 1, + + .nr_gate_clks = ARRAY_SIZE(th1520_vo_gate_clks), +}; + static int th1520_clk_probe(struct platform_device *pdev) { + const struct th1520_plat_data *plat_data; struct device *dev = &pdev->dev; struct clk_hw_onecell_data *priv; @@ -982,11 +1110,17 @@ static int th1520_clk_probe(struct platform_device *pdev) struct clk_hw *hw; int ret, i; - priv = devm_kzalloc(dev, struct_size(priv, hws, NR_CLKS), GFP_KERNEL); + plat_data = device_get_match_data(&pdev->dev); + if (!plat_data) { + dev_err(&pdev->dev, "Error: No device match data found\n"); + return -ENODEV; + } + + priv = devm_kzalloc(dev, struct_size(priv, hws, plat_data->nr_clks), GFP_KERNEL); if (!priv) return -ENOMEM; - priv->num = NR_CLKS; + priv->num = plat_data->nr_clks; base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) @@ -996,35 +1130,35 @@ static int th1520_clk_probe(struct platform_device *pdev) if (IS_ERR(map)) return PTR_ERR(map); - for (i = 0; i < ARRAY_SIZE(th1520_pll_clks); i++) { - struct ccu_pll *cp = hw_to_ccu_pll(&th1520_pll_clks[i]->hw); + for (i = 0; i < plat_data->nr_pll_clks; i++) { + struct ccu_pll *cp = hw_to_ccu_pll(&plat_data->th1520_pll_clks[i]->hw); - th1520_pll_clks[i]->map = map; + plat_data->th1520_pll_clks[i]->map = map; - ret = devm_clk_hw_register(dev, &th1520_pll_clks[i]->hw); + ret = devm_clk_hw_register(dev, &plat_data->th1520_pll_clks[i]->hw); if (ret) return ret; priv->hws[cp->common.clkid] = &cp->common.hw; } - for (i = 0; i < ARRAY_SIZE(th1520_div_clks); i++) { - struct ccu_div *cd = hw_to_ccu_div(&th1520_div_clks[i]->hw); + for (i = 0; i < plat_data->nr_div_clks; i++) { + struct ccu_div *cd = hw_to_ccu_div(&plat_data->th1520_div_clks[i]->hw); - th1520_div_clks[i]->map = map; + plat_data->th1520_div_clks[i]->map = map; - ret = devm_clk_hw_register(dev, &th1520_div_clks[i]->hw); + ret = devm_clk_hw_register(dev, &plat_data->th1520_div_clks[i]->hw); if (ret) return ret; priv->hws[cd->common.clkid] = &cd->common.hw; } - for (i = 0; i < ARRAY_SIZE(th1520_mux_clks); i++) { - struct ccu_mux *cm = hw_to_ccu_mux(&th1520_mux_clks[i]->hw); + for (i = 0; i < plat_data->nr_mux_clks; i++) { + struct ccu_mux *cm = hw_to_ccu_mux(&plat_data->th1520_mux_clks[i]->hw); const struct clk_init_data *init = cm->common.hw.init; - th1520_mux_clks[i]->map = map; + plat_data->th1520_mux_clks[i]->map = map; hw = devm_clk_hw_register_mux_parent_data_table(dev, init->name, init->parent_data, @@ -1040,10 +1174,10 @@ static int th1520_clk_probe(struct platform_device *pdev) priv->hws[cm->common.clkid] = hw; } - for (i = 0; i < ARRAY_SIZE(th1520_gate_clks); i++) { - struct ccu_gate *cg = hw_to_ccu_gate(&th1520_gate_clks[i]->hw); + for (i = 0; i < plat_data->nr_gate_clks; i++) { + struct ccu_gate *cg = hw_to_ccu_gate(&plat_data->th1520_gate_clks[i]->hw); - th1520_gate_clks[i]->map = map; + plat_data->th1520_gate_clks[i]->map = map; hw = devm_clk_hw_register_gate_parent_data(dev, cg->common.hw.init->name, @@ -1056,19 +1190,21 @@ static int th1520_clk_probe(struct platform_device *pdev) priv->hws[cg->common.clkid] = hw; } - ret = devm_clk_hw_register(dev, &osc12m_clk.hw); - if (ret) - return ret; - priv->hws[CLK_OSC12M] = &osc12m_clk.hw; + if (plat_data == &th1520_ap_platdata) { + ret = devm_clk_hw_register(dev, &osc12m_clk.hw); + if (ret) + return ret; + priv->hws[CLK_OSC12M] = &osc12m_clk.hw; - ret = devm_clk_hw_register(dev, &gmac_pll_clk_100m.hw); - if (ret) - return ret; - priv->hws[CLK_PLL_GMAC_100M] = &gmac_pll_clk_100m.hw; + ret = devm_clk_hw_register(dev, &gmac_pll_clk_100m.hw); + if (ret) + return ret; + priv->hws[CLK_PLL_GMAC_100M] = &gmac_pll_clk_100m.hw; - ret = devm_clk_hw_register(dev, &emmc_sdio_ref_clk.hw); - if (ret) - return ret; + ret = devm_clk_hw_register(dev, &emmc_sdio_ref_clk.hw); + if (ret) + return ret; + } ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv); if (ret) @@ -1080,6 +1216,11 @@ static int th1520_clk_probe(struct platform_device *pdev) static const struct of_device_id th1520_clk_match[] = { { .compatible = "thead,th1520-clk-ap", + .data = &th1520_ap_platdata, + }, + { + .compatible = "thead,th1520-clk-vo", + .data = &th1520_vo_platdata, }, { /* sentinel */ }, }; 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Mon, 20 Jan 2025 17:21:21 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC v3 03/18] dt-bindings: firmware: thead,th1520: Add support for firmware node Date: Mon, 20 Jan 2025 18:20:56 +0100 Message-Id: <20250120172111.3492708-4-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250120172111.3492708-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Se0xTZxjG851zes6hS/XQuvGFLTK6jYlzXHZxn0AEshnOXJxsWaJOs63T Y61ySwvbxCkgpaOsXKdZVmA4ROmIrGtLK0U6kJWLE4nKRbJIB5HL6LiWi4oBR23d/O95n/f3 fs/7Jh+NCy+S/rQsKZWTJ0kSxCSfsLTd73pVpCqQho10vIg6blViyPxAS6ELti4MVdi7eMhx sw5DPQvTJPpl5DqF/rZlEahPV06h7DY9ica1DhLNahw81N1QRqK5fDtAljkliWrtAxTSL1Rg 6KdZM4Gq6hsAUqnP89CNP7ahAUcHgca7NThSadeih431FFrpMxCodKqJQnUTxTzUXrsLKZtO ETHr2en+HIqdGB8n2N9z5ynWtniGYK3aAYrVWDsBa6xRk+ztvkaS/fHKB+xf37ZjrKkqg1XW tmFs4XIYO/1bL8kW1NUA9mb2LSpe+DE/6gCXIPuCk4du/Yx/yKKzYyn5z39VUtBLZQKXfx7w oSHzBjxnN5B5gE8LGR2AJS13ME8xD+D5gn8oTzEH4MV8Jfl4ZLTTxPM0qgEsmr7kpSYAXKjW Y26KZF6Dg9UVj6h1TA4Bc1qzgLvAmTEALcNlj94SMfugaWh+laJpgnkJNhu3uG0BEw0NeTpv XABsunwNd2sfJgbe7bVRHsYXXvlhmHBrfJXJNpfi7vchY+DD5qVR3DP8Dry3VEp5tAg62+u8 +jn40FqBeXQyHDS7vPzX0Kpp9+pIeLtriXTvhjPBUN8Q6rFjYVGhCnfbkFkD+yd9PSusgSWW 7722AOaqhB46CJ7W5P8X2qWzeENZWHL9T14RCNQ+cYz2iWO0/+eeAXgN8OPSFIlSThGexH0Z opAkKtKSpCH7kxONYPVvX11pd9WDcudsSAvAaNACII2L1wmentFIhYIDkqPpnDz5U3laAqdo Ac/ShNhPUNmUIxUyUkkqd4TjUjj54y5G+/hnYjsyN0j3aLv70o8HzULnuQ0HD+60ica2x9wt nJUPF5jeq9rbOhOKy2g84/BTkXqN4ZM76lyuxy/oRITAJ/BsrLFVHbMrv2zTyzu2BFYvz0+Z phTKyuISrTrAqXnb6rBPKUVFwabytb6/yhKCwzePDMlPPnPPOjgpYBs3x7YMhU5ePWF85cP4 /XFj8Xs3ORfxB2EZbwo6P3ohPXXPvrGIz8XW8aCI0VHqBtJtPdYv4w8X68Ni1BWXr2136QLN ccfFG0PjVN8ZLxl8oqM6x96VRe6+MHfkGP/k6+EpPxeu7wkw56qduxUrOdHvJzS7slJCmOVv 3jp7f2ZxW9RMAHH4qGFnnZhQHJKEb8TlCsm/xXnsUEoEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrCKsWRmVeSWpSXmKPExsVy+t/xu7rCbX3pBhuvslucuL6IyWLr71ns Fmv2nmOymH/kHKvFvUtbmCyufH3PZrHu6QV2ixd7G1ksrq2Yy27RfGw9m8XLWffYLD723GO1 uLxrDpvF594jjBbbPrewWaw9cpfdYv3X+UwWCz9uZbFYsmMXo0Vb5zJWi4unXC3u3jvBYvHy cg+zRdssfov/e3awW/y7tpHFYva7/ewWW95MZLU4vjbcomX/FBYHOY/3N1rZPd68fMnicbjj C7vH3m8LWDx2zrrL7tGz8wyjx6ZVnWwed67tYfOYdzLQ4373cSaPzUvqPVrWHmPy6P9r4PF+ 31U2j74tqxg9LjVfZw8QitKzKcovLUlVyMgvLrFVija0MNIztLTQMzKx1DM0No+1MjJV0rez SUnNySxLLdK3S9DL2LbiCFNBr0LFpL6r7A2Mn6S6GDk5JARMJJ6d2czaxcjFISSwlFFi7+mH 7BAJGYlr3S9ZIGxhiT/XuthAbCGBV4wS9xaGgdhsAkYSD5bPZwWxRQQWs0js3VcJMohZ4C2j xPWZG8GahQWiJO6uW8DUxcjBwSKgKnFgkyVImFfAXmJj1wo2iPnyEvsPnmUGsTkFHCS+X93L DrHLXuLO1W5GiHpBiZMzn4CNZAaqb946m3kCo8AsJKlZSFILGJlWMYqklhbnpucWG+oVJ+YW l+al6yXn525iBCaXbcd+bt7BOO/VR71DjEwcjIcYJTiYlUR4RT/0pAvxpiRWVqUW5ccXleak Fh9iNAU6eyKzlGhyPjC95ZXEG5oZmBqamFkamFqaGSuJ87pdPp8mJJCeWJKanZpakFoE08fE wSnVwDTNfx9P2qmM1Yu3tjx5VhPSt/n98tbuQx/q+u4VTm1r9gtPmherqH/J/uyznR++H87r X3dBUPr7Xgduzrtsn1UZr3zamzi9Wrzv5dLUz1+2tVoXKt2+OWXjztU9mX/9JeZc4UswOJg3 lfVehNiFib/217GGXr4qlHd0UqJTrOLfoKPHbjf+3LlX8Sajpa30pxv/SgKup6w7saLUZc2L jvP/WNIsjDnD+9t/XPLwuHW8Qa8kNbhwxr7C2Hgrk5QTN14VXDzx4O2LreExPTHF05qn+HqW ll+f62njWRpZZtLAo1Ln2Sk8M7clyelT070+qal1VQWHbobeV5vR8iS0+qFEvde9qE4TA/9d Ku8tWpRYijMSDbWYi4oTATFqopu3AwAA X-CMS-MailID: 20250120172123eucas1p13564bf2d07000506caf44cf55bda7fd9 X-Msg-Generator: CA X-RootMTR: 20250120172123eucas1p13564bf2d07000506caf44cf55bda7fd9 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250120172123eucas1p13564bf2d07000506caf44cf55bda7fd9 References: <20250120172111.3492708-1-m.wilczynski@samsung.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The kernel communicates with the E902 core through the mailbox transport using AON firmware protocol. Add dt-bindings to document it the dt node. Signed-off-by: Michal Wilczynski --- .../bindings/firmware/thead,th1520-aon.yaml | 53 +++++++++++++++++++ MAINTAINERS | 2 + .../dt-bindings/firmware/thead,th1520-aon.h | 18 +++++++ 3 files changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml create mode 100644 include/dt-bindings/firmware/thead,th1520-aon.h diff --git a/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml b/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml new file mode 100644 index 000000000000..bbc183200400 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/thead,th1520-aon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD TH1520 AON (Always-On) Firmware + +description: | + The Always-On (AON) subsystem in the TH1520 SoC is responsible for managing + low-power states, system wakeup events, and power management tasks. It is + designed to operate independently in a dedicated power domain, allowing it to + remain functional even during the SoC's deep sleep states. + + At the heart of the AON subsystem is the E902, a low-power core that executes + firmware responsible for coordinating tasks such as power domain control, + clock management, and system wakeup signaling. Communication between the main + SoC and the AON subsystem is handled through a mailbox interface, which + enables message-based interactions with the AON firmware. + +maintainers: + - Michal Wilczynski + +properties: + compatible: + const: thead,th1520-aon + + mboxes: + maxItems: 1 + + mbox-names: + items: + - const: aon + + "#power-domain-cells": + const: 1 + +required: + - compatible + - mboxes + - mbox-names + - "#power-domain-cells" + +additionalProperties: false + +examples: + - | + aon: aon { + compatible = "thead,th1520-aon"; + mboxes = <&mbox_910t 1>; + mbox-names = "aon"; + #power-domain-cells = <1>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 0fa7c5728f1e..c56a1fb6e02a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20184,6 +20184,7 @@ M: Fu Wei L: linux-riscv@lists.infradead.org S: Maintained T: git https://github.com/pdp7/linux.git +F: Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml F: Documentation/devicetree/bindings/mailbox/thead,th1520-mbox.yaml F: Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml @@ -20194,6 +20195,7 @@ F: drivers/mailbox/mailbox-th1520.c F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: drivers/pinctrl/pinctrl-th1520.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h +F: include/dt-bindings/firmware/thead,th1520-aon.h RNBD BLOCK DRIVERS M: Md. Haris Iqbal diff --git a/include/dt-bindings/firmware/thead,th1520-aon.h b/include/dt-bindings/firmware/thead,th1520-aon.h new file mode 100644 index 000000000000..7607522289f7 --- /dev/null +++ b/include/dt-bindings/firmware/thead,th1520-aon.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 Alibaba Group Holding Limited. + * Copyright (c) 2024 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + */ + +#ifndef __DT_BINDINGS_AON_TH1520_H +#define __DT_BINDINGS_AON_TH1520_H + +#define TH1520_AON_VDEC_PD 1 +#define TH1520_AON_NPU_PD 2 +#define TH1520_AON_VENC_PD 3 +#define TH1520_AON_GPU_PD 4 +#define TH1520_AON_DSP0_PD 5 +#define TH1520_AON_DSP1_PD 6 + +#endif From patchwork Mon Jan 20 17:20:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13945304 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B2FE6C02182 for ; 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s=mail20170921; t=1737393685; bh=sd08BWohXem3dBVuHX3dCJ58apCrb9/s0z26DVgq2O8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Td2TCgD/Zq8kxf/98vIBsGiwXE+sO5Dd59JV1aImZZZWCYU1DCtTcLwtNElpy79xd KJXu3yAwzQ0UYgwwpK/4ISV9wvF5HH6MsfoAnWtbMcf6vXeCrVrLEvu9xsHaFNdTFq laRUVucmMRQGwqKO95ZdRxhfRklMd935VfJgYkVY= Received: from eusmges3new.samsung.com (unknown [203.254.199.245]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20250120172125eucas1p28c3c0a3da0fa486b827be5e76b2c6aea~cdln2KwWH3179431794eucas1p2S; Mon, 20 Jan 2025 17:21:25 +0000 (GMT) Received: from eucas1p1.samsung.com ( [182.198.249.206]) by eusmges3new.samsung.com (EUCPMTA) with SMTP id DF.56.20397.4168E876; Mon, 20 Jan 2025 17:21:24 +0000 (GMT) Received: from eusmtrp2.samsung.com (unknown [182.198.249.139]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20250120172124eucas1p233b3f6da39e7064db62b02a66bc1ac29~cdlnW93ux1089910899eucas1p2r; Mon, 20 Jan 2025 17:21:24 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20250120172124eusmtrp234fa8332a1f78f797bda0b78dede1c28~cdlnWM6hV0490804908eusmtrp2h; Mon, 20 Jan 2025 17:21:24 +0000 (GMT) X-AuditID: cbfec7f5-ed1d670000004fad-46-678e86148686 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 58.95.19654.4168E876; Mon, 20 Jan 2025 17:21:24 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250120172123eusmtip1c95c0bf6f2ec1cb55a478acbb133f612~cdlmGpqQq1013910139eusmtip1W; Mon, 20 Jan 2025 17:21:23 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC v3 04/18] firmware: thead: Add AON firmware protocol driver Date: Mon, 20 Jan 2025 18:20:57 +0100 Message-Id: <20250120172111.3492708-5-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250120172111.3492708-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Sf1CTdRzH+T7Pw/NsO6cPk45vlHHg2W9RjJOvByQFdg9HlxZ3eHp1NONx EDC8TQzLBI6f0mSGkDHUAXEySEJwLOBkKxibCiybMjmDoYjWCBtzMpQMYj1U/vf6fD7vz+f9 fd99ebhISwby0qT7WZlUnBFCCgid6ZFlvX9xuWTjGX0Euni9HkMdf6oodLbHgiG10eKL7FYt hq7NOkn03Z0rFPqtJ59ANs0pChWYWknkUNlJ5FLYfdHV7pMkch81AqRzF5KoxThGodZZNYbq XB0EaujsBqj4yBlf9PPlbWjMfpFAjqsKHBWrVqHFC50UWrC1EajmDwOFtNNf+iJzy05UaKgk Yp5jnCNFFDPtcBBMX+kDiunx1BJMl2qMYhRdg4Bpbz5CMqO2CyRz+tK7zPgXZow535DLFLaY MEb510bGqR8mmXJtM2CsBdepHaLdgqgUNiPtACvb8PqHgtQbxjpq39QJkFPfd43IA48OlAEe D9LhsLkksAzweSJaA2B5TXoZECzxAwBNiz/gXOEGcKxWRXhV3oUCdQnFDRoBfGyYJrj1aQDb Z3K9TNKb4M1Gta9X5E8XEbCoPx94C5z+FUDd5EnSq1pNx8OB7y9jXibodfD0RCHlZSG9FdYZ 7CRnFwQNPw7hXubTMXBuuGdZ4wcvVU/+44wvaQo6anBO3yaAV0YyuWxx8L7jVa69Gk6ZtRTH z8LFLjXGcRa82XF/efUQ7FKYlzkSjlrmSe8ZnH4JtnZv4NpvwLaKaZK7vhKO3PPjHrASVuhO 4FxbCEuLRZz6eVilOPqfqUWjWzZl4EjlLHkMBKueiKJ6Iorqf99agDeDADZbnilh5a9J2U9C 5eJMebZUEvpRVmY7WPrYAwvm2U6gmXKF9gKMB3oB5OEh/sKnZhQSkTBFfPBTVpaVLMvOYOW9 4BkeERIgrDcUSUS0RLyfTWfZfazs3ynG4wfmYQnUCzGSgYGy22V7wtY+nbTOWVO5V+qzsCpm +2i11dpPOA3RlZ+vyd285Zv0YAu/q6K/wZUQu2sQ3rpz1/lKKH9zTZjLGb1rSH5er5yYL9rz baPPcWn5lrfOJYbejYyMLf8gfi721Jt73w7Ly8nZ6YHuHSJTonj+eF9UbPzwYVfszIqzAUEH Bw8t7A68J3hH8svDpu1RK/y+MqfeduqHPouIK9VtO+yTEiRp//3GuHFOlsxvjGAF4dat8S8m VFV/LY22VXzsGE9M0r6/JjwaOKfO5U6891BpsnncVe5NqG59yU9K4VxyvicxWFPKKtP0Qk2A dNLDxDVV1t2aT2KbHlvXhhDyVHHYy7hMLv4b7pGbZkcEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrOKsWRmVeSWpSXmKPExsVy+t/xu7oibX3pBqubJSxOXF/EZLH19yx2 izV7zzFZzD9yjtXi3qUtTBZXvr5ns1j39AK7xYu9jSwW11bMZbdoPraezeLlrHtsFh977rFa XN41h83ic+8RRottn1vYLNYeuctusf7rfCaLhR+3slgs2bGL0aKtcxmrxcVTrhZ3751gsXh5 uYfZom0Wv8X/PTvYLf5d28hiMfvdfnaLLW8mslocXxtu0bJ/CouDnMf7G63sHm9evmTxONzx hd1j77cFLB47Z91l9+jZeYbRY9OqTjaPO9f2sHnMOxnocb/7OJPH5iX1Hi1rjzF59P818Hi/ 7yqbR9+WVYwel5qvswcIRenZFOWXlqQqZOQXl9gqRRtaGOkZWlroGZlY6hkam8daGZkq6dvZ pKTmZJalFunbJehl3DqykL3g1XTGikWHr7A0MP4s62Lk5JAQMJFont/O3sXIxSEksJRRYl/z MnaIhIzEte6XLBC2sMSfa11sEEWvGCV2b53ICJJgEzCSeLB8PiuILSKwmEVi775KkCJmgbeM EtdnbgTrFhbwlDi9/RQTiM0ioCox71EL2AZeAXuJhfvvsUFskJfYf/AsM4jNKeAg8f3qXrAa IaCaO1e7GSHqBSVOznwCNpMZqL5562zmCYwCs5CkZiFJLWBkWsUoklpanJueW2ykV5yYW1ya l66XnJ+7iRGYYrYd+7llB+PKVx/1DjEycTAeYpTgYFYS4RX90JMuxJuSWFmVWpQfX1Sak1p8 iNEU6O6JzFKiyfnAJJdXEm9oZmBqaGJmaWBqaWasJM7LduV8mpBAemJJanZqakFqEUwfEwen VAPT5pfGB0S0Vxz3Kj668cMT+Q17Ja/POLvA89/yqV59HqLRCZ1bbq3azzN5qdWul9usVhWI GgYxMu35kLdGwDOb/V/x0qOLc2+++Oh00m/VtgNvLxYeE0s6N6Vn0kzFtbMtL+axSD7T0e09 a2QcIclr+W7yddv/hgwltREL7uaxFT9sz68V3nMtce/jSeFhGyJqLFeqnmibGya/8cbm0783 nt56KEeo6bawCf+s2+fe/V6i8i9PocPmxG7eX0mlHW5W02YvXbH5wt+aOE2O7aETf171DZ8k XBHq8vdwFJ9EiPKfeXslYtk6bVbWiOh+Pf3Z6J/OtXQH+UflU+/J6BhyqcdOqlOZ+0B3nsnH xzlnipRYijMSDbWYi4oTATGGHlm6AwAA X-CMS-MailID: 20250120172124eucas1p233b3f6da39e7064db62b02a66bc1ac29 X-Msg-Generator: CA X-RootMTR: 20250120172124eucas1p233b3f6da39e7064db62b02a66bc1ac29 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250120172124eucas1p233b3f6da39e7064db62b02a66bc1ac29 References: <20250120172111.3492708-1-m.wilczynski@samsung.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The T-Head TH1520 SoC uses an E902 co-processor running Always-On (AON) firmware to manage power, clock, and other system resources [1]. This patch introduces a driver implementing the AON firmware protocol, allowing the Linux kernel to communicate with the firmware via mailbox channels. Through an RPC-based interface, the kernel can initiate power state transitions, update resource configurations, and perform other AON-related tasks. Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf [1] Signed-off-by: Michal Wilczynski --- MAINTAINERS | 2 + drivers/firmware/Kconfig | 9 + drivers/firmware/Makefile | 1 + drivers/firmware/thead,th1520-aon.c | 271 ++++++++++++++++++ .../linux/firmware/thead/thead,th1520-aon.h | 186 ++++++++++++ 5 files changed, 469 insertions(+) create mode 100644 drivers/firmware/thead,th1520-aon.c create mode 100644 include/linux/firmware/thead/thead,th1520-aon.h diff --git a/MAINTAINERS b/MAINTAINERS index c56a1fb6e02a..c96a1e6c8831 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20191,11 +20191,13 @@ F: Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml F: arch/riscv/boot/dts/thead/ F: drivers/clk/thead/clk-th1520-ap.c +F: drivers/firmware/thead,th1520-aon.c F: drivers/mailbox/mailbox-th1520.c F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: drivers/pinctrl/pinctrl-th1520.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h F: include/dt-bindings/firmware/thead,th1520-aon.h +F: include/linux/firmware/thead/thead,th1520-aon.h RNBD BLOCK DRIVERS M: Md. Haris Iqbal diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index 71d8b26c4103..4d84288cc290 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -212,6 +212,15 @@ config SYSFB_SIMPLEFB If unsure, say Y. +config TH1520_AON_PROTOCOL + tristate "Always-On firmware protocol" + depends on ARCH_THEAD || COMPILE_TEST + help + Power, clock, and resource management capabilities on the TH1520 SoC are + managed by the E902 core. Firmware running on this core communicates with + the kernel through the Always-On protocol, using hardware mailbox as a medium. + Say yes if you need such capabilities. + config TI_SCI_PROTOCOL tristate "TI System Control Interface (TISCI) Message Protocol" depends on TI_MESSAGE_MANAGER diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile index 7a8d486e718f..5db9c042430c 100644 --- a/drivers/firmware/Makefile +++ b/drivers/firmware/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_RASPBERRYPI_FIRMWARE) += raspberrypi.o obj-$(CONFIG_FW_CFG_SYSFS) += qemu_fw_cfg.o obj-$(CONFIG_SYSFB) += sysfb.o obj-$(CONFIG_SYSFB_SIMPLEFB) += sysfb_simplefb.o +obj-$(CONFIG_TH1520_AON_PROTOCOL) += thead,th1520-aon.o obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o obj-$(CONFIG_TRUSTED_FOUNDATIONS) += trusted_foundations.o obj-$(CONFIG_TURRIS_MOX_RWTM) += turris-mox-rwtm.o diff --git a/drivers/firmware/thead,th1520-aon.c b/drivers/firmware/thead,th1520-aon.c new file mode 100644 index 000000000000..32d159f46ebb --- /dev/null +++ b/drivers/firmware/thead,th1520-aon.c @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + * Copyright (c) 2024 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define MAX_RX_TIMEOUT (msecs_to_jiffies(3000)) +#define MAX_TX_TIMEOUT 500 + +struct th1520_aon_chan { + struct platform_device *pd; + struct mbox_chan *ch; + struct th1520_aon_rpc_ack_common ack_msg; + struct mbox_client cl; + struct completion done; + + /* make sure only one RPC is perfomed at a time */ + struct mutex transaction_lock; +}; + +struct th1520_aon_msg_req_set_resource_power_mode { + struct th1520_aon_rpc_msg_hdr hdr; + u16 resource; + u16 mode; + u16 reserved[10]; +} __packed __aligned(1); + +/* + * This type is used to indicate error response for most functions. + */ +enum th1520_aon_error_codes { + LIGHT_AON_ERR_NONE = 0, /* Success */ + LIGHT_AON_ERR_VERSION = 1, /* Incompatible API version */ + LIGHT_AON_ERR_CONFIG = 2, /* Configuration error */ + LIGHT_AON_ERR_PARM = 3, /* Bad parameter */ + LIGHT_AON_ERR_NOACCESS = 4, /* Permission error (no access) */ + LIGHT_AON_ERR_LOCKED = 5, /* Permission error (locked) */ + LIGHT_AON_ERR_UNAVAILABLE = 6, /* Unavailable (out of resources) */ + LIGHT_AON_ERR_NOTFOUND = 7, /* Not found */ + LIGHT_AON_ERR_NOPOWER = 8, /* No power */ + LIGHT_AON_ERR_IPC = 9, /* Generic IPC error */ + LIGHT_AON_ERR_BUSY = 10, /* Resource is currently busy/active */ + LIGHT_AON_ERR_FAIL = 11, /* General I/O failure */ + LIGHT_AON_ERR_LAST +}; + +static int th1520_aon_linux_errmap[LIGHT_AON_ERR_LAST] = { + 0, /* LIGHT_AON_ERR_NONE */ + -EINVAL, /* LIGHT_AON_ERR_VERSION */ + -EINVAL, /* LIGHT_AON_ERR_CONFIG */ + -EINVAL, /* LIGHT_AON_ERR_PARM */ + -EACCES, /* LIGHT_AON_ERR_NOACCESS */ + -EACCES, /* LIGHT_AON_ERR_LOCKED */ + -ERANGE, /* LIGHT_AON_ERR_UNAVAILABLE */ + -EEXIST, /* LIGHT_AON_ERR_NOTFOUND */ + -EPERM, /* LIGHT_AON_ERR_NOPOWER */ + -EPIPE, /* LIGHT_AON_ERR_IPC */ + -EBUSY, /* LIGHT_AON_ERR_BUSY */ + -EIO, /* LIGHT_AON_ERR_FAIL */ +}; + +static inline int th1520_aon_to_linux_errno(int errno) +{ + if (errno >= LIGHT_AON_ERR_NONE && errno < LIGHT_AON_ERR_LAST) + return th1520_aon_linux_errmap[errno]; + + return -EIO; +} + +static void th1520_aon_rx_callback(struct mbox_client *c, void *rx_msg) +{ + struct th1520_aon_chan *aon_chan = + container_of(c, struct th1520_aon_chan, cl); + struct th1520_aon_rpc_msg_hdr *hdr = + (struct th1520_aon_rpc_msg_hdr *)rx_msg; + u8 recv_size = sizeof(struct th1520_aon_rpc_msg_hdr) + hdr->size; + + if (recv_size != sizeof(struct th1520_aon_rpc_ack_common)) { + dev_err(c->dev, "Invalid ack size, not completing\n"); + return; + } + + memcpy(&aon_chan->ack_msg, rx_msg, recv_size); + complete(&aon_chan->done); +} + +/** + * th1520_aon_call_rpc() - Send an RPC request to the TH1520 AON subsystem + * @aon_chan: Pointer to the AON channel structure + * @msg: Pointer to the message (RPC payload) that will be sent + * + * This function sends an RPC message to the TH1520 AON subsystem via mailbox. + * It takes the provided @msg buffer, formats it with version and service flags, + * then blocks until the RPC completes or times out. The completion is signaled + * by the `aon_chan->done` completion, which is waited upon for a duration + * defined by `MAX_RX_TIMEOUT`. + * + * Return: + * * 0 on success + * * -ETIMEDOUT if the RPC call times out + * * A negative error code if the mailbox send fails or if AON responds with + * a non-zero error code (converted via th1520_aon_to_linux_errno()). + */ +int th1520_aon_call_rpc(struct th1520_aon_chan *aon_chan, void *msg) +{ + struct th1520_aon_rpc_msg_hdr *hdr = msg; + int ret; + + mutex_lock(&aon_chan->transaction_lock); + reinit_completion(&aon_chan->done); + + RPC_SET_VER(hdr, TH1520_AON_RPC_VERSION); + RPC_SET_SVC_ID(hdr, hdr->svc); + RPC_SET_SVC_FLAG_MSG_TYPE(hdr, RPC_SVC_MSG_TYPE_DATA); + RPC_SET_SVC_FLAG_ACK_TYPE(hdr, RPC_SVC_MSG_NEED_ACK); + + ret = mbox_send_message(aon_chan->ch, msg); + if (ret < 0) { + dev_err(aon_chan->cl.dev, "RPC send msg failed: %d\n", ret); + goto out; + } + + if (!wait_for_completion_timeout(&aon_chan->done, MAX_RX_TIMEOUT)) { + dev_err(aon_chan->cl.dev, "RPC send msg timeout\n"); + mutex_unlock(&aon_chan->transaction_lock); + return -ETIMEDOUT; + } + + ret = aon_chan->ack_msg.err_code; + +out: + mutex_unlock(&aon_chan->transaction_lock); + + return th1520_aon_to_linux_errno(ret); +} +EXPORT_SYMBOL_GPL(th1520_aon_call_rpc); + +/** + * th1520_aon_power_update() - Change power state of a resource via TH1520 AON + * @aon_chan: Pointer to the AON channel structure + * @rsrc: Resource ID whose power state needs to be updated + * @power_on: Boolean indicating whether the resource should be powered on (true) + * or powered off (false) + * + * This function requests the TH1520 AON subsystem to set the power mode of the + * given resource (@rsrc) to either on or off. It constructs the message in + * `struct th1520_aon_msg_req_set_resource_power_mode` and then invokes + * th1520_aon_call_rpc() to make the request. If the AON call fails, an error + * message is logged along with the specific return code. + * + * Return: + * * 0 on success + * * A negative error code in case of failures (propagated from + * th1520_aon_call_rpc()). + */ +int th1520_aon_power_update(struct th1520_aon_chan *aon_chan, u16 rsrc, + bool power_on) +{ + struct th1520_aon_msg_req_set_resource_power_mode msg = {}; + struct th1520_aon_rpc_msg_hdr *hdr = &msg.hdr; + int ret; + + hdr->svc = TH1520_AON_RPC_SVC_PM; + hdr->func = TH1520_AON_PM_FUNC_SET_RESOURCE_POWER_MODE; + hdr->size = TH1520_AON_RPC_MSG_NUM; + + RPC_SET_BE16(&msg.resource, 0, rsrc); + RPC_SET_BE16(&msg.resource, 2, + (power_on ? TH1520_AON_PM_PW_MODE_ON : + TH1520_AON_PM_PW_MODE_OFF)); + + ret = th1520_aon_call_rpc(aon_chan, &msg); + if (ret) + dev_err(aon_chan->cl.dev, "failed to power %s resource %d ret %d\n", + power_on ? "up" : "off", rsrc, ret); + + return ret; +} +EXPORT_SYMBOL_GPL(th1520_aon_power_update); + +static int th1520_aon_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct th1520_aon_chan *aon_chan; + struct mbox_client *cl; + int ret; + struct platform_device_info pdevinfo = { + .name = "th1520-pd", + .id = PLATFORM_DEVID_AUTO, + .parent = dev, + }; + + aon_chan = devm_kzalloc(dev, sizeof(*aon_chan), GFP_KERNEL); + if (!aon_chan) + return -ENOMEM; + + cl = &aon_chan->cl; + cl->dev = dev; + cl->tx_block = true; + cl->tx_tout = MAX_TX_TIMEOUT; + cl->rx_callback = th1520_aon_rx_callback; + + aon_chan->ch = mbox_request_channel_byname(cl, "aon"); + if (IS_ERR(aon_chan->ch)) { + ret = PTR_ERR(aon_chan->ch); + return dev_err_probe(dev, ret, "Failed to request aon mbox chan\n"); + } + + mutex_init(&aon_chan->transaction_lock); + init_completion(&aon_chan->done); + + platform_set_drvdata(pdev, aon_chan); + + aon_chan->pd = platform_device_register_full(&pdevinfo); + ret = PTR_ERR_OR_ZERO(aon_chan->pd); + if (ret) { + dev_err(dev, "Failed to register child device 'th1520-pd': %d\n", ret); + goto free_mbox_chan; + } + + ret = devm_of_platform_populate(dev); + if (ret) + goto unregister_pd; + + return 0; + +unregister_pd: + platform_device_unregister(aon_chan->pd); +free_mbox_chan: + mbox_free_channel(aon_chan->ch); + + return ret; +} + +static void th1520_aon_remove(struct platform_device *pdev) +{ + struct th1520_aon_chan *aon_chan = platform_get_drvdata(pdev); + + platform_device_unregister(aon_chan->pd); + mbox_free_channel(aon_chan->ch); +} + +static const struct of_device_id th1520_aon_match[] = { + { .compatible = "thead,th1520-aon" }, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, th1520_aon_match); + +static struct platform_driver th1520_aon_driver = { + .driver = { + .name = "th1520-aon", + .of_match_table = th1520_aon_match, + }, + .probe = th1520_aon_probe, + .remove = th1520_aon_remove, +}; +module_platform_driver(th1520_aon_driver); + +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_DESCRIPTION("T-HEAD TH1520 Always-On firmware driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/firmware/thead/thead,th1520-aon.h b/include/linux/firmware/thead/thead,th1520-aon.h new file mode 100644 index 000000000000..3daa17c01d17 --- /dev/null +++ b/include/linux/firmware/thead/thead,th1520-aon.h @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +#ifndef _THEAD_AON_H +#define _THEAD_AON_H + +#include +#include + +#define AON_RPC_MSG_MAGIC (0xef) +#define TH1520_AON_RPC_VERSION 2 +#define TH1520_AON_RPC_MSG_NUM 7 + +extern struct th1520_aon_chan *aon_chan; + +enum th1520_aon_rpc_svc { + TH1520_AON_RPC_SVC_UNKNOWN = 0, + TH1520_AON_RPC_SVC_PM = 1, + TH1520_AON_RPC_SVC_MISC = 2, + TH1520_AON_RPC_SVC_AVFS = 3, + TH1520_AON_RPC_SVC_SYS = 4, + TH1520_AON_RPC_SVC_WDG = 5, + TH1520_AON_RPC_SVC_LPM = 6, + TH1520_AON_RPC_SVC_MAX = 0x3F, +}; + +enum th1520_aon_misc_func { + TH1520_AON_MISC_FUNC_UNKNOWN = 0, + TH1520_AON_MISC_FUNC_SET_CONTROL = 1, + TH1520_AON_MISC_FUNC_GET_CONTROL = 2, + TH1520_AON_MISC_FUNC_REGDUMP_CFG = 3, +}; + +enum th1520_aon_wdg_func { + TH1520_AON_WDG_FUNC_UNKNOWN = 0, + TH1520_AON_WDG_FUNC_START = 1, + TH1520_AON_WDG_FUNC_STOP = 2, + TH1520_AON_WDG_FUNC_PING = 3, + TH1520_AON_WDG_FUNC_TIMEOUTSET = 4, + TH1520_AON_WDG_FUNC_RESTART = 5, + TH1520_AON_WDG_FUNC_GET_STATE = 6, + TH1520_AON_WDG_FUNC_POWER_OFF = 7, + TH1520_AON_WDG_FUNC_AON_WDT_ON = 8, + TH1520_AON_WDG_FUNC_AON_WDT_OFF = 9, +}; + +enum th1520_aon_sys_func { + TH1520_AON_SYS_FUNC_UNKNOWN = 0, + TH1520_AON_SYS_FUNC_AON_RESERVE_MEM = 1, +}; + +enum th1520_aon_lpm_func { + TH1520_AON_LPM_FUNC_UNKNOWN = 0, + TH1520_AON_LPM_FUNC_REQUIRE_STR = 1, + TH1520_AON_LPM_FUNC_RESUME_STR = 2, + TH1520_AON_LPM_FUNC_REQUIRE_STD = 3, + TH1520_AON_LPM_FUNC_CPUHP = 4, + TH1520_AON_LPM_FUNC_REGDUMP_CFG = 5, +}; + +enum th1520_aon_pm_func { + TH1520_AON_PM_FUNC_UNKNOWN = 0, + TH1520_AON_PM_FUNC_SET_RESOURCE_REGULATOR = 1, + TH1520_AON_PM_FUNC_GET_RESOURCE_REGULATOR = 2, + TH1520_AON_PM_FUNC_SET_RESOURCE_POWER_MODE = 3, + TH1520_AON_PM_FUNC_PWR_SET = 4, + TH1520_AON_PM_FUNC_PWR_GET = 5, + TH1520_AON_PM_FUNC_CHECK_FAULT = 6, + TH1520_AON_PM_FUNC_GET_TEMPERATURE = 7, +}; + +struct th1520_aon_rpc_msg_hdr { + u8 ver; /* version of msg hdr */ + u8 size; /* msg size ,uinit in bytes,the size includes rpc msg header self */ + u8 svc; /* rpc main service id */ + u8 func; /* rpc sub func id of specific service, sent by caller */ +} __packed __aligned(1); + +struct th1520_aon_rpc_ack_common { + struct th1520_aon_rpc_msg_hdr hdr; + u8 err_code; +} __packed __aligned(1); + +#define RPC_SVC_MSG_TYPE_DATA 0 +#define RPC_SVC_MSG_TYPE_ACK 1 +#define RPC_SVC_MSG_NEED_ACK 0 +#define RPC_SVC_MSG_NO_NEED_ACK 1 + +#define RPC_GET_VER(MESG) ((MESG)->ver) +#define RPC_SET_VER(MESG, VER) ((MESG)->ver = (VER)) +#define RPC_GET_SVC_ID(MESG) ((MESG)->svc & 0x3F) +#define RPC_SET_SVC_ID(MESG, ID) ((MESG)->svc |= 0x3F & (ID)) +#define RPC_GET_SVC_FLAG_MSG_TYPE(MESG) (((MESG)->svc & 0x80) >> 7) +#define RPC_SET_SVC_FLAG_MSG_TYPE(MESG, TYPE) ((MESG)->svc |= (TYPE) << 7) +#define RPC_GET_SVC_FLAG_ACK_TYPE(MESG) (((MESG)->svc & 0x40) >> 6) +#define RPC_SET_SVC_FLAG_ACK_TYPE(MESG, ACK) ((MESG)->svc |= (ACK) << 6) + +#define RPC_SET_BE64(MESG, OFFSET, SET_DATA) \ + do { \ + u8 *data = (u8 *)(MESG); \ + u64 _offset = (OFFSET); \ + u64 _set_data = (SET_DATA); \ + data[_offset + 7] = _set_data & 0xFF; \ + data[_offset + 6] = (_set_data & 0xFF00) >> 8; \ + data[_offset + 5] = (_set_data & 0xFF0000) >> 16; \ + data[_offset + 4] = (_set_data & 0xFF000000) >> 24; \ + data[_offset + 3] = (_set_data & 0xFF00000000) >> 32; \ + data[_offset + 2] = (_set_data & 0xFF0000000000) >> 40; \ + data[_offset + 1] = (_set_data & 0xFF000000000000) >> 48; \ + data[_offset + 0] = (_set_data & 0xFF00000000000000) >> 56; \ + } while (0) + +#define RPC_SET_BE32(MESG, OFFSET, SET_DATA) \ + do { \ + u8 *data = (u8 *)(MESG); \ + u64 _offset = (OFFSET); \ + u64 _set_data = (SET_DATA); \ + data[_offset + 3] = (_set_data) & 0xFF; \ + data[_offset + 2] = (_set_data & 0xFF00) >> 8; \ + data[_offset + 1] = (_set_data & 0xFF0000) >> 16; \ + data[_offset + 0] = (_set_data & 0xFF000000) >> 24; \ + } while (0) + +#define RPC_SET_BE16(MESG, OFFSET, SET_DATA) \ + do { \ + u8 *data = (u8 *)(MESG); \ + u64 _offset = (OFFSET); \ + u64 _set_data = (SET_DATA); \ + data[_offset + 1] = (_set_data) & 0xFF; \ + data[_offset + 0] = (_set_data & 0xFF00) >> 8; \ + } while (0) + +#define RPC_SET_U8(MESG, OFFSET, SET_DATA) \ + do { \ + u8 *data = (u8 *)(MESG); \ + data[OFFSET] = (SET_DATA) & 0xFF; \ + } while (0) + +#define RPC_GET_BE64(MESG, OFFSET, PTR) \ + do { \ + u8 *data = (u8 *)(MESG); \ + u64 _offset = (OFFSET); \ + *(u32 *)(PTR) = \ + (data[_offset + 7] | data[_offset + 6] << 8 | \ + data[_offset + 5] << 16 | data[_offset + 4] << 24 | \ + data[_offset + 3] << 32 | data[_offset + 2] << 40 | \ + data[_offset + 1] << 48 | data[_offset + 0] << 56); \ + } while (0) + +#define RPC_GET_BE32(MESG, OFFSET, PTR) \ + do { \ + u8 *data = (u8 *)(MESG); \ + u64 _offset = (OFFSET); \ + *(u32 *)(PTR) = \ + (data[_offset + 3] | data[_offset + 2] << 8 | \ + data[_offset + 1] << 16 | data[_offset + 0] << 24); \ + } while (0) + +#define RPC_GET_BE16(MESG, OFFSET, PTR) \ + do { \ + u8 *data = (u8 *)(MESG); \ + u64 _offset = (OFFSET); \ + *(u16 *)(PTR) = (data[_offset + 1] | data[_offset + 0] << 8); \ + } while (0) + +#define RPC_GET_U8(MESG, OFFSET, PTR) \ + do { \ + u8 *data = (u8 *)(MESG); \ + *(u8 *)(PTR) = (data[OFFSET]); \ + } while (0) + +/* + * Defines for SC PM Power Mode + */ +#define TH1520_AON_PM_PW_MODE_OFF 0 /* Power off */ +#define TH1520_AON_PM_PW_MODE_STBY 1 /* Power in standby */ +#define TH1520_AON_PM_PW_MODE_LP 2 /* Power in low-power */ +#define TH1520_AON_PM_PW_MODE_ON 3 /* Power on */ + +int th1520_aon_call_rpc(struct th1520_aon_chan *aon_chan, void *msg); +int th1520_aon_power_update(struct th1520_aon_chan *aon_chan, u16 rsrc, + bool power_on); + +#endif /* _THEAD_AON_H */ From patchwork Mon Jan 20 17:20:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13945305 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AED2CC02185 for ; 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Mon, 20 Jan 2025 17:21:25 +0000 (GMT) X-AuditID: cbfec7f4-c39fa70000004fb9-c6-678e86162ebb Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id AA.95.19654.5168E876; Mon, 20 Jan 2025 17:21:25 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250120172124eusmtip1fc55a85f3401af220c94dce8ebf491f2~cdlnSNFmS1307113071eusmtip1P; Mon, 20 Jan 2025 17:21:24 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC v3 05/18] pmdomain: thead: Add power-domain driver for TH1520 Date: Mon, 20 Jan 2025 18:20:58 +0100 Message-Id: <20250120172111.3492708-6-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250120172111.3492708-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Sf1CTdRzH+T7Ps+cZcKOHofANyo6dadkJRBHfuzqClOtJ5M6uTA4rG/I0 MH7dJgheXSobqU2Cjq5zMjYmwuQcGzIW4yBsIJs/QJAfwgnbMowf8UMCNI0wxmb53/v7+bze 3/fnc/fh4vyfyGBuetZBVpwlzBCQPoSp8+GNrYFFxaKIHsdryHZLg6HGvxUUutDajSFVRzcH 2W8aMdS/NEeiurs9FJpoPUqgQa2SQoWdehJNKuwkmpfbOaivuZxEC6c6ADItSEmk6xilkH5J haHK+UYCVTU1A1R0opqDeq/Go1G7jUCTfXIcFSmeQY9bmii0MlhPoDOzbRQyTpdykFW3B0nb yojYDczckIxipicnCab9+CLFtN5XE4xZMUoxcvN1wFysPUEyI4MtJFNx5X3G8a0VYxqqvmak uk6M+e6fCGbu5wGSKTbWAuZm4S1qFz/Z561UNiM9jxWHx3zmk6YxVHFyDNvylWYZdgQsR58E 3lxIvw5blJeok8CHy6e1ANadHwfuxyKA5VIDcFF8egHAXn3ME4ehbxp3QzUAalQaj2MaQOmv PRwXRdKR0Fmj4rga62gZAWWXj65ROD0OoGmsnHRRAXQCvHP/xpqDoF+ELYXFmEvz6LehZlZG ufNegG2/dOEu7U3HwgcDrZSb8YdXTo8RLo2vMoWNZ9ZmgrTOB/bbVoDbvB06K87ibh0Ap6xG z6fPwcdmFebW2dDZ+KeH+RKa5VaPfhOOdD9aHZS7GvAy1DeHu8txsH1KibvKkPaDQzP+7hH8 4PemHz1lHjxexHfTm+AP8lP/hXZrTZ5QBtafv0eVgFDFU8sonlpG8X+uGuC1IIjNlWSKWElk FnsoTCLMlORmicL2Z2deBKu3fW3FutgEaqbmwywA4wILgFxcsI63/p5cxOelCgsOs+LsfeLc DFZiASFcQhDE07TJRHxaJDzIfsGyOaz4SRfjegcfwYJiU7JHhlOuarb2J174PdKUr1WFTxSI HZV31H7f2K75flJZaslWO2FNRe/QXke6JakkUDf1bM7Z9fZHtcRLuoYSr1dCNu+K5OVEbPoo JTHPkrD3N9OO0urqzVjyPuOoIK7r9jsFM97nHNG7I3ZLU/vCgsu1d49lRvnTx/Z/DroCkga8 DtVdfoOzmOf7Qew5357hwzsnNWW8D0ejgSykPClxR4MtdaMthGuXVw/mbxmPmEn23xDeGees ejdpSfnXe2msYea2PnDbV8Pkw09DQoPE1sqNzgdlByaGxvfMRuPR25frP1aGX/dKyLSEtqov Rf3hOKAbarc+H59sirKNxXcsxwgISZrw1S24WCL8F1A8aJVKBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA02SbUwbdRzH87+73pXFjrNQvTAR1zhNMJS2K92/OtgComdIzPbCmWgIVjgL rA+zLTII7iEtKFBRGqdSYGXlaSPioCus3ehQRoBZ2XTQAhvtjGHEUgQJg4nbqi1osnef5Pv0 e/Fjo9x2VgK7SK1ntGq5ko9vwzzhUX8Kr6pOIXxw6yU4NmVDYN8DCwG/dV9HoHX4OgsGbjoQ OLm2jMPv7v5MwN/dJzHoO9tMQMPIeRwGLQEcrpgCLDhxqQmHq58NA9i/asRh97CfgOfXrAg8 s9KHwTbnJQCrqjtY8Jcfs6E/MIbB4IQJhVWWWPjPgJOAYV8vBhuXBgnoWKxnwdHut6Fx8Ets /7P08nQlQS8Ggxh99dN7BO1eb8Fol8VP0CbXT4C2d1Xj9KxvAKdPXztI36kdRegLbcdpY/cI Qn/+SEgvX/HidJ2jC9A3DVPEAe47gr1aTYmeea5Qo9On898VQbFAJIMCsUQmEO3ek/uyOI2f mrG3gFEWfcRoUzPeExTaetpYR3qyjja7KpET4OGeGhDDpkgJ1TOxiNaAbWwu2Q6o0FgI2xKe oXy1wf84jnroq8GjzCUXIqaWpCjjpJj6tdPKinI82YpR7itl0SKU/ANQUw29m+E4Mof6bf3G pgkjd1EDhjokyhxyH2VbqiS2BpKowR/G0SjHkPup+143sTW2j5r11oIt/5PUtYa5zU404jf0 NaJfANLymGR5TGoBSBeIZ0p0KoVKJxbo5CpdiVohyNeo7CDyL/0jGw4nOLewIhgCCBsMAYqN 8uM5vD9NCi6nQF5Wzmg1edoSJaMbAmmRu+vRBF6+JvJwan2eSCpME0mkMmGaTLqb/zQHn7zx AZdUyPXMYYY5wmj/zyHsmIQTSOLHpmKp0UMeUlmzXYdiG53TfCZxR8ob0lDDUW4pESz/RGm9 J1G++ddVta0oFPf16+a2C2bqYufkyfkK9dz6qlRy/7Rz5v2UrEfmpeCGfWcYkrlKdovslui2 8qtXZeVh11S2IqR8StsX7szJzJ55MfB35oHOJ6yWxKyMrNZW+/hcylus7lc6JvpnD64XZ6Yy AfP2ZM8xTxs6PVL2fZ4Qb/Lf3VEvOZ7vZvFs4/rkmcsFS7fJBe9ry97xcwOmO0kGizF2Ib1H 3SRZVJUers6tuGxx8DnY87L5jt6N9p3N6bvO6L+ppfxmT479VOn2smNrPLf8w7PFGxUX54Uv aPmYrlAuSka1Ovm/ELO5PbgDAAA= X-CMS-MailID: 20250120172125eucas1p141540607f423eea4c55b2bd22ff5adf0 X-Msg-Generator: CA X-RootMTR: 20250120172125eucas1p141540607f423eea4c55b2bd22ff5adf0 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250120172125eucas1p141540607f423eea4c55b2bd22ff5adf0 References: <20250120172111.3492708-1-m.wilczynski@samsung.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The T-Head TH1520 SoC contains multiple power islands that can be programmatically turned on and off using the AON (Always-On) protocol and a hardware mailbox [1]. The relevant mailbox driver has already been merged into the mainline kernel in commit 5d4d263e1c6b ("mailbox: Introduce support for T-head TH1520 Mailbox driver"); This commit introduces a power-domain driver for the TH1520 SoC, which is using AON firmware protocol to communicate with E902 core through the hardware mailbox. This way it can send power on/off commands to the E902 core. Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf [1] Signed-off-by: Michal Wilczynski --- MAINTAINERS | 1 + drivers/pmdomain/Kconfig | 1 + drivers/pmdomain/Makefile | 1 + drivers/pmdomain/thead/Kconfig | 12 ++ drivers/pmdomain/thead/Makefile | 2 + drivers/pmdomain/thead/th1520-pm-domains.c | 174 +++++++++++++++++++++ 6 files changed, 191 insertions(+) create mode 100644 drivers/pmdomain/thead/Kconfig create mode 100644 drivers/pmdomain/thead/Makefile create mode 100644 drivers/pmdomain/thead/th1520-pm-domains.c diff --git a/MAINTAINERS b/MAINTAINERS index c96a1e6c8831..363bb3471a33 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20195,6 +20195,7 @@ F: drivers/firmware/thead,th1520-aon.c F: drivers/mailbox/mailbox-th1520.c F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: drivers/pinctrl/pinctrl-th1520.c +F: drivers/pmdomain/thead/ F: include/dt-bindings/clock/thead,th1520-clk-ap.h F: include/dt-bindings/firmware/thead,th1520-aon.h F: include/linux/firmware/thead/thead,th1520-aon.h diff --git a/drivers/pmdomain/Kconfig b/drivers/pmdomain/Kconfig index 23c64851a5b0..91f04ace35d4 100644 --- a/drivers/pmdomain/Kconfig +++ b/drivers/pmdomain/Kconfig @@ -16,6 +16,7 @@ source "drivers/pmdomain/st/Kconfig" source "drivers/pmdomain/starfive/Kconfig" source "drivers/pmdomain/sunxi/Kconfig" source "drivers/pmdomain/tegra/Kconfig" +source "drivers/pmdomain/thead/Kconfig" source "drivers/pmdomain/ti/Kconfig" source "drivers/pmdomain/xilinx/Kconfig" diff --git a/drivers/pmdomain/Makefile b/drivers/pmdomain/Makefile index a68ece2f4c68..7030f44a49df 100644 --- a/drivers/pmdomain/Makefile +++ b/drivers/pmdomain/Makefile @@ -14,6 +14,7 @@ obj-y += st/ obj-y += starfive/ obj-y += sunxi/ obj-y += tegra/ +obj-y += thead/ obj-y += ti/ obj-y += xilinx/ obj-y += core.o governor.o diff --git a/drivers/pmdomain/thead/Kconfig b/drivers/pmdomain/thead/Kconfig new file mode 100644 index 000000000000..c7a1ac0c61dc --- /dev/null +++ b/drivers/pmdomain/thead/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config TH1520_PM_DOMAINS + tristate "Support TH1520 Power Domains" + depends on TH1520_AON_PROTOCOL || !TH1520_AON_PROTOCOL + select REGMAP_MMIO + help + This driver enables power domain management for the T-HEAD + TH-1520 SoC. On this SoC there are number of power domains, + which can be managed independently. For example GPU, NPU, + and DPU reside in their own power domains which can be + turned on/off. diff --git a/drivers/pmdomain/thead/Makefile b/drivers/pmdomain/thead/Makefile new file mode 100644 index 000000000000..adfdf5479c68 --- /dev/null +++ b/drivers/pmdomain/thead/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_TH1520_PM_DOMAINS) += th1520-pm-domains.o diff --git a/drivers/pmdomain/thead/th1520-pm-domains.c b/drivers/pmdomain/thead/th1520-pm-domains.c new file mode 100644 index 000000000000..d913ad40fb76 --- /dev/null +++ b/drivers/pmdomain/thead/th1520-pm-domains.c @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + * Copyright (c) 2024 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + */ + +#include +#include +#include +#include + +#include + +struct th1520_power_domain { + struct th1520_aon_chan *aon_chan; + struct generic_pm_domain genpd; + u32 rsrc; +}; + +struct th1520_power_info { + const char *name; + u32 rsrc; +}; + +static const struct th1520_power_info th1520_pd_ranges[] = { + { "vdec", TH1520_AON_VDEC_PD }, + { "npu", TH1520_AON_NPU_PD }, + { "venc", TH1520_AON_VENC_PD }, + { "gpu", TH1520_AON_GPU_PD }, + { "dsp0", TH1520_AON_DSP0_PD }, + { "dsp1", TH1520_AON_DSP1_PD } +}; + +static inline struct th1520_power_domain * +to_th1520_power_domain(struct generic_pm_domain *genpd) +{ + return container_of(genpd, struct th1520_power_domain, genpd); +} + +static int th1520_pd_power_on(struct generic_pm_domain *domain) +{ + struct th1520_power_domain *pd = to_th1520_power_domain(domain); + + return th1520_aon_power_update(pd->aon_chan, pd->rsrc, true); +} + +static int th1520_pd_power_off(struct generic_pm_domain *domain) +{ + struct th1520_power_domain *pd = to_th1520_power_domain(domain); + + return th1520_aon_power_update(pd->aon_chan, pd->rsrc, false); +} + +static struct generic_pm_domain *th1520_pd_xlate(const struct of_phandle_args *spec, + void *data) +{ + struct generic_pm_domain *domain = ERR_PTR(-ENOENT); + struct genpd_onecell_data *pd_data = data; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(th1520_pd_ranges); i++) { + struct th1520_power_domain *pd; + + pd = to_th1520_power_domain(pd_data->domains[i]); + if (pd->rsrc == spec->args[0]) { + domain = &pd->genpd; + break; + } + } + + return domain; +} + +static struct th1520_power_domain * +th1520_add_pm_domain(struct device *dev, const struct th1520_power_info *pi) +{ + struct th1520_power_domain *pd; + int ret; + + pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); + if (!pd) + return ERR_PTR(-ENOMEM); + + pd->rsrc = pi->rsrc; + pd->genpd.power_on = th1520_pd_power_on; + pd->genpd.power_off = th1520_pd_power_off; + pd->genpd.name = pi->name; + + ret = pm_genpd_init(&pd->genpd, NULL, true); + if (ret) + return ERR_PTR(ret); + + return pd; +} + +static void th1520_pd_init_all_off(struct generic_pm_domain **domains, + struct device *dev) +{ + int ret; + int i; + + for (i = 0; i < ARRAY_SIZE(th1520_pd_ranges); i++) { + struct th1520_power_domain *pd = + to_th1520_power_domain(domains[i]); + + ret = th1520_aon_power_update(pd->aon_chan, pd->rsrc, false); + if (ret) + dev_err(dev, + "Failed to initially power down power domain %s\n", + pd->genpd.name); + } +} + +static int th1520_pd_probe(struct platform_device *pdev) +{ + struct generic_pm_domain **domains; + struct genpd_onecell_data *pd_data; + struct th1520_aon_chan *aon_chan; + struct device *dev = &pdev->dev; + int i; + + aon_chan = dev_get_drvdata(dev->parent); + if (!aon_chan) { + dev_err(dev, "Failed to get AON channel from parent\n"); + return -EINVAL; + } + + domains = devm_kcalloc(dev, ARRAY_SIZE(th1520_pd_ranges), + sizeof(*domains), GFP_KERNEL); + if (!domains) + return -ENOMEM; + + pd_data = devm_kzalloc(dev, sizeof(*pd_data), GFP_KERNEL); + if (!pd_data) + return -ENOMEM; + + for (i = 0; i < ARRAY_SIZE(th1520_pd_ranges); i++) { + struct th1520_power_domain *pd; + + pd = th1520_add_pm_domain(dev, &th1520_pd_ranges[i]); + if (IS_ERR(pd)) + return PTR_ERR(pd); + + pd->aon_chan = aon_chan; + domains[i] = &pd->genpd; + dev_dbg(dev, "added power domain %s\n", pd->genpd.name); + } + + pd_data->domains = domains; + pd_data->num_domains = ARRAY_SIZE(th1520_pd_ranges); + pd_data->xlate = th1520_pd_xlate; + + /* + * Initialize all power domains to off to ensure they start in a + * low-power state. This allows device drivers to manage power + * domains by turning them on or off as needed. + */ + th1520_pd_init_all_off(domains, dev); + + return of_genpd_add_provider_onecell(dev->parent->of_node, pd_data); +} + +static struct platform_driver th1520_pd_driver = { + .driver = { + .name = "th1520-pd", + }, + .probe = th1520_pd_probe, +}; +module_platform_driver(th1520_pd_driver); + +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_DESCRIPTION("T-HEAD TH1520 SoC power domain controller"); +MODULE_LICENSE("GPL"); From patchwork Mon Jan 20 17:20:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13945309 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C057DC02182 for ; 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Mon, 20 Jan 2025 17:21:27 +0000 (GMT) X-AuditID: cbfec7f5-ed1d670000004fad-4c-678e86178917 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id ED.C8.19920.6168E876; Mon, 20 Jan 2025 17:21:27 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250120172125eusmtip1758d65ab598a3e22c766c4e95e43e656~cdlohfgLz0708407084eusmtip1n; Mon, 20 Jan 2025 17:21:25 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC v3 06/18] riscv: Enable PM_GENERIC_DOMAINS for T-Head SoCs Date: Mon, 20 Jan 2025 18:20:59 +0100 Message-Id: <20250120172111.3492708-7-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250120172111.3492708-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02SfUxTVxiHOffe3tt2q14LrmcgUzEzEyeoY/HMyVYNy27C/gBZtqBboMhN raPAWmCbMQoBqmJxihSyFgWbCpXByLCtwMQqYguo1fFVFmxHDGarQRnyJRJw0Iub/z3nfX/v ec6bHD4utpDBfEV6FqtKl6WFkULC5phxbZJoTso3D1tDUIfbiCHrrJ5Cda0uDFW2u3jI223B UO/kKIl+eXiPQn+35hGo33yWQvmOBhL59F4SjWm9PNTTUkGi8eJ2gGzjBSSqb/dQqGGyEkPn x6wEMjW1AKQ5Xs1Dv3d9gjzeDgL5erQ40uiXoxdXmig03/8rgQxP7BSyjJzmIWf9l6jAXkpI 32JGBwopZsTnI5gbxyYopnWqimCa9R6K0TbfBkxj7XGSud9/hWTOdcYzf55wYswl0xGmoN6B MT/ObWZGr/aRzElLLWC6891UnHiPcEcqm6bIYVWRHyUL99+01eGZpYLvC8rrqFxwiyoCAj6k o+CortPPYtoM4KVqUREQLvAEgB2VNpJrjAN4vg5/OdB5tozHhWoAvKt5QHChEQD1E8wik/RW OFRT6Q8F0YUELLyZBxYPOP0XgLbhCv+1gTQDPUft/msJ+m1ovzGCLbKI/hg23jMu6VZD+/U7 fhbQUjjd10pxmRWw86dhvxlfyORbDfiiANIXhTCvs4TghmOgtsFEchwIHzktS0uvgi+aKzGO M+CQ9emS7BBs1jqX+EN43/V8YZa/INgAG1oiufJOWDXlIBbLkF4GBx6v4J6wDJbYynGuLILH NGIuvR7qtMX/SV1mG8ZFGDhds/EUWKt/ZRf9K7vo/9dWAbwWSNhstVLOqt9LZ7+LUMuU6ux0 ecS+DGUjWPjYt+adk03A/Ggsog1gfNAGIB8PCxKt/EcrF4tSZT8cZFUZSarsNFbdBkL4RJhE ZLQXysW0XJbFfsOymazqZRfjC4JzMcnPu97ZvTbtt8MxXbl5y4e3KgcvnxIVxBYfTDBrQp7Y PVF7Zx4Hl885dhq7hXEV2669lr83vKTrstG7biJkR1Ts4eRV0dHzf8w+XTc0177dFLrFHf2+ Ii58n67o86zJ+F131WcU0ZkK38OVxYaS0k0VVUTkV9V3YkNz1ggCUnm4JGsg5YDr6pt7LBsw 44MUa+jtFG/0kQsSCTpwQvEGzYtxmtd8mjtoSjLpykTPdeK+cwFZU33bv74mNYwZEuMz3IMf fLtaTwT2Rm7r7XEdsn02HWSWNkVoZr4ImElU1rTGrr9ehr2b7xuLcs+qn8XUJ7DxR09TGxOT S3N2J0i7n73ekxRGqPfLtoTjKrXsXxK41F9HBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGKsWRmVeSWpSXmKPExsVy+t/xu7ribX3pBq8+MVmcuL6IyWLr71ns Fmv2nmOymH/kHKvFvUtbmCyufH3PZrHu6QV2ixd7G1ksrq2Yy27RfGw9m8XLWffYLD723GO1 uLxrDpvF594jjBbbPrewWaw9cpfdYv3X+UwWCz9uZbFYsmMXo0Vb5zJWi4unXC3u3jvBYvHy cg+zRdssfov/e3awW/y7tpHFYva7/ewWW95MZLU4vjbcomX/FBYHOY/3N1rZPd68fMnicbjj C7vH3m8LWDx2zrrL7tGz8wyjx6ZVnWwed67tYfOYdzLQ4373cSaPzUvqPVrWHmPy6P9r4PF+ 31U2j74tqxg9LjVfZw8QitKzKcovLUlVyMgvLrFVija0MNIztLTQMzKx1DM0No+1MjJV0rez SUnNySxLLdK3S9DLOLptDXPBFM6Klulr2BsYT7N3MXJySAiYSJycO421i5GLQ0hgKaPE6nWH mSESMhLXul+yQNjCEn+udbFBFL1ilHi/YgoTSIJNwEjiwfL5rCC2iMBiFom9+ypBipgF3jJK XJ+5EaxbWMBD4m77frCpLAKqEvsPvwFr5hWwl9h0YRHUNnmJ/QfPgtmcAg4S36/uBTtPCKjm ztVuRoh6QYmTM5+AzWQGqm/eOpt5AqPALCSpWUhSCxiZVjGKpJYW56bnFhvqFSfmFpfmpesl 5+duYgQmmG3Hfm7ewTjv1Ue9Q4xMHIyHGCU4mJVEeEU/9KQL8aYkVlalFuXHF5XmpBYfYjQF unsis5Rocj4wxeWVxBuaGZgamphZGphamhkrifO6XT6fJiSQnliSmp2aWpBaBNPHxMEp1cC0 9fJ+PbM8HZZ9Z3d4Cc8y758/5dYigR8xzbP3hm0T4s51PPNssu3364EhpqsywpVqlMI0m/+X 3TqsOrvL+abx7cKr0xInpBvpr45s2pu6yTX3f1DeoutnF2dnnL/j9cPhx3ettxM760oW6Wbo MfbaXU48mMkSvsVca+Pm7j4mn/sdbxrEXMT0lVPdVlUb3nigziD0z/tJdidj01zbPp+c1arx H86wf8gqNZnxKrDg6bNgzdPCjEmRaddb10335zu2p1RUM7NbO8aTzzvvhP9nBqkci3QGw7qr j8ImFe1jcg7b0LyH52qfV7nZajGVQ5rpT1dNVjdtq+64eCny5QvtANfTT6Rtp0l9b049osRS nJFoqMVcVJwIAN4Rz1i5AwAA X-CMS-MailID: 20250120172127eucas1p18a33aa80018ff77317c7f02cf94f8e79 X-Msg-Generator: CA X-RootMTR: 20250120172127eucas1p18a33aa80018ff77317c7f02cf94f8e79 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250120172127eucas1p18a33aa80018ff77317c7f02cf94f8e79 References: <20250120172111.3492708-1-m.wilczynski@samsung.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" T-Head SoCs feature separate power domains (power islands) for major components like the GPU, Audio, and NPU. To manage the power states of these components effectively, the kernel requires generic power domain support. This commit enables `CONFIG_PM_GENERIC_DOMAINS` for T-Head SoCs, allowing the power domain driver for these components to be compiled and integrated. This ensures proper power management and energy efficiency on T-Head platforms. By selecting `PM_GENERIC_DOMAINS`, we provide the necessary framework for the power domain drivers to function correctly on RISC-V architecture with T-Head SoCs. Signed-off-by: Michal Wilczynski --- arch/riscv/Kconfig.socs | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index f51bb24bc84c..c414dc618b66 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -48,6 +48,7 @@ config ARCH_THEAD bool "T-HEAD RISC-V SoCs" depends on MMU && !XIP_KERNEL select ERRATA_THEAD + select PM_GENERIC_DOMAINS if PM help This enables support for the RISC-V based T-HEAD SoCs. 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Mon, 20 Jan 2025 17:21:27 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC v3 07/18] dt-bindings: reset: Add T-HEAD TH1520 SoC Reset Controller Date: Mon, 20 Jan 2025 18:21:00 +0100 Message-Id: <20250120172111.3492708-8-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250120172111.3492708-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Se0xTZxjG+c45PefQrHooLHxhC7p62RQFdP7xjZEJCbIvMZjpbmQXXTdO ipGLtsI2XKZcg67cGt1G6SgwNgiChK603AoZt4JoM2FCTQBxlkAbNixUmTJglNbN/57nfX/v 97xv8rGkuIUOYk+mnOXlKdIkCS2kDP2PLXthXqEs3DmzDw2MVRGoeVnNoHqThUDaXosATQ7r CfT7w3kaXZv+jUGzpkwKjdb+wKDs/kYa2dWTNHIqJwVopE1Do8WCXoAMizk0auidYFDjQy2B Kp3NFKpuaQMo7+LPAnTr+iE0MTlAIfuIkkR56s1oraOFQaujTRQq+6uLQfq5EgEyN7yPcrou U1HBeN6ay+A5u53CPfkuBpseVVC4VT3BYGXrDYB1dRdpPD7aQePywaP47jdmAv9SfR7nNPQT uGglHM933qZxob4O4OHsMeYt8QfCyAQ+6WQ6Lw974xNh4g29DZzWib8orZ4mLwDV5kvAl4Xc AXjLoaYuASEr5moBLOpTCzzGBWDbioHwmEUAzaofBU9Hlm0mL1UD4EybkfaYOQC/z1ncoGhu P5yq0W5QAVwuBXP7MoHbkNwMgAabhnZT/tw7UDPwZENT3A54daEduLWIOwjrm43evC2w69eb pFv7clFw6baJ8TB+cLDURrk1uc5kN5eR7gDINQmhfbac8AzHwPb2Iu9D/tBh1jMe/SJca9V6 mVQ41bxAevRXsFVp9urX4bjFvRy7HrALNraFecrRsFN/hXGXIbcJWv/086ywCaoM35Gesgjm 54k99E54RVnwX6il1uANxTBfZyWKwUvqZ45RP3OM+v/cCkDWgUA+TZEs4xX7U/jPQxXSZEVa iiz0s9RkHVj/3EOrZlcLqHE4Q7sBwYJuAFlSEiB6/oFSJhYlSL/M4OWpJ+RpSbyiG7zAUpJA UVVXrkzMyaRn+VM8f5qXP+0SrG/QBSLyVewIDS8s5rRr8RX32/fuCJEUyaI/ZI7s0QQtiXz7 sDVEkFJes8uY8+A5+Icg2Hqk0TVVnq5la2J1nOrlEv+l1Ujh4EfndmYGflqiGlaP2c+EaXoe rbw5dC+E0Z6fKdk+YvTriYs/FX9iOCvBaOWTsoLj3o0NvVfoU5x+/agjC9//qWko05ZxtaRg +K7k8DmbD/vP9PGvDy0e3hpjqQsMSSLTIgocsY+3VB6LHhj59ljQa5Wu9Fc6th9ciDuePVuf +MRnt2+0qytvLvZamWbbe86qO4bxjIhSU5o///EZ4zbsn3En2OeAqfBvNmBGvAx6dBFRN8Hb uk5uK3bG7AmUUIpE6b7dpFwh/RcLWxw0SwQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGKsWRmVeSWpSXmKPExsVy+t/xu7oSbX3pBgceiFqcuL6IyWLr71ns Fmv2nmOymH/kHKvFvUtbmCyufH3PZrHu6QV2ixd7G1ksrq2Yy27RfGw9m8XLWffYLD723GO1 uLxrDpvF594jjBbbPrewWaw9cpfdYv3X+UwWCz9uZbFYsmMXo0Vb5zJWi4unXC3u3jvBYvHy cg+zRdssfov/e3awW/y7tpHFYva7/ewWW95MZLU4vjbcomX/FBYHOY/3N1rZPd68fMnicbjj C7vH3m8LWDx2zrrL7tGz8wyjx6ZVnWwed67tYfOYdzLQ4373cSaPzUvqPVrWHmPy6P9r4PF+ 31U2j74tqxg9LjVfZw8QitKzKcovLUlVyMgvLrFVija0MNIztLTQMzKx1DM0No+1MjJV0rez SUnNySxLLdK3S9DLOLPlCWPBJqGKmUueMjcwTuLvYuTkkBAwkfj9ZC9rFyMXh5DAUkaJM3/6 mCASMhLXul+yQNjCEn+udbFBFL1ilHjVOIsVJMEmYCTxYPl8MFtEYDGLxN59lSBFzAJvGSWu z9wI1i0sECRx6eohZhCbRUBVYvWn3YwgNq+AvcSardtZITbIS+w/eBashlPAQeL71b3sILYQ UM2dq91Q9YISJ2c+AZvJDFTfvHU28wRGgVlIUrOQpBYwMq1iFEktLc5Nzy020itOzC0uzUvX S87P3cQITDDbjv3csoNx5auPeocYmTgYDzFKcDArifCKfuhJF+JNSaysSi3Kjy8qzUktPsRo CnT3RGYp0eR8YIrLK4k3NDMwNTQxszQwtTQzVhLnZbtyPk1IID2xJDU7NbUgtQimj4mDU6qB qSrwJSvr9bcV5iHBtiy7/KdmrTMTfL8l/7t64Naa5bsdLpg/eeXGEdD6d4GVWuac6xciH+80 Nnt3w5ijuVTtT1b4vo6d/2I4kr/xXja6ULerZnFB+AS3NQUXd6+aeZfpp6+6qdECa/WJO54p b17LeD3OKqD+YmPb816eKuv5ibJ8e1j3d26f63z75uenf488+vxBUOCkUMRxtWVxO9hWHprh xFC2PSNIPEPuyyu7V685jrZeeO9wOrJSbf/yGH+93GCPxVM+unyUTy379WQz6/U7MxjEqvJf vFARtA9gD312rU5glcIXHsWIH6d0Z9rdWj1v3qYL68qMWX10Njhf2f7aaNaUFSyZpiEHRE/P OqDEUpyRaKjFXFScCADlvV6auQMAAA== X-CMS-MailID: 20250120172128eucas1p2847f0863524b53d2d5029e5e9d238298 X-Msg-Generator: CA X-RootMTR: 20250120172128eucas1p2847f0863524b53d2d5029e5e9d238298 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250120172128eucas1p2847f0863524b53d2d5029e5e9d238298 References: <20250120172111.3492708-1-m.wilczynski@samsung.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a YAML schema for the T-HEAD TH1520 SoC reset controller. This controller manages resets for subsystems such as the GPU within the TH1520 SoC. Signed-off-by: Michal Wilczynski --- .../bindings/reset/thead,th1520-reset.yaml | 44 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml diff --git a/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml new file mode 100644 index 000000000000..c15a80e00935 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/thead,th1520-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD TH1520 SoC Reset Controller + +description: + The T-HEAD TH1520 reset controller is a hardware block that asserts/deasserts + resets for SoC subsystems. + +maintainers: + - Michal Wilczynski + +properties: + compatible: + enum: + - thead,th1520-reset + + reg: + maxItems: 1 + + "#reset-cells": + const: 0 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + rst: reset-controller@ffef528000 { + compatible = "thead,th1520-reset"; + reg = <0xff 0xef528000 0x0 0x1000>; + #reset-cells = <0>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 363bb3471a33..1b6e894500ef 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20189,6 +20189,7 @@ F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml F: Documentation/devicetree/bindings/mailbox/thead,th1520-mbox.yaml F: Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml +F: Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml F: arch/riscv/boot/dts/thead/ F: drivers/clk/thead/clk-th1520-ap.c F: drivers/firmware/thead,th1520-aon.c From patchwork Mon Jan 20 17:21:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13945306 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DD365C02181 for ; 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Mon, 20 Jan 2025 17:21:29 +0000 (GMT) X-AuditID: cbfec7f4-c39fa70000004fb9-d0-678e861a990b Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 5F.95.19654.9168E876; Mon, 20 Jan 2025 17:21:29 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250120172128eusmtip1632a5aa33c614fcf0e348d989c2d4acf~cdlq_7Oca0819408194eusmtip1q; Mon, 20 Jan 2025 17:21:28 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC v3 08/18] reset: thead: Add TH1520 reset controller driver Date: Mon, 20 Jan 2025 18:21:01 +0100 Message-Id: <20250120172111.3492708-9-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250120172111.3492708-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02SbUxTVxjHd+69vbcQC5fC4IwZiESJoCvgnDl7yYQ4yNHMxLkPRD+I3bwp yJu2gtPohgNqcRUFX3ClyEtRCAhEKAwIrMiwiIOGwUCXAIMJdCVlFVrc5rCMcuvmt9//ef7P +T9PcoSk+Ds6UJiUdoKTp0lTQmhPqsX4t+mtQGW+LHL0rgA9eFRBoOZ/NAy602kiUGmPSYAm hvQE+nnJRqP6mUEG/d55jkKj1SUMyjY20MiimaDRgnpCgIbbtTSyX+wBqMWeQ6O6nnEGNSyV Eqh8oZlCla3tACnzbgvQTw9j0fjEAwpZhtUkUmq80UpHK4Oco3cpVPyHgUF6a4EA9dbFoxzD VSo6CNse5zLYarFQ+AeVg8Gdz8oo3KYZZ7C6rR/gxpo8Go+NdtD4Zt8n+NdvegncVPkVzqkz EvjSi0hs+36Exvn6GoCHsh8x+8QHPT84wqUkZXLyiA8PeyY6bL8Rx5a3f9Fkr2eygGHrBeAh hOx2uFJUzFwAnkIxWw3gdPGwWzgAnNE9FfDCDuBU+S/kyxFHVpPbVQVg/62HFC+sAHY5lZTL RbPb4GRV6dq4H5tLwdz754BLkKwZwJZpLe1y+bIYGke6CRdT7Ca48OwJcLGI3Qk7dWaKzwuG hnsDa9kebDT8c6ST4T0+sO/b6TUPuerJbi5271fnCbtrA3n+CLYPvgA8+8K5Xj3D83q40lZK 8JwOJ5sX3bNnYJu6183vwzHT89U9havvh8GG9gi+HANzvr5KusqQ9YKP5334DbxgYUuRuyyC KqWYd4fCa+qL/4WaqlvcoRiWGbX0ZbBB88otmldu0fyfWwbIGhDAZShSZZxiWxp3UqKQpioy 0mSSz9NTG8Hq3/7R2etoBVVzC5JuQAhBN4BCMsRP9PpTtUwsOiI9dZqTpyfIM1I4RTd4U0iF BIgqDLkyMSuTnuCSOe4YJ3/ZJYQegVlExfz9Hb5Ho29yZeF56PgZ8cfxFQXka6HWS9JTyQfP 3zJ4R0gVsT6Ty0TfkgqHxVm3KPwv/xWqsUeGX3m+GPflemlQ7WepziT1e1NndadnP51xXtu8 3GFhd0vHSqwqS3oUjgq+vjWuxMu8wzG/LvOoJLQQe1vgxs0281x8QUr5bd3+TaK0k9otu5rt U0Hle95eOWQa2OVdP+Z/3HQ+Kk4zuyHmcOPu9C5xqUVvLFTd2Fi8cy8dcOVsbKWvqDbT73qC 18y6e8H5s8mF+9/pSoyUqDwI5Z2ExndD6v33VugKnmj7Y7SLWeZRXbJtsOlG2AHfooEhMtap 9YvbM7HPJnljIYRSJEqjwkm5QvovuSvx6koEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKKsWRmVeSWpSXmKPExsVy+t/xu7qSbX3pBv2rNC1OXF/EZLH19yx2 izV7zzFZzD9yjtXi3qUtTBZXvr5ns1j39AK7xYu9jSwW11bMZbdoPraezeLlrHtsFh977rFa XN41h83ic+8RRottn1vYLNYeuctusf7rfCaLhR+3slgs2bGL0aKtcxmrxcVTrhZ3751gsXh5 uYfZom0Wv8X/PTvYLf5d28hiMfvdfnaLLW8mslocXxtu0bJ/CouDnMf7G63sHm9evmTxONzx hd1j77cFLB47Z91l9+jZeYbRY9OqTjaPO9f2sHnMOxnocb/7OJPH5iX1Hi1rjzF59P818Hi/ 7yqbR9+WVYwel5qvswcIRenZFOWXlqQqZOQXl9gqRRtaGOkZWlroGZlY6hkam8daGZkq6dvZ pKTmZJalFunbJehlfHn/iKngj0nF5s/r2BsY9+t0MXJySAiYSHxp2MwOYgsJLGWUaPqUDxGX kbjW/ZIFwhaW+HOti62LkQuo5hWjxK49c5hAEmwCRhIPls9nBbFFBBazSOzdVwlSxCzwllHi +syNYN3CAh4Sx64eAmtgEVCV+PjtMSOIzStgL7F38XOoDfIS+w+eZQaxOQUcJL5f3Qt1kb3E navdUPWCEidnPgGrZwaqb946m3kCo8AsJKlZSFILGJlWMYqklhbnpucWG+kVJ+YWl+al6yXn 525iBKaXbcd+btnBuPLVR71DjEwcjIcYJTiYlUR4RT/0pAvxpiRWVqUW5ccXleakFh9iNAW6 eyKzlGhyPjDB5ZXEG5oZmBqamFkamFqaGSuJ87JdOZ8mJJCeWJKanZpakFoE08fEwSnVwCR8 Q+/b6XUrg2ZNv+ITdaHDPDn3/Z20NuXgvSwPd13pWN96SrmMkdHMIml7hHKAx/+Dkdc+VAVu jQzaq2BzfKHMZyEt29TTT5bZbN3UfdrJ/smU3l//pzVWSMX7+EpJGXdOyVLT3uXy3mDLiioV JeYpxnEPoyb82TFjW4jNm5NSISatZTM3fF83ha3Z3qL47c+HMlMv+JqIHa5b3eA2yZhz+gSN kLC+p2nKYZ4P6y/fMW/8f2fOIr3DR3i3l6nfLucSfZb8xVmt4uOU79asc1bfPHIjRyIi49pf Q/XEHVfz/qyM3xcmK2DtZNrs96l84yHNLYmqZryTjT8H31nnc6nmDWOIspPQlNtvLdyfGCqx FGckGmoxFxUnAgBEeIX3uAMAAA== X-CMS-MailID: 20250120172129eucas1p236f71df4e30f821f7682263ee8ecec06 X-Msg-Generator: CA X-RootMTR: 20250120172129eucas1p236f71df4e30f821f7682263ee8ecec06 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250120172129eucas1p236f71df4e30f821f7682263ee8ecec06 References: <20250120172111.3492708-1-m.wilczynski@samsung.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Introduce reset controller driver for the T-HEAD TH1520 SoC. The controller manages hardware reset lines for various SoC subsystems, such as the GPU. By exposing these resets via the Linux reset subsystem, drivers can request and control hardware resets to reliably initialize or recover key components. Signed-off-by: Michal Wilczynski --- MAINTAINERS | 1 + drivers/reset/Kconfig | 10 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-th1520.c | 144 +++++++++++++++++++++++++++++++++++ 4 files changed, 156 insertions(+) create mode 100644 drivers/reset/reset-th1520.c diff --git a/MAINTAINERS b/MAINTAINERS index 1b6e894500ef..18382a356b12 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20197,6 +20197,7 @@ F: drivers/mailbox/mailbox-th1520.c F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: drivers/pinctrl/pinctrl-th1520.c F: drivers/pmdomain/thead/ +F: drivers/reset/reset-th1520.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h F: include/dt-bindings/firmware/thead,th1520-aon.h F: include/linux/firmware/thead/thead,th1520-aon.h diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 5b3abb6db248..fa0943c3d1de 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -272,6 +272,16 @@ config RESET_SUNXI help This enables the reset driver for Allwinner SoCs. +config RESET_TH1520 + tristate "T-HEAD 1520 reset controller" + depends on ARCH_THEAD || COMPILE_TEST + select REGMAP_MMIO + help + This driver provides support for the T-HEAD TH1520 SoC reset controller, + which manages hardware reset lines for SoC components such as the GPU. + Enable this option if you need to control hardware resets on TH1520-based + systems. + config RESET_TI_SCI tristate "TI System Control Interface (TI-SCI) reset driver" depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n) diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 677c4d1e2632..d6c2774407ae 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o +obj-$(CONFIG_RESET_TH1520) += reset-th1520.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o obj-$(CONFIG_RESET_TI_TPS380X) += reset-tps380x.o diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c new file mode 100644 index 000000000000..e4278f49c62f --- /dev/null +++ b/drivers/reset/reset-th1520.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + */ + +#include +#include +#include +#include + + /* register offset in VOSYS_REGMAP */ +#define TH1520_GPU_RST_CFG 0x0 +#define TH1520_GPU_RST_CFG_MASK GENMASK(2, 0) + +/* register values */ +#define TH1520_GPU_SW_GPU_RST BIT(0) +#define TH1520_GPU_SW_CLKGEN_RST BIT(1) + +struct th1520_reset_priv { + struct reset_controller_dev rcdev; + struct regmap *map; +}; + +static inline struct th1520_reset_priv * +to_th1520_reset(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct th1520_reset_priv, rcdev); +} + +static void th1520_rst_gpu_enable(struct regmap *reg) +{ + int val; + + /* if the GPU is not in a reset state it, put it into one */ + regmap_read(reg, TH1520_GPU_RST_CFG, &val); + if (val) + regmap_update_bits(reg, TH1520_GPU_RST_CFG, + TH1520_GPU_RST_CFG_MASK, 0x0); + + /* rst gpu clkgen */ + regmap_set_bits(reg, TH1520_GPU_RST_CFG, TH1520_GPU_SW_CLKGEN_RST); + + /* + * According to the hardware manual, a delay of at least 32 clock + * cycles is required between de-asserting the clkgen reset and + * de-asserting the GPU reset. Assuming a worst-case scenario with + * a very high GPU clock frequency, a delay of 1 microsecond is + * sufficient to ensure this requirement is met across all + * feasible GPU clock speeds. + */ + udelay(1); + + /* rst gpu */ + regmap_set_bits(reg, TH1520_GPU_RST_CFG, TH1520_GPU_SW_GPU_RST); +} + +static void th1520_rst_gpu_disable(struct regmap *reg) +{ + regmap_update_bits(reg, TH1520_GPU_RST_CFG, TH1520_GPU_RST_CFG_MASK, 0x0); +} + +static int th1520_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct th1520_reset_priv *priv = to_th1520_reset(rcdev); + + th1520_rst_gpu_disable(priv->map); + + return 0; +} + +static int th1520_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct th1520_reset_priv *priv = to_th1520_reset(rcdev); + + th1520_rst_gpu_enable(priv->map); + + return 0; +} + +static int th1520_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + return 0; +} + +static const struct reset_control_ops th1520_reset_ops = { + .assert = th1520_reset_assert, + .deassert = th1520_reset_deassert, +}; + +static const struct regmap_config th1520_reset_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .fast_io = true, +}; + +static int th1520_reset_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct th1520_reset_priv *priv; + void __iomem *base; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + priv->map = devm_regmap_init_mmio(dev, base, + &th1520_reset_regmap_config); + if (IS_ERR(priv->map)) + return PTR_ERR(priv->map); + + priv->rcdev.owner = THIS_MODULE; + priv->rcdev.nr_resets = 1; + priv->rcdev.ops = &th1520_reset_ops; + priv->rcdev.of_node = dev->of_node; + priv->rcdev.of_xlate = th1520_reset_xlate; + + return devm_reset_controller_register(dev, &priv->rcdev); +} + +static const struct of_device_id th1520_reset_match[] = { + { .compatible = "thead,th1520-reset" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, th1520_reset_match); + +static struct platform_driver th1520_reset_driver = { + .driver = { + .name = "th1520-reset", + .of_match_table = th1520_reset_match, + }, + .probe = th1520_reset_probe, +}; +module_platform_driver(th1520_reset_driver); + +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_DESCRIPTION("T-HEAD TH1520 SoC reset controller"); +MODULE_LICENSE("GPL"); From patchwork Mon Jan 20 17:21:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13945313 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E8B9AC02185 for ; Mon, 20 Jan 2025 17:21:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3905A10E471; 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Mon, 20 Jan 2025 17:21:29 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC v3 09/18] drm/imagination: Add reset controller support for GPU initialization Date: Mon, 20 Jan 2025 18:21:02 +0100 Message-Id: <20250120172111.3492708-10-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250120172111.3492708-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01Sf0xbVRj1vvf6XlstPAqTKxDGmogZicA2TW7iVEy27CU6dZhoxERXx7Ms QGEt4BibtmlhWykTxha0MIoDoRCBgbThR7GIQFec1YFlNRvd5nBYVtcx6ABxIOWh7r/zfefc c76TXD4uNpNR/IPyPFYhl2ZJSCFhGVlyPhtTckqWPKYWoYtXzmPIvGyg0Nf9TgwZh5w85Bnr wtAvAT+J2n7/mUJ/9KsJNGE6RyHNSDuJvAYPiWb1Hh4a760h0VzZEECWOS2JWocmKdQeMGLo y1kzgRq6ewEqOdnIQ5dHd6NJz0UCecf1OCoxhKJVazeFViY6CFR910ahLl8FD9lb30Fa2xki JZbxu4spxuf1Esz3J+Yppv9BHcH0GCYpRt9zCTCdLSdJ5tqElWRqHfuY66V2jPmm4VNG2zqC MZ89TGb837pI5lRXC2DGNFeoN8Vpwp3pbNbBAlaR9NJ+YUaTaZLIdWw5PKfdowKr0TrA50P6 Obhy/CMdEPLFtAlAx1UPwQ3zAC5qvwLcMLfG1NdSOiBYf/Gr48yGqgnApalKiht8AN7pLOcF VSS9Hd5oMvKCRARdTMDiYfW6F05PA2iZqiGDqnD6fVjReXXdl6CfhvPVViyIRXQKbFb3AS5v M7R99yMexIK1/YKrn+I0YdDxxRQRxPiaRmOuxoMBkG4VQtN8G4+rtwv+XS7ifMLhjL1ro0MM XO0xYhzOgTfM93EOH4U9evsGfgFec/5FBm1weits703i1q/Aqt+uU5x7CHT/GcZdEAJPW6pw bi2CJ0rEnDoentWX/RfqNFk2Qhl4tu4yXg62GB7pYniki+H/3DqAt4BINl+ZLWOVO+Tsx4lK abYyXy5LPJCT3QnWfvYPK/ZANzDNzCYOAowPBgHk45II0aZ7eplYlC4tPMIqcj5Q5GexykEQ zSckkaLztmKZmJZJ89hMls1lFf+yGF8QpcIaCwIDTzZPE9apXmeH6Pat6KLM0/EL7Z8f2prp 2u41ZKTEPdSNp0elWS7scEqwviRRc+NwpTm1eUFWL5xTVRS920fulh2z7ZzpyGOGPZFFYYcj kv3uu7xxOrS3sT7Vtdftzl6+0FYfHuJ6am/svVzNh1aQOVMW6xPEx+GV594YaHiw6jI+rkB3 bt1Pf97wcnRi3wE1kRP6etM2VcIz6vIXS30ltYs3w0Uxs098ctPGHHIWCtkVVxkh5useK51W DSRkb56tmU99u8p2bHCTNU35XmFN/B7/voD/UtztfPHk8qtHCgRHh/fv0hiiLZik6CfXqFzu fksVtpSTd3x08TUJocyQbkvAFUrpP6TLE1JIBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKKsWRmVeSWpSXmKPExsVy+t/xu7rSbX3pBtd26FqcuL6IyWLr71ns Fmv2nmOymH/kHKvFvUtbmCyufH3PZrHu6QV2ixd7G1ksrq2Yy27RfGw9m8XLWffYLD723GO1 uLxrDpvF594jjBbbPrewWaw9cpfdYv3X+UwWCz9uZbFYsmMXo0Vb5zJWi4unXC3u3jvBYvHy cg+zRdssfov/e3awW/y7tpHFYva7/ewWW95MZLU4vjbcomX/FBYHOY/3N1rZPd68fMnicbjj C7vH3m8LWDx2zrrL7tGz8wyjx6ZVnWwed67tYfOYdzLQ4373cSaPzUvqPVrWHmPy6P9r4PF+ 31U2j74tqxg9LjVfZw8QitKzKcovLUlVyMgvLrFVija0MNIztLTQMzKx1DM0No+1MjJV0rez SUnNySxLLdK3S9DLWL7iLkvBScWKzy3uDYz/pbsYOTkkBEwkbp6cwtLFyMUhJLCUUeL24Ufs EAkZiWvdL1kgbGGJP9e62CCKXjFKXF6zhxEkwSZgJPFg+XxWEFtEYDGLxN59lSBFzAJvGSWu z9wI1i0sECNxuOEd2FQWAVWJL7P3MIHYvAIOEisbdzNCbJCX2H/wLDOIzQkU/351L1i9kIC9 xJ2r3YwQ9YISJ2c+AZvJDFTfvHU28wRGgVlIUrOQpBYwMq1iFEktLc5Nzy020itOzC0uzUvX S87P3cQITC/bjv3csoNx5auPeocYmTgYDzFKcDArifCKfuhJF+JNSaysSi3Kjy8qzUktPsRo CnT3RGYp0eR8YILLK4k3NDMwNTQxszQwtTQzVhLnZbtyPk1IID2xJDU7NbUgtQimj4mDU6qB aVfd7kn9Mv15J82WmJ++dPmqxjwpxp6e/P+JawWblk3/5Pl267V3lvNULk1VKXbWtb7dKlFv voI/eJ3F7Mp6Ro4+E+mtrRHSdReN3PyncnpJyyiLCTuIWF2Y6nEt0f6r9o9T9Zcn31j9sHar XN2SH98exJc9WRzPfT9BfuaLsO6MN/PNjY9PY9+rE/jows7tGrs+1Ll/TrvSITljR3/UZIb+ 81YWX/lqGGs3KFRVvJ8UJhe/WGKzxlGjb2JfV3j87bWbe9NSQbx/0+JSfb72g5ldDB8q2zpt Lk6ZG7aCYcsRW6vJNleXRHPNT1g0b3P9wxrfFQl5PadvHtn6L6Im+khBR+P31sXHve60Hmt4 ocRSnJFoqMVcVJwIAP0TrMa4AwAA X-CMS-MailID: 20250120172131eucas1p1ed7fc14a96c66b1dc9e14e9fc7cbb2b7 X-Msg-Generator: CA X-RootMTR: 20250120172131eucas1p1ed7fc14a96c66b1dc9e14e9fc7cbb2b7 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250120172131eucas1p1ed7fc14a96c66b1dc9e14e9fc7cbb2b7 References: <20250120172111.3492708-1-m.wilczynski@samsung.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Certain platforms, such as the T-Head TH1520 and Banana Pi BPI-F3, require a controlled GPU reset sequence during the power-up procedure to ensure proper initialization. Without this reset, the GPU may remain in an undefined state, potentially leading to stability or performance issues. This commit integrates a dedicated reset controller within the drm/imagination driver. By doing so, the driver can coordinate the necessary reset operations as part of the normal GPU bring-up process, improving reliability and ensuring that the hardware is ready for operation. Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/imagination/pvr_device.c | 21 +++++++++++++++++++++ drivers/gpu/drm/imagination/pvr_device.h | 9 +++++++++ drivers/gpu/drm/imagination/pvr_power.c | 15 ++++++++++++++- 3 files changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.c b/drivers/gpu/drm/imagination/pvr_device.c index 1704c0268589..7ae9875d8d74 100644 --- a/drivers/gpu/drm/imagination/pvr_device.c +++ b/drivers/gpu/drm/imagination/pvr_device.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -120,6 +121,21 @@ static int pvr_device_clk_init(struct pvr_device *pvr_dev) return 0; } +static int pvr_device_reset_init(struct pvr_device *pvr_dev) +{ + struct drm_device *drm_dev = from_pvr_device(pvr_dev); + struct reset_control *reset; + + reset = devm_reset_control_get_exclusive_by_index(drm_dev->dev, 0); + if (IS_ERR(reset)) + return dev_err_probe(drm_dev->dev, PTR_ERR(reset), + "failed to get gpu reset line\n"); + + pvr_dev->reset = reset; + + return 0; +} + /** * pvr_device_process_active_queues() - Process all queue related events. * @pvr_dev: PowerVR device to check @@ -509,6 +525,11 @@ pvr_device_init(struct pvr_device *pvr_dev) if (err) return err; + /* Get the reset line for the GPU */ + err = pvr_device_reset_init(pvr_dev); + if (err) + return err; + /* Explicitly power the GPU so we can access control registers before the FW is booted. */ err = pm_runtime_resume_and_get(dev); if (err) diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/imagination/pvr_device.h index 6d0dfacb677b..f6576c08111c 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -131,6 +131,15 @@ struct pvr_device { */ struct clk *mem_clk; + /** + * @reset: Optional reset line. + * + * This may be used on some platforms to provide a reset line that needs to be de-asserted + * after power-up procedure. It would also need to be asserted after the power-down + * procedure. + */ + struct reset_control *reset; + /** @irq: IRQ number. */ int irq; diff --git a/drivers/gpu/drm/imagination/pvr_power.c b/drivers/gpu/drm/imagination/pvr_power.c index ba7816fd28ec..87a955600d8b 100644 --- a/drivers/gpu/drm/imagination/pvr_power.c +++ b/drivers/gpu/drm/imagination/pvr_power.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -252,6 +253,9 @@ pvr_power_device_suspend(struct device *dev) clk_disable_unprepare(pvr_dev->sys_clk); clk_disable_unprepare(pvr_dev->core_clk); + if (pvr_dev->reset) + err = reset_control_assert(pvr_dev->reset); + err_drm_dev_exit: drm_dev_exit(idx); @@ -282,16 +286,25 @@ pvr_power_device_resume(struct device *dev) if (err) goto err_sys_clk_disable; + if (pvr_dev->reset) { + err = reset_control_deassert(pvr_dev->reset); + if (err) + goto err_mem_clk_disable; + } + if (pvr_dev->fw_dev.booted) { err = pvr_power_fw_enable(pvr_dev); if (err) - goto err_mem_clk_disable; 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Mon, 20 Jan 2025 17:21:31 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC v3 10/18] dt-bindings: gpu: Add 'resets' property for GPU initialization Date: Mon, 20 Jan 2025 18:21:03 +0100 Message-Id: <20250120172111.3492708-11-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250120172111.3492708-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02SfVBUVRjGPffevffCtHhdZDghSe6MzFSGrEMzZ8QazBpvjWVWUww05ebe FhAW3AXSBk1avnQXE0chl0/N4kORYD9YcNcdgXaRtR2CYKmAGLQAhw8BtaJht2Uvlv897/M+ z/zeM3NoXGQmw+hkRSanVEhTxWQgYbL/7Xr+qYJT8mhPcRjqdl/EkPEfHYWuWF0Yqu5yCdBo nwFDPz2YI9HV33spNGnNJdBgXSWF1PYmEk3pRkk0rx0VoP72ChItFncBZFrMI1Fj1wiFmh5U Y+jCvJFAl8ztABWc+FaAfux5FY2MdhNoql+LowLdWuS1mCnkGWwmUPmsjUKG6RIBcjS+j/Js Z4m4jezcUD7FTk9NEWxn0X2KtT6sIdg23QjFattuAbal4QTJDg9aSLbq5j72N40DY/WXPmfz Gu0Y++VyNDt3fYBkTxkaANundlNviRICd8i41ORsTrn1pf2BSVd67ViGnTrc5RyhjoNm8iQI oCETA/O8XuwkCKRFTB2AlZcLCX64D6B6qB7wwyKA183nBI8q7qLS1UUtgIUzRgE/TAP4sKKV WEmRzDY4VlvtX6xn8gmY/32uv4IzEwCa7lT48cFMPLxqKcZXNMFshubOen9byMTB+mUd4HkR 0HbjB38mwOf/OWCl+Mw6ePP8HX8e92XUxnJ8BQCZxkB4euZXii+/Ase+cK3qYHjXYVjV4dDb Vo3xOh2OGRdwXufANq1jVcfCYdeS71DaB3gGNrVv5e2d8OsZL7FiQyYIDs2s408IgmdMZThv C2FRgYhPR8Jz2uL/oK460yqUhV1NzdhpsEn32GN0jz1G9z+3BuANIJTLUqXJOZVEwX0apZKm qbIU8qgD6WktwPe5nR7HghlU3p2P6gAYDToApHHxemHIPa1cJJRJj3zGKdM/UmalcqoOsIEm xKHCi7Z8uYiRSzO5gxyXwSkfbTE6IOw4dnSpzNms0KLgiLMSy/b0yS0ySrswN1D/XrQl1tN+ LVtzO+XIweQ3O/WasBe8hef7EqremPaUq0ufk0fVieYUbueHGvGaPQdynowPqS4LMuk3bBxw HFoOSEpHf/R8d6tH/sG9CLHQmDxe1B9zbcn29IJgNrxR1uJpUe22RTyxwz1RtTA5HBL79mZ5 sLqmW3eZ+3iLu/CYYTL0dmt8ogoCwvXOmXcjc38ZvOHQ9F5Imdn3cnikbufrJQn0X4cSNS2S XRPHvhnf5VybE3Y4prS7JzPjNc+sPsWq3PvJz60V+2u/6j6aZx6XZce9aJE5Y9foS5JD0iS7 JZumyvduS9wepacjxYQqSSp5FleqpP8C9l3HPEsEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA02Se0xbZRjG851zes4p2ngsRc8IAdPMxSzS0q6lX7VcjFtyYuKiLkrUzK1h x0KAdvaCYjR2gh2lFcHg5ooDZBsbhEuKBctYYZamsBtstLRuo5V4XQnKYDBcELAUTfbfk+f5 Pe/7/vGSKL+Nk0oWa42sXqsuFeJJ2JX10UhmmqVWk3W053k4Fm5FYN+qg4CdnnEENvvGOTA6 6UJgcHkeh92/XSfgHc8RDIbOnSRgpb8HhzFHFIcL9igHBs5/g8N7n/sA7L9XhcMuX4SAPcvN CPx2oQ+Dp93nAbRY2zjwxuU9MBIdw2AsYEehxfEY3LjgJuB6yInBxr+GCeiaq+fA0a4CWDXc gOWnM/M/fkYwc7EYxoxULxGM534Lxgw4IgRjH7gKmN4OK85Mhy7gTNOlV5mfbKMI893pT5iq Lj/CfLGWxcwPTeFMrasDMJOVYeIV/lsilV5nMrJPFekMxhzh2xIoFUmUUCSVKUWSXYr9z0nl QnGu6hBbWlzO6sW5B0VFndf9yGE/8YHvSoQwAydeA7gkTcnocPUxUAOSSD51BtCj/VfBVpBG h2wxbEsn0/+EavAtaBbQ3UdaE22cktIzZ5s5m1pAncJoz1DFJoRSfwI6fMKZaCdTb9CeGX9i KkY9TbtH2hM+j8qn29cc/23LoId/uIZuam7cX5nyEJuaT+XR01M2sMU/Tl868Wuii8b5yr5G tA5Qjocix0NRC0A6gIA1Gco0ZQapyKAuM5i0GlGhrqwXxB+m3//A5QbtswsiL0BI4AU0iQoF vJS7dg2fd0hd8SGr1x3Qm0pZgxfI43fXo6kphbr4x2mNByTZWXKJLFuZJVdm7xI+ycODE+/y KY3ayJaw7GFW/38PIbmpZkT1UsTf2rbjmcUA9sC43LV7cLsnx/1IddD3tWB49aAqIFqV8cKZ g01L+d23S74UPzFjGi8Y/GXvDGnDonXHybsqbvltc8HFk38EbhznfKXY+6yifod3cV9pttSa 0+EY+3RE1wDNd3Zj6+IRU/OjxH17WoaiPt0wbWfXlXLLzQLRmZJbMmshq7hIfl9jzuCs5Dal bkysreqOCi7n1fUsJon3CWiUF6nav2T5+VjJrfQV7QTMefPFzp0vDBhfY2++UxE9xw3uadCW C9VKbW/xto3ge5EWhX5b3mSfCX3/9yFvrell4Snrx87Gv5Mz566dlYe3O2e5r+s/4rmmbLwU IWYoUkt2onqD+l/B6xEuuQMAAA== X-CMS-MailID: 20250120172133eucas1p232c85cb934148427e52dd939c974a82b X-Msg-Generator: CA X-RootMTR: 20250120172133eucas1p232c85cb934148427e52dd939c974a82b X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250120172133eucas1p232c85cb934148427e52dd939c974a82b References: <20250120172111.3492708-1-m.wilczynski@samsung.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Many RISC-V boards featuring Imagination Technologies GPUs require a reset line to be de-asserted as part of the GPU power-up sequence. To support this, add a 'resets' property (and corresponding 'reset-names') to the GPU device tree bindings. This ensures the GPU can be properly initialized on these platforms. Signed-off-by: Michal Wilczynski --- Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 256e252f8087..bb607d4b1e07 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -37,6 +37,9 @@ properties: power-domains: maxItems: 1 + resets: + maxItems: 1 + required: - compatible - reg From patchwork Mon Jan 20 17:21:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13945312 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 29DD2C02181 for ; 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Mon, 20 Jan 2025 17:21:34 +0000 (GMT) X-AuditID: cbfec7f5-ed1d670000004fad-5c-678e861ed9be Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 85.A5.19654.E168E876; Mon, 20 Jan 2025 17:21:34 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250120172132eusmtip156c00c2a165f8d99eb90bc0451aa709c~cdlvRl8za1308113081eusmtip1b; Mon, 20 Jan 2025 17:21:32 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC v3 11/18] dt-bindings: gpu: Add compatibles for T-HEAD TH1520 GPU Date: Mon, 20 Jan 2025 18:21:04 +0100 Message-Id: <20250120172111.3492708-12-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250120172111.3492708-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01Sf1CTdRjn+77v3vdlNXwZGN8To4sSgU6Y0tVX9BA7Pd8zCfmjg9JOZrw3 LBi2QUVkYcBOcIBpXDB+DD0uJhetzW3xe4Bjg9JJkINKFpx4MSQQgTzqkhgvlv99nufzeT6f 57l7aFxsJjfRJ+TZnEIuzQglhYTFvnxjW4iqTCYxuiWof+QShsx/ayj0dacTQ1qbU4DcQyYM /bQ0R6Jv7gxSaKrzNIFculoKFdj1JPJo3CSaV7sFaLithkQLpTaALAuFJGq2jVFIv6TF0MV5 M4EaWtoAUhV/JUA/fr8fjbn7CeQZVuNIpdmAVjpaKPTQZSBQ9ayVQqaZzwXI0ZyMCq1fEPEh 7NxoEcXOeDwEe/XMIsV2/llPsK2aMYpVt14DrLGpmGRvuTpItm4gif3trANjrzR8yhY22zG2 /B8JO9d1k2TLTE2AHSoYoQ6L3xTuTuMyTrzPKaLjUoXpjRX5gpP9QR/W2luwfNDOlABfGjIv wva71VQJENJiRgdgXV8/4ItFAId+6VlnFgC0Xq7BHo3MuysJLxYzjQDeHk/jRTMA2jzGNRHJ 7IDjjVqBlwhkighY1Hd6zRdnfgfQMllDlgCaDmCSYPGoyDtAMFug06YHXixi4mFJYz3Bpz0D rT3XcS/2Xe0/uNlJ8Rp/OFA1uabBVzUF5mrc6w8ZgxDqZr0EvVrsg2VqCe8TAKcdJorHm+FK q3b9miw4br6P8/hj2Kp2rONd8Jbzr7U1cSYC6tui+fZeWFtXifPufnD0D39+Az943vLlelsE z6jEvDoMVqhL/wt16izroSw0Dd7AzoFnNY/donnsFs3/ufUAbwJBXI4yU8YpY+TcB1FKaaYy Ry6Lejsr0whWP/uHh46lFqCbno/qBRgNegGk8dBA0cZ7aplYlCbN/YhTZB1T5GRwyl4QTBOh QaJL1iKZmJFJs7l3Oe4kp3jEYrTvpnws/r1Q5wvlO9PDfZqnj4V8qw2/HZczMRzzhnE+5Wr5 g4wL+b8W7znSro9MTnidqTokSSVcPs3329vOxSYcfOfl7pSjkuXuprqVxJjsvJFX9aYn8sI3 z01PWiwTeWyH71sVW4MvJh/1fzK2gMoNIKYqVWD5acOpHRPBT+1e0iaZlgK7fbYMR1xPlCce VNCL9bUJssFOfLvJlRjth11JOjKQcffCa9bUQ4o9kfHpYRUNhsuvkAcMBtFQVeHx2J+3fnZv 13nF88rnpnX6TzxxG1X2wwIOk6ecmhOV7ZstvVYd+5KQKBL6c3s3TGBdB/ZHnE3IntrpyO3a Fi/t8wzK7xy3hX3XE0oo06XbI3GFUvovUa0VuEgEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGKsWRmVeSWpSXmKPExsVy+t/xu7pybX3pBr2z+S1OXF/EZLH19yx2 izV7zzFZzD9yjtXi3qUtTBZXvr5ns1j39AK7xYu9jSwW11bMZbdoPraezeLlrHtsFh977rFa XN41h83ic+8RRottn1vYLNYeuctusf7rfCaLhR+3slgs2bGL0aKtcxmrxcVTrhZ3751gsXh5 uYfZom0Wv8X/PTvYLf5d28hiMfvdfnaLLW8mslocXxtu0bJ/CouDnMf7G63sHm9evmTxONzx hd1j77cFLB47Z91l9+jZeYbRY9OqTjaPO9f2sHnMOxnocb/7OJPH5iX1Hi1rjzF59P818Hi/ 7yqbR9+WVYwel5qvswcIRenZFOWXlqQqZOQXl9gqRRtaGOkZWlroGZlY6hkam8daGZkq6dvZ pKTmZJalFunbJehlLJ/awFpwQrxi7rEdTA2MuwW6GDk5JARMJD7em8HSxcjFISSwlFHi6adf bBAJGYlr3S9ZIGxhiT/Xutggil4xSpxde40dJMEmYCTxYPl8VhBbRGAxi8TefZUgRcwCbxkl rs/cCNYtLOAv8ePAUiYQm0VAVeLckfWMIDavgINE1/IFUBvkJfYfPMsMYnMCxb9f3Qu2QEjA XuLO1W6oekGJkzOfgNUzA9U3b53NPIFRYBaS1CwkqQWMTKsYRVJLi3PTc4uN9IoTc4tL89L1 kvNzNzECE8y2Yz+37GBc+eqj3iFGJg7GQ4wSHMxKIryiH3rShXhTEiurUovy44tKc1KLDzGa At09kVlKNDkfmOLySuINzQxMDU3MLA1MLc2MlcR52a6cTxMSSE8sSc1OTS1ILYLpY+LglGpg WnP0fl7Bt+zvRYedHlufcJ9hy3/qTWSz9fI9oWHmMvWbJgeHNqu1i8yYYf2hwz5o/xPVc3a9 6ww0Os7VHFuV8GTOzU+5UpsfTJyScPC86RTVqz5pU2OlTN3aLf6tWfVobvfyFOkJ0/85qV6b L7y0Yz/vyvQ3jziuKRn8WJVt/KrC8k/chb+mgX82bE7nP53ssu6fdUnP7u9S+y6L60rOmvCh je/YxvJDM2SO7I58KLQ78cx2TZ4TGfdeHUqwZv8UqZtWq3cn6PH7pqsLZNueb/Y7r71pgsF8 DQ+eX0Lun8ujFrOa3FdYxnTCfeYkJYa8AKeXxxu337g1Ve7FHdO16le/P7r8I7A/86Pjxsa9 XuuUWIozEg21mIuKEwFhmFEIuQMAAA== X-CMS-MailID: 20250120172134eucas1p18cbf29a4ade281df10efce210cc8893e X-Msg-Generator: CA X-RootMTR: 20250120172134eucas1p18cbf29a4ade281df10efce210cc8893e X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250120172134eucas1p18cbf29a4ade281df10efce210cc8893e References: <20250120172111.3492708-1-m.wilczynski@samsung.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a new SoC-specific compatible ("thead,th1520-gpu") for the T-HEAD TH1520 GPU, alongside the Imagination BXM family compatible ("img,img-bxm"). This documents the GPU integration on the T-HEAD platform. Also adjust clock name constraints to accommodate a second clock named "sys" instead of "mem" for T-HEAD. This is achieved by using allOf. For now there are no users of 'mem' so remove it. Provide example of the new GPU node. Signed-off-by: Michal Wilczynski --- .../bindings/gpu/img,powervr-rogue.yaml | 55 +++++++++++++++---- 1 file changed, 45 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index bb607d4b1e07..3c0eaa0ae827 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -12,10 +12,15 @@ maintainers: properties: compatible: - items: - - enum: - - ti,am62-gpu - - const: img,img-axe # IMG AXE GPU model/revision is fully discoverable + oneOf: + - items: + - enum: + - ti,am62-gpu + - const: img,img-axe + - items: + - enum: + - thead,th1520-gpu + - const: img,img-bxm reg: maxItems: 1 @@ -25,11 +30,8 @@ properties: maxItems: 3 clock-names: - items: - - const: core - - const: mem - - const: sys minItems: 1 + maxItems: 3 interrupts: maxItems: 1 @@ -47,8 +49,6 @@ required: - clock-names - interrupts -additionalProperties: false - allOf: - if: properties: @@ -58,7 +58,28 @@ allOf: then: properties: clocks: + minItems: 1 maxItems: 1 + clock-names: + items: + - const: core + + - if: + properties: + compatible: + contains: + const: thead,th1520-gpu + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: core + - const: sys + +unevaluatedProperties: false examples: - | @@ -74,3 +95,17 @@ examples: interrupts = ; power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; }; + + #include + #include + + gpu: gpu@fff0000 { + compatible = "thead,th1520-gpu", "img,img-bxm"; + reg = <0xfff0000 0x1000>; + interrupt-parent = <&plic>; + interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_GPU_CORE>, <&clk CLK_GPU_CFG_ACLK>; + clock-names = "core", "sys"; + power-domains = <&pd TH1520_AON_GPU_PD>; + resets = <&rst>; + }; From patchwork Mon Jan 20 17:21:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13945310 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AC301C0218B for ; Mon, 20 Jan 2025 17:21:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 94BCA10E470; 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Mon, 20 Jan 2025 17:21:34 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC v3 12/18] drm/imagination: Add support for IMG BXM-4-64 GPU Date: Mon, 20 Jan 2025 18:21:05 +0100 Message-Id: <20250120172111.3492708-13-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250120172111.3492708-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01SbUxTZxjNe+/l3kuTukuB8KKLmxXnWDJgDPGdMj+iS66Z2ebGNMoYdvOm CLSQFvzaDJBSRrFS0U2kyECGoysr+NEi7aiNgFQ3KSBSdIPCDxdoZSICuuEGo1zd/HfO857n OeckL42LzORieq88m1PIJRliUkA0dfzV9frLhSXSmEofjq7112DI8kRPoR/tLgxVtbsCkOem GUO3psdJ1PB7N4VG7fkEchsqKaTqaCSRV+8h0YTWE4B6badJNHm0HaCmyQISmdoHKdQ4XYWh MxMWAtU22wAq1HwfgHp+fgcNeq4RyNurxVGh/gU019JMoVn3eQJV3HdQyDxWGoCcph2owPE1 sWEpO35bTbFjXi/BthVNUaz9UTXBWvWDFKu13gDsBaOGZAfcLST77fVt7NARJ8ZerM1lC0wd GKv7J4Ydv9xHsiVmI2BvqvqpD0S7BAl7uIy9+zhF9LrdglSHrRzLqqcPdLnqyDygoooBTUMm Dmp0qBgIaBFjALDuXB7JkykAe/ssRDEInCeTAPqOBfuxf6HUWRzAi+oAvHG/kuDJGICDVjPp V5FMLByuq1pQhTBqAqqv5gM/wZkRAJvunib95sHMFqh5tMa/QDAr4MjAyYVlIbMB5vdeBLzd S9BxpRP348D5+eM+O8VrguD18rsL8fB5jcpSgfvvQ8YkgGNuI8aX2wwrhln+TjD0Oc0Uj1+E c9YqjMeZcNjyEOfxl9CqdT7Fa+GAa2YhJs5EwkZbND/eCIe6y3D++iJ4+48gPsEieLzp2VgI iwpFvPoV+I326H+mLkPTU1MW1lfrsGNgmf65Lvrnuuj/960GuBGEcTlKmZRTvinn9kcpJTJl jlwa9Xmm7AKY/9i/zDqnm4HBNxHVCjAatAJI4+IQYegDrVQk3CM5eIhTZKYocjI4ZStYQhPi MGGNQy0VMVJJNpfOcVmc4tkrRgcuzsOsJ+M/2/auMbxWJD0U+9b0kbgS25MIphLlzqiSHs6E RgrfW34WtcV2m8p8gvg2Z3RjxKhGnbzS9NXyXeLElq65NctmZZfEZWHe7FzFWaWgPCbi4/gz q13rXl3fYOsZaNyUl/XdgwZ58hJ7X704nd4dq756vmLL7IfbHWn3dPvYpM0JBys6LW4QeQf/ WzLy51bWF6JzDq5MuNTdGXrYUPR+qaw5f3j7r2lV1hObbq0KS/wo9wdp8lSQ7fGV9p92eE58 URvXOmrcuPOTtjup6w8n2VIcSz8dYYp7wn/D3cTEqXOJ/UMRQJy8sz4zqCZ9ZP8kaU9722tY lbJaG741+8C9y2NrxYQyVfLGa7hCKfkXz7s3x0cEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKKsWRmVeSWpSXmKPExsVy+t/xu7rybX3pBuebFC1OXF/EZLH19yx2 izV7zzFZzD9yjtXi3qUtTBZXvr5ns1j39AK7xYu9jSwW11bMZbdoPraezeLlrHtsFh977rFa XN41h83ic+8RRottn1vYLNYeuctusf7rfCaLhR+3slgs2bGL0aKtcxmrxcVTrhZ3751gsXh5 uYfZom0Wv8X/PTvYLf5d28hiMfvdfnaLLW8mslocXxtu0bJ/CouDnMf7G63sHm9evmTxONzx hd1j77cFLB47Z91l9+jZeYbRY9OqTjaPO9f2sHnMOxnocb/7OJPH5iX1Hi1rjzF59P818Hi/ 7yqbR9+WVYwel5qvswcIRenZFOWXlqQqZOQXl9gqRRtaGOkZWlroGZlY6hkam8daGZkq6dvZ pKTmZJalFunbJehl7N81k6lgNUfF+XPL2RoYm9m7GDk5JARMJCYe72LtYuTiEBJYyihx9usK RoiEjMS17pcsELawxJ9rXWwQRa8YJX713WIGSbAJGEk8WD6fFcQWEVjMIrF3XyVIEbPAW0aJ 6zM3AnVzcAgLeEp0frMCqWERUJV4fmcaG4jNK+Ag0Xh5M9QyeYn9B8+CzeQEin+/uhfsOiEB e4k7V7sZIeoFJU7OfAJ2EDNQffPW2cwTGAVmIUnNQpJawMi0ilEktbQ4Nz232EivODG3uDQv XS85P3cTIzC9bDv2c8sOxpWvPuodYmTiYDzEKMHBrCTCK/qhJ12INyWxsiq1KD++qDQntfgQ oynQ3ROZpUST84EJLq8k3tDMwNTQxMzSwNTSzFhJnJftyvk0IYH0xJLU7NTUgtQimD4mDk6p Bia9/oLj23UTvfVDnFWXqAXMMLmx6GTa2ap3J9SLmFpiHsf+P6fxdELjrMKSHWY+nY+LLr71 kL1jY831x8DhW1q7R8DDZYd3cN0RM/m3Ok/WtZmjKcDRTO3aS7s/qe/vZvTO2GD+QE40ssj6 Qp5apf7hVJFQlzX/L69er32/6OXcFyv+pfM2OXKV3D2csi6zLvdaH89rj/BDC0rM5ey6eVzL xPZI2DJfmu945+z0Ncc+GtUvnXzn+fYDHM3OB2+Y3z7G3aNyK70+qMSr6M01K2POhfOPS0jU rYk1+LCgXnMR54XH+9Pv/lexvm8+73hMnXXmJI+jP0T11p651CArtCEwyZHLxZl366WlXJsl mZVYijMSDbWYi4oTATY/yji4AwAA X-CMS-MailID: 20250120172135eucas1p22f50d9db3fb656fbaf6ccc096dcb8c9f X-Msg-Generator: CA X-RootMTR: 20250120172135eucas1p22f50d9db3fb656fbaf6ccc096dcb8c9f X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250120172135eucas1p22f50d9db3fb656fbaf6ccc096dcb8c9f References: <20250120172111.3492708-1-m.wilczynski@samsung.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The IMG BXM-4-64 GPU is integrated into the T-Head TH1520 SoC. This commit adds the compatible string "img,img-bxm" to the device tree match table in the drm/imagination driver, enabling support for this GPU. By including this GPU in the compatible devices list, the driver can initialize and manage the BXM-4-64 GPU on the TH1520 SoC, providing graphics acceleration capabilities upstream. Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/imagination/pvr_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/imagination/pvr_drv.c b/drivers/gpu/drm/imagination/pvr_drv.c index 85ee9abd1811..91af060bb3e0 100644 --- a/drivers/gpu/drm/imagination/pvr_drv.c +++ b/drivers/gpu/drm/imagination/pvr_drv.c @@ -1475,6 +1475,7 @@ static void pvr_remove(struct platform_device *plat_dev) static const struct of_device_id dt_match[] = { { .compatible = "img,img-axe", .data = NULL }, + { .compatible = "img,img-bxm", .data = NULL }, {} }; MODULE_DEVICE_TABLE(of, dt_match); From patchwork Mon Jan 20 17:21:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13945316 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BF3ACC0218C for ; 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Mon, 20 Jan 2025 17:21:36 +0000 (GMT) X-AuditID: cbfec7f5-ed1d670000004fad-66-678e86212fb4 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id E2.D8.19920.0268E876; Mon, 20 Jan 2025 17:21:36 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250120172135eusmtip1a3bbf8b8e44cde18b4db74e4cde13572~cdlxq3Mr00819408194eusmtip1s; Mon, 20 Jan 2025 17:21:35 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC v3 13/18] drm/imagination: Enable PowerVR driver for RISC-V Date: Mon, 20 Jan 2025 18:21:06 +0100 Message-Id: <20250120172111.3492708-14-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250120172111.3492708-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01Se0xTZxzdd+/tvZdmhWuV+A2ZhiZCJBFQXPIle0EyyF2yP2Axmpllrspd ZfKyFWWoAwZFkOKADQgFpQpBAhSClAqdBeVVwFEmjMc2XtvQ8RyFtqIu1lFu2fzvnN853+/8 TvLRuPgO6UVHx53l5HHSGAkpJPQ9z8z7fTKvyoJs2W+g3rGbGGr+R02hOqMZQ+VdZgGaGtJh 6Gf7ConqH/1EoTljGoFGq69RKL2ngUTz6ikSraqmBGjYUEYia24XQHprBom0XZMUarCXY+jG ajOBKlsMAGVmVwnQw/4wNDnVS6D5YRWOMtUe6OXdFgo5RhsJVPp3O4V0S/kCZNIeRRnt3xMh u9mVcSXFLs3PE2xnlo1ijU80BNuqnqRYVeuPgL1dk02yE6N3SfZ6XyQ7nWPC2KbKFDZD24Ox 374IYlfaRkj2qq4GsEPpY1SE+JjwnSguJvocJw9873PhqXuGNSzBQCflz77AU8Fl6gpwoyFz CNY2TWBXgJAWM9UAquuGSJ7YAKzNaaN4YgWwWFeIbz0xpD0geOEWgN3FjwQ8WQJwZGFa4HSR zEE4c6t8U9jBKAmo7E4DToIzfwGony0jna7tzIdQM9C4uZdg9kKN4TnhxCImBOY3WAV83h7Y fn9g0+O2MV8fMVK8ZxvsK5nd9OMbnvTmUtwZAJlGIbTYtvp9AC1PJl2LtsMFk84194YvW8sx HsfDmeY1V7mLsFVlcuG34YT5+cah9EbAPthgCHRCyIRCR044D93h+PI2/gJ3WKAvxvmxCGZl ivkdvrBQlftfprla78pkoaX9GyoP+Khf6aJ+pYv6/1gNwGvATi5RESvjFMFx3PkAhTRWkRgn CzgZH3sbbPztBw6TvQVUL6wGdACMBh0A0rhkh8jTopKJRVHSr5I5efxxeWIMp+gAu2hCslN0 s10pEzMy6VnuNMclcPItFaPdvFIxTe7+3H32CtrviH+tR+ruQ/Xhpm5d9pspniWP798IPP3b x5fmzoQ6jL1zpdLlcz5H++nIgcVCvK7Nr1HFRKWEv98Zqb30VonjXtJ6WVHnUAh62hz5w0d2 zzOVzz6ZDhlfjj7vd9CqtQX/GuKLDH2Wx9e/CC27YxvzTpUY/vzO/V3vlOKngxHaw1WiwfE8 VdFnypz8a/Xre37xEg0E095WwiOD9hXmKtHKZfuiZ5Youcr/4WFj8qekZtYCl18roGfc+/E/ mvZGrHnIC76uCTpQpLwIEv3DBlv0i8WloV++bh3WTKljREUVu/ovJA2eiGv8vTBsRgMvDB9L WImoOO6F5UkIxSnpAX9crpD+Cxl3GstKBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGKsWRmVeSWpSXmKPExsVy+t/xu7oKbX3pBtv+G1ucuL6IyWLr71ns Fmv2nmOymH/kHKvFvUtbmCyufH3PZrHu6QV2ixd7G1ksrq2Yy27RfGw9m8XLWffYLD723GO1 uLxrDpvF594jjBbbPrewWaw9cpfdYv3X+UwWCz9uZbFYsmMXo0Vb5zJWi4unXC3u3jvBYvHy cg+zRdssfov/e3awW/y7tpHFYva7/ewWW95MZLU4vjbcomX/FBYHOY/3N1rZPd68fMnicbjj C7vH3m8LWDx2zrrL7tGz8wyjx6ZVnWwed67tYfOYdzLQ4373cSaPzUvqPVrWHmPy6P9r4PF+ 31U2j74tqxg9LjVfZw8QitKzKcovLUlVyMgvLrFVija0MNIztLTQMzKx1DM0No+1MjJV0rez SUnNySxLLdK3S9DLOLDrE1PBLo6KiU/+MjcwtrN3MXJySAiYSOxqPM3SxcjFISSwlFHi7L35 jBAJGYlr3S9ZIGxhiT/Xutggil4xSsxomMwMkmATMJJ4sHw+K4gtIrCYRWLvvkqQImaBt4wS 12duBOsWFvCUWHB2I1gDi4CqxIJdv8DivAIOEhPXf2aF2CAvsf/gWbAaTqD496t7wc4TErCX uHO1mxGiXlDi5MwnYL3MQPXNW2czT2AUmIUkNQtJagEj0ypGkdTS4tz03GJDveLE3OLSvHS9 5PzcTYzABLPt2M/NOxjnvfqod4iRiYPxEKMEB7OSCK/oh550Id6UxMqq1KL8+KLSnNTiQ4ym QHdPZJYSTc4Hpri8knhDMwNTQxMzSwNTSzNjJXFet8vn04QE0hNLUrNTUwtSi2D6mDg4pRqY +G95/v7+M2GN7N4jc0T6JvAt//nVMD0j8Ebnw69OTcx/7u6YyV/nuEXWaMu7iocC3H01y56p Hb5WknxpsXhi62qNh7vbjzjUvm554bjj2XuPh75VH4oqbe3eTsuf9HLPz5qHFdHLOHIZ3e+V 6EqbbFmdEKBq2ct8oOp7sO17zQc9G7/LFi47GuMVLPR8n8tbgweccwSXLq1aXPpp+syLbzk8 Y5duilrT1ZfrvF5UjWHC+d+LE34yW1cXP90+5a5GwWKuqQZZx249/FKeyu53/OAyl/8LdwTc XvPr3ZTd7xq/ClyV73r0/fNr1SDrN+yP9v/Zq37s9PXyoLVOBzgSit/r6C5562Jyu/KxgEzb fA0lluKMREMt5qLiRACZNBB7uQMAAA== X-CMS-MailID: 20250120172136eucas1p2a8348fbcfdf42efa8c130d558381f599 X-Msg-Generator: CA X-RootMTR: 20250120172136eucas1p2a8348fbcfdf42efa8c130d558381f599 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250120172136eucas1p2a8348fbcfdf42efa8c130d558381f599 References: <20250120172111.3492708-1-m.wilczynski@samsung.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Several RISC-V boards feature Imagination GPUs that are compatible with the PowerVR driver. An example is the IMG BXM-4-64 GPU on the Lichee Pi 4A board. This commit adjusts the driver's Kconfig dependencies to allow the PowerVR driver to be compiled on the RISC-V architecture. By enabling compilation on RISC-V, we expand support for these GPUs, providing graphics acceleration capabilities and enhancing hardware compatibility on RISC-V platforms. Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/imagination/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/imagination/Kconfig b/drivers/gpu/drm/imagination/Kconfig index 3bfa2ac212dc..5f218896114c 100644 --- a/drivers/gpu/drm/imagination/Kconfig +++ b/drivers/gpu/drm/imagination/Kconfig @@ -3,7 +3,7 @@ config DRM_POWERVR tristate "Imagination Technologies PowerVR (Series 6 and later) & IMG Graphics" - depends on ARM64 + depends on (ARM64 || RISCV) depends on DRM depends on PM select DRM_EXEC From patchwork Mon Jan 20 17:21:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13945319 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 45A12C02182 for ; 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Mon, 20 Jan 2025 17:21:38 +0000 (GMT) X-AuditID: cbfec7f5-ed1d670000004fad-68-678e86223bec Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id CB.A5.19654.2268E876; Mon, 20 Jan 2025 17:21:38 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250120172136eusmtip1e9c6acac091371dd6cdf44efec214b8c~cdly4yg4m1013910139eusmtip1Y; Mon, 20 Jan 2025 17:21:36 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC v3 14/18] riscv: dts: thead: Add device tree VO clock controller Date: Mon, 20 Jan 2025 18:21:07 +0100 Message-Id: <20250120172111.3492708-15-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250120172111.3492708-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02SbUxTZxTH99x7e++ls3Atbj5BlIzBXthEx0x4MliRbGZ3iR/ww9gy3aQb NwUHpbaC05CIFBpeiuBmMas4XibQsCEBWgQCdlSgVKAIjBcJrejACUGQYQeC4Citm99+55z/ Of9zkkPjQj3pQ8dLT3ByqTjBn+QTDZ1PrLv9Vecke1cf7UZdI2UYMqxqKfRbqxVDxe1WHrIP 6DH0h2OeRFenblHoQetZAg3rLlNI2VlDommtnUQLajsPDTYXkWgxrx2ghsUMElW32yhU4yjG UOmCgUBXGpsBUmVX8FD/zQPIZu8i0PSgGkcqrRd61tJIofXhWgJdmjNSSD97nofM1Z+jDOMF Yv8udn40k2Jnp6cJ9kbWY4pt/aeEYJu0NopVN/UAtq4qm2THh1tI9mfLIfZOrhlj66+cYTOq OzE2f20vO399iGTP6asAO6AcoaKEX/LDY7mE+BROvkcUw4+73tGLyW5S39eO/QnSQBGZAzxo yOyDtjYHngP4tJDRAaix9bmDxwDazErCFSwC2NaRQT1v6SvQuAuVAI6la3FnQcjMAtj0O3Iy yYTAicpinlO0jckkYGbHWeAMcOYvABsmXe7eTBRcvzG4OZZgAuHdpeUNEU0LmP1QN/KRy80P Gtt6Nw08NtJLQ62bcgGzFVp+miScjG9olIZLuEtfy4fTyiAXfwzLnowTLvaGM2a9+wJf+Kyp GHNxEpww/O3uTYVNarObw+C4dYV0roMzb8Oa5j1OhEwkrCnFXegJRx9udS3gCX9ouOhOC2CW Suia8QbUqPP+87TqGtyeLMwu7eYVgNe0L5yifeEU7f+2JQCvAtu5ZEWihFO8L+VOBivEiYpk qST426TEOrDx2N3rZkcj0M0sBJsARgMTgDTuv03wyiO1RCiIFZ86zcmTjsqTEziFCeygCf/t gjJjpkTISMQnuO84TsbJn1cx2sMnDau5axl9s3+LqlIbRF6UHZH53TILJeHvnr5aeNLhe23n 8cNTfSNH8QBr6Ceqxp1jIUs9ByKt+7IrDFMvnUqpiC6KWL3tRUVntRC8h3JZm+h+bvrr4/iU 1+GoCROb/7JFU/HVA9HXsyu+wl+Mn0bc65amBqTdER25fWZELsqh8+NqLal+ax6Tx85/kTr2 wZaZmF8L29OUAXm7FsOW7SmB5V36tQHimx3l3nO5cdUHw46V1DdHoDXJ8cyn9fh6b929t57W 39f46qMXDStwNH44pLDcs+DQauxcLt3vIwiVer0TMZT+4fKrJh26/FkkqMgPuRYRmNfSc9A7 vKA65kd9aIklzZ9QxInfC8LlCvG/btA/AUcEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrCKsWRmVeSWpSXmKPExsVy+t/xu7pKbX3pBqefclqcuL6IyWLr71ns Fmv2nmOymH/kHKvFvUtbmCyufH3PZrHu6QV2ixd7G1ksrq2Yy27RfGw9m8XLWffYLD723GO1 uLxrDpvF594jjBbbPrewWaw9cpfdYv3X+UwWCz9uZbFYsmMXo0Vb5zJWi4unXC3u3jvBYvHy cg+zRdssfov/e3awW/y7tpHFYva7/ewWW95MZLU4vjbcomX/FBYHOY/3N1rZPd68fMnicbjj C7vH3m8LWDx2zrrL7tGz8wyjx6ZVnWwed67tYfOYdzLQ4373cSaPzUvqPVrWHmPy6P9r4PF+ 31U2j74tqxg9LjVfZw8QitKzKcovLUlVyMgvLrFVija0MNIztLTQMzKx1DM0No+1MjJV0rez SUnNySxLLdK3S9DL2Hf0LFPBKfaKjbceMzYwzmHrYuTkkBAwkTg/YSoLiC0ksJRRYtfhEoi4 jMS17pcsELawxJ9rXUD1XEA1rxglvi88DpZgEzCSeLB8PiuILSKwmEVi775KkCJmgbeMEtdn bgQrEhbwk1i1/weYzSKgKvHw+w/GLkYODl4BB4kV150hFshL7D94lhnE5gQKf7+6lx3iIHuJ O1e7GUFsXgFBiZMzn4CNYQaqb946m3kCo8AsJKlZSFILGJlWMYqklhbnpucWG+kVJ+YWl+al 6yXn525iBCaXbcd+btnBuPLVR71DjEwcjIcYJTiYlUR4RT/0pAvxpiRWVqUW5ccXleakFh9i NAU6eyKzlGhyPjC95ZXEG5oZmBqamFkamFqaGSuJ87JdOZ8mJJCeWJKanZpakFoE08fEwSnV wLT6B/t+mZyD0jf9ilxEOYpnWbxX4zB48finbayOl5bSgdyE3F9+ZzMP3RY52MjtvvxEWdX2 CTLXP9zjStI5vDvqc87iPXPSvrSer/6sL57YtFjFRLFJ0CFpT9pHxqJvTYdWOsWqXNX6+ivv n9+HR2xna9vWnONX215xJPHkp+lOXv877xXObmita396ZNmvTMONvYKeBluKn7ycUr2WQfaP 33pOHY7w94KplneXC65dNeuLBHN72jybySliVd0znJ9Ge65vP/1YuHfZ3ViWq9PO7RLlmPDc el9ld/G26b1b0s4+y1rnzcizJu7brHUvdqjz3V43u0dEoOP81ckty7unZE/44bn/Zlz03tA9 u14osRRnJBpqMRcVJwIAxmV81LcDAAA= X-CMS-MailID: 20250120172138eucas1p294698126686b5d3a9281c0a5428f2cf6 X-Msg-Generator: CA X-RootMTR: 20250120172138eucas1p294698126686b5d3a9281c0a5428f2cf6 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250120172138eucas1p294698126686b5d3a9281c0a5428f2cf6 References: <20250120172111.3492708-1-m.wilczynski@samsung.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" VO clocks reside in a different address space from the AP clocks on the T-HEAD SoC. Add the device tree node of a clock-controller to handle VO address space as well. Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index acfe030e803a..5e515a9d69b2 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -489,6 +489,13 @@ clk: clock-controller@ffef010000 { #clock-cells = <1>; }; + clk_vo: clock-controller@ffef528050 { + compatible = "thead,th1520-clk-vo"; + reg = <0xff 0xef528050 0x0 0xfb0>; + clocks = <&clk CLK_VIDEO_PLL>; + #clock-cells = <1>; + }; + dmac0: dma-controller@ffefc00000 { compatible = "snps,axi-dma-1.01a"; reg = <0xff 0xefc00000 0x0 0x1000>; From patchwork Mon Jan 20 17:21:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13945314 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CAC22C02181 for ; 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Mon, 20 Jan 2025 17:21:39 +0000 (GMT) X-AuditID: cbfec7f5-ed1d670000004fad-6c-678e86236563 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 3E.A5.19654.3268E876; Mon, 20 Jan 2025 17:21:39 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250120172138eusmtip137e7f2a18d2217166b0002c0f86bb0b4~cdl0HKaKp1070610706eusmtip16; Mon, 20 Jan 2025 17:21:38 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski , Drew Fustini Subject: [RFC v3 15/18] riscv: dts: thead: Add mailbox node Date: Mon, 20 Jan 2025 18:21:08 +0100 Message-Id: <20250120172111.3492708-16-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250120172111.3492708-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Se0xTZxjG851zes5pZ/VQYHzBTTOm08lEN3b5MgxxU5djGm/sFjW7VD0p bFyatkx0TiGUDrAgLjBjqxYZU8ZAArSMIqyl1FZ0IxNGYcwWdsENBlagnRlgHeUw53/P+3uf 93veN/loXNJCRtMp6WpOmS5LjSFFRJPzn661K7TF8vXDNhJd7avAkHlGT6Gati4MGR1dAmRr VSNvtwlDPwZ8JLo0/AOF/mzLIZC76iyFcp11JBrRe0k0ofMKUE/LGRJNFTkAaprSkKjW4aFQ XcCIofMTZgJVNrcApC24IEA3rm1BHu9VAo306HCk1S9B91ubKRR01xPIcNtKIdPYSQFy1b6N NNZSYuNy1tefR7FjIyME25Hvp9i2v8sJ1qL3UKzO8h1gG6oLSPamu5Vkz3XuYgePuzC2sfIY q6l1YuyJe+tZ37e9JFtsqgZsd24ftTN8j2jDAS415SNOuS7xfVFyU3+2QHFHlNXnd4Bs8Add CIQ0ZJ6Hs4YRQSEQ0RKmCkBz6yweakgYP4CeX4S8ngJQ+8WDgQLPEMUPXASwseMGwRdjAGab nCDkIpnn4NBF4/yzEUweAfOu5IBQgTMlGKxwn5vPCGcSYHvJp4KQJpiVMPe37nkuZjbCgaFe wOcth9b27+e5cI7f7W2jeE8Y7Dz9OxHS+Jwn12zAQwGQsYigWz+D8cOb4WRz2YIOh6MuE8Xr x+B9i3GBZ8Ah8yTO6yPQonMt6AR4s2uaLAT0XMDTsK5lHY9fgbrgCSqEIbMY9o+H8Ssshp81 ncJ5LIb5WgnvfgqW6YoehHZVNS2EstBmLAUl4An9Q8foHzpG/39uOcCrQRSXqUqTc6r4dO5g nEqWpspMl8ftz0hrAHPf+3rQFWgGVaMTcXaA0cAOII3HRIgj7+jkEvEB2aHDnDLjPWVmKqey g6U0ERMlrrDmySWMXKbmPuQ4Baf8r4vRwuhs7J22nL0ax71etauIirDG2nUvPCr3zyiXeqXs a78a2t8aLIt85k3F1qK7t/yC+p8ZuaMssn/cJ57s+DKx3jhr2L3tg6R9u2If+bw24kps9V8V 2/ZJzzgHapJOu7cedq89aT91K0yhkCZ81VBZfn2HaUX2nuLkLGY6cMhqqg9EXx79aTxqw7L8 5k2dl7FYs/Bs8fCLWkPa5h3xPtXApb3jsdLtjw/0Rqqn4ruX0Ee9a/zLnhybFlmG+mZ9bwQT v1706oXAUenMQdT4kvNamXm3Zn9YygT+7subEo8fOZZlK12kjOtZ9YktyR7+Tc2g5HZtzMrV 2z8OilNXd74+YaKrmUodmb8qhlAly55dgytVsn8BA0Xh000EAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrJKsWRmVeSWpSXmKPExsVy+t/xu7rKbX3pBh0X5SxOXF/EZLH19yx2 izV7zzFZzD9yjtXiwJ4Si3uXtjBZXPn6ns1i3dML7BYv9jayWFxbMZfdovnYejaLl7PusVl8 7LnHanF51xw2i8+9Rxgttn1uYbNYe+Quu8X6r/OZLBZ+3MpisWTHLkaLts5lrBYXT7la3L13 gsXi5eUeZou2WfwW//fsYLf4d20ji8Xsd/vZLba8mchqcXxtuEXL/iksDvIe72+0snu8efmS xeNwxxd2j73fFrB47Jx1l92jZ+cZRo9NqzrZPO5c28PmMe9koMf97uNMHpuX1Hu0rD3G5NH/ 18Dj/b6rbB59W1Yxelxqvs4eIBylZ1OUX1qSqpCRX1xiqxRtaGGkZ2hpoWdkYqlnaGwea2Vk qqRvZ5OSmpNZllqkb5egl7HtRgNrwQeuiutfjjA2MD7n6GLk5JAQMJHovPuAvYuRi0NIYCmj xIT5j5ggEjIS17pfskDYwhJ/rnWxgdhCAq8YJdpvJILYbAJGEg+Wz2cFsUUEFrNI7N1XCTKI WWAGk8Se51cYQRLCAtYSBye0gxWxCKhKND++xAxi8wo4SNx6cJURYoG8xP6DZ8HinEDx71f3 skMss5e4c7WbEaJeUOLkzCdgBzED1Tdvnc08gVFgFpLULCSpBYxMqxhFUkuLc9Nzi430ihNz i0vz0vWS83M3MQLTzLZjP7fsYFz56qPeIUYmDsZDjBIczEoivKIfetKFeFMSK6tSi/Lji0pz UosPMZoC3T2RWUo0OR+Y6PJK4g3NDEwNTcwsDUwtzYyVxHnZrpxPExJITyxJzU5NLUgtgulj 4uCUamDK1Xzdmz11VrtNT+Na9p0Xj10onPA97+a7gwUffjH4si+vWKhyU+n+zIzUVec3bTbf MHW51DZ22Yu1Nv8OiE94IVvCV6rwa7nbfa+HMxf7txy7vmoua/uOvhf/di1Yc+t8Ml/mlSeT t314e6vCP7PFXyiebwubUsqkK8++njwpsmRC/o1ZHeqmUdfy/lWFHQt+/rrlaNnRpW53jwuy tOQcfdte0XCwvfFmjnd38SpPiZ3f9745UcEymXHG9Dxr01kXazedemrDW7fPoMn1SvbTDQsv 2P3VrL4Xojztpc/OH8JCS3XYLf8++sYVWX42xndbVcOc36Yq33zl1ybVHsi1cc36f+QKXx2r 5P8VW1o/flJiKc5INNRiLipOBADuLq8nvAMAAA== X-CMS-MailID: 20250120172139eucas1p276872579d306da801c455630c0b5c8e5 X-Msg-Generator: CA X-RootMTR: 20250120172139eucas1p276872579d306da801c455630c0b5c8e5 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250120172139eucas1p276872579d306da801c455630c0b5c8e5 References: <20250120172111.3492708-1-m.wilczynski@samsung.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add mailbox device tree node. This work is based on the vendor kernel [1]. Link: https://github.com/revyos/thead-kernel.git [1] Reviewed-by: Drew Fustini Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 5e515a9d69b2..d4cba0713cab 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -606,6 +606,22 @@ timer7: timer@ffffc3303c { status = "disabled"; }; + mbox_910t: mailbox@ffffc38000 { + compatible = "thead,th1520-mbox"; + reg = <0xff 0xffc38000 0x0 0x6000>, + <0xff 0xffc40000 0x0 0x6000>, + <0xff 0xffc4c000 0x0 0x2000>, + <0xff 0xffc54000 0x0 0x2000>; + reg-names = "local", "remote-icu0", "remote-icu1", "remote-icu2"; + clocks = <&clk CLK_MBOX0>, <&clk CLK_MBOX1>, <&clk CLK_MBOX2>, + <&clk CLK_MBOX3>; + clock-names = "clk-local", "clk-remote-icu0", "clk-remote-icu1", + "clk-remote-icu2"; + interrupt-parent = <&plic>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; 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Mon, 20 Jan 2025 17:21:39 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC v3 16/18] riscv: dts: thead: Introduce power domain nodes with aon firmware Date: Mon, 20 Jan 2025 18:21:09 +0100 Message-Id: <20250120172111.3492708-17-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250120172111.3492708-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01Se0xTdxTe797be9vG6qUw+cUtc3TrHiyjsDj5GWXq5rZrzMJcFrY5o6t6 rY0UTAsKugiE0vAoqARDrNAiUXmEjodtRxlIQGgBtaIMCk4eSxiuHVoQyoYGGKV187/vfOc7 5/tOcri48GdyHVeekMQqE6TxIpJPWGzzd94XawpkkQODYtTlLMeQ+ZmOQjUtDgwZOhwcNHLP hKFfvR4S/fRHL4X+bMkg0EBlKYUybbUkculGSDStHeGgvqYSEs3kdwBkmVGTyNgxTKFarwFD l6bNBLrc2ASQJucqB93t+RQNj3QRyNWnxZFGtwYtNTdSaHGgnkAXH7dSyDR5joPsxm+QurWI 2PYa4xnMophJl4tgbmTPUkzLXBnBWHXDFKO13gJMQ3UOyTwYaCYZffduZjTPjjHXLqcxaqMN Y84sRDKe6/0kU2CqBsy9TCf1pXAPf8shNl5+nFVKPvqBf+Rhgw0cs/FSZtyidDBH5QIeF9Ib YL/hGScX8LlCuhJAfckY5i9mAbQ750l/MQPgJesZ4vlI3tht4G9UANjfNhQoJgEsu9XJ8alI +gM4VmFYWRxCZxEwqzNjRYXTDwG0jJeQPlUw/T3M9s5jPkzQYph/3bsSS0Bvg7/33AhEXA9b 227jPsxb5v/ubwlogmD3hfGVTPiyJtN8EfcZQLqKD8e0vwH/8A7oVmtxPw6GbrspsPRVuGQ1 YH6cCMfMTwKaH6FVaw/gzfCB4+lyUO6ywbuwtknip7dDq6mc8NGQXg0HHwX5I6yGhZZi3E8L YLZG6Fe/Bc9r8/8zdVRaAqYMbG6oJ86CMN0Lx+heOEb3v28ZwKtBKJusUshYVVQCeyJCJVWo khNkEQcTFQ1g+bdvLtqfNIJS93REO8C4oB1ALi4KEbw8pZUJBYekqSdZZeJ+ZXI8q2oHr3AJ UaigvDVLJqRl0iT2KMseY5XPuxiXty4dS3VeWBUjLzqX6lK/Z9sooeOuhBV12A+0hPxSHBu2 /ruv5qrC68adHvYw7t4Q/Xp13/4qZU12uqa7LunA068l2EKNaW+44JOS88Q7W6LSeJ6X2FKk 3cljMkajIxc7Jow5lbx/4tZgUWq58G7wpuS1e4vqQ8UpAzvn3973+Ns9uzTXYrcXPjqV+YY7 umc22VWwdbTtMPFmb/XVXRMLQX2f9eNexdGuK8VRsRW5QzDYUZgirT9+Om94Hxq6r9/8hVzf ezBJsWDw4uYGx26lNL9q9pREcefDSeFfn5uK75PiupOeqdPWrWvZHZsmmmQi/Ym0uM6YqbOr jEtt4psxXuPixxtFhOqINCocV6qk/wKK4qUMSgQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKKsWRmVeSWpSXmKPExsVy+t/xu7oqbX3pBreWGlucuL6IyWLr71ns Fmv2nmOymH/kHKvFvUtbmCyufH3PZrHu6QV2ixd7G1ksrq2Yy27RfGw9m8XLWffYLD723GO1 uLxrDpvF594jjBbbPrewWaw9cpfdYv3X+UwWCz9uZbFYsmMXo0Vb5zJWi4unXC3u3jvBYvHy cg+zRdssfov/e3awW/y7tpHFYva7/ewWW95MZLU4vjbcomX/FBYHOY/3N1rZPd68fMnicbjj C7vH3m8LWDx2zrrL7tGz8wyjx6ZVnWwed67tYfOYdzLQ4373cSaPzUvqPVrWHmPy6P9r4PF+ 31U2j74tqxg9LjVfZw8QitKzKcovLUlVyMgvLrFVija0MNIztLTQMzKx1DM0No+1MjJV0rez SUnNySxLLdK3S9DLeL7pGGPBMc6Kz6+UGhi/sXcxcnJICJhIdD84y9jFyMUhJLCUUeL80mNs EAkZiWvdL1kgbGGJP9e62CCKXjFK7Pz5FizBJmAk8WD5fFYQW0RgMYvE3n2VIEXMAm8ZJa7P 3AhWJCwQKfHp2TUwm0VAVaJ331ew1bwCDhIPTx2GOkNeYv/Bs8wgNidQ/PvVvWBxIQF7iTtX uxkh6gUlTs58AjaHGai+eets5gmMArOQpGYhSS1gZFrFKJJaWpybnltsqFecmFtcmpeul5yf u4kRmF62Hfu5eQfjvFcf9Q4xMnEwHmKU4GBWEuEV/dCTLsSbklhZlVqUH19UmpNafIjRFOju icxSosn5wASXVxJvaGZgamhiZmlgamlmrCTO63b5fJqQQHpiSWp2ampBahFMHxMHp1QDk12f s9D3vZNKOPvEVaf88PzZXh/Pk/fL28es+79h1w1xMedut4B76qL+0V2nKl9Lu+yU1/592/K/ lBDnc5NkLws+9rfG0sx5LLzJjxZrPthgub3Bjfvjbwn1C4mtfs8PnTORv20p/rF6Xumvm9wH G+9G8U/ZMjV+l4aZWvOkg3y9p9+8/fP3qU7ubMbZzBuqlpq7cVxduj2v6uKknNrFPN863Cq2 NIbe9nM4beTgllTp3q5WOu+1ydM+hhXnWUXvM9n8ZQtfU3OgizenWbQ+4ce1I5zs/F9uHbof MH//63/T1h5INerWrhNa9F3o5uItG5yqXLnU4/c1x09JrBVcmB10iNn1T2pX8/enkf+UWIoz Eg21mIuKEwEuj26huAMAAA== X-CMS-MailID: 20250120172140eucas1p26bd83fb8195d0ed01b7b214ed374948f X-Msg-Generator: CA X-RootMTR: 20250120172140eucas1p26bd83fb8195d0ed01b7b214ed374948f X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250120172140eucas1p26bd83fb8195d0ed01b7b214ed374948f References: <20250120172111.3492708-1-m.wilczynski@samsung.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The DRM Imagination GPU requires a power-domain driver. In the T-HEAD TH1520 SoC implements power management capabilities through the E902 core, which can be communicated with through the mailbox, using firmware protocol. Add AON node, which servers as a power-domain controller. Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index d4cba0713cab..d6af27cbb786 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -6,6 +6,7 @@ #include #include +#include / { compatible = "thead,th1520"; @@ -229,6 +230,13 @@ stmmac_axi_config: stmmac-axi-config { snps,blen = <0 0 64 32 0 0 0>; }; + aon: aon { + compatible = "thead,th1520-aon"; + mboxes = <&mbox_910t 1>; + mbox-names = "aon"; + #power-domain-cells = <1>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; From patchwork Mon Jan 20 17:21:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13945315 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CCE91C02182 for ; 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Mon, 20 Jan 2025 17:21:42 +0000 (GMT) X-AuditID: cbfec7f2-b11c470000005155-2c-678e8626854d Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 30.B5.19654.6268E876; Mon, 20 Jan 2025 17:21:42 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250120172140eusmtip14b96f653172afd92586847c2fc504f27~cdl2mcYoy1070610706eusmtip17; Mon, 20 Jan 2025 17:21:40 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC v3 17/18] riscv: dts: thead: Introduce reset controller node Date: Mon, 20 Jan 2025 18:21:10 +0100 Message-Id: <20250120172111.3492708-18-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250120172111.3492708-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Se0xTZxjG851zes4pS+FQdHyyAgMiRjOKEDM+M+PcNWfOP+bYBZBEmnks Rm5p6S7MZUKBWNaq4DpZBYtIBikiU6EDBpYhN4FVVy4iQiVbHZcUOiiIOIejHtz87/c97/Pm ed7ko3HxFTKAPpSWySnSZCmhpBdh7ly+ERGef1y+dVqNUPetcgzV/22g0IUWK4aM7VYBstvq MDSw6CLRxXs3KTTZkk2goapSCqk7a0k0ZbCTaE5rF6D+phISuXXtAJnduSSqaR+jUO2iEUPn 5uoJVNHQBFC+5gcB+q3nLTRm7ybQVL8WR/kGH/S4uYFCK0OXCHRm1kKhOmehAHXVfIxyLd8S u4JY13AexTqnpgj22rEFim25X0awjYYxitU29gH2sklDsqNDzSR79vpe9u43XRh7peJrNrem E2NP/LOVdV0dJNnjdSbA2tS3qPfECV47DnAphz7lFJE7k7ySK5Y1WIad/PxUwwh+FHQICoCQ hsw2aB00Eh4WM1UAFtdl8rwA4IhpZwHwWmU3gDOFavB0odXtxvhBJYADRgvgN5wAVg/He5hk ouF4pVHgMa1j8giY15ENPA+cmQDQ7CghPS4/ZjesPm/FPUwwG6F6oIkqADQtYnbBnm6STwuG ll9+fWIRrspLgy2Uh0WML7z+veNJbXzVo64/g/P+S17QVP0Vz29Cm3VuTfeD0111FM8S+LjR iPGcDsfr59c8R2CjtmuNX4Gj1oekpw7ObIa1TZG8/Brsu2bDPDJkvOHwjC/fwBsWmU/jvCyC x/LFvDsc6rW6/0KtVea1UBZe/ENHngQhhmduMTxzi+H/3DKAm4A/p1KmyjllVBr3mVQpS1Wq 0uTST9JTL4PVf9270jXfAEqn56RtAKNBG4A0HrpOtP4vrVwsOiD7IotTpO9XqFI4ZRt4gSZC /UXlljy5mJHLMrnDHJfBKZ5OMVoYcBSLqt5UplF577uxMS6rszdE1zPfLjwf82Wc88IHP65k OSRBUaOPgu7WbBD7Sn/aY4p4TqJ/lLhUODsmCRH6SW/bPgwwnZjdvr+i4/fbk4sJCd4xCQMT d2zv9E0Wh8UHCsn3CTgs0fua/Nz3R83yIqN0r88bjYbT/hKf0o7k6N6DJ4dUk66wj8IsY/hM TvlK+KY41duR4a7EhYxExcTLBxfTN9tjZ4ujHdsbgn/OjDfrYx+2Hi7CkpPOopy8wG1te9Lp lP6RiO80d5JyIl7c8uDcn0uVuuXxwvx4v9HXd2jePdWftT649dVAuvnmkZIHG2Id+EvZJc59 s7YY/fMjinv47qutoYQyWRa1BVcoZf8CuKz5X0YEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKKsWRmVeSWpSXmKPExsVy+t/xu7pqbX3pBp/OclmcuL6IyWLr71ns Fmv2nmOymH/kHKvFvUtbmCyufH3PZrHu6QV2ixd7G1ksrq2Yy27RfGw9m8XLWffYLD723GO1 uLxrDpvF594jjBbbPrewWaw9cpfdYv3X+UwWCz9uZbFYsmMXo0Vb5zJWi4unXC3u3jvBYvHy cg+zRdssfov/e3awW/y7tpHFYva7/ewWW95MZLU4vjbcomX/FBYHOY/3N1rZPd68fMnicbjj C7vH3m8LWDx2zrrL7tGz8wyjx6ZVnWwed67tYfOYdzLQ4373cSaPzUvqPVrWHmPy6P9r4PF+ 31U2j74tqxg9LjVfZw8QitKzKcovLUlVyMgvLrFVija0MNIztLTQMzKx1DM0No+1MjJV0rez SUnNySxLLdK3S9DLWPKzk6ngHlvF5B23mBsYj7J2MXJySAiYSBz4/Jmpi5GLQ0hgKaNE/58L jBAJGYlr3S9ZIGxhiT/Xutggil4xSjR+O8YOkmATMJJ4sHw+2CQRgcUsEnv3VYIUMQu8ZZS4 PnMjWLewgJfE6sXnmEFsFgFVieYru4CaOTh4BRwkTp1gg1ggL7H/4FmwEk6g8Pere8HmCwnY S9y52g12EK+AoMTJmU/ARjID1Tdvnc08gVFgFpLULCSpBYxMqxhFUkuLc9Nzi430ihNzi0vz 0vWS83M3MQLTy7ZjP7fsYFz56qPeIUYmDsZDjBIczEoivKIfetKFeFMSK6tSi/Lji0pzUosP MZoCnT2RWUo0OR+Y4PJK4g3NDEwNTcwsDUwtzYyVxHnZrpxPExJITyxJzU5NLUgtgulj4uCU amBid7+27YLi2jrBXfkuH0RNJizv/RobsjqiPP9i934GhY78lcHL7d90Pn9r0hs03ac1w7ON L407WkhunbquiOCrx8+NCqcx3NR+Kd2y5ckt0WWBOzaXmNut/OJp81zwwMREb9+d6mZtTUv1 fmivc9qxg/PeitIXuy22XTq4ddO1U9NULocstD7/0enZwl9OBq+CPjX98XM4JrDFdaqDtEDq hPWpXGf/crosmcL16KD/tcpVm/36lbjOpn64bfz/3jPrjqkSUu4yN19/q56zY/qE5odujHxW b3y4ypr/nph5VWTRlffLejtu7qsStu/Z19qxdvI/xWV5AgJiQlf3yk3V2ytdnJN64dave67X ToUbKrEUZyQaajEXFScCAIIYsuS4AwAA X-CMS-MailID: 20250120172142eucas1p1028244022b09039f4cc9ce1235c5d80c X-Msg-Generator: CA X-RootMTR: 20250120172142eucas1p1028244022b09039f4cc9ce1235c5d80c X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250120172142eucas1p1028244022b09039f4cc9ce1235c5d80c References: <20250120172111.3492708-1-m.wilczynski@samsung.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" T-HEAD TH1520 SoC requires to put the GPU out of the reset state as part of the power-up sequence. Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index d6af27cbb786..f2c6937341a5 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -497,6 +497,12 @@ clk: clock-controller@ffef010000 { #clock-cells = <1>; }; + rst: reset-controller@ffef528000 { + compatible = "thead,th1520-reset"; + reg = <0xff 0xef528000 0x0 0x4f>; + #reset-cells = <0>; + }; + clk_vo: clock-controller@ffef528050 { compatible = "thead,th1520-clk-vo"; reg = <0xff 0xef528050 0x0 0xfb0>; From patchwork Mon Jan 20 17:21:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13945317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EA897C0218B for ; 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Mon, 20 Jan 2025 17:21:43 +0000 (GMT) X-AuditID: cbfec7f5-e59c770000004fad-73-678e862705f6 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 22.B5.19654.7268E876; Mon, 20 Jan 2025 17:21:43 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250120172142eusmtip1c497cda178b3d2f540bee966e89acc27~cdl31vwG70462804628eusmtip1w; Mon, 20 Jan 2025 17:21:42 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC v3 18/18] riscv: dts: thead: Add GPU node to TH1520 device tree Date: Mon, 20 Jan 2025 18:21:11 +0100 Message-Id: <20250120172111.3492708-19-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250120172111.3492708-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01Se0xTdxTmd+/tvZduxWtx4xfcIzRTokasssRf5kJcBHPnyKZu0WXZgt24 KYQWTAtzshEotBVZAcfckII8jBGCIAFpeaSMDbBFWYs85JEVaJSNx6qAQBXIZJSLm/993znf +b5zkkPj4gYykI6NT+RU8TKFhBQSZuuSY3ewPkcu7XfsR52DVzBkWjFSqKrFgaGSDocAjfbW Y6h/cYZEN/68S6HJFg2BBiouUyjDWkOiKeMoieYMowLU11xEovnsDoDM81oSVXeMUKhmsQRD ZXMmAl1tbAZIf/6aAPXciUAjo50Emuoz4Ehv3IRWLY0UejZQS6DCR60Uqnf/IEC26pNI23qR OPgGOzOko1j31BTBtmcuUGyLp5Rgm4wjFGto+h2wdZXnSdY5YCHZ4tvH2LHvbRh782oqq622 YmzuP1J25pd7JJtTXwnY3oxB6qj4M+G70Zwi9mtOtSfslDDm17IH4PSg8JsCfTlIA046C/jS kHkbprfbqCwgpMVMBYBDjzQ4TxYAXJq8jPFkHsDZznnq+cjIj5MCvlEOoPFp9saIG8A23R+4 V0Uy+6CrvGRdtYXREVB3SwO8BGcmADSPF5FelT/zEVx2VAEvJpht0FX3ZB2LmIOwuawH4/Pe hK2/2dddfdfqT+61ULxmM7xdME54Mb6myTAVrq8BmWohNN2wrUXTayQcpg0j3scfTtvqN254 Da42lWz4J0CX6THO4+9gk8G2gQ9Ap2OZ9NrgzA5Y07yHL78Ha7vGMN7dDw493Mxv4AfzzPk4 XxbBTL2YV2+HPxmy/wt1VJg3QlmY7+ihLoAg4wu3GF+4xfh/binAK0EAl6RWyjl1aDx3JkQt U6qT4uUhXyUo68Dab3c9sy02gorpuZA2gNGgDUAal2wRvTJrkItF0bKzyZwqIUqVpODUbWAr TUgCRFdadXIxI5clcnEcd5pTPe9itG9gGpb7UpRnuao2rHj2wtFLGQ+Pby2qTclu/3KsYNgd aVDo73JLnpmJlb/Lzh7bNx6xP9W9be8JrUfgssYag0T3nQpLwkp3uCdLeiIFP/z6kfyPHd3h mdq5lF0H4iLzJsqm045HHPpkYbtPr/3M/R3yV3e1/Ky82ZDerlk5V3nJ0SDJ/yIoyfPXKbL2 rZc/8LHPPI7+drkvMP3Qh0NPSxmrWVG55Cs852yWBfsXSAtnu4oSocUlYYcik7UnJ/P8THea lq3F0sNOVeOnF69HJg/gyZsCioZt14gjdL+SfD/lneLc1ethcQ92BltCQoNCfWK6unPCNPbd k1HzhnBVqp36/FZfgYRQx8j27sRVatm/RYXFSEoEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGKsWRmVeSWpSXmKPExsVy+t/xu7rqbX3pBm92SVucuL6IyWLr71ns Fmv2nmOymH/kHKvFvUtbmCyufH3PZrHu6QV2ixd7G1ksrq2Yy27RfGw9m8XLWffYLD723GO1 uLxrDpvF594jjBbbPrewWaw9cpfdYv3X+UwWCz9uZbFYsmMXo0Vb5zJWi4unXC3u3jvBYvHy cg+zRdssfov/e3awW/y7tpHFYva7/ewWW95MZLU4vjbcomX/FBYHOY/3N1rZPd68fMnicbjj C7vH3m8LWDx2zrrL7tGz8wyjx6ZVnWwed67tYfOYdzLQ4373cSaPzUvqPVrWHmPy6P9r4PF+ 31U2j74tqxg9LjVfZw8QitKzKcovLUlVyMgvLrFVija0MNIztLTQMzKx1DM0No+1MjJV0rez SUnNySxLLdK3S9DLOLDwMWPBda6KmW3LGRsY73B0MXJySAiYSNyd/IK1i5GLQ0hgKaPEyq/r 2SESMhLXul+yQNjCEn+udbFBFL1ilDj+ex4rSIJNwEjiwfL5YLaIwGIWib37KkGKmAXeMkpc n7kRrFtYwFfi4pejbCA2i4CqxINN3xlBbF4BB4ldCy8yQWyQl9h/8CwziM0JFP9+dS/YFUIC 9hJ3rnZD1QtKnJz5BGwmM1B989bZzBMYBWYhSc1CklrAyLSKUSS1tDg3PbfYSK84Mbe4NC9d Lzk/dxMjMMFsO/Zzyw7Gla8+6h1iZOJgPMQowcGsJMIr+qEnXYg3JbGyKrUoP76oNCe1+BCj KdDdE5mlRJPzgSkuryTe0MzA1NDEzNLA1NLMWEmcl+3K+TQhgfTEktTs1NSC1CKYPiYOTqkG JhY9oQdV2maRz9ZabOfU/sG/enpOKUva5Mx7+v+StKfXyIqw8k+u4Cnfc1F9auyUfbFqvbGM f/WmvnU4szYuukTk1Z1EB7PM+VGRlztiXnMxRq31KmaYsKt6dsTu9dwXY8uzmyQ0yoNb5gaJ uynbu5Xmnczt/TQtwWh3Y0i+gPZGbcWtbAdCH9UxPrae7LFv91Q1vlWG4nsDvoZcN3s97d3t FSkVu/wSj0iUXfwt9uS0f73KR6nQx/6ST8xu97psajlXHxkVuvp7ZPOOSW3lGjEzT7eEmK15 MEfkcYZbAPvTTna9goJN8aXCbW+2rWmN26KiMZPNvezCnN1Orb9evtDe/DNwzevlV5lLeP4p sRRnJBpqMRcVJwIA2EHKMrkDAAA= X-CMS-MailID: 20250120172143eucas1p2cb4c77eee4833b4de668a2aadb5a2087 X-Msg-Generator: CA X-RootMTR: 20250120172143eucas1p2cb4c77eee4833b4de668a2aadb5a2087 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250120172143eucas1p2cb4c77eee4833b4de668a2aadb5a2087 References: <20250120172111.3492708-1-m.wilczynski@samsung.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a device tree node for the IMG BXM-4-64 GPU present in the T-HEAD TH1520 SoC used by the Lichee Pi 4A board. This node enables support for the GPU using the drm/imagination driver. By adding this node, the kernel can recognize and initialize the GPU, providing graphics acceleration capabilities on the Lichee Pi 4A and other boards based on the TH1520 SoC. Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index f2c6937341a5..cf2b1bb2ee96 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -497,6 +497,18 @@ clk: clock-controller@ffef010000 { #clock-cells = <1>; }; + gpu: gpu@ffef400000 { + compatible = "thead,th1520-gpu", "img,img-bxm"; + reg = <0xff 0xef400000 0x0 0x100000>; + interrupt-parent = <&plic>; + interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_vo CLK_GPU_CORE>, + <&clk_vo CLK_GPU_CFG_ACLK>; + clock-names = "core", "sys"; + power-domains = <&aon TH1520_AON_GPU_PD>; + resets = <&rst>; + }; + rst: reset-controller@ffef528000 { compatible = "thead,th1520-reset"; reg = <0xff 0xef528000 0x0 0x4f>;