From patchwork Tue Jan 21 16:18:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13946446 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 603B6C02182 for ; Tue, 21 Jan 2025 16:18:55 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1taGxU-0000NY-Jh; Tue, 21 Jan 2025 11:18:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1taGxP-0000Lu-ML for qemu-devel@nongnu.org; Tue, 21 Jan 2025 11:18:28 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1taGxN-0005zT-R6 for qemu-devel@nongnu.org; Tue, 21 Jan 2025 11:18:27 -0500 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-436a39e4891so40398045e9.1 for ; Tue, 21 Jan 2025 08:18:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1737476304; x=1738081104; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+2sEtAFoFWHQ01p5+N4SGtbcml5iyx/5IH+2u55pyYU=; b=uWmqTyWAUkYeY11VIzZzNu6dkww2abQGqIPyIPcJiT6iiW53J9mPvCLcIzMHdPWed/ ML+nUUvEiFtIwCYzDqmDCzqblnJaybxjbp2oEwbmSUMeKU9KIVb1OZYhr6KlSe+4CTF4 vKWsJq95jnDlc4UmFwkPYZXZwN3gIi6554wGS0Wb8pmeRnL5lZ5HugUhq+5sZxWQyypv /m7H8IiTSem7UbSuPqg41JabIt6WMpfoydt/Vo08cFK9kToYxjJFkEjpbWMX2lKNwX/W kB2CzQmPfPtZm6oAfZrdg59+qbAYx4stB3j/87uUnkga/Ac3bZfoUvRGSZbC5w5hIoJP GgVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737476304; x=1738081104; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+2sEtAFoFWHQ01p5+N4SGtbcml5iyx/5IH+2u55pyYU=; b=C9ihxdttRYUrRaryyyHTAz+lBiwy7TgWcVAr2/d076BgNbu407y9OVZ3YZ9sFFI9wM 79Q41Th2t/uBU7WocGjUbpBBnBETmS0yiCBOEHO5NODBvCBjhRjs8rm/ifIwKAemy6Po rOHC28+sVBuyx7xOo05REmTQK5jHo8bxI9f2pMD1zQMPYndn0oRVusvDmbeYAb43WA1R AXDahb9CafE+QlBhRE9mipAcBdIQYK+GXZoV4mnRPelXI+QTKvDaiP5TDJxf/OmK5Eks XRWTkmnGn5YUTEDGoJzgEzVE+Egk4vcgPrsykJyw/wcVMsZpkUbDQh+68rG7MmkAgN+q iZdQ== X-Gm-Message-State: AOJu0Yy2VX4pZgFneBIYfGHYSBOUfD3vVE8GqMpFOThqhCyHfUoU01Zc flXTvoACMo7NBBKL6to7o7PZSRp1aTWaageIIylMzvTlnrfKGc5qQJ6k9R/gNFDd7L7k5akkumm nojM= X-Gm-Gg: ASbGncsZiYgTIpaIR3srxQdevKrIrCzoRYSiTF0Ju30Hn63Wvr3It+X8v5ACJU71yqt MjceuVr8Q96zoVZNRKZrM2dbetWECOwgNoWkdMOBkDrpXK1q2zFRZDagkpbVrwl9HIC7J1/+HGn XSHZ5Wbr5khMuD0bWVtUfT2vd9yQfAe/tNrwRfgmaZ+8QlrMXLuVvWR4L2vUZOCS2/7Ld2CPT1O iq8zUL5j79jZAOiTnJNlHqOB4o/cbyqoLGCUZxb8rfHnLsUBlmhiiVJiz2BTQ6i3nOcvYQcKtIc A8ze0qmxYXCkuGz4mvhp+MuF5N/GZx9d2nloCtn9Q2ge X-Google-Smtp-Source: AGHT+IHVqbmzrHpbpgLX2XakH9ckSR0ikqCPW62HV7ihCVZEp/lxxvZN70vOCdo3IgRSKmMJZzamwA== X-Received: by 2002:adf:f1cc:0:b0:38b:ed88:f045 with SMTP id ffacd0b85a97d-38bf566fb1bmr14177124f8f.33.1737476303934; Tue, 21 Jan 2025 08:18:23 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38bf322ad81sm13927504f8f.52.2025.01.21.08.18.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 21 Jan 2025 08:18:23 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Aleksandar Rikalo , Jiaxun Yang , Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Huacai Chen , Aurelien Jarno Subject: [PATCH 1/6] hw/pci-host/bonito: Expose output IRQ as QDev GPIO Date: Tue, 21 Jan 2025 17:18:12 +0100 Message-ID: <20250121161817.33654-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250121161817.33654-1-philmd@linaro.org> References: <20250121161817.33654-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Expose IRQ using qdev_init_gpio_out() in bonito_host_realize(), wire it using qdev_connect_gpio_out() in bonito_init(). Signed-off-by: Philippe Mathieu-Daudé --- include/hw/mips/mips.h | 2 +- hw/mips/fuloong2e.c | 2 +- hw/pci-host/bonito.c | 14 +++++++------- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/hw/mips/mips.h b/include/hw/mips/mips.h index 101799f7d3e..1176291cca6 100644 --- a/include/hw/mips/mips.h +++ b/include/hw/mips/mips.h @@ -10,7 +10,7 @@ #include "exec/memory.h" /* bonito.c */ -PCIBus *bonito_init(qemu_irq *pic); +PCIBus *bonito_init(qemu_irq irq); /* rc4030.c */ typedef struct rc4030DMAState *rc4030_dma; diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index 16b6a5129e7..160ceb769dc 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -282,7 +282,7 @@ static void mips_fuloong2e_init(MachineState *machine) cpu_mips_clock_init(cpu); /* North bridge, Bonito --> IP2 */ - pci_bus = bonito_init((qemu_irq *)&(env->irq[2])); + pci_bus = bonito_init(env->irq[2]); /* South bridge -> IP5 */ pci_dev = pci_new_multifunction(PCI_DEVFN(FULOONG2E_VIA_SLOT, 0), diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c index 49669148923..6bc66c9e227 100644 --- a/hw/pci-host/bonito.c +++ b/hw/pci-host/bonito.c @@ -234,7 +234,7 @@ typedef struct PCIBonitoState PCIBonitoState; struct BonitoState { PCIHostState parent_obj; - qemu_irq *pic; + qemu_irq irq; PCIBonitoState *pci_dev; MemoryRegion pci_mem; }; @@ -554,17 +554,16 @@ static const MemoryRegionOps bonito_spciconf_ops = { static void pci_bonito_set_irq(void *opaque, int irq_num, int level) { BonitoState *s = opaque; - qemu_irq *pic = s->pic; PCIBonitoState *bonito_state = s->pci_dev; int internal_irq = irq_num - BONITO_IRQ_BASE; if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) { - qemu_irq_pulse(*pic); + qemu_irq_pulse(s->irq); } else { /* level triggered */ if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) { - qemu_irq_raise(*pic); + qemu_irq_raise(s->irq); } else { - qemu_irq_lower(*pic); + qemu_irq_lower(s->irq); } } } @@ -631,6 +630,7 @@ static void bonito_host_realize(DeviceState *dev, Error **errp) BonitoState *bs = BONITO_PCI_HOST_BRIDGE(dev); MemoryRegion *pcimem_lo_alias = g_new(MemoryRegion, 3); + qdev_init_gpio_out(dev, &bs->irq, 1); memory_region_init(&bs->pci_mem, OBJECT(dev), "pci.mem", BONITO_PCIHI_SIZE); phb->bus = pci_register_root_bus(dev, "pci", pci_bonito_set_irq, pci_bonito_map_irq, @@ -734,7 +734,7 @@ static void bonito_pci_realize(PCIDevice *dev, Error **errp) pci_set_byte(dev->config + PCI_MAX_LAT, 0x00); } -PCIBus *bonito_init(qemu_irq *pic) +PCIBus *bonito_init(qemu_irq irq) { DeviceState *dev; BonitoState *pcihost; @@ -745,8 +745,8 @@ PCIBus *bonito_init(qemu_irq *pic) dev = qdev_new(TYPE_BONITO_PCI_HOST_BRIDGE); phb = PCI_HOST_BRIDGE(dev); pcihost = BONITO_PCI_HOST_BRIDGE(dev); - pcihost->pic = pic; sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + qdev_connect_gpio_out(dev, 0, irq); d = pci_new(PCI_DEVFN(0, 0), TYPE_PCI_BONITO); s = PCI_BONITO(d); From patchwork Tue Jan 21 16:18:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13946452 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BA1CFC0218B for ; Tue, 21 Jan 2025 16:19:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1taGxZ-0000QU-6s; Tue, 21 Jan 2025 11:18:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1taGxU-0000Nd-K1 for qemu-devel@nongnu.org; Tue, 21 Jan 2025 11:18:32 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1taGxS-000609-Kl for qemu-devel@nongnu.org; Tue, 21 Jan 2025 11:18:31 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-43621d27adeso40350745e9.2 for ; Tue, 21 Jan 2025 08:18:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1737476309; x=1738081109; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4AQT8m8tl5nDLX+ETLTSG96DbyWQcasjgSWfLcAwrhg=; b=bQ+0j9EPkOxrwWI0iG8ILlSOQOO6MEezvOWBdCTEvDx2MfCk3nhFgbPH/blP7D2XUn HjI43qUl6VlIM8zY0opQDdPVSlAYjbVfeDp4ge7DUW2JBiXwjNN4RJxLxh52eJZIAGuA ULeLO44SrMl8q035e7y2+KYLLL06RDfUy7d/3xQXwZ7ltK/3fkGWOw2u1X3BTLyEdb6M kg7NVwlGImNF0TWUhmSre5D1dq5Y+9lp8ll5DOvmALb4iS5/SQX/2ZXVOi0yvrjcmUmY O0m/+SXtfu4MUncvDAHJzz5om2hpJ1DCv2C19GSZ+IAjiMSQSQlQ1shCY0ejN0JaI2Bm ssHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737476309; x=1738081109; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4AQT8m8tl5nDLX+ETLTSG96DbyWQcasjgSWfLcAwrhg=; b=ntnwGaAgsVDdL2HC6kJvh7IsIIVGetgMMmyJjIrBXisMBhr/BHSaVW4MJMbVzj874f r4unWkXbvwvIquSA0PSTGnF6ws5JGhd+YdCq03LpGBPLVeVrqshgGzIIk4r5DjPhV/PA fxN5VCVzQgiXRk+TIrjqvMiHb+SU5xLtcjuali1Je+Zn3QZyfmc7NS9+pgomvg5wXxTw m7znswO7bIHLjsGQ2cIanJ0FfsPPsQWlpqd83ivS04i4pcfQTDhRxlDp4Biqz1906BHR WyOwwO3M7NTKd/ex+jY6LurqBd0UYwsb03c922nbuhogj8Ez77q9eXwC61CGntkfmFD3 OjRg== X-Gm-Message-State: AOJu0YwrGnpYeUyffDRgXH8HOxACoFVBwx8A3JsgeBjjdXDOVAUp1Ibc XGil54YTQFMI6Wvfx5foAkk17ql7lpVKmzOmxu4Rh+3T6Nt9mALy8X6jZq2T+HlP8e+AHPSMlt8 Cl+4= X-Gm-Gg: ASbGnctsb1cLzx3iZEzzmqG/OPS59saXkiqLnZkVc09f+qyxpBOKrnkp6jKCybMzeZY n3XRNGIMAhVfdMNs4xxvRKV8ku5wvvxfW8hCDjmF4OUGc0SEkCBRgqLpXsfjI6CxhEr8GFjJDxW qGVhwAiau0y6oT3sJWWR1u5xf//DyZoAG1R3GGTA8/rKmDd3IVyVETWSIYCY2ZfJYmQLMB9/7i/ nA0ZAAmU1/lKi/yDmUGjrmVw08d3B8C7e2brLl0EsBe6Ogv2kMAaXpn1LnPnA2TGDH3QV4tYJBn w9PfDvmMDPdhQpU1A5rQLiXqUrL03PUclNCAEaVDoqUB X-Google-Smtp-Source: AGHT+IGxC/Y3dOIvCvZZz1/tVy6LDHduH8KEbQ/91AQXvuWOks2izhVM+gNaeze66ac0fs1klldjWg== X-Received: by 2002:a05:6000:1a8c:b0:38a:888c:6786 with SMTP id ffacd0b85a97d-38bf57c063fmr16833268f8f.52.1737476308711; Tue, 21 Jan 2025 08:18:28 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38bf322aa0asm14022691f8f.50.2025.01.21.08.18.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 21 Jan 2025 08:18:28 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Aleksandar Rikalo , Jiaxun Yang , Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Huacai Chen , Aurelien Jarno , Richard Henderson Subject: [PATCH 2/6] target/mips: Create clock *after* accelerator vCPU is realized Date: Tue, 21 Jan 2025 17:18:13 +0100 Message-ID: <20250121161817.33654-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250121161817.33654-1-philmd@linaro.org> References: <20250121161817.33654-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Architecture specific hardware doesn't have a particular dependency on the accelerator vCPU (created with cpu_exec_realizefn), and can be initialized *after* the vCPU is realized. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 0b3ac4e60a3..028a3c91afb 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -462,20 +462,6 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev); Error *local_err = NULL; - if (!clock_get(cpu->clock)) { -#ifndef CONFIG_USER_ONLY - if (!qtest_enabled()) { - g_autofree char *cpu_freq_str = freq_to_str(CPU_FREQ_HZ_DEFAULT); - - warn_report("CPU input clock is not connected to any output clock, " - "using default frequency of %s.", cpu_freq_str); - } -#endif - /* Initialize the frequency in case the clock remains unconnected. */ - clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT); - } - mips_cp0_period_set(cpu); - cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); @@ -490,6 +476,20 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) fpu_init(env, env->cpu_model); mvp_init(env); + if (!clock_get(cpu->clock)) { +#ifndef CONFIG_USER_ONLY + if (!qtest_enabled()) { + g_autofree char *cpu_freq_str = freq_to_str(CPU_FREQ_HZ_DEFAULT); + + warn_report("CPU input clock is not connected to any output clock, " + "using default frequency of %s.", cpu_freq_str); + } +#endif + /* Initialize the frequency in case the clock remains unconnected. */ + clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT); + } + mips_cp0_period_set(cpu); + cpu_reset(cs); qemu_init_vcpu(cs); From patchwork Tue Jan 21 16:18:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13946448 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6D5B6C0218E for ; Tue, 21 Jan 2025 16:18:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1taGxa-0000RD-Jc; Tue, 21 Jan 2025 11:18:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1taGxY-0000QL-Uu for qemu-devel@nongnu.org; Tue, 21 Jan 2025 11:18:36 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1taGxX-00060V-8C for qemu-devel@nongnu.org; Tue, 21 Jan 2025 11:18:36 -0500 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-385ef8b64b3so5145797f8f.0 for ; Tue, 21 Jan 2025 08:18:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1737476313; x=1738081113; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9F5G+EcENNTFhblljg4GhllRgsxg85NXRho6Bc5oIjk=; b=riFpidDK/+rvtxGm2DB11zRvudWLvId8tHlNq+3yC0Y0gn8h+JKguAcJ8tJBk4DQoJ uHKlABB2BfEA1UHdUsMWHns4zVxUKC6Hv67Uv/lydhgrmOOA+KAzBUQRL4D7oi+dVXjv /OeUhIGXgMa2AI52UwLHmwGlZOv1DneP8HemDcq3eHgIoxiD6dtP2N4hceI9EYZRVXC5 aXEHcpjpVumC0i/lXAnv/ZlYwHfAtLa8a40CQndtpp+e7v1hfbnrBReGxK1MY5+BdxmP 8xNE+n8sv+VRCgd1Ukii0whnNDK6XDJtSmyBBYb/LBQ5R1oXskrwwvw+SdnvAlikf2/k degg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737476313; x=1738081113; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9F5G+EcENNTFhblljg4GhllRgsxg85NXRho6Bc5oIjk=; b=Iyj2/dX1YLUDE+H5Ii6l4PwN6C9fCJwq/gl5IUB/0cw7PThYaYrZ0oc7jQ5/1B3i9m OKHQvHuuP2rWazfnfIThQcJgU4Otv6A9y8VDCqXHFkjnlAzCOXPrF31u1/y+N8GTxJDW /Dfs2yAq2xLNe+7iqF8CntbisUKevty3jJDHbUCiQw8wEmetE58d4YizL74DVWGiMA+Z 56M/+c7W982Hj/5DOGu0VyJC+qWHdFe7Z6nYF/MzOV7ss38TPqJWeuslpVd1Elp0hLIo WiHK9XyRMEC0DELwZfLkkYdOwOFZTVDSfBkEHZ3MiOxWkgffLG1VG77aNRj7cEdL8LQk oKiw== X-Gm-Message-State: AOJu0YzwYp9QivpT+1/cV3tXC4M0SM40ncrdCTL5euCp9T4qSCDonGiu UKNkqIU+H8JsJM+HG/jLORlsR3L5JMmS66ckaG3IotaL/wkRyVX85dmhj/7k5LwImZOkN9Gr1h7 dHgA= X-Gm-Gg: ASbGncsqJskp0ipiqurdEd1PjKDw0cgXMWoEWvnV+lvrsLoks9ihlbedcZplmOzGJht uyGWjDLknsXskETvs9qd/gLCbfw0tNM+YzU7uotKsOKeJNZcyVCti/oRj+m/J0vzSL0QbKL+Pa0 04zd/k4iKf7oad7PazMcDJyV3LoqkzgbW+MEDFMJByz7xSjGB5+rQPoNqZxcfHilbt/+LWqX0sQ d71A5zothe6Ej1YeC1ekOwk2FF/XbRNper2cg+0G9sTFwaH0QDlemDyTnpyLaJq+Hd27BlOh6dW nfQdCPNErTTFjU/cRwxkb9VW4rOoGUeIRzGlDe1kTUOz X-Google-Smtp-Source: AGHT+IHyD1OyEejg3KwiYKZPeG5lIBRojV9nsSWa6HQA99IbEAqG8O1CxBiVLkEk1Y3f88P4/pUCGQ== X-Received: by 2002:a05:6000:1445:b0:386:37af:dd9a with SMTP id ffacd0b85a97d-38bf57b76a4mr17831665f8f.35.1737476313299; Tue, 21 Jan 2025 08:18:33 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38bf322ad74sm13989453f8f.56.2025.01.21.08.18.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 21 Jan 2025 08:18:32 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Aleksandar Rikalo , Jiaxun Yang , Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Huacai Chen , Aurelien Jarno Subject: [PATCH 3/6] target/mips: Initialize CPU-specific timer/IRQs once in DeviceRealize Date: Tue, 21 Jan 2025 17:18:14 +0100 Message-ID: <20250121161817.33654-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250121161817.33654-1-philmd@linaro.org> References: <20250121161817.33654-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The MIPS timer and IRQs are tied to the CPU. Creating them outside in board code isn't correct. Do it once in the DeviceRealize() handler. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/mips/cps.c | 4 ---- hw/mips/fuloong2e.c | 4 ---- hw/mips/jazz.c | 4 ---- hw/mips/loongson3_virt.c | 4 ---- hw/mips/malta.c | 4 ---- hw/mips/mipssim.c | 4 ---- target/mips/cpu.c | 5 +++++ 7 files changed, 5 insertions(+), 24 deletions(-) diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 0d8cbdc8924..f85fb4458af 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -91,10 +91,6 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) return; } - /* Init internal devices */ - cpu_mips_irq_init_cpu(cpu); - cpu_mips_clock_init(cpu); - if (cpu_mips_itu_supported(env)) { itu_present = true; /* Attach ITC Tag to the VP */ diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index 160ceb769dc..9a638f596bd 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -277,10 +277,6 @@ static void mips_fuloong2e_init(MachineState *machine) } } - /* Init internal devices */ - cpu_mips_irq_init_cpu(cpu); - cpu_mips_clock_init(cpu); - /* North bridge, Bonito --> IP2 */ pci_bus = bonito_init(env->irq[2]); diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index c89610639a9..ce4a702aa53 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -259,10 +259,6 @@ static void mips_jazz_init(MachineState *machine, exit(1); } - /* Init CPU internal devices */ - cpu_mips_irq_init_cpu(cpu); - cpu_mips_clock_init(cpu); - /* Chipset */ rc4030 = rc4030_init(&dmas, &rc4030_dma_mr); sysbus = SYS_BUS_DEVICE(rc4030); diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c index f3cc7a8376f..91070824bbe 100644 --- a/hw/mips/loongson3_virt.c +++ b/hw/mips/loongson3_virt.c @@ -568,10 +568,6 @@ static void mips_loongson3_virt_init(MachineState *machine) /* init CPUs */ cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, false); - - /* Init internal devices */ - cpu_mips_irq_init_cpu(cpu); - cpu_mips_clock_init(cpu); qemu_register_reset(main_cpu_reset, cpu); if (!kvm_enabled()) { diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 4e9cccaa347..ac3b16229c8 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1037,10 +1037,6 @@ static void create_cpu_without_cps(MachineState *ms, MaltaState *s, for (i = 0; i < ms->smp.cpus; i++) { cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk, TARGET_BIG_ENDIAN); - - /* Init internal devices */ - cpu_mips_irq_init_cpu(cpu); - cpu_mips_clock_init(cpu); qemu_register_reset(main_cpu_reset, cpu); } diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c index a294779a82b..d4b3b043053 100644 --- a/hw/mips/mipssim.c +++ b/hw/mips/mipssim.c @@ -203,10 +203,6 @@ mips_mipssim_init(MachineState *machine) reset_info->vector = load_kernel(); } - /* Init CPU internal devices. */ - cpu_mips_irq_init_cpu(cpu); - cpu_mips_clock_init(cpu); - /* * Register 64 KB of ISA IO space at 0x1fd00000. But without interrupts * (except for the hardcoded serial port interrupt) -device cannot work, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 028a3c91afb..95df8985bc6 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -476,6 +476,11 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) fpu_init(env, env->cpu_model); mvp_init(env); + /* Init internal devices */ +#ifndef CONFIG_USER_ONLY + cpu_mips_irq_init_cpu(cpu); + cpu_mips_clock_init(cpu); +#endif if (!clock_get(cpu->clock)) { #ifndef CONFIG_USER_ONLY if (!qtest_enabled()) { From patchwork Tue Jan 21 16:18:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13946451 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 144DFC0218C for ; Tue, 21 Jan 2025 16:19:26 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1taGxk-0000UC-9e; Tue, 21 Jan 2025 11:18:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1taGxe-0000T4-Oe for qemu-devel@nongnu.org; Tue, 21 Jan 2025 11:18:42 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1taGxd-00061D-0w for qemu-devel@nongnu.org; Tue, 21 Jan 2025 11:18:42 -0500 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-436202dd7f6so67587445e9.0 for ; Tue, 21 Jan 2025 08:18:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1737476318; x=1738081118; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Yt2HLyysx4apERQYQylU+akZvlVRd55ruaMuX7GMQQg=; b=NApL2wfOBlYWofXS/PwGNVOei6Y5HnKhrmJ5MuwswUzBO7kINn7pY9/j44JRG23XEc ek+T3rPqATDdLw56D/JL9EVRro0OhI4JZADhJSo1BGqj4X0VGMJJXaMQOWUJC6Nrfp5+ so+I+gthqfkiOQDgh/uIPgyBSnV1lbKFpEGgSQGv5Rmv9odoroLll96V5kGUiS2V1brE pRQ3brgRTRhOfdxUV4+Bst3Tzw75VrupUqS3in66bxWmZTPxOYqeKVBLgQMFXHc+OQdi uL/7im+MoQWnkAbBmIHPgNhOVQzG0r4lpy9fEdorG6xjYY4IQMqhVkHgUl8oLgk881BN ZzAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737476318; x=1738081118; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Yt2HLyysx4apERQYQylU+akZvlVRd55ruaMuX7GMQQg=; b=pHZOZwX8Div2DbbP2hJ+tZE8bOq9YKGqg30LoLndtToKbV6OescYXiDAtGg0orZmyI 4dnDqU6ugatsZv59bjwmNgbzulTOLFP4rBUgYxBk5GVEdXF4rijWOhzbHa7rDaNRvA2x JT7DwAPmWk11djptCaWiUwDLzWS/OI/fNFTg7PPhipB4xSwyagz97rnbAQy+egxVdK+d m+MtxSWCD881nUFhxOj2kKMJtKyM1vSqH+cVVuX9yW4as7csMPh8TYz2akw4Nlm81XNC HDszlNvV+8wcW7qwHW5q13dPQ5tK13hc44Yvk3tkkypl/cjphG4xRyq3qBg9oo+XEAip DO6Q== X-Gm-Message-State: AOJu0YwzV/crJtd59XNdVHeQfozCzadk0deSld7suPzIff0h/DI/362M jDFXsXFJcwi8UQacRiZKayjT0k6cGarKUseNWhXt71v3e7yV01M6RtoUafNukonQtK07ei7bYEV z/wk= X-Gm-Gg: ASbGncsTK/iReh8xNVVVzN/IsjvVQ6TIkj4Y8yVJpCk+SpSGrCOnkRPOtKg0lQcY1tb p3dERGYEERUElGsVC+SaVL3NZwCZEC/juMx/e5ll1ylI05qgUXDlYX6ysQb8jYu5LA7DdUUJuu0 oxoKAxpauwY2YBbqugPA9VjcLglV9OF6i/4+J11I/ISOKUTsuorMXyyyrlRARKG71+1E0dRTfkM Lz1bwIUlkLvmcd05ZEKHIzF2gvUUjSiZHCSI9OKu2EFPZU8WP4gB9B5PWZVzFhXYynsAEEFrYT1 +HKdvNkqb6fAUeBPPh1SgwMpgS9iNJM7i3gkaaHa/H3R X-Google-Smtp-Source: AGHT+IGZW3JIAN3dV0dqZL4zhY0trbXlZuYejIcfpvgB1Hx5XWPeh0szKqLz6CCqWXYDoBRdEgQSBg== X-Received: by 2002:a05:600c:5027:b0:435:294:f1c8 with SMTP id 5b1f17b1804b1-4389143164dmr146199865e9.28.1737476318079; Tue, 21 Jan 2025 08:18:38 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-437c74ac61csm244464805e9.14.2025.01.21.08.18.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 21 Jan 2025 08:18:37 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Aleksandar Rikalo , Jiaxun Yang , Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Huacai Chen , Aurelien Jarno Subject: [PATCH 4/6] target/mips: Pass env to cpu_mips_clock_init() Date: Tue, 21 Jan 2025 17:18:15 +0100 Message-ID: <20250121161817.33654-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250121161817.33654-1-philmd@linaro.org> References: <20250121161817.33654-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Simplify cpu_mips_clock_init() by having it directly take a CPU env, move its declaration from "cpu.h" to "internal.h", as it shouldn't be accessible from hw/. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.h | 1 - target/mips/internal.h | 1 + target/mips/cpu.c | 2 +- target/mips/system/cp0_timer.c | 4 +--- 4 files changed, 3 insertions(+), 5 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index f6877ece8b4..e5767ea9cf3 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1361,7 +1361,6 @@ uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr); /* HW declaration specific to the MIPS target */ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); void cpu_mips_irq_init_cpu(MIPSCPU *cpu); -void cpu_mips_clock_init(MIPSCPU *cpu); #endif /* !CONFIG_USER_ONLY */ diff --git a/target/mips/internal.h b/target/mips/internal.h index 28eb28936ba..69452aae5bc 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -214,6 +214,7 @@ void cpu_mips_store_count(CPUMIPSState *env, uint32_t value); void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value); void cpu_mips_start_count(CPUMIPSState *env); void cpu_mips_stop_count(CPUMIPSState *env); +void cpu_mips_clock_init(CPUMIPSState *env); static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value) { diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 95df8985bc6..99f442a4b98 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -479,7 +479,7 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) /* Init internal devices */ #ifndef CONFIG_USER_ONLY cpu_mips_irq_init_cpu(cpu); - cpu_mips_clock_init(cpu); + cpu_mips_clock_init(env); #endif if (!clock_get(cpu->clock)) { #ifndef CONFIG_USER_ONLY diff --git a/target/mips/system/cp0_timer.c b/target/mips/system/cp0_timer.c index ca16945cee1..07641cab521 100644 --- a/target/mips/system/cp0_timer.c +++ b/target/mips/system/cp0_timer.c @@ -133,10 +133,8 @@ static void mips_timer_cb(void *opaque) cpu_mips_timer_expire(env); } -void cpu_mips_clock_init(MIPSCPU *cpu) +void cpu_mips_clock_init(CPUMIPSState *env) { - CPUMIPSState *env = &cpu->env; - /* * If we're in KVM mode, don't create the periodic timer, that is handled in * kernel. From patchwork Tue Jan 21 16:18:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13946450 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CFA81C0218C for ; Tue, 21 Jan 2025 16:19:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1taGxn-0000WI-5N; Tue, 21 Jan 2025 11:18:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1taGxi-0000US-Bz for qemu-devel@nongnu.org; Tue, 21 Jan 2025 11:18:48 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1taGxg-00061b-Nm for qemu-devel@nongnu.org; Tue, 21 Jan 2025 11:18:46 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-436202dd7f6so67588615e9.0 for ; Tue, 21 Jan 2025 08:18:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1737476323; x=1738081123; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jD9cKuVG+XCXNdxUzPMfstzm3XeEou9OddK//dDoGtY=; b=ZomgAgN99xb988bXVVrdspoR08ewc2ow2Hj27290qoAoRcQlevEpVW1pChcuhcN8dx HpsQXASlkr6D0wNpBftfF2WznMH7NfRyIQ62skfAh8fhq9abtjcvmkz/rSu5B0bkJMLy 48SXs7WVx9/FxQ74oK/7n1s7CTogSn6J9be5YeOCnmiEVsWBEuOsSwDLUJVNvREg+SFK 8xNzHfz3cDH0Nbz0RiJRriGpyks6A7p/xgO6FjPWsbR30+7wq1nfcbNTlXSEuvSJ889j PvoBsLXFfXFTRjiM0dXvXy00jT03Z23121tKD+/IV1GDxN33AOm4ot0pALXWZ8KU9zvN /uRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737476323; x=1738081123; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jD9cKuVG+XCXNdxUzPMfstzm3XeEou9OddK//dDoGtY=; b=aNU6IFgD6dN1c9jFKY6Wu5ED1HEvED0GFeXSirdU5TnSCGvB1DUhGgALsqBtnMXPaC H/4Vr9q8SIqjuLd6TvMG9FWunAt10RGyisez+z+jn+wcrzkW9/POiWdyNBW3D6eOcUNF qZ7uMcRGupIFI3nvBVfHW7bhDA1iaex7ZBj4J6Yt5+uHLoZXEYp66OexOwX6VB9kIQ/X f555iYxPM+iqVyMGRNU4jP8UFGdX8zOefgpDOIYXSdtkLtv39dGGLHPuIfrZanhuskp3 YyfZDmwykyRo8vwVhBZ/IxiWWOEzhxkFHsp3s9eLTBduZAdJCPVzCazDTmE2+fqAUJRM s6mA== X-Gm-Message-State: AOJu0Yymw/KSFj4PK1I59x1C4V+hXWpbi1unosPBm10M5JW/efoemAPz yCG5wHc9CTrIqInyq0KfpejiKU2nKcj+1jLX6m2mTYz8pHmOJlvi/pzaZ3s49eGbDq8z3uhvSab z55c= X-Gm-Gg: ASbGncsQipgWLT5ZPFJdNAURA0wcjeuM6QyfhcJdnONCb54w+vSZROuhKBV3Nwliz5i Mt9dOz2FDE4JTuXJRIrJz/34obdTW/HxqrWOeEVjqyZVqIdl+UEKvNx7JcCUbgaW0EYVKDMPdGL PNw53B1eKM7ooAtC+tYfvEQLosAymii9WW9/QKUajOAMWEpNSZfK1k6xvlIVTeTWfwIglghkeUQ ddy/YvcHtBzlheJ7xA0BnMbQwbEqaeRI7LDQYUcq2h1cLjgNZTHMTIHYmUPn1AxgTtFdAsib6Zk buHUY/kInN9XsYkZkuLEm6Ij65VOt45RRRx8G5lWlXx7 X-Google-Smtp-Source: AGHT+IF7vvsUi381YAGAe41EtW3dijPioRmlnJwl+LbFrjfbgmN18MuSaaQs8D8+VDw6ucoPmrCJuw== X-Received: by 2002:a05:600c:5119:b0:434:fa61:fdfb with SMTP id 5b1f17b1804b1-438913f0620mr163155385e9.18.1737476322835; Tue, 21 Jan 2025 08:18:42 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43890468c67sm187575405e9.34.2025.01.21.08.18.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 21 Jan 2025 08:18:42 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Aleksandar Rikalo , Jiaxun Yang , Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Huacai Chen , Aurelien Jarno Subject: [PATCH 5/6] target/mips: Move CPU timer from hw/mips/ to target/mips/system/ Date: Tue, 21 Jan 2025 17:18:16 +0100 Message-ID: <20250121161817.33654-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250121161817.33654-1-philmd@linaro.org> References: <20250121161817.33654-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org MIPS CPU timer is tied to the CPU, no point of modelling it as a general timer device. Move mips_int.c to target/mips/system/. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/mips/mips_int.c => target/mips/system/interrupts.c | 0 hw/mips/meson.build | 2 +- target/mips/system/meson.build | 1 + 3 files changed, 2 insertions(+), 1 deletion(-) rename hw/mips/mips_int.c => target/mips/system/interrupts.c (100%) diff --git a/hw/mips/mips_int.c b/target/mips/system/interrupts.c similarity index 100% rename from hw/mips/mips_int.c rename to target/mips/system/interrupts.c diff --git a/hw/mips/meson.build b/hw/mips/meson.build index fcbee53bb32..6dd97331ca7 100644 --- a/hw/mips/meson.build +++ b/hw/mips/meson.build @@ -1,5 +1,5 @@ mips_ss = ss.source_set() -mips_ss.add(files('bootloader.c', 'mips_int.c')) +mips_ss.add(files('bootloader.c')) common_ss.add(when: 'CONFIG_FW_CFG_MIPS', if_true: files('fw_cfg.c')) mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c', 'loongson3_virt.c')) mips_ss.add(when: 'CONFIG_MALTA', if_true: files('malta.c')) diff --git a/target/mips/system/meson.build b/target/mips/system/meson.build index 498cf289d6f..cf232c9edad 100644 --- a/target/mips/system/meson.build +++ b/target/mips/system/meson.build @@ -2,6 +2,7 @@ mips_system_ss.add(files( 'addr.c', 'cp0.c', 'cp0_timer.c', + 'interrupts.c', 'machine.c', 'mips-qmp-cmds.c', 'physaddr.c', From patchwork Tue Jan 21 16:18:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13946449 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 15C5DC02182 for ; Tue, 21 Jan 2025 16:19:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1taGxq-0000e3-VO; Tue, 21 Jan 2025 11:18:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1taGxn-0000WJ-GT for qemu-devel@nongnu.org; Tue, 21 Jan 2025 11:18:51 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1taGxl-000623-ET for qemu-devel@nongnu.org; Tue, 21 Jan 2025 11:18:51 -0500 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-385f06d0c8eso3125629f8f.0 for ; Tue, 21 Jan 2025 08:18:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1737476327; x=1738081127; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ymQLxILP6KEtEAWt2AfXSUgSXSVS/hfsSOWZfTMTJgk=; b=IwcOs87YnVU7NeJkbTQNMr99fzgK64J+E4tG3oSn001PTnptdT1l7knTSSfVLry3oN pKMFfsnRp365QrZ33wqUPIhzAYCRYTqyH1TtZMH9wXdUFoLQcZpdOUNvXLhFLTWH+RCI xutBj+0eOB9NtDnOSME9pq2ixL+yCCKqc7cQJS5STbB1jALIax3SpPvGTgfAan+yizkR bt+PExAiQtuA7PuOVtox6U0RwSpSB/rI5B386NGypZBsppGJMrHjaGEzN7CKLvufZ/BE GK9Zx1SKdHD4ELYEuiDeGIJ4UpWXQM5/RBbqaJELW3wG9Sv902xgS+V0OvzyWlE944Wu ccPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737476327; x=1738081127; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ymQLxILP6KEtEAWt2AfXSUgSXSVS/hfsSOWZfTMTJgk=; b=fuTKr5D5PX1G6JCCagW20/hEMXyxxk7A/ZXs6X6P+5Zx7yI/1e1zV0f+9VzQXQSQO6 Q/03SnnJs37S/OuC9I5Y81Qv5Y/K7GfK/VeQvbwcQX/XFNYUJPD9OMKDPiDICEbTWXod UTMmoOZx9pE9vb7u7ff0hFVrT6dvzSjb19wmiA4ZeUsxrP41Cv5YurYC9pCl9YZP0keR D/fX3vvsMlAk9iA64QUXkHRrXEpSO/WMtLkAs9hjGh12GkdEaZWY2kuPRQznkHZZnIw/ gwsVMw62mLKruTgOqIobszbqd/B1YR+ku95K+111nl4pyeV5Oi9PtKiI6slxUPdXttJE QU/g== X-Gm-Message-State: AOJu0Yx3pKMWD/lcfAPCqFlZEc62Ujyh9/IkD+hPzMccRKZ5kqJY+aJQ FUDp8PdKE2a9U9suHsdkDEAdcKUa0t48pursWkgPCucFJ214LbJwqZ6rb6eND/PtG4u//KnZ5+t dhSo= X-Gm-Gg: ASbGncsB+08Z0AiwhiLd5E90g6sqP2MaQD5Zz0oda2icDXtBrlsI1GSFJ7I4d5x8iug yeOp/kBSxkYqwlvzKMCiuFk2NxL+JmABlqTatu8aznEC16x6XxJl1UyfH4lWkh2f0YYFmiNr2ZF qsqj9W23KtqURPqWSbgZA9+v3uMMJcqD53qA0r9WlgZLM9FS56XO865nLehVyL07sPO3A5SU5Ea 6crOGsVW0QcX+uZ4lBOyd21TYkaQIa8ppj+OaEK2LfAaHxveEAHe8LxFolZkneM1MG+60wEV2Vw TQBsjZCJZLCg7xtj7Y8/3QlNi7pEjuGcu1ml7vDVEkhm X-Google-Smtp-Source: AGHT+IEoRsjblS7awvdbiWLy0wu2UxsFNRcTVd8ZOpWBkQKaYkdOSg68eiPPYtzdETE8IbTdb6jOIA== X-Received: by 2002:a05:6000:1564:b0:38b:d7d2:12f2 with SMTP id ffacd0b85a97d-38bf59f4422mr17330799f8f.54.1737476327518; Tue, 21 Jan 2025 08:18:47 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38bf321505asm13655776f8f.7.2025.01.21.08.18.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 21 Jan 2025 08:18:47 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Aleksandar Rikalo , Jiaxun Yang , Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Huacai Chen , Aurelien Jarno Subject: [PATCH 6/6] target/mips: Allocate CPU IRQs within CPUMIPSState Date: Tue, 21 Jan 2025 17:18:17 +0100 Message-ID: <20250121161817.33654-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250121161817.33654-1-philmd@linaro.org> References: <20250121161817.33654-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org There are always 8 IRQs created with a MIPS CPU. Allocate their state once in CPUMIPSState, initialize them in place in cpu_mips_irq_init_cpu(). Update hw/ uses. Move cpu_mips_irq_init_cpu() declaration from "cpu.h" to "internal.h", as it shouldn't be accessible from hw/. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/cpu.h | 4 ++-- target/mips/internal.h | 2 ++ hw/intc/mips_gic.c | 4 ++-- hw/mips/fuloong2e.c | 4 ++-- hw/mips/jazz.c | 6 +++--- hw/mips/loongson3_virt.c | 4 ++-- hw/mips/malta.c | 4 ++-- hw/mips/mipssim.c | 4 ++-- target/mips/system/cp0_timer.c | 4 ++-- target/mips/system/interrupts.c | 11 +++-------- 10 files changed, 22 insertions(+), 25 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index e5767ea9cf3..25a19b61913 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -8,6 +8,7 @@ #endif #include "fpu/softfloat-types.h" #include "hw/clock.h" +#include "hw/irq.h" #include "mips-defs.h" typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; @@ -1177,7 +1178,7 @@ typedef struct CPUArchState { CPUMIPSMVPContext *mvp; #if !defined(CONFIG_USER_ONLY) CPUMIPSTLBContext *tlb; - qemu_irq irq[8]; + IRQState irq[8]; MemoryRegion *itc_tag; /* ITC Configuration Tags */ /* Loongson IOCSR memory */ @@ -1360,7 +1361,6 @@ uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr); /* HW declaration specific to the MIPS target */ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); -void cpu_mips_irq_init_cpu(MIPSCPU *cpu); #endif /* !CONFIG_USER_ONLY */ diff --git a/target/mips/internal.h b/target/mips/internal.h index 69452aae5bc..63a56254bee 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -160,6 +160,8 @@ void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); +void cpu_mips_irq_init_cpu(MIPSCPU *cpu); + extern const VMStateDescription vmstate_mips_cpu; static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) diff --git a/hw/intc/mips_gic.c b/hw/intc/mips_gic.c index 5e3cbeabece..e5b16538305 100644 --- a/hw/intc/mips_gic.c +++ b/hw/intc/mips_gic.c @@ -50,7 +50,7 @@ static void mips_gic_set_vp_irq(MIPSGICState *gic, int vp, int pin) pin + GIC_CPU_PIN_OFFSET, ored_level); } else { - qemu_set_irq(gic->vps[vp].env->irq[pin + GIC_CPU_PIN_OFFSET], + qemu_set_irq(&gic->vps[vp].env->irq[pin + GIC_CPU_PIN_OFFSET], ored_level); } } @@ -203,7 +203,7 @@ static void gic_timer_expire_cb(void *opaque, uint32_t vp_index) if (gic->vps[vp_index].compare_map & GIC_MAP_TO_PIN_MSK) { /* it is safe to set the irq high regardless of other GIC IRQs */ uint32_t pin = (gic->vps[vp_index].compare_map & GIC_MAP_MSK); - qemu_irq_raise(gic->vps[vp_index].env->irq + qemu_irq_raise(&gic->vps[vp_index].env->irq [pin + GIC_CPU_PIN_OFFSET]); } } diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index 9a638f596bd..ccebc56adec 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -278,7 +278,7 @@ static void mips_fuloong2e_init(MachineState *machine) } /* North bridge, Bonito --> IP2 */ - pci_bus = bonito_init(env->irq[2]); + pci_bus = bonito_init(&env->irq[2]); /* South bridge -> IP5 */ pci_dev = pci_new_multifunction(PCI_DEVFN(FULOONG2E_VIA_SLOT, 0), @@ -296,7 +296,7 @@ static void mips_fuloong2e_init(MachineState *machine) object_resolve_path_component(OBJECT(pci_dev), "rtc"), "date"); - qdev_connect_gpio_out_named(DEVICE(pci_dev), "intr", 0, env->irq[5]); + qdev_connect_gpio_out_named(DEVICE(pci_dev), "intr", 0, &env->irq[5]); dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide")); pci_ide_create_devs(PCI_DEVICE(dev)); diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index ce4a702aa53..85728ab45ad 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -262,8 +262,8 @@ static void mips_jazz_init(MachineState *machine, /* Chipset */ rc4030 = rc4030_init(&dmas, &rc4030_dma_mr); sysbus = SYS_BUS_DEVICE(rc4030); - sysbus_connect_irq(sysbus, 0, env->irq[6]); - sysbus_connect_irq(sysbus, 1, env->irq[3]); + sysbus_connect_irq(sysbus, 0, &env->irq[6]); + sysbus_connect_irq(sysbus, 1, &env->irq[3]); memory_region_add_subregion(address_space, 0x80000000, sysbus_mmio_get_region(sysbus, 0)); memory_region_add_subregion(address_space, 0xf0000000, @@ -284,7 +284,7 @@ static void mips_jazz_init(MachineState *machine, isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort); /* ISA devices */ - i8259 = i8259_init(isa_bus, env->irq[4]); + i8259 = i8259_init(isa_bus, &env->irq[4]); isa_bus_register_input_irqs(isa_bus, i8259); i8257_dma_init(OBJECT(rc4030), isa_bus, 0); pit = i8254_pit_init(isa_bus, 0x40, 0, NULL); diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c index 91070824bbe..f1403826fc5 100644 --- a/hw/mips/loongson3_virt.c +++ b/hw/mips/loongson3_virt.c @@ -573,7 +573,7 @@ static void mips_loongson3_virt_init(MachineState *machine) if (!kvm_enabled()) { hwaddr base = ((hwaddr)node << 44) + virt_memmap[VIRT_IPI].base; base += core * 0x100; - qdev_connect_gpio_out(ipi, i, cpu->env.irq[6]); + qdev_connect_gpio_out(ipi, i, &cpu->env.irq[6]); sysbus_mmio_map(SYS_BUS_DEVICE(ipi), i + 2, base); } @@ -594,7 +594,7 @@ static void mips_loongson3_virt_init(MachineState *machine) for (ip = 0; ip < 4 ; ip++) { int pin = core * LOONGSON3_CORE_PER_NODE + ip; sysbus_connect_irq(SYS_BUS_DEVICE(liointc), - pin, cpu->env.irq[ip + 2]); + pin, &cpu->env.irq[ip + 2]); } } env = &MIPS_CPU(first_cpu)->env; diff --git a/hw/mips/malta.c b/hw/mips/malta.c index ac3b16229c8..425d836f476 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1042,8 +1042,8 @@ static void create_cpu_without_cps(MachineState *ms, MaltaState *s, cpu = MIPS_CPU(first_cpu); env = &cpu->env; - *i8259_irq = env->irq[2]; - *cbus_irq = env->irq[4]; + *i8259_irq = &env->irq[2]; + *cbus_irq = &env->irq[4]; } static void create_cps(MachineState *ms, MaltaState *s, diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c index d4b3b043053..4277b40d723 100644 --- a/hw/mips/mipssim.c +++ b/hw/mips/mipssim.c @@ -223,13 +223,13 @@ mips_mipssim_init(MachineState *machine) qdev_prop_set_uint8(dev, "regshift", 0); qdev_prop_set_uint8(dev, "endianness", DEVICE_LITTLE_ENDIAN); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, env->irq[4]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, &env->irq[4]); memory_region_add_subregion(get_system_io(), 0x3f8, sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); } /* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */ - mipsnet_init(0x4200, env->irq[2]); + mipsnet_init(0x4200, &env->irq[2]); } static void mips_mipssim_machine_init(MachineClass *mc) diff --git a/target/mips/system/cp0_timer.c b/target/mips/system/cp0_timer.c index 07641cab521..5600af66bc4 100644 --- a/target/mips/system/cp0_timer.c +++ b/target/mips/system/cp0_timer.c @@ -57,7 +57,7 @@ static void cpu_mips_timer_expire(CPUMIPSState *env) if (env->insn_flags & ISA_MIPS_R2) { env->CP0_Cause |= 1 << CP0Ca_TI; } - qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); + qemu_irq_raise(&env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); } uint32_t cpu_mips_get_count(CPUMIPSState *env) @@ -105,7 +105,7 @@ void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value) if (env->insn_flags & ISA_MIPS_R2) { env->CP0_Cause &= ~(1 << CP0Ca_TI); } - qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); + qemu_irq_lower(&env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); } void cpu_mips_start_count(CPUMIPSState *env) diff --git a/target/mips/system/interrupts.c b/target/mips/system/interrupts.c index 26fdb934f50..f85bb66de3c 100644 --- a/target/mips/system/interrupts.c +++ b/target/mips/system/interrupts.c @@ -25,6 +25,7 @@ #include "hw/irq.h" #include "system/kvm.h" #include "kvm_mips.h" +#include "internal.h" static void cpu_mips_irq_request(void *opaque, int irq, int level) { @@ -58,14 +59,8 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level) void cpu_mips_irq_init_cpu(MIPSCPU *cpu) { CPUMIPSState *env = &cpu->env; - qemu_irq *qi; - int i; - qi = qemu_allocate_irqs(cpu_mips_irq_request, cpu, 8); - for (i = 0; i < 8; i++) { - env->irq[i] = qi[i]; - } - g_free(qi); + qemu_init_irqs(env->irq, ARRAY_SIZE(env->irq), cpu_mips_irq_request, cpu); } void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level) @@ -74,5 +69,5 @@ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level) return; } - qemu_set_irq(env->irq[irq], level); + qemu_set_irq(&env->irq[irq], level); }