From patchwork Wed Jan 22 09:30:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Govindapillai, Vinod" X-Patchwork-Id: 13947049 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 31060C0218C for ; Wed, 22 Jan 2025 09:30:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CE1A310E5B6; Wed, 22 Jan 2025 09:30:28 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="kkBUxA8d"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id AADB210E38D; Wed, 22 Jan 2025 09:30:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737538226; x=1769074226; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GnFxqkSDfVsOE00WUPsVpcNEcEIZ+bzTe6jNX9+501U=; b=kkBUxA8djPG+aWR2uW80ptB2UhBW+3zZYXd3AAa3S7gpB7HVn2x09HuT HyJI7Aj/vzYHrKL2KxP224XUIgX4MgIlvnvuuIoNVfmR0NVfrXWwvtg5n X8tAbnshab31GFtzNnexsSh72sWUDhopcq3A0pve70P2abM3fnObAfreH p5snqCrnnJC0i9EzjvV4K2+qKaaPR1Ku+ju7lzr+QhCtQH3TbqfjOnFBe emwFuffop53vGWmCFQJZagFngBqSw52dBscYxHpMVoyqfUihIWz+aoMn/ DuUY4Xw/YXeYFqq3ugxEoyb3W6kVhoZrCyTTUPzNluIs6oSKaTgTNer1I w==; X-CSE-ConnectionGUID: w2e2UwwITGycL1kUvE2Jew== X-CSE-MsgGUID: 3DWDN+EBQSWAcEOqDsdOcA== X-IronPort-AV: E=McAfee;i="6700,10204,11322"; a="38156740" X-IronPort-AV: E=Sophos;i="6.13,224,1732608000"; d="scan'208";a="38156740" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2025 01:30:26 -0800 X-CSE-ConnectionGUID: WtmbllZGTAyMHvWtvcBi4w== X-CSE-MsgGUID: r6GYKjSiQeW5OLnUWlxb4g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,224,1732608000"; d="scan'208";a="137929343" Received: from kniemiec-mobl1.ger.corp.intel.com (HELO vgovind2-mobl3.intel.com) ([10.245.246.31]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2025 01:30:24 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, santhosh.reddy.guddati@intel.com, jani.saarinen@intel.com Subject: [PATCH v4 1/6] drm/i915/xe3: avoid calling fbc activate if fbc is active Date: Wed, 22 Jan 2025 11:30:01 +0200 Message-ID: <20250122093006.405711-2-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122093006.405711-1-vinod.govindapillai@intel.com> References: <20250122093006.405711-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" If FBC is already active, we don't need to call FBC activate routine again during the post plane update. As this will explicitly call the nuke and also rewrite the FBC ctl registers. Xe doesn't support legacy fences. Hence fence programming also not required as part of this fbc_haw_activate. "intel_atomic_commit_tail-> intel_post_plane_update-> intel_fbc_post_update-> _intel_fbc_post_update" path will be executed during the normal flip cases. FBC HW will nuke on sync flip event and driver do not need to call the nuke explicitly. This is much more relevant in case of dirty rectangle support in FBC with the follow-up patches. Nuke on flip in that case will remove all the benefits of fetching only the modified region. Also any FBC related register updates with dirty rectangle support enabled will trigger nuke by FBC HW. The front buffer rendering sequence will call intel_fbc_flush() and which will call intel_fbc_nuke() or intel_fbc_activate() based on FBC status explicitly and won't get impacted by this change. Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/intel_fbc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index df05904bac8a..ab9649dd606c 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1556,11 +1556,22 @@ static void __intel_fbc_disable(struct intel_fbc *fbc) static void __intel_fbc_post_update(struct intel_fbc *fbc) { + struct intel_display *display = fbc->display; + lockdep_assert_held(&fbc->lock); fbc->flip_pending = false; fbc->busy_bits = 0; + /* + * When dirty rectangle is enabled, any updates to FBC registers will + * trigger nuke. So avoid calling intel_fbc_activate if fbc is already + * active and for XE3 cases. Xe doesn't support legacy fences. So + * no need to update the fences as well. + */ + if (DISPLAY_VER(display) >= 30 && fbc->active) + return; + intel_fbc_activate(fbc); } From patchwork Wed Jan 22 09:30:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Govindapillai, Vinod" X-Patchwork-Id: 13947050 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CCA91C02182 for ; Wed, 22 Jan 2025 09:30:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7645C10E69E; Wed, 22 Jan 2025 09:30:31 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="I2Abo9pd"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 31D2310E69C; Wed, 22 Jan 2025 09:30:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737538230; x=1769074230; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XYsyJT8J2OF9pn7ILpJ7PNkcACDwCS/nczJsWSJyF/4=; b=I2Abo9pd7t1aSFa/rf7lUSomeqaW3+uwe+H0393TcOEMyE1G/RxeXlnP do0vO85rqYaMoY464wNiqzf4ROINDtcwoPEmFRQ5XpoLIzdHQ0Vu6ULOE HJTP5zqXyjsT6FVeVmM5FhI/1XqFvTtqm+q9Shpz6ORsg5nCqb9QQNNqS 0lG9BQb6b5AE9mYR35iwlEeX6iGgq2KMCpotmj5TNUNAVayoVzeFTJHg2 e95gYCGss+qdzbw97eByvvI2tV6294VBJe5UtwuxkQvIXOW7Nfl6joaSY t9xpv/KroAWXqFJBDx6H2S27YDDB/FksFv4jxq+LE50OFPrih+fz056p+ A==; X-CSE-ConnectionGUID: XpxGGjCPTUmiSA3kNqsH8g== X-CSE-MsgGUID: LYI15aAKRwuW7rMxAIZ6bA== X-IronPort-AV: E=McAfee;i="6700,10204,11322"; a="38156744" X-IronPort-AV: E=Sophos;i="6.13,224,1732608000"; d="scan'208";a="38156744" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2025 01:30:30 -0800 X-CSE-ConnectionGUID: 1WyhVEsYSW+s26x6kjHoWQ== X-CSE-MsgGUID: mjWknrZiQYWlNzelfLlQnA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,224,1732608000"; d="scan'208";a="137929373" Received: from kniemiec-mobl1.ger.corp.intel.com (HELO vgovind2-mobl3.intel.com) ([10.245.246.31]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2025 01:30:27 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, santhosh.reddy.guddati@intel.com, jani.saarinen@intel.com Subject: [PATCH v4 2/6] drm/i915/xe3: add register definitions for fbc dirty rect support Date: Wed, 22 Jan 2025 11:30:02 +0200 Message-ID: <20250122093006.405711-3-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122093006.405711-1-vinod.govindapillai@intel.com> References: <20250122093006.405711-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Register definitions for FBC dirty rect support Bspec: 71675, 73424 Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/intel_fbc_regs.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h index ae0699c3c2fe..b1d0161a3196 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h @@ -100,6 +100,15 @@ #define FBC_STRIDE_MASK REG_GENMASK(14, 0) #define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x)) +#define XE3_FBC_DIRTY_RECT(fbc_id) _MMIO_PIPE((fbc_id), 0x43230, 0x43270) +#define FBC_DIRTY_RECT_END_LINE_MASK REG_GENMASK(31, 16) +#define FBC_DIRTY_RECT_END_LINE(val) REG_FIELD_PREP(FBC_DIRTY_RECT_END_LINE_MASK, (val)) +#define FBC_DIRTY_RECT_START_LINE_MASK REG_GENMASK(15, 0) +#define FBC_DIRTY_RECT_START_LINE(val) REG_FIELD_PREP(FBC_DIRTY_RECT_START_LINE_MASK, (val)) + +#define XE3_FBC_DIRTY_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x43234, 0x43274) +#define FBC_DIRTY_RECT_EN REG_BIT(31) + #define ILK_FBC_RT_BASE _MMIO(0x2128) #define ILK_FBC_RT_VALID REG_BIT(0) #define SNB_FBC_FRONT_BUFFER REG_BIT(1) From patchwork Wed Jan 22 09:30:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Govindapillai, Vinod" X-Patchwork-Id: 13947051 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9267FC02182 for ; Wed, 22 Jan 2025 09:30:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 158C610E69F; Wed, 22 Jan 2025 09:30:35 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="C4LG8nNF"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8340D10E6A0; Wed, 22 Jan 2025 09:30:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737538233; x=1769074233; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nN9C9wtx4sawb7ch9Ipovk90jG7UMVvTXS9O9dVn2vs=; b=C4LG8nNFKQpDFLoSP53z4tUmBRo3p30SRJUgLsMpA9Tv6f11M96f/aUy WI8WllDPWOoUOEXJgorylws5yeaNxalsIcAXdZRra/seicqWDR09eJ7+Y RyVmyMQmi4yDR36C/bYG3U5d9dVSsaUFLCXSbtTN3VNSZXjjfqiumxwKw wyxlqI0J9bpNObIEK/7dfaeA3BORaacvdNHyzw2XWvH+4rzJOL10FO/wx pvVYSwrw32bPn/gpU9RYH8tgWXQp3ubbddTisJoVTzWVcVJsmB/aaSpFD 7RfR1Z8M808nEan1iHgRJVSO7JNyJ30G+f9Xdvn8MvGlxkrWq1UukhSDF w==; X-CSE-ConnectionGUID: 2Bn/zhKKTtaK+ESDuWR64A== X-CSE-MsgGUID: Qfl5srUKTriB9d/SJmpsHw== X-IronPort-AV: E=McAfee;i="6700,10204,11322"; a="38156746" X-IronPort-AV: E=Sophos;i="6.13,224,1732608000"; d="scan'208";a="38156746" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2025 01:30:33 -0800 X-CSE-ConnectionGUID: iZHqeiQpRW+MrabaX8WGxA== X-CSE-MsgGUID: 3Wdzrx68Sainh1g5pgrjUQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,224,1732608000"; d="scan'208";a="137929406" Received: from kniemiec-mobl1.ger.corp.intel.com (HELO vgovind2-mobl3.intel.com) ([10.245.246.31]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2025 01:30:31 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, santhosh.reddy.guddati@intel.com, jani.saarinen@intel.com Subject: [PATCH v4 3/6] drm/i915/xe3: disable FBC if PSR2 selective fetch is enabled Date: Wed, 22 Jan 2025 11:30:03 +0200 Message-ID: <20250122093006.405711-4-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122093006.405711-1-vinod.govindapillai@intel.com> References: <20250122093006.405711-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" It is not recommended to have both FBC and PSR2 selective fetch be enabled at the same time in a plane. If PSR2 selective fetch or panel replay is on, mark FBC as not possible in that plane. v2: fix the condition to disable FBC if PSR2 enabled (Jani) Bspec: 68881 Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index ab9649dd606c..7eefe699a0e6 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1338,9 +1338,14 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, * Display 12+ is not supporting FBC with PSR2. * Recommendation is to keep this combination disabled * Bspec: 50422 HSD: 14010260002 + * + * In Xe3, PSR2 selective fetch and FBC dirty rect feature cannot + * coexist. So if PSR2 selective fetch is supported then mark that + * FBC is not supported. + * TODO: Need a logic to decide between PSR2 and FBC Dirty rect */ - if (IS_DISPLAY_VER(display, 12, 14) && crtc_state->has_sel_update && - !crtc_state->has_panel_replay) { + if ((IS_DISPLAY_VER(display, 12, 14) || DISPLAY_VER(display) >= 30) && + crtc_state->has_sel_update && !crtc_state->has_panel_replay) { plane_state->no_fbc_reason = "PSR2 enabled"; return 0; } From patchwork Wed Jan 22 09:30:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Govindapillai, Vinod" X-Patchwork-Id: 13947052 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 95DD0C02182 for ; Wed, 22 Jan 2025 09:30:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3B95410E6A1; Wed, 22 Jan 2025 09:30:38 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Fy31gVNP"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1333410E6A0; Wed, 22 Jan 2025 09:30:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737538237; x=1769074237; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cKjobsoe7DIbMk7qRY4RIilWN/J6IxEaiYMi/w0TSdg=; b=Fy31gVNPa6v58POg7hita74qDq8qSg4+8IYYaVy7zSsu5uPBYUqnvGby lHSe1qbdJPtCgt7RG9BKf3GyKu3xqBtDwYetTE21RzqiHVR1BkrGrscLi YJx5wzdz3yFFBwN78ivrMfYkOCoa3pOfKO/nXpJpIANDgkUbOUf7Iudvw UdokpPVhBmZSC27kKQP8zLmcTKsRUhomvHVkvV1kqHhG8gEjM6nbYAsng 2ZzQHn1E0KMoblKYo4n9fz+oLENw1gv5N8KkV3PpyPxvFr5VoYyiWYS+K Pvo+dedCYzX1xismjf1e60HHYZ1O4/EBF/gbrlVMLhqENJZzHwKANOXPH g==; X-CSE-ConnectionGUID: QwjUCXHyR5K7BuMExJ/l7Q== X-CSE-MsgGUID: O3T6faQkSyuiNIj6nk83fg== X-IronPort-AV: E=McAfee;i="6700,10204,11322"; a="38156748" X-IronPort-AV: E=Sophos;i="6.13,224,1732608000"; d="scan'208";a="38156748" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2025 01:30:37 -0800 X-CSE-ConnectionGUID: I9mJmGm2SfWiib/B3oDRAw== X-CSE-MsgGUID: aEuyTVBGToWOwYnkPW0Wyw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,224,1732608000"; d="scan'208";a="137929449" Received: from kniemiec-mobl1.ger.corp.intel.com (HELO vgovind2-mobl3.intel.com) ([10.245.246.31]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2025 01:30:34 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, santhosh.reddy.guddati@intel.com, jani.saarinen@intel.com Subject: [PATCH v4 4/6] drm/i915/xe3: add dirty rect support for FBC Date: Wed, 22 Jan 2025 11:30:04 +0200 Message-ID: <20250122093006.405711-5-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122093006.405711-1-vinod.govindapillai@intel.com> References: <20250122093006.405711-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Dirty rectangle feature allows FBC to recompress a subsection of a frame. When this feature is enabled, display will read the scan lines between dirty rectangle start line and dirty rectangle end line in subsequent frames. v2: Move dirty rect handling to fbc state (Ville) Bspec: 71675, 73424 Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/intel_display.c | 4 + drivers/gpu/drm/i915/display/intel_fbc.c | 96 +++++++++++++++++++- drivers/gpu/drm/i915/display/intel_fbc.h | 4 + 3 files changed, 103 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 10550bc0778e..d154fcd0e77a 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7263,6 +7263,8 @@ static void intel_update_crtc(struct intel_atomic_state *state, commit_pipe_pre_planes(state, crtc); + intel_fbc_program_dirty_rect(NULL, state, crtc); + intel_crtc_planes_update_arm(NULL, state, crtc); commit_pipe_post_planes(state, crtc); @@ -7731,6 +7733,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, new_crtc_state); bdw_set_pipe_misc(new_crtc_state->dsb_commit, new_crtc_state); + intel_fbc_program_dirty_rect(new_crtc_state->dsb_commit, + state, crtc); intel_crtc_planes_update_arm(new_crtc_state->dsb_commit, state, crtc); diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 7eefe699a0e6..963fbe2c7361 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -42,6 +42,7 @@ #include #include +#include #include #include "gem/i915_gem_stolen.h" @@ -58,6 +59,7 @@ #include "intel_display_trace.h" #include "intel_display_types.h" #include "intel_display_wa.h" +#include "intel_dsb.h" #include "intel_fbc.h" #include "intel_fbc_regs.h" #include "intel_frontbuffer.h" @@ -88,6 +90,7 @@ struct intel_fbc_state { u16 override_cfb_stride; u16 interval; s8 fence_id; + struct drm_rect dirty_rect; }; struct intel_fbc { @@ -527,6 +530,9 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc) struct intel_display *display = fbc->display; u32 dpfc_ctl; + if (DISPLAY_VER(display) >= 30) + intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), 0); + /* Disable compression */ dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id)); if (dpfc_ctl & DPFC_CTL_EN) { @@ -670,6 +676,10 @@ static void ivb_fbc_activate(struct intel_fbc *fbc) if (DISPLAY_VER(display) >= 20) intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); + if (DISPLAY_VER(display) >= 30) + intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), + FBC_DIRTY_RECT_EN); + intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), DPFC_CTL_EN | dpfc_ctl); } @@ -1203,6 +1213,85 @@ static bool tiling_is_valid(const struct intel_plane_state *plane_state) return i8xx_fbc_tiling_valid(plane_state); } +static void +__intel_fbc_program_dirty_rect(struct intel_dsb *dsb, struct intel_plane *plane) +{ + struct intel_display *display = to_intel_display(plane); + struct intel_fbc *fbc = plane->fbc; + struct intel_fbc_state *fbc_state = &fbc->state; + + if (fbc_state->plane != plane) + return; + + intel_de_write_dsb(display, dsb, XE3_FBC_DIRTY_RECT(fbc->id), + FBC_DIRTY_RECT_START_LINE(fbc_state->dirty_rect.y1) | + FBC_DIRTY_RECT_END_LINE(fbc_state->dirty_rect.y2)); +} + +void +intel_fbc_program_dirty_rect(struct intel_dsb *dsb, + struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + struct intel_display *display = to_intel_display(state); + struct intel_plane_state __maybe_unused *plane_state; + struct intel_plane *plane; + int i; + + if (DISPLAY_VER(display) < 30) + return; + + for_each_new_intel_plane_in_state(state, plane, plane_state, i) { + struct intel_fbc *fbc = plane->fbc; + + if (!fbc || plane->pipe != crtc->pipe) + continue; + + __intel_fbc_program_dirty_rect(dsb, plane); + } +} + + +static void +update_dirty_rect_to_full_region(struct intel_plane_state *plane_state, + struct drm_rect *dirty_rect) +{ + int y_offset = plane_state->view.color_plane[0].y; + int plane_height = drm_rect_height(&plane_state->uapi.src) >> 16; + + dirty_rect->y1 = y_offset; + dirty_rect->y2 = y_offset + plane_height - 1; +} + +static void +validate_and_clip_dirty_rect(struct intel_plane_state *plane_state, + struct drm_rect *dirty_rect) +{ + int y_offset = plane_state->view.color_plane[0].y; + int plane_height = drm_rect_height(&plane_state->uapi.src) >> 16; + int max_endline = y_offset + plane_height; + + dirty_rect->y1 = clamp(dirty_rect->y1, y_offset, max_endline); + dirty_rect->y2 = clamp(dirty_rect->y2, dirty_rect->y1, max_endline); +} + +static void +intel_fbc_compute_dirty_rect(struct intel_plane *plane, + struct intel_plane_state *old_plane_state, + struct intel_plane_state *new_plane_state) +{ + struct intel_fbc *fbc = plane->fbc; + struct intel_fbc_state *fbc_state = &fbc->state; + struct drm_rect *fbc_dirty_rect = &fbc_state->dirty_rect; + + if (drm_atomic_helper_damage_merged(&old_plane_state->uapi, + &new_plane_state->uapi, + fbc_dirty_rect)) + validate_and_clip_dirty_rect(new_plane_state, fbc_dirty_rect); + else + update_dirty_rect_to_full_region(new_plane_state, fbc_dirty_rect); +} + static void intel_fbc_update_state(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_plane *plane) @@ -1210,8 +1299,10 @@ static void intel_fbc_update_state(struct intel_atomic_state *state, struct intel_display *display = to_intel_display(state->base.dev); const struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - const struct intel_plane_state *plane_state = + struct intel_plane_state *plane_state = intel_atomic_get_new_plane_state(state, plane); + struct intel_plane_state *old_plane_state = + intel_atomic_get_old_plane_state(state, plane); struct intel_fbc *fbc = plane->fbc; struct intel_fbc_state *fbc_state = &fbc->state; @@ -1236,6 +1327,9 @@ static void intel_fbc_update_state(struct intel_atomic_state *state, fbc_state->cfb_stride = intel_fbc_cfb_stride(plane_state); fbc_state->cfb_size = intel_fbc_cfb_size(plane_state); fbc_state->override_cfb_stride = intel_fbc_override_cfb_stride(plane_state); + + if (DISPLAY_VER(display) >= 30) + intel_fbc_compute_dirty_rect(plane, old_plane_state, plane_state); } static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h index ceae55458e14..acaebe15f312 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.h +++ b/drivers/gpu/drm/i915/display/intel_fbc.h @@ -14,6 +14,7 @@ struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; struct intel_display; +struct intel_dsb; struct intel_fbc; struct intel_plane; struct intel_plane_state; @@ -48,5 +49,8 @@ void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display); void intel_fbc_reset_underrun(struct intel_display *display); void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc); void intel_fbc_debugfs_register(struct intel_display *display); +void intel_fbc_program_dirty_rect(struct intel_dsb *dsb, + struct intel_atomic_state *state, + struct intel_crtc *crtc); #endif /* __INTEL_FBC_H__ */ From patchwork Wed Jan 22 09:30:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Govindapillai, Vinod" X-Patchwork-Id: 13947053 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9059AC0218D for ; Wed, 22 Jan 2025 09:30:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3875B10E69C; Wed, 22 Jan 2025 09:30:44 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="nt+wBMaF"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0804010E38D; Wed, 22 Jan 2025 09:30:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737538241; x=1769074241; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zJ5bTZyWFubaBQGIJ6DN7yhT4+Sfu9kpITvAZ+WpoK8=; b=nt+wBMaFyy+WXeDi/G3JiV5PBPrGXTCD0ajQXAmaTqP1L/MCLakVb9Zv R+nku5xD2PEImLXndld/oP7BQ502sw33qYHWPrXlnyHOh7YL6zFelCRNG rpQZfd/d4F+KWj2pR1SSs/ZqfxueVdXCT2xMDzhLjsDjhDOJIT/9gPHKR V5ZG6CbbIy3Rlqu/eBbrnI+75eFACJPD2/KLZw61WKkmAgcQT8R0tqF9T cnI3FAKtFDqnUl76fr0janFxInCGG2zPT9T00LrbAuf9PaItFotFf81iN reEJOE2rRtiLyCLFrBPkWoWEIRXXPeJtcERYT9jiAkIg0tOJ+fDvajtu2 A==; X-CSE-ConnectionGUID: 4UESrMqASpKCwSJX+zZfSA== X-CSE-MsgGUID: VylK/9dISM6Qgsj54Y9DfQ== X-IronPort-AV: E=McAfee;i="6700,10204,11322"; a="38156751" X-IronPort-AV: E=Sophos;i="6.13,224,1732608000"; d="scan'208";a="38156751" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2025 01:30:41 -0800 X-CSE-ConnectionGUID: 9RDXV5tOQKSdIk+cPzSkRw== X-CSE-MsgGUID: ++BZxmL3SPq1sNRxU55hyg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,224,1732608000"; d="scan'208";a="137929522" Received: from kniemiec-mobl1.ger.corp.intel.com (HELO vgovind2-mobl3.intel.com) ([10.245.246.31]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2025 01:30:38 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, santhosh.reddy.guddati@intel.com, jani.saarinen@intel.com Subject: [PATCH v4 5/6] drm/i915/xe3: handle dirty rect update within the scope of DSB Date: Wed, 22 Jan 2025 11:30:05 +0200 Message-ID: <20250122093006.405711-6-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122093006.405711-1-vinod.govindapillai@intel.com> References: <20250122093006.405711-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Programming of the dirty rectangle coordinates should happen within the scope of DSB prepare and finish calls. So call the compute and programming of dirty rectangle related routines early within the DSB programming window. Some of the FBC state handling is done later as part of pre-plane or post-plane updates. So enabling / disabling / hw activate will happen later but it should handle the sequence without any issue. Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/intel_display.c | 3 ++ drivers/gpu/drm/i915/display/intel_fbc.c | 47 ++++++++++++++++---- drivers/gpu/drm/i915/display/intel_fbc.h | 3 ++ 3 files changed, 44 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index d154fcd0e77a..e6e017e65da6 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7773,6 +7773,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_atomic_prepare_plane_clear_colors(state); + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) + intel_fbc_compute_dirty_rect(state, crtc); + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) intel_atomic_dsb_finish(state, crtc); diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 963fbe2c7361..033eb4a3eab0 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1213,6 +1213,10 @@ static bool tiling_is_valid(const struct intel_plane_state *plane_state) return i8xx_fbc_tiling_valid(plane_state); } +static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state, + struct intel_crtc *crtc, + struct intel_plane *plane); + static void __intel_fbc_program_dirty_rect(struct intel_dsb *dsb, struct intel_plane *plane) { @@ -1251,7 +1255,6 @@ intel_fbc_program_dirty_rect(struct intel_dsb *dsb, } } - static void update_dirty_rect_to_full_region(struct intel_plane_state *plane_state, struct drm_rect *dirty_rect) @@ -1276,9 +1279,9 @@ validate_and_clip_dirty_rect(struct intel_plane_state *plane_state, } static void -intel_fbc_compute_dirty_rect(struct intel_plane *plane, - struct intel_plane_state *old_plane_state, - struct intel_plane_state *new_plane_state) +__intel_fbc_compute_dirty_rect(struct intel_plane *plane, + struct intel_plane_state *old_plane_state, + struct intel_plane_state *new_plane_state) { struct intel_fbc *fbc = plane->fbc; struct intel_fbc_state *fbc_state = &fbc->state; @@ -1292,6 +1295,37 @@ intel_fbc_compute_dirty_rect(struct intel_plane *plane, update_dirty_rect_to_full_region(new_plane_state, fbc_dirty_rect); } +void +intel_fbc_compute_dirty_rect(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + struct intel_display *display = to_intel_display(state); + struct intel_plane_state *new_plane_state; + struct intel_plane_state *old_plane_state; + struct intel_plane *plane; + int i; + + if (DISPLAY_VER(display) < 30) + return; + + for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { + struct intel_fbc *fbc = plane->fbc; + + if (!fbc || plane->pipe != crtc->pipe) + continue; + + /* If plane not visible, dirty rect might have invalid coordinates */ + if (!new_plane_state->uapi.visible) + continue; + + /* If FBC to be disabled, then no need to update dirty rect */ + if (!intel_fbc_can_flip_nuke(state, crtc, plane)) + continue; + + __intel_fbc_compute_dirty_rect(plane, old_plane_state, new_plane_state); + } +} + static void intel_fbc_update_state(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_plane *plane) @@ -1301,8 +1335,6 @@ static void intel_fbc_update_state(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); struct intel_plane_state *plane_state = intel_atomic_get_new_plane_state(state, plane); - struct intel_plane_state *old_plane_state = - intel_atomic_get_old_plane_state(state, plane); struct intel_fbc *fbc = plane->fbc; struct intel_fbc_state *fbc_state = &fbc->state; @@ -1327,9 +1359,6 @@ static void intel_fbc_update_state(struct intel_atomic_state *state, fbc_state->cfb_stride = intel_fbc_cfb_stride(plane_state); fbc_state->cfb_size = intel_fbc_cfb_size(plane_state); fbc_state->override_cfb_stride = intel_fbc_override_cfb_stride(plane_state); - - if (DISPLAY_VER(display) >= 30) - intel_fbc_compute_dirty_rect(plane, old_plane_state, plane_state); } static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h index acaebe15f312..87be5653db0f 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.h +++ b/drivers/gpu/drm/i915/display/intel_fbc.h @@ -49,8 +49,11 @@ void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display); void intel_fbc_reset_underrun(struct intel_display *display); void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc); void intel_fbc_debugfs_register(struct intel_display *display); +void intel_fbc_compute_dirty_rect(struct intel_atomic_state *state, + struct intel_crtc *crtc); void intel_fbc_program_dirty_rect(struct intel_dsb *dsb, struct intel_atomic_state *state, struct intel_crtc *crtc); + #endif /* __INTEL_FBC_H__ */ From patchwork Wed Jan 22 09:30:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Govindapillai, Vinod" X-Patchwork-Id: 13947054 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9070C02182 for ; Wed, 22 Jan 2025 09:30:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 725E110E5B9; Wed, 22 Jan 2025 09:30:46 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="efxPpFYm"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5599710E6A3; Wed, 22 Jan 2025 09:30:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737538245; x=1769074245; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4nE2alQEe5k9mjtgvKIETST063OKt/9ueWcsVaa/sDg=; b=efxPpFYmwc8cefLCPYHoRh+HdWq6ZEIlaGknm9i+aa/1QhGRNT4Gv0GL 7/GQAskk553PDoZno/vN+1d5drcKCs77ruVfOTU5sk8nSqxU8KkNVZ00k KmgEFXDFO/L67M9OcttlbwxQ2AObdUcui4tuWcd70KFwutV+xqdSqJ8w+ nMj2AihQ1CzcISs5T1dydJn2Bn/FlL3fhTuAYuRnTAsrY8RcKwua2KqaT 6pSRydMAxxiYXA93CC8sPx7Y8TkuQodTQq/0EQcF7rGrwVpOK0zWaMpnm /lW92Q8XS1UbIIRVmopqWn6gJ+T1bZtOew8+11z/0sVyAP5IN9OrZE+gW A==; X-CSE-ConnectionGUID: U69oexSnQ5u0YedvVvHkSg== X-CSE-MsgGUID: jxPxurfITNijr6IQmPyMMA== X-IronPort-AV: E=McAfee;i="6700,10204,11322"; a="38156760" X-IronPort-AV: E=Sophos;i="6.13,224,1732608000"; d="scan'208";a="38156760" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2025 01:30:45 -0800 X-CSE-ConnectionGUID: 0CBWvVUXSFai9LEwqGVPmQ== X-CSE-MsgGUID: NQDSIl2kTV+Aswm0TLNArA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,224,1732608000"; d="scan'208";a="137929625" Received: from kniemiec-mobl1.ger.corp.intel.com (HELO vgovind2-mobl3.intel.com) ([10.245.246.31]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2025 01:30:42 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, santhosh.reddy.guddati@intel.com, jani.saarinen@intel.com Subject: [PATCH v4 6/6] drm/i915/xe3: introduce a dirty rectangle state variable Date: Wed, 22 Jan 2025 11:30:06 +0200 Message-ID: <20250122093006.405711-7-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122093006.405711-1-vinod.govindapillai@intel.com> References: <20250122093006.405711-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To avoid programming garbage to dirty rectangle registers, introduce a state variable to track the validity of the dirty rectangle update scenarios. Program the dirty rectangle coordinate only if this state variable is valid. Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/intel_fbc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 033eb4a3eab0..ab8acb1cc090 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -91,6 +91,7 @@ struct intel_fbc_state { u16 interval; s8 fence_id; struct drm_rect dirty_rect; + bool dr_valid; }; struct intel_fbc { @@ -1227,6 +1228,9 @@ __intel_fbc_program_dirty_rect(struct intel_dsb *dsb, struct intel_plane *plane) if (fbc_state->plane != plane) return; + if (!fbc_state->dr_valid) + return; + intel_de_write_dsb(display, dsb, XE3_FBC_DIRTY_RECT(fbc->id), FBC_DIRTY_RECT_START_LINE(fbc_state->dirty_rect.y1) | FBC_DIRTY_RECT_END_LINE(fbc_state->dirty_rect.y2)); @@ -1314,6 +1318,8 @@ intel_fbc_compute_dirty_rect(struct intel_atomic_state *state, if (!fbc || plane->pipe != crtc->pipe) continue; + fbc->state.dr_valid = false; + /* If plane not visible, dirty rect might have invalid coordinates */ if (!new_plane_state->uapi.visible) continue; @@ -1323,6 +1329,8 @@ intel_fbc_compute_dirty_rect(struct intel_atomic_state *state, continue; __intel_fbc_compute_dirty_rect(plane, old_plane_state, new_plane_state); + + fbc->state.dr_valid = true; } }