From patchwork Wed Jan 22 10:39:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Madieu X-Patchwork-Id: 13947133 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2DFD71F8F19; Wed, 22 Jan 2025 10:40:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737542411; cv=none; b=Ut0QVPAr6hgduZ5lsbRlrX7fZKK/XLo8P1p7CFQjL2pIU5RslUM5rISIOwPWhORHzFP+T/GvjHvXVKsGYRCN7ZZePQfKEi6RhOhZgwdM8JLiGSqYavNGIzFeowGYnCT0D+Zv79mLLkPEz5VI+zxeB+ToFAS/hEkbxgBgmbdrOUk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737542411; c=relaxed/simple; bh=IQJYEKqqPV66UaX7kV7U1KA4As0EUMJFYpGEexqOt7w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=erktfGSiljglnZ/PmyyxK/3Ujc5EAUG+bHaMsbGd9avtuObOwFRUtfsIQ47G42TKvBpgUPOflzGY8Wwu+Xx1Knr56Ci520f89dHN7WlRh49QGC0s4nmK3m0Q9uHU/6mBR/YFP/U0eKBaWPykdfhHgejsLowPfflxMOo7+zRCiB8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: EjOAwJoUTTO1KgKJtlFqug== X-CSE-MsgGUID: ENwONIfgTde2BE1XJKANEw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 22 Jan 2025 19:40:05 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.193]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id F03FA400755D; Wed, 22 Jan 2025 19:39:47 +0900 (JST) From: John Madieu To: geert+renesas@glider.be, robh@kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org Cc: biju.das.jz@bp.renesas.com, claudiu.beznea.uj@bp.renesas.com, conor+dt@kernel.org, john.madieu@gmail.com, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, magnus.damm@gmail.com, john.madieu.xa@bp.renesas.com Subject: [PATCH v3 1/9] soc: renesas: Add SYSC driver for Renesas RZ family Date: Wed, 22 Jan 2025 11:39:03 +0100 Message-ID: <20250122103911.517484-2-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122103911.517484-1-john.madieu.xa@bp.renesas.com> References: <20250122103911.517484-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The RZ/G3S system controller (SYSC) has various registers that control different functionalities. One of the exposed register offsers information about the SoC identification. Add a driver that identifies the SoC. Later the driver will be extended with other functionalities. Signed-off-by: Claudiu Beznea Signed-off-by: John Madieu --- drivers/soc/renesas/Kconfig | 3 + drivers/soc/renesas/Makefile | 1 + drivers/soc/renesas/rz-sysc.c | 119 ++++++++++++++++++++++++++++++++++ drivers/soc/renesas/rz-sysc.h | 37 +++++++++++ 4 files changed, 160 insertions(+) create mode 100644 drivers/soc/renesas/rz-sysc.c create mode 100644 drivers/soc/renesas/rz-sysc.h diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 6d2e135eed89..937ab43fae6a 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -383,4 +383,7 @@ config PWC_RZV2M config RST_RCAR bool "Reset Controller support for R-Car" if COMPILE_TEST +config SYSC_RZ + bool "System controller for RZ SoCs" if COMPILE_TEST + endif # SOC_RENESAS diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 734f8f8cefa4..3d5f847ed889 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -10,3 +10,4 @@ endif # Family obj-$(CONFIG_PWC_RZV2M) += pwc-rzv2m.o obj-$(CONFIG_RST_RCAR) += rcar-rst.o +obj-$(CONFIG_SYSC_RZ) += rz-sysc.o diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c new file mode 100644 index 000000000000..64fc56229440 --- /dev/null +++ b/drivers/soc/renesas/rz-sysc.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ System controller driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +#include "rz-sysc.h" + +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) + +/** + * struct rz_sysc - RZ SYSC private data structure + * @base: SYSC base address + * @dev: SYSC device pointer + */ +struct rz_sysc { + void __iomem *base; + struct device *dev; +}; + +static int rz_sysc_soc_init(struct rz_sysc *sysc, const struct of_device_id *match) +{ + const struct rz_sysc_init_data *sysc_data = match->data; + const struct rz_sysc_soc_id_init_data *soc_data = sysc_data->soc_id_init_data; + struct soc_device_attribute *soc_dev_attr; + const char *soc_id_start, *soc_id_end; + u32 val, revision, specific_id; + struct soc_device *soc_dev; + char soc_id[32] = {0}; + size_t size; + + soc_id_start = strchr(match->compatible, ',') + 1; + soc_id_end = strchr(match->compatible, '-'); + size = soc_id_end - soc_id_start + 1; + if (size > 32) + size = sizeof(soc_id); + strscpy(soc_id, soc_id_start, size); + + soc_dev_attr = devm_kzalloc(sysc->dev, sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return -ENOMEM; + + soc_dev_attr->family = devm_kstrdup(sysc->dev, soc_data->family, GFP_KERNEL); + soc_dev_attr->soc_id = devm_kstrdup(sysc->dev, soc_id, GFP_KERNEL); + if (!soc_dev_attr->soc_id) + return -ENOMEM; + + val = readl(sysc->base + soc_data->offset); + revision = field_get(soc_data->revision_mask, val); + specific_id = field_get(soc_data->specific_id_mask, val); + soc_dev_attr->revision = devm_kasprintf(sysc->dev, GFP_KERNEL, "%u", revision); + if (!soc_dev_attr->revision) + return -ENOMEM; + + if (soc_data->id && specific_id != soc_data->id) { + dev_warn(sysc->dev, "SoC mismatch (product = 0x%x)\n", specific_id); + return -ENODEV; + } + + dev_info(sysc->dev, "Detected Renesas %s %s Rev %s\n", soc_dev_attr->family, + soc_dev_attr->soc_id, soc_dev_attr->revision); + + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR(soc_dev)) + return PTR_ERR(soc_dev); + + return 0; +} + +static const struct of_device_id rz_sysc_match[] = { + { } +}; +MODULE_DEVICE_TABLE(of, rz_sysc_match); + +static int rz_sysc_probe(struct platform_device *pdev) +{ + const struct of_device_id *match; + struct device *dev = &pdev->dev; + struct rz_sysc *sysc; + + match = of_match_node(rz_sysc_match, dev->of_node); + if (!match) + return -ENODEV; + + sysc = devm_kzalloc(dev, sizeof(*sysc), GFP_KERNEL); + if (!sysc) + return -ENOMEM; + + sysc->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(sysc->base)) + return PTR_ERR(sysc->base); + + sysc->dev = dev; + return rz_sysc_soc_init(sysc, match); +} + +static struct platform_driver rz_sysc_driver = { + .driver = { + .name = "renesas-rz-sysc", + .of_match_table = rz_sysc_match + }, + .probe = rz_sysc_probe +}; + +static int __init rz_sysc_init(void) +{ + return platform_driver_register(&rz_sysc_driver); +} +subsys_initcall(rz_sysc_init); + +MODULE_DESCRIPTION("Renesas RZ System Controller Driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h new file mode 100644 index 000000000000..d74047686988 --- /dev/null +++ b/drivers/soc/renesas/rz-sysc.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Renesas RZ System Controller + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#ifndef __SOC_RENESAS_RZ_SYSC_H__ +#define __SOC_RENESAS_RZ_SYSC_H__ + +#include + +/** + * struct rz_syc_soc_id_init_data - RZ SYSC SoC identification initialization data + * @family: RZ SoC family + * @id: RZ SoC expected ID + * @offset: SYSC SoC ID register offset + * @revision_mask: SYSC SoC ID revision mask + * @specific_id_mask: SYSC SoC ID specific ID mask + */ +struct rz_sysc_soc_id_init_data { + const char * const family; + u32 id; + u32 offset; + u32 revision_mask; + u32 specific_id_mask; +}; + +/** + * struct rz_sysc_init_data - RZ SYSC initialization data + * @soc_id_init_data: RZ SYSC SoC ID initialization data + */ +struct rz_sysc_init_data { + const struct rz_sysc_soc_id_init_data *soc_id_init_data; +}; + +#endif /* __SOC_RENESAS_RZ_SYSC_H__ */ From patchwork Wed Jan 22 10:39:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Madieu X-Patchwork-Id: 13947132 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 52F0221128F; Wed, 22 Jan 2025 10:40:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737542409; cv=none; b=GmM2A2WtlEGpfdV75n+lx2IDOBoO4iV2jEdacvgOjFnoOfZ8Xdodh8tEwcvSkvQEuf0nsHqlcRnh180aaWWaMtL6swbviDLs+zg6g4mKZagO8uXJROUgfriOJNxSUSVsVO84mpjUtp4ebK7v5nj9Y6QVhymSyAqljmYe8+9SklA= ARC-Message-Signature: i=1; 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Wed, 22 Jan 2025 19:39:53 +0900 (JST) From: John Madieu To: geert+renesas@glider.be, robh@kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org Cc: biju.das.jz@bp.renesas.com, claudiu.beznea.uj@bp.renesas.com, conor+dt@kernel.org, john.madieu@gmail.com, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, magnus.damm@gmail.com, john.madieu.xa@bp.renesas.com Subject: [PATCH v3 2/9] dt-bindings: soc: renesas: Add RZ/G3E variant SYS binding Date: Wed, 22 Jan 2025 11:39:04 +0100 Message-ID: <20250122103911.517484-3-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122103911.517484-1-john.madieu.xa@bp.renesas.com> References: <20250122103911.517484-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add RZ/G3E (R9A09G047) variant to the existing RZ/V2H System Controller (SYS) binding as both IPs are compatible. They however have different SoC IDs, RZ/G3E has has VSP control Register compared to RZ/V2H SYS IP. Hence a new compatible string renesas,r9a09g047-sys introduced to handle these differences. Signed-off-by: John Madieu --- .../bindings/soc/renesas/renesas,r9a09g057-sys.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml index ebbf0c9109ce..e0f7503a9f35 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml @@ -22,7 +22,10 @@ description: | properties: compatible: - const: renesas,r9a09g057-sys + items: + - enum: + - renesas,r9a09g047-sys # RZ/G3E + - renesas,r9a09g057-sys # RZ/V2H reg: maxItems: 1 From patchwork Wed Jan 22 10:39:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Madieu X-Patchwork-Id: 13947135 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EF1F72116E8; Wed, 22 Jan 2025 10:40:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737542413; cv=none; b=ojr/Gpwv8UIIt7C/HzaW2/ByCeJEyKqYX0ZML5oolqEGU6In0ZHzIbySNPfqGAv8EXfng2IYfTsk3CkXpngonodzasV9uqXh3IkaVhbJaZMVzc/AZh1DRrIT1VLJr/TORT8ACNMfkIPF5/fJ2Bp/XCmWQ+mla9cBkjFSrwUOu9w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737542413; c=relaxed/simple; bh=OToF6orM4/HCnEz/PdwoXHcLm5sD/MLg2j6FsO1aFTw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bqP/4xvsJE3uveneqjxgZgdC0jSpJqmHNQggJ8i8aNFULegHdm3dHupmld3BcFv9d3GUkjI03ZG4oqrEzFSaWP3G6reW+PhBPuhn3gnZkwO8AsgAVIoeOvLvTxg8koBxv7sh2imlYOVN8vd3+ROltB6T0EOUEaUNngYK3acv/7g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: 8TdJl0tDR4CVoUYeNcdj+A== X-CSE-MsgGUID: R6jxYWAyQ22WDBzWBJE9fQ== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 22 Jan 2025 19:40:05 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.193]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 88E9840065B9; Wed, 22 Jan 2025 19:40:00 +0900 (JST) From: John Madieu To: geert+renesas@glider.be, robh@kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org Cc: biju.das.jz@bp.renesas.com, claudiu.beznea.uj@bp.renesas.com, conor+dt@kernel.org, john.madieu@gmail.com, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, magnus.damm@gmail.com, john.madieu.xa@bp.renesas.com Subject: [PATCH v3 3/9] soc: renesas: rz-sysc: Move RZ/G3S SoC detection to the SYSC driver Date: Wed, 22 Jan 2025 11:39:05 +0100 Message-ID: <20250122103911.517484-4-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122103911.517484-1-john.madieu.xa@bp.renesas.com> References: <20250122103911.517484-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Now that we have SoC detection in the RZ SYSC driver, move the RZ/G3S SoC detection to it. The SYSC provides SoC ID in its own registers. Signed-off-by: Claudiu Beznea Signed-off-by: John Madieu --- drivers/soc/renesas/Kconfig | 5 +++++ drivers/soc/renesas/Makefile | 1 + drivers/soc/renesas/r9a08g045-sysc.c | 28 ++++++++++++++++++++++++++++ drivers/soc/renesas/renesas-soc.c | 12 ------------ drivers/soc/renesas/rz-sysc.c | 3 +++ drivers/soc/renesas/rz-sysc.h | 2 ++ 6 files changed, 39 insertions(+), 12 deletions(-) create mode 100644 drivers/soc/renesas/r9a08g045-sysc.c diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 937ab43fae6a..a792a3e915fe 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -334,6 +334,7 @@ config ARCH_R9A07G054 config ARCH_R9A08G045 bool "ARM64 Platform support for RZ/G3S" select ARCH_RZG2L + select SYSC_R9A08G045 help This enables support for the Renesas RZ/G3S SoC variants. @@ -386,4 +387,8 @@ config RST_RCAR config SYSC_RZ bool "System controller for RZ SoCs" if COMPILE_TEST +config SYSC_R9A08G045 + bool "Renesas RZ/G3S System controller support" if COMPILE_TEST + select SYSC_RZ + endif # SOC_RENESAS diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 3d5f847ed889..8cd139b3dd0a 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_SOC_RENESAS) += renesas-soc.o ifdef CONFIG_SMP obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o endif +obj-$(CONFIG_SYSC_R9A08G045) += r9a08g045-sysc.o # Family obj-$(CONFIG_PWC_RZV2M) += pwc-rzv2m.o diff --git a/drivers/soc/renesas/r9a08g045-sysc.c b/drivers/soc/renesas/r9a08g045-sysc.c new file mode 100644 index 000000000000..babcf1cbcb49 --- /dev/null +++ b/drivers/soc/renesas/r9a08g045-sysc.c @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G3S System controller driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include + +#include "rz-sysc.h" + +#define SYS_LSI_DEVID 0xa04 +#define SYS_LSI_DEVID_REV GENMASK(31, 28) +#define SYS_LSI_DEVID_SPECIFIC GENMASK(27, 0) +#define SYS_MAX_REG 0xe20 + +static const struct rz_sysc_soc_id_init_data rzg3s_sysc_soc_id_init_data __initconst = { + .family = "RZ/G3S", + .id = 0x85e0447, + .offset = SYS_LSI_DEVID, + .revision_mask = SYS_LSI_DEVID_REV, + .specific_id_mask = SYS_LSI_DEVID_SPECIFIC +}; + +const struct rz_sysc_init_data rzg3s_sysc_init_data __initconst = { + .soc_id_init_data = &rzg3s_sysc_soc_id_init_data, +}; diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index 172d59e6fbcf..425d9037dcd0 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -71,10 +71,6 @@ static const struct renesas_family fam_rzg2ul __initconst __maybe_unused = { .name = "RZ/G2UL", }; -static const struct renesas_family fam_rzg3s __initconst __maybe_unused = { - .name = "RZ/G3S", -}; - static const struct renesas_family fam_rzv2h __initconst __maybe_unused = { .name = "RZ/V2H", }; @@ -176,11 +172,6 @@ static const struct renesas_soc soc_rz_g2ul __initconst __maybe_unused = { .id = 0x8450447, }; -static const struct renesas_soc soc_rz_g3s __initconst __maybe_unused = { - .family = &fam_rzg3s, - .id = 0x85e0447, -}; - static const struct renesas_soc soc_rz_v2h __initconst __maybe_unused = { .family = &fam_rzv2h, .id = 0x847a447, @@ -410,9 +401,6 @@ static const struct of_device_id renesas_socs[] __initconst __maybe_unused = { #ifdef CONFIG_ARCH_R9A07G054 { .compatible = "renesas,r9a07g054", .data = &soc_rz_v2l }, #endif -#ifdef CONFIG_ARCH_R9A08G045 - { .compatible = "renesas,r9a08g045", .data = &soc_rz_g3s }, -#endif #ifdef CONFIG_ARCH_R9A09G011 { .compatible = "renesas,r9a09g011", .data = &soc_rz_v2m }, #endif diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c index 64fc56229440..c0d4aca4c2b6 100644 --- a/drivers/soc/renesas/rz-sysc.c +++ b/drivers/soc/renesas/rz-sysc.c @@ -74,6 +74,9 @@ static int rz_sysc_soc_init(struct rz_sysc *sysc, const struct of_device_id *mat } static const struct of_device_id rz_sysc_match[] = { +#ifdef CONFIG_SYSC_R9A08G045 + { .compatible = "renesas,r9a08g045-sysc", .data = &rzg3s_sysc_init_data }, +#endif { } }; MODULE_DEVICE_TABLE(of, rz_sysc_match); diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h index d74047686988..1ee25c78ba8b 100644 --- a/drivers/soc/renesas/rz-sysc.h +++ b/drivers/soc/renesas/rz-sysc.h @@ -34,4 +34,6 @@ struct rz_sysc_init_data { const struct rz_sysc_soc_id_init_data *soc_id_init_data; }; +extern const struct rz_sysc_init_data rzg3s_sysc_init_data; + #endif /* __SOC_RENESAS_RZ_SYSC_H__ */ From patchwork Wed Jan 22 10:39:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Madieu X-Patchwork-Id: 13947136 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 30B4D211464; Wed, 22 Jan 2025 10:40:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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22 Jan 2025 19:40:27 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.193]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id BB4CF40071FA; Wed, 22 Jan 2025 19:40:05 +0900 (JST) From: John Madieu To: geert+renesas@glider.be, robh@kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org Cc: biju.das.jz@bp.renesas.com, claudiu.beznea.uj@bp.renesas.com, conor+dt@kernel.org, john.madieu@gmail.com, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, magnus.damm@gmail.com, john.madieu.xa@bp.renesas.com Subject: [PATCH v3 4/9] soc: renesas: rz-sysc: Add support for RZ/G3E family Date: Wed, 22 Jan 2025 11:39:06 +0100 Message-ID: <20250122103911.517484-5-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122103911.517484-1-john.madieu.xa@bp.renesas.com> References: <20250122103911.517484-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add SoC detection support for RZ/G3E SoC. Also add support for detecting the number of cores and ETHOS-U55 NPU and also detect PLL mismatch for SW settings other than 1.7GHz. Signed-off-by: John Madieu --- drivers/soc/renesas/Kconfig | 4 ++ drivers/soc/renesas/Makefile | 1 + drivers/soc/renesas/r9a09g047-sys.c | 71 +++++++++++++++++++++++++++++ drivers/soc/renesas/rz-sysc.c | 12 ++++- drivers/soc/renesas/rz-sysc.h | 6 +++ 5 files changed, 92 insertions(+), 2 deletions(-) create mode 100644 drivers/soc/renesas/r9a09g047-sys.c diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index a792a3e915fe..173d4f60d17a 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -348,6 +348,7 @@ config ARCH_R9A09G011 config ARCH_R9A09G047 bool "ARM64 Platform support for RZ/G3E" + select SYS_R9A09G047 help This enables support for the Renesas RZ/G3E SoC variants. @@ -391,4 +392,7 @@ config SYSC_R9A08G045 bool "Renesas RZ/G3S System controller support" if COMPILE_TEST select SYSC_RZ +config SYS_R9A09G047 + bool "Renesas RZ/G3E System controller support" if COMPILE_TEST + select SYSC_RZ endif # SOC_RENESAS diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 8cd139b3dd0a..17b86d3ae478 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -7,6 +7,7 @@ ifdef CONFIG_SMP obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o endif obj-$(CONFIG_SYSC_R9A08G045) += r9a08g045-sysc.o +obj-$(CONFIG_SYS_R9A09G047) += r9a09g047-sys.o # Family obj-$(CONFIG_PWC_RZV2M) += pwc-rzv2m.o diff --git a/drivers/soc/renesas/r9a09g047-sys.c b/drivers/soc/renesas/r9a09g047-sys.c new file mode 100644 index 000000000000..db5406eb9e05 --- /dev/null +++ b/drivers/soc/renesas/r9a09g047-sys.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G3E System controller (SYS) driver + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +#include "rz-sysc.h" + +/* Register Offsets */ +#define SYS_LSI_MODE 0x300 +/* + * BOOTPLLCA[1:0] + * [0,0] => 1.1GHZ + * [0,1] => 1.5GHZ + * [1,0] => 1.6GHZ + * [1,1] => 1.7GHZ + */ +#define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11) +#define SYS_LSI_MODE_CA55_1_7GHZ 0x3 +#define SYS_LSI_DEVID 0x304 +#define SYS_LSI_DEVID_REV GENMASK(31, 28) +#define SYS_LSI_DEVID_SPECIFIC GENMASK(27, 0) +#define SYS_LSI_PRR 0x308 +#define SYS_LSI_PRR_CA55_DIS BIT(8) +#define SYS_LSI_PRR_NPU_DIS BIT(1) + + +static void rzg3e_sys_print_id(struct device *dev, + void __iomem *sysc_base, + struct soc_device_attribute *soc_dev_attr) +{ + bool is_quad_core, npu_enabled; + u32 prr_val, mode_val; + + prr_val = readl(sysc_base + SYS_LSI_PRR); + mode_val = readl(sysc_base + SYS_LSI_MODE); + + /* Check CPU and NPU configuration */ + is_quad_core = !(prr_val & SYS_LSI_PRR_CA55_DIS); + npu_enabled = !(prr_val & SYS_LSI_PRR_NPU_DIS); + + dev_info(dev, "Detected Renesas %s Core %s %s Rev %s%s\n", + is_quad_core ? "Quad" : "Dual", + soc_dev_attr->family, + soc_dev_attr->soc_id, + soc_dev_attr->revision, + npu_enabled ? " with Ethos-U55" : ""); + + /* Check CA55 PLL configuration */ + if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ) + dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n"); +} + +static const struct rz_sysc_soc_id_init_data rzg3e_sys_soc_id_init_data __initconst = { + .family = "RZ/G3E", + .id = 0x8679447, + .offset = SYS_LSI_DEVID, + .revision_mask = SYS_LSI_DEVID_REV, + .specific_id_mask = SYS_LSI_DEVID_SPECIFIC, + .print_id = rzg3e_sys_print_id, +}; + +const struct rz_sysc_init_data rzg3e_sys_init_data = { + .soc_id_init_data = &rzg3e_sys_soc_id_init_data, +}; diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c index c0d4aca4c2b6..cedc2ca51979 100644 --- a/drivers/soc/renesas/rz-sysc.c +++ b/drivers/soc/renesas/rz-sysc.c @@ -63,8 +63,13 @@ static int rz_sysc_soc_init(struct rz_sysc *sysc, const struct of_device_id *mat return -ENODEV; } - dev_info(sysc->dev, "Detected Renesas %s %s Rev %s\n", soc_dev_attr->family, - soc_dev_attr->soc_id, soc_dev_attr->revision); + /* Try to call SoC-specific device identification */ + if (soc_data->print_id) { + soc_data->print_id(sysc->dev, sysc->base, soc_dev_attr); + } else { + dev_info(sysc->dev, "Detected Renesas %s %s Rev %s\n", + soc_dev_attr->family, soc_dev_attr->soc_id, soc_dev_attr->revision); + } soc_dev = soc_device_register(soc_dev_attr); if (IS_ERR(soc_dev)) @@ -76,6 +81,9 @@ static int rz_sysc_soc_init(struct rz_sysc *sysc, const struct of_device_id *mat static const struct of_device_id rz_sysc_match[] = { #ifdef CONFIG_SYSC_R9A08G045 { .compatible = "renesas,r9a08g045-sysc", .data = &rzg3s_sysc_init_data }, +#endif +#ifdef CONFIG_SYS_R9A09G047 + { .compatible = "renesas,r9a09g047-sys", .data = &rzg3e_sys_init_data }, #endif { } }; diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h index 1ee25c78ba8b..3f628eb15677 100644 --- a/drivers/soc/renesas/rz-sysc.h +++ b/drivers/soc/renesas/rz-sysc.h @@ -8,6 +8,8 @@ #ifndef __SOC_RENESAS_RZ_SYSC_H__ #define __SOC_RENESAS_RZ_SYSC_H__ +#include +#include #include /** @@ -17,6 +19,7 @@ * @offset: SYSC SoC ID register offset * @revision_mask: SYSC SoC ID revision mask * @specific_id_mask: SYSC SoC ID specific ID mask + * @print_id: SoC-specific extended device identification */ struct rz_sysc_soc_id_init_data { const char * const family; @@ -24,6 +27,8 @@ struct rz_sysc_soc_id_init_data { u32 offset; u32 revision_mask; u32 specific_id_mask; + void (*print_id)(struct device *dev, void __iomem *sysc_base, + struct soc_device_attribute *soc_dev_attr); }; /** @@ -34,6 +39,7 @@ struct rz_sysc_init_data { const struct rz_sysc_soc_id_init_data *soc_id_init_data; }; +extern const struct rz_sysc_init_data rzg3e_sys_init_data; extern const struct rz_sysc_init_data rzg3s_sysc_init_data; #endif /* __SOC_RENESAS_RZ_SYSC_H__ */ From patchwork Wed Jan 22 10:39:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Madieu X-Patchwork-Id: 13947139 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 36D77211499; Wed, 22 Jan 2025 10:40:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: X9xj5Q7qTmG+W8XZD22hWg== X-CSE-MsgGUID: 0693p53ASXOG2tI6PpEPfg== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 22 Jan 2025 19:40:39 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.193]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 2AFA94001942; Wed, 22 Jan 2025 19:40:10 +0900 (JST) From: John Madieu To: geert+renesas@glider.be, robh@kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org Cc: biju.das.jz@bp.renesas.com, claudiu.beznea.uj@bp.renesas.com, conor+dt@kernel.org, john.madieu@gmail.com, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, magnus.damm@gmail.com, john.madieu.xa@bp.renesas.com Subject: [PATCH v3 5/9] soc: renesas: rz-sysc: Move RZ/V2H SoC detection to the SYS driver Date: Wed, 22 Jan 2025 11:39:07 +0100 Message-ID: <20250122103911.517484-6-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122103911.517484-1-john.madieu.xa@bp.renesas.com> References: <20250122103911.517484-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 As per the other SoC variant of the same family, the system controller provides SoC ID in its own registers. Signed-off-by: John Madieu --- drivers/soc/renesas/Kconfig | 5 +++++ drivers/soc/renesas/Makefile | 1 + drivers/soc/renesas/r9a09g047-sys.c | 22 ++++------------------ drivers/soc/renesas/r9a09g057-sys.c | 26 ++++++++++++++++++++++++++ drivers/soc/renesas/renesas-soc.c | 21 +-------------------- drivers/soc/renesas/rz-sysc.c | 3 +++ drivers/soc/renesas/rz-sysc.h | 1 + drivers/soc/renesas/rzg3e-sys.h | 28 ++++++++++++++++++++++++++++ 8 files changed, 69 insertions(+), 38 deletions(-) create mode 100644 drivers/soc/renesas/r9a09g057-sys.c create mode 100644 drivers/soc/renesas/rzg3e-sys.h diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 173d4f60d17a..9f7650e15603 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -355,6 +355,7 @@ config ARCH_R9A09G047 config ARCH_R9A09G057 bool "ARM64 Platform support for RZ/V2H(P)" select RENESAS_RZV2H_ICU + select SYS_R9A09G057 help This enables support for the Renesas RZ/V2H(P) SoC variants. @@ -395,4 +396,8 @@ config SYSC_R9A08G045 config SYS_R9A09G047 bool "Renesas RZ/G3E System controller support" if COMPILE_TEST select SYSC_RZ + +config SYS_R9A09G057 + bool "Renesas RZ/V2H System controller support" if COMPILE_TEST + select SYSC_RZ endif # SOC_RENESAS diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 17b86d3ae478..81d4c5726e4c 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o endif obj-$(CONFIG_SYSC_R9A08G045) += r9a08g045-sysc.o obj-$(CONFIG_SYS_R9A09G047) += r9a09g047-sys.o +obj-$(CONFIG_SYS_R9A09G057) += r9a09g057-sys.o # Family obj-$(CONFIG_PWC_RZV2M) += pwc-rzv2m.o diff --git a/drivers/soc/renesas/r9a09g047-sys.c b/drivers/soc/renesas/r9a09g047-sys.c index db5406eb9e05..860374cbd2ee 100644 --- a/drivers/soc/renesas/r9a09g047-sys.c +++ b/drivers/soc/renesas/r9a09g047-sys.c @@ -11,25 +11,11 @@ #include #include "rz-sysc.h" +#include "rzg3e-sys.h" -/* Register Offsets */ -#define SYS_LSI_MODE 0x300 -/* - * BOOTPLLCA[1:0] - * [0,0] => 1.1GHZ - * [0,1] => 1.5GHZ - * [1,0] => 1.6GHZ - * [1,1] => 1.7GHZ - */ -#define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11) -#define SYS_LSI_MODE_CA55_1_7GHZ 0x3 -#define SYS_LSI_DEVID 0x304 -#define SYS_LSI_DEVID_REV GENMASK(31, 28) -#define SYS_LSI_DEVID_SPECIFIC GENMASK(27, 0) -#define SYS_LSI_PRR 0x308 -#define SYS_LSI_PRR_CA55_DIS BIT(8) -#define SYS_LSI_PRR_NPU_DIS BIT(1) - +/* RZ/G3E-specific feature bits */ +#define SYS_LSI_PRR_CA55_DIS BIT(8) +#define SYS_LSI_PRR_NPU_DIS BIT(1) static void rzg3e_sys_print_id(struct device *dev, void __iomem *sysc_base, diff --git a/drivers/soc/renesas/r9a09g057-sys.c b/drivers/soc/renesas/r9a09g057-sys.c new file mode 100644 index 000000000000..dc7885b340c4 --- /dev/null +++ b/drivers/soc/renesas/r9a09g057-sys.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/V2H System controller (SYS) driver + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +#include "rz-sysc.h" +#include "rzg3e-sys.h" + +static const struct rz_sysc_soc_id_init_data rzv2h_sys_soc_id_init_data __initconst = { + .family = "RZ/V2H", + .id = 0x847a447, + .offset = SYS_LSI_DEVID, + .revision_mask = SYS_LSI_DEVID_REV, + .specific_id_mask = SYS_LSI_DEVID_SPECIFIC, +}; + +const struct rz_sysc_init_data rzv2h_sys_init_data = { + .soc_id_init_data = &rzv2h_sys_soc_id_init_data, +}; diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index 425d9037dcd0..df2b38417b80 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -71,10 +71,6 @@ static const struct renesas_family fam_rzg2ul __initconst __maybe_unused = { .name = "RZ/G2UL", }; -static const struct renesas_family fam_rzv2h __initconst __maybe_unused = { - .name = "RZ/V2H", -}; - static const struct renesas_family fam_rzv2l __initconst __maybe_unused = { .name = "RZ/V2L", }; @@ -172,11 +168,6 @@ static const struct renesas_soc soc_rz_g2ul __initconst __maybe_unused = { .id = 0x8450447, }; -static const struct renesas_soc soc_rz_v2h __initconst __maybe_unused = { - .family = &fam_rzv2h, - .id = 0x847a447, -}; - static const struct renesas_soc soc_rz_v2l __initconst __maybe_unused = { .family = &fam_rzv2l, .id = 0x8447447, @@ -280,7 +271,6 @@ static const struct renesas_soc soc_shmobile_ag5 __initconst __maybe_unused = { .id = 0x37, }; - static const struct of_device_id renesas_socs[] __initconst __maybe_unused = { #ifdef CONFIG_ARCH_R7S72100 { .compatible = "renesas,r7s72100", .data = &soc_rz_a1h }, @@ -404,9 +394,6 @@ static const struct of_device_id renesas_socs[] __initconst __maybe_unused = { #ifdef CONFIG_ARCH_R9A09G011 { .compatible = "renesas,r9a09g011", .data = &soc_rz_v2m }, #endif -#ifdef CONFIG_ARCH_R9A09G057 - { .compatible = "renesas,r9a09g057", .data = &soc_rz_v2h }, -#endif #ifdef CONFIG_ARCH_SH73A0 { .compatible = "renesas,sh73a0", .data = &soc_shmobile_ag5 }, #endif @@ -432,11 +419,6 @@ static const struct renesas_id id_rzg2l __initconst = { .mask = 0xfffffff, }; -static const struct renesas_id id_rzv2h __initconst = { - .offset = 0x304, - .mask = 0xfffffff, -}; - static const struct renesas_id id_rzv2m __initconst = { .offset = 0x104, .mask = 0xff, @@ -454,7 +436,6 @@ static const struct of_device_id renesas_ids[] __initconst = { { .compatible = "renesas,r9a07g054-sysc", .data = &id_rzg2l }, { .compatible = "renesas,r9a08g045-sysc", .data = &id_rzg2l }, { .compatible = "renesas,r9a09g011-sys", .data = &id_rzv2m }, - { .compatible = "renesas,r9a09g057-sys", .data = &id_rzv2h }, { .compatible = "renesas,prr", .data = &id_prr }, { /* sentinel */ } }; @@ -519,7 +500,7 @@ static int __init renesas_soc_init(void) eslo = product & 0xf; soc_dev_attr->revision = kasprintf(GFP_KERNEL, "ES%u.%u", eshi, eslo); - } else if (id == &id_rzg2l || id == &id_rzv2h) { + } else if (id == &id_rzg2l) { eshi = ((product >> 28) & 0x0f); soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%u", eshi); diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c index cedc2ca51979..874ab6cf36cb 100644 --- a/drivers/soc/renesas/rz-sysc.c +++ b/drivers/soc/renesas/rz-sysc.c @@ -84,6 +84,9 @@ static const struct of_device_id rz_sysc_match[] = { #endif #ifdef CONFIG_SYS_R9A09G047 { .compatible = "renesas,r9a09g047-sys", .data = &rzg3e_sys_init_data }, +#endif +#ifdef CONFIG_SYS_R9A09G057 + { .compatible = "renesas,r9a09g057-sys", .data = &rzv2h_sys_init_data }, #endif { } }; diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h index 3f628eb15677..c87fd6ee23f2 100644 --- a/drivers/soc/renesas/rz-sysc.h +++ b/drivers/soc/renesas/rz-sysc.h @@ -41,5 +41,6 @@ struct rz_sysc_init_data { extern const struct rz_sysc_init_data rzg3e_sys_init_data; extern const struct rz_sysc_init_data rzg3s_sysc_init_data; +extern const struct rz_sysc_init_data rzv2h_sys_init_data; #endif /* __SOC_RENESAS_RZ_SYSC_H__ */ diff --git a/drivers/soc/renesas/rzg3e-sys.h b/drivers/soc/renesas/rzg3e-sys.h new file mode 100644 index 000000000000..2e492a85baa6 --- /dev/null +++ b/drivers/soc/renesas/rzg3e-sys.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Renesas RZ/G3E (SYS) System Controller + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#ifndef __RZG3E_SYS_H__ +#define __RZG3E_SYS_H__ + +/* SYS Common Register Offsets */ + +#define SYS_LSI_MODE 0x300 +/* + * BOOTPLLCA[1:0] + * [0,0] => 1.1GHZ + * [0,1] => 1.5GHZ + * [1,0] => 1.6GHZ + * [1,1] => 1.7GHZ + */ +#define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11) +#define SYS_LSI_MODE_CA55_1_7GHZ 0x3 +#define SYS_LSI_DEVID 0x304 +#define SYS_LSI_DEVID_REV GENMASK(31, 28) +#define SYS_LSI_DEVID_SPECIFIC GENMASK(27, 0) +#define SYS_LSI_PRR 0x308 + +#endif /* __RZG3E_SYSC_H__ */ From patchwork Wed Jan 22 10:39:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Madieu X-Patchwork-Id: 13947138 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3CF5221171F; Wed, 22 Jan 2025 10:40:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737542442; cv=none; b=vCEHTb9xiI/HkExhc9KhYCF32Mdw/Cwo6juymDAuVHR8joQHtw0ckgI3hT/RiNE9bSTdQdQJBdlST52CUFw/F4swmwCJ8yALbXJxOD8zORlUgixFd4yPjmmSFKHZA850AOMvC+4fTe0/8YMHJCyUCtCCigQsZxkKEL5RkaGbxQo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737542442; c=relaxed/simple; bh=lMymBWpxiLkE0u2AskUo/QiExu/+RCZqw5191ouJq7Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EugcG7KjHSGKGbG97AKNGDhk5lgTPNy52eVLa2f1Lv54jzgIdBihG1psspouZm5ovdwgigb5jocnSnHXauoJtDgdwVpAMqFcHbIJX+Kb7ArQh4AWB0xdZORfpNrkmcdhAfO90ZNVu6tElzT0jC1Bp0ANKjiDigb5qHpP07Sv2fw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: JDVc6oeUT8Co5AK6ACTWPA== X-CSE-MsgGUID: ezPnPT1MRyuvxv3MoexUug== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 22 Jan 2025 19:40:39 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.193]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id AC0064007F45; Wed, 22 Jan 2025 19:40:16 +0900 (JST) From: John Madieu To: geert+renesas@glider.be, robh@kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org Cc: biju.das.jz@bp.renesas.com, claudiu.beznea.uj@bp.renesas.com, conor+dt@kernel.org, john.madieu@gmail.com, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, magnus.damm@gmail.com, john.madieu.xa@bp.renesas.com Subject: [PATCH v3 6/9] soc: renesas: rzv2h: Add a callback to print SoC-specific extra features Date: Wed, 22 Jan 2025 11:39:08 +0100 Message-ID: <20250122103911.517484-7-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122103911.517484-1-john.madieu.xa@bp.renesas.com> References: <20250122103911.517484-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Some RZ/V2H SoC variants feature a Mali-G31 (GPU) and/or a Mali-C55 (ISP) IP(s). Detect and inform about their presence during SoC identification. Also detect PLL frequency and warn in case of mismatch. Signed-off-by: John Madieu --- drivers/soc/renesas/r9a09g057-sys.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/soc/renesas/r9a09g057-sys.c b/drivers/soc/renesas/r9a09g057-sys.c index dc7885b340c4..18a79e68bade 100644 --- a/drivers/soc/renesas/r9a09g057-sys.c +++ b/drivers/soc/renesas/r9a09g057-sys.c @@ -13,12 +13,41 @@ #include "rz-sysc.h" #include "rzg3e-sys.h" +/* RZ/V2H-specific feature bits */ +#define SYS_LSI_PRR_GPU_DIS BIT(0) +#define SYS_LSI_PRR_ISP_DIS BIT(4) + +static void rzv2h_sys_print_id(struct device *dev, + void __iomem *sysc_base, + struct soc_device_attribute *soc_dev_attr) +{ + bool gpu_enabled, isp_enabled; + u32 prr_val, mode_val; + + prr_val = readl(sysc_base + SYS_LSI_PRR); + mode_val = readl(sysc_base + SYS_LSI_MODE); + + /* Check GPU and ISP configuration */ + gpu_enabled = !(prr_val & SYS_LSI_PRR_GPU_DIS); + isp_enabled = !(prr_val & SYS_LSI_PRR_ISP_DIS); + + dev_info(dev, "Detected Renesas %s %s Rev %s%s%s\n", + soc_dev_attr->family, soc_dev_attr->soc_id, soc_dev_attr->revision, + gpu_enabled ? " with GE3D (Mali-G31)" : "", + isp_enabled ? " with ISP (Mali-C55)" : ""); + + /* Check CA55 PLL configuration */ + if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ) + dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n"); +} + static const struct rz_sysc_soc_id_init_data rzv2h_sys_soc_id_init_data __initconst = { .family = "RZ/V2H", .id = 0x847a447, .offset = SYS_LSI_DEVID, .revision_mask = SYS_LSI_DEVID_REV, .specific_id_mask = SYS_LSI_DEVID_SPECIFIC, + .print_id = rzv2h_sys_print_id, }; const struct rz_sysc_init_data rzv2h_sys_init_data = { From patchwork Wed Jan 22 10:39:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Madieu X-Patchwork-Id: 13947137 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 02425211499; Wed, 22 Jan 2025 10:40:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737542433; cv=none; b=syVL5cA4/yynyCqJCzJX+/UnG/dMmvgn4KjiWgF/SHQl90ZqiQE/mvaYlTHtEDgYwLylhwHRHPqwyuyXn1iMSPq7ZfVAXYUlUfzHRE47mngXUwQryqZC+LRDUtqVFgODFuXppmp36IRciGVWhcoLhKglVJmkBbaCocgb5QCzHuY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737542433; c=relaxed/simple; bh=z6IOhJDVuM2aTEnSolKR4WjaZxBsbyVQqStYbnEgOks=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=COQlCKNba5xNIP+AqEc6iGZdqQZyNcKxNcWG9Un4n/J/Us8n6os5sBpB+IYSmaiuHIzuEOL0WQdADBqZDC2420zxRt2A3JuMrcKtDxJtmtGEgo5lJlAKDHbTpmr14o/fEiCbrk0a5EVXQzfNyb/85lyAxLVa4FcJs1bZTmrMgLQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: peCLAoABSsmYl01ouvlUqw== X-CSE-MsgGUID: bAOyWgzETMWICReeD6I93A== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 22 Jan 2025 19:40:28 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.193]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 6417A400562D; Wed, 22 Jan 2025 19:40:22 +0900 (JST) From: John Madieu To: geert+renesas@glider.be, robh@kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org Cc: biju.das.jz@bp.renesas.com, claudiu.beznea.uj@bp.renesas.com, conor+dt@kernel.org, john.madieu@gmail.com, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, magnus.damm@gmail.com, john.madieu.xa@bp.renesas.com Subject: [PATCH v3 7/9] arm64: dts: renesas: r9a08g045: Enable the system controller Date: Wed, 22 Jan 2025 11:39:09 +0100 Message-ID: <20250122103911.517484-8-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122103911.517484-1-john.madieu.xa@bp.renesas.com> References: <20250122103911.517484-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Enable the system controller. It is needed for SoC identification. Signed-off-by: Claudiu Beznea Signed-off-by: John Madieu --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index a9b98db9ef95..d1e228b439df 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -443,7 +443,6 @@ sysc: system-controller@11020000 { ; interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", "ca55_deny"; - status = "disabled"; }; pinctrl: pinctrl@11030000 { From patchwork Wed Jan 22 10:39:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Madieu X-Patchwork-Id: 13947141 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5715F211A08; Wed, 22 Jan 2025 10:40:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: jMCgajAFQyay1P80nF7Wfg== X-CSE-MsgGUID: IgGYaMSuQWmhezKSWuIMRw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 22 Jan 2025 19:40:47 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.193]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id E3E3740071FA; Wed, 22 Jan 2025 19:40:29 +0900 (JST) From: John Madieu To: geert+renesas@glider.be, robh@kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org Cc: biju.das.jz@bp.renesas.com, claudiu.beznea.uj@bp.renesas.com, conor+dt@kernel.org, john.madieu@gmail.com, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, magnus.damm@gmail.com, john.madieu.xa@bp.renesas.com Subject: [PATCH v3 8/9] arm64: dts: renesas: r9a09g047: Add sys node Date: Wed, 22 Jan 2025 11:39:10 +0100 Message-ID: <20250122103911.517484-9-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122103911.517484-1-john.madieu.xa@bp.renesas.com> References: <20250122103911.517484-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add system controller node to RZ/G3E (R9A09G047) SoC DTSI, as it is also required for SoC identification Signed-off-by: John Madieu --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 444fadaf7254..0840450dda47 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -162,6 +162,13 @@ cpg: clock-controller@10420000 { #power-domain-cells = <0>; }; + sys: system-controller@10430000 { + compatible = "renesas,r9a09g047-sys"; + reg = <0 0x10430000 0 0x10000>; + clocks = <&cpg CPG_CORE R9A09G047_SYS_0_PCLK>; + resets = <&cpg 0x30>; + }; + ostm0: timer@11800000 { compatible = "renesas,r9a09g047-ostm", "renesas,ostm"; reg = <0x0 0x11800000 0x0 0x1000>; From patchwork Wed Jan 22 10:39:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Madieu X-Patchwork-Id: 13947140 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D289B212B0A; Wed, 22 Jan 2025 10:40:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737542443; cv=none; b=mTWj46OecSqdr6IbhbQQuRunzMixEn5mzzSvgWqWwoR75KfKAY3G2EZexUPwgLKe4SkGJpH9CYUUF4mDwdGdLrjI/+7xK6S/3WTkWgHyt1pKJi9USqiLNxqv3+18W2NaWR3JuwMRndjH+oAsrsU20yUbNVuS0PpVPbav6rc/XWM= ARC-Message-Signature: i=1; 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Wed, 22 Jan 2025 19:40:35 +0900 (JST) From: John Madieu To: geert+renesas@glider.be, robh@kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org Cc: biju.das.jz@bp.renesas.com, claudiu.beznea.uj@bp.renesas.com, conor+dt@kernel.org, john.madieu@gmail.com, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, magnus.damm@gmail.com, john.madieu.xa@bp.renesas.com Subject: [PATCH v3 9/9] arm64: dts: renesas: r9a09g057: Enable SYS node Date: Wed, 22 Jan 2025 11:39:11 +0100 Message-ID: <20250122103911.517484-10-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122103911.517484-1-john.madieu.xa@bp.renesas.com> References: <20250122103911.517484-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 SoC identification needs the system controller. Enable it. Signed-off-by: John Madieu --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 1c550b22b164..f7a2f8ca864f 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -249,7 +249,6 @@ sys: system-controller@10430000 { reg = <0 0x10430000 0 0x10000>; clocks = <&cpg CPG_CORE R9A09G057_SYS_0_PCLK>; resets = <&cpg 0x30>; - status = "disabled"; }; ostm0: timer@11800000 {