From patchwork Wed Jan 22 11:51:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947179 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56D17C02182 for ; Wed, 22 Jan 2025 11:51:30 +0000 (UTC) Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) by mx.groups.io with SMTP id smtpd.web10.41869.1737546685381102887 for ; Wed, 22 Jan 2025 03:51:25 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=qLMAyZyr; spf=pass (domain: tuxon.dev, ip: 209.85.128.46, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-4361f664af5so77993795e9.1 for ; Wed, 22 Jan 2025 03:51:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737546684; x=1738151484; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SIusFfIulEkImaMM6nQeNJ7aWzOksXms0pWRi/lmrVw=; b=qLMAyZyrF2Ky+fAsFCYBxU5ijzSDUreumKQ9jicOIqW93MBcrJei+IdF4xC8+t/ZDU VIlCJoqcNBZBVdF2QcWW5X3rytrIQE3fMCch6IzJtBmQq9rApU4UXovZCxx3YOwcBRLL vaD/tBcWQd1MM7PFQII58F3gymRpPOvI0BLQHHAFw0uBIrgq8khswxP5Pi/lsCCvIeXl Z0nFMU8hzRJ1lbqutfGR4ptK+qDP8fe0IfOv4ZZ/2VmMfiUMbOQ2zfTdRNR0kogFrciU s7vtFvvDHegMF2qfTP1ryC9h/rvEzP18mxCDsQ6mAgUxox4+C86agFx0jGzEG2voQn/d iilg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737546684; x=1738151484; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SIusFfIulEkImaMM6nQeNJ7aWzOksXms0pWRi/lmrVw=; b=bDD9M779dBkif/FSopajpBZjlTDPI96XzNtCE6mdrKiKU7fIgDDplSDJrTNZx2at+b VVFbm91cq27AiekoSVBJPHYFX1MtE8Rq5CQBB71/mIC38b20AuiuAGZYpepArOQ9bS5Y ULdSW07kHACuNeJtFP8FLZSVqSYcK+K/uqmVTtj8tqf5Buj346kIwqbUlKB4+pZ+szra RUVOZopHRtDOWpSIZYNR/866Rc7v/2quo+3DdAD23S6cH2UIu/T5vFMQ61FDi/tLUcOU CJEvzWmr56r5WXMyhhqYjVhwZ6mWFtXOihIo9OrKTL/i1/efUrT50S9DYrxMoVAE9YOu S8oQ== X-Forwarded-Encrypted: i=1; AJvYcCWZOCoHShB+E+G+a65R6eUw2P29HgZYRr3sHPnpMtLinjgK6jeHH6Zr+ygAJsc6rVkST9XpWyhg@lists.cip-project.org X-Gm-Message-State: AOJu0YzVcRinFx6BjdbV9CztDcB+iX1wx/TCjMYIAiv0JX/10TCPcmr8 AAJqSlzoJeEgO+y6BrtDADsOwUGSgsamDCkfnIwTQwtmZYH4j8wwC5O/wqluAj41vBmwv/bgeax 4 X-Gm-Gg: ASbGnctlL8WiR7StShmRfh0v92B0AUpFeo6X+QVVn9XAZKNSUzCvWxqiIUo+sfuxj34 VgSSPCCzue81DGc5NTxrxDUz/zOqmbQzv2sYEi97RGHXmSCvnu2imB7eNv5ElMieOrTuiwBhjqq MjfTfqYvhIjOEVkb5rYAdE9GBTIYMiWW7xTiuNcljMPjlF6yfbWGPDE4mv/pKVEwGQZ7EQa4zb6 /0vJm/WvJ31NGDI+VXWon4jHU2+4AkNFJC84QSyf2cJ0uijpvRYJpp0admwtpMVGba2+24A8OLv tdXRgBGeX4g4OClJPKoYf28OmiTGeLZ4LA== X-Google-Smtp-Source: AGHT+IGxk32RwQLurWY1PRpzIPJEOvV3j6Y788LoL4Xdg3P/W8pLkZemxP06NOdq/+At+2OpOtJt/g== X-Received: by 2002:a05:600c:35c5:b0:436:ed38:5c85 with SMTP id 5b1f17b1804b1-438913df210mr214808675e9.14.1737546683836; Wed, 22 Jan 2025 03:51:23 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b31aea72sm21474765e9.21.2025.01.22.03.51.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:51:23 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip 01/14] clk: Add Sunplus SP7021 clock driver Date: Wed, 22 Jan 2025 13:51:06 +0200 Message-ID: <20250122115120.2885015-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:51:30 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17564 From: Qin Jian commit d54c1fd4a51e8fbc7f9da86b0cd338a4f7cd2bb2 upstream. Add clock driver for Sunplus SP7021 SoC. Signed-off-by: Qin Jian Link: https://lore.kernel.org/r/20221219015130.42621-1-qinjian@cqplus1.com Signed-off-by: Stephen Boyd [claudiu.beznea: kept only the code from include/linux/clk-provider.h] Signed-off-by: Claudiu Beznea --- include/linux/clk-provider.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index d2c799595d5e..53dd7c9dcc94 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -606,6 +606,25 @@ struct clk *clk_register_gate(struct device *dev, const char *name, __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ NULL, (flags), (reg), (bit_idx), \ (clk_gate_flags), (lock)) +/** + * devm_clk_hw_register_gate_parent_data - register a gate clock with the + * clock framework + * @dev: device that is registering this clock + * @name: name of this clock + * @parent_data: parent clk data + * @flags: framework-specific flags for this clock + * @reg: register address to control gating of this clock + * @bit_idx: which bit in the register controls gating of this clock + * @clk_gate_flags: gate-specific flags for this clock + * @lock: shared register lock for this clock + */ +#define devm_clk_hw_register_gate_parent_data(dev, name, parent_data, flags, \ + reg, bit_idx, clk_gate_flags, \ + lock) \ + __devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL, \ + (parent_data), (flags), (reg), (bit_idx), \ + (clk_gate_flags), (lock)) + void clk_unregister_gate(struct clk *clk); void clk_hw_unregister_gate(struct clk_hw *hw); int clk_gate_is_enabled(struct clk_hw *hw); From patchwork Wed Jan 22 11:51:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947180 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E313C0218E for ; Wed, 22 Jan 2025 11:51:30 +0000 (UTC) Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.groups.io with SMTP id smtpd.web11.41683.1737546686712926045 for ; Wed, 22 Jan 2025 03:51:27 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=P5LeqyxE; spf=pass (domain: tuxon.dev, ip: 209.85.128.49, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-438a39e659cso27481695e9.2 for ; Wed, 22 Jan 2025 03:51:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737546685; x=1738151485; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8AGIwR5dix3cBevysVkNwWGSAXw1Uxe87cB4A40YKpQ=; b=P5LeqyxE5qLJ3nQsnDhwzMyKsPVadmgdU2BwQd58buFF2nPXaVCSpNTO/F+R8Lzxmv YgNagi41Ga98cw2wUNM+cTUIds7XWzzoq0v1PJWUadIfQK4xWTEwMU7zQ0zyJY6i39D+ qXC+lmxjyS5nIGgObBpvcNg8i6SFPln8Jk5YzmC8oagcyOApL3EO3HXS/3lf+Oh/Mm7I V5HfHSeqjKwekO4obreUJI5UTAIcQqAKyKCfv4DaVbiAoG2iF2btNhOCLlkcuMbBYqTw gmXUtMfHR6oktqztFh/baIyzvwIqm8I8ZS7dCySY+pv4aT92eiMPZOwQphqi4hQO+ETd CIXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737546685; x=1738151485; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8AGIwR5dix3cBevysVkNwWGSAXw1Uxe87cB4A40YKpQ=; b=qKG1J1ILsL9+JvobBbmn2Kars5RsClQ7440UO7nlCYf0oZVL9f8xUHYdaSDPbke95Y ONWM7Ji1u0ckuCrdzHLYWlHPEiSGu9NPePogtN2Z+tmnpTFzluveDlemETi+XouowYbS wCWWtF8QBRhpEDsMAqbPCwS7M21aMoPz4JVXqmZqKSEnxr2AJUQZq8NNh4RPUxWZwvt1 +XOI5gvbfV5Cy7cTrBB9xKd0Muw/njsQ5qxePL21YOtpEcUvUjWnpaY7FWbj7bXdAjvO dwzjVvMYw0CKqQbZcclL843q0R5A5bzDtDWI8CF/ttWE3nEG6xWpzTXf/y9fhSgFG0Jp f3rw== X-Forwarded-Encrypted: i=1; AJvYcCVC8fG/XcB6TOip4hPO1PynD23Vc7x96/ELHZ3X9ObaG14BzvgGrrmDc5AbldA17w+kHJWZE98x@lists.cip-project.org X-Gm-Message-State: AOJu0Ywh1JkLYlDsY8i2wLHrBEjVNpCg/UF/qWPQqcbtWRjhWyaTufnI DZeqh8XX62mXAzmaM9EAmLObqq02ujh1lA81r71bRDVjRtPxhkgsrc+ztMJPizJd4TSMdmzyoA9 O X-Gm-Gg: ASbGncvYCHvuTKwE5TyLBOomU/38qJGk12Xm4c1Konn+4bl7zdUQmCRKGswOcsHADTB Tmt3+f9Fm6HD1FK1PLuTq1VvDrgS/VU6nLG0Nf8DvGc0dDTO647edPON5FQCbMYV9ssEp/8X0fY RN6GzPUrf6Qq8VMUMCkL+RdFvrVGqR6+aPLsN7oZPL31sSx/dx8zShz3ye+lOKFP6Xd0WgfeWuZ /Gy9kObezlADBzu4OHei5+C1oAq0UUZcj3MEDqR83pE7s3vWG1596CEKEmlfvW5FGwGtCS7FYOq eeVrNfpiDBf7Y4igOmIk/5w= X-Google-Smtp-Source: AGHT+IE+jsbv3OVqDcIl7LmmSrVlN9W6L/Hh+LaNfU2AGisQCRNIqaYEgS508G8gByNHcNw3/ae9tA== X-Received: by 2002:a05:600c:a03:b0:434:f7e3:bfbd with SMTP id 5b1f17b1804b1-4389142e8b5mr193890985e9.23.1737546685033; Wed, 22 Jan 2025 03:51:25 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b31aea72sm21474765e9.21.2025.01.22.03.51.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:51:24 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip 02/14] clk: fixed-factor: add fwname-based constructor functions Date: Wed, 22 Jan 2025 13:51:07 +0200 Message-ID: <20250122115120.2885015-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:51:30 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17565 From: Théo Lebrun commit ae156a3633d377d43990eb539f8a007c0c2bf769 upstream. Add four functions to register clk_hw based on the fw_name field in clk_parent_data, ie the value in the DT property `clock-names`. There are variants for devm or not and passing an accuracy or not passing one: - clk_hw_register_fixed_factor_fwname - clk_hw_register_fixed_factor_with_accuracy_fwname - devm_clk_hw_register_fixed_factor_fwname - devm_clk_hw_register_fixed_factor_with_accuracy_fwname The `struct clk_parent_data` init is extracted from __clk_hw_register_fixed_factor to each calling function. It is required to allow each function to pass whatever field they want, not only index. Signed-off-by: Théo Lebrun Link: https://lore.kernel.org/r/20240221-mbly-clk-v7-2-31d4ce3630c3@bootlin.com Signed-off-by: Stephen Boyd [claudiu.beznea: dropped accuracy part] Signed-off-by: Claudiu Beznea --- drivers/clk/clk-fixed-factor.c | 59 ++++++++++++++++++++++++++-------- include/linux/clk-provider.h | 6 ++++ 2 files changed, 51 insertions(+), 14 deletions(-) diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index f734e34735a9..6b30f6a05613 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -79,13 +79,12 @@ static void devm_clk_hw_register_fixed_factor_release(struct device *dev, void * static struct clk_hw * __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, const char *name, const char *parent_name, - const struct clk_hw *parent_hw, int index, + const struct clk_hw *parent_hw, const struct clk_parent_data *pdata, unsigned long flags, unsigned int mult, unsigned int div, bool devm) { struct clk_fixed_factor *fix; struct clk_init_data init = { }; - struct clk_parent_data pdata = { .index = index }; struct clk_hw *hw; int ret; @@ -114,7 +113,7 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, else if (parent_hw) init.parent_hws = &parent_hw; else - init.parent_data = &pdata; + init.parent_data = pdata; init.num_parents = 1; hw = &fix->hw; @@ -151,7 +150,9 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, const char *name, unsigned int index, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL, index, + const struct clk_parent_data pdata = { .index = index }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL, &pdata, flags, mult, div, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_index); @@ -173,8 +174,10 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev, const char *name, const struct clk_hw *parent_hw, unsigned long flags, unsigned int mult, unsigned int div) { + const struct clk_parent_data pdata = { .index = -1 }; + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw, - -1, flags, mult, div, true); + &pdata, flags, mult, div, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_parent_hw); @@ -182,9 +185,10 @@ struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev, const char *name, const struct clk_hw *parent_hw, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, - parent_hw, -1, flags, mult, div, - false); + const struct clk_parent_data pdata = { .index = -1 }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw, + &pdata, flags, mult, div, false); } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_parent_hw); @@ -192,11 +196,24 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1, - flags, mult, div, false); + const struct clk_parent_data pdata = { .index = -1 }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, + &pdata, flags, mult, div, false); } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor); +struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div) +{ + const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name }; + + return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL, + &pdata, flags, mult, div, false); +} +EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_fwname); + struct clk *clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) @@ -239,16 +256,30 @@ struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1, - flags, mult, div, true); + const struct clk_parent_data pdata = { .index = -1 }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, + &pdata, flags, mult, div, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor); +struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div) +{ + const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name }; + + return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL, + &pdata, flags, mult, div, true); +} +EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_fwname); + #ifdef CONFIG_OF static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node) { struct clk_hw *hw; const char *clk_name = node->name; + const struct clk_parent_data pdata = { .index = 0 }; u32 div, mult; int ret; @@ -266,8 +297,8 @@ static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node) of_property_read_string(node, "clock-output-names", &clk_name); - hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, NULL, 0, - 0, mult, div, false); + hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, NULL, + &pdata, 0, mult, div, false); if (IS_ERR(hw)) { /* * Clear OF_POPULATED flag so that clock registration can be diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 53dd7c9dcc94..19bd0ad70b08 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -1104,10 +1104,16 @@ void clk_unregister_fixed_factor(struct clk *clk); struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); +struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div); void clk_hw_unregister_fixed_factor(struct clk_hw *hw); struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); +struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div); struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, const char *name, unsigned int index, unsigned long flags, unsigned int mult, unsigned int div); From patchwork Wed Jan 22 11:51:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947178 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45EF1C02181 for ; Wed, 22 Jan 2025 11:51:30 +0000 (UTC) Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) by mx.groups.io with SMTP id smtpd.web11.41684.1737546688139812310 for ; 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([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b31aea72sm21474765e9.21.2025.01.22.03.51.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:51:25 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip 03/14] clk: Add devm_clk_hw_register_gate_parent_hw() Date: Wed, 22 Jan 2025 13:51:08 +0200 Message-ID: <20250122115120.2885015-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:51:30 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17566 From: Claudiu Beznea commit e1ef630c56d36770e180f0d0bf7b61b5289f5c48 upstream. Add devm_clk_hw_register_gate_parent_hw() macro to allow registering devres managed gate clocks providing struct clk_hw object as parent. Reviewed-by: Geert Uytterhoeven Acked-by: Stephen Boyd Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- include/linux/clk-provider.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 19bd0ad70b08..a0c7ff8d8928 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -606,6 +606,24 @@ struct clk *clk_register_gate(struct device *dev, const char *name, __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ NULL, (flags), (reg), (bit_idx), \ (clk_gate_flags), (lock)) +/** + * devm_clk_hw_register_gate_parent_hw - register a gate clock with the clock + * framework + * @dev: device that is registering this clock + * @name: name of this clock + * @parent_hw: pointer to parent clk + * @flags: framework-specific flags for this clock + * @reg: register address to control gating of this clock + * @bit_idx: which bit in the register controls gating of this clock + * @clk_gate_flags: gate-specific flags for this clock + * @lock: shared register lock for this clock + */ +#define devm_clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, \ + reg, bit_idx, clk_gate_flags, \ + lock) \ + __devm_clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \ + NULL, (flags), (reg), (bit_idx), \ + (clk_gate_flags), (lock)) /** * devm_clk_hw_register_gate_parent_data - register a gate clock with the * clock framework From patchwork Wed Jan 22 11:51:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947177 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B45DC0218C for ; Wed, 22 Jan 2025 11:51:30 +0000 (UTC) Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) by mx.groups.io with SMTP id smtpd.web10.41870.1737546689202168806 for ; Wed, 22 Jan 2025 03:51:29 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=ACFSStB5; spf=pass (domain: tuxon.dev, ip: 209.85.128.53, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-4361f796586so74257925e9.3 for ; Wed, 22 Jan 2025 03:51:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737546687; x=1738151487; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VwTM5alHxiV99WoSjSGaeY10FKz85c0VVLpWvkRdO+c=; b=ACFSStB5qpSqbO2esRfoLeDBvE8GXMrHSxgH5MAg97l/PsD8Q6eNH0e2zO1xGQMaMC ID2ilWKOJL8u1W0yHwhWALapxKjAn+BrtIN3qw4dZ2v6IHaM7BcPNy0u6jhvb5U4CsWL gSZx/7fLQi4Ag4FzBon7onLL2pUH31pBvYDBKCZ/QYZ8GTVbZ4IWmfEMVLZ7WjW5OAQe HcfMINOC/IHeHMnr7D4rS7Xlbzr1Qv1PM5Ci5TWSWkHUFAjEqeo/DyVDici6FIq3Vwg5 Hnq3AUD6VN5ZrFD34UGu7598Rmbw/znVO5cddUcDaaZiCGvnpzBQ88KvZoKjeLtWeT3q sFGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737546687; x=1738151487; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VwTM5alHxiV99WoSjSGaeY10FKz85c0VVLpWvkRdO+c=; b=n8Hhnqt9RB24M8i7sL6O2KZyL/FRK8K5oZsWXmaXPoHw9wXt4my6aEJwBR1MuL9RUX 8Lp9+XpYLzcFY/1pDvlZqLYpjnGsxPEQ6umchp4ZBw5dE7AFVmaqWNbsqi6962wiZA7A 0+5SMNWEvo/dxkqdmuVP1/g2bktshc9jp2a9UPhGn/3dkqJujvjqIYZ2QdNv8EbyKYRD T4/mHDMXddOSacGQh/LlqGKitbM/960jPD6m/E3ZxRuSMPVeLRZ2bWSiWPHtJa9140Xl BCifOIeIjOmYtLFLYDVlMKh4U1Fvk5qqUbhbWkYbjUY2P51diQL1CpT/VMvCziRA41Bd pMAQ== X-Forwarded-Encrypted: i=1; AJvYcCUIefPr57ovYuCv/y69Ft6wHWJgVX3tGq4kgwwTnCCF2L8h6W3RIC1y42RnJ62Z9o3cFYKbZJJm@lists.cip-project.org X-Gm-Message-State: AOJu0YxNrILus+GULdwSx16mErdu1lIR0p/LXvQfvg+sItXrTN2gqZQO UuUSu7rNUAu77mgOTbmm1QlFCNKYrjZJ/OeU1oXzZHF9Yh4cUKIRUxr2g0bCBZE= X-Gm-Gg: ASbGnctdAew84bK3IJe8qUjbCauYaV25ZQytQESjlCYqamJSTdNUQsYWu3T8gphW4B1 3F6RboWJFZpkV1bh1dP1mfnckHJgaLK5KhMa1HjqHyqZ9ZS/wK2OaBnYYuTPXJBKwKwG+RrBfi/ pCvwci/7GhQ0dFNIJRmc5zIOg1hKjR3B/pEoPzBneCPXT5z731HDfUK7I2Mq3K9LtjaLdA4+W3P PT7w0mg/QV81P247lXfTblG1c72OsM8LwB2BoxfktgGT577UHG/WyAn6pIXV51Q3pRlB05jOR/2 MBs+2/H0AVk2xgLP9NSuJNs= X-Google-Smtp-Source: AGHT+IFvGTjB5t6YhqaiNASrv/TyPGTmkW+RqWcSv3LTGooteWpDMdUuziPiFpxWVC8P/BGYd+Qd6Q== X-Received: by 2002:a05:600c:4ed4:b0:434:f586:7520 with SMTP id 5b1f17b1804b1-438913c5d53mr196441565e9.6.1737546687572; Wed, 22 Jan 2025 03:51:27 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b31aea72sm21474765e9.21.2025.01.22.03.51.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:51:27 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip 04/14] clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP Date: Wed, 22 Jan 2025 13:51:09 +0200 Message-ID: <20250122115120.2885015-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:51:30 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17567 From: Claudiu Beznea commit c8bd9bd6446fa034a1877b553bf118606b37c025 upstream. The Renesas RZ/G3S SoC has an IP named Battery Backup Function (VBATTB) that generates the RTC clock. Add clock, reset and power domain support for it. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240614071932.1014067-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [claudiu.beznea: dropped PM domain part as it is not ready yet] Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/r9a08g045-cpg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index c3e6da2de197..55e7d42dc472 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -215,6 +215,7 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9), DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0), DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0), + DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0), }; static const struct rzg2l_reset r9a08g045_resets[] = { @@ -231,6 +232,7 @@ static const struct rzg2l_reset r9a08g045_resets[] = { DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0), DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1), DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2), + DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0), }; static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { @@ -238,6 +240,7 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { MOD_CLK_BASE + R9A08G045_IA55_PCLK, MOD_CLK_BASE + R9A08G045_IA55_CLK, MOD_CLK_BASE + R9A08G045_DMAC_ACLK, + MOD_CLK_BASE + R9A08G045_VBAT_BCLK, }; const struct rzg2l_cpg_info r9a08g045_cpg_info = { From patchwork Wed Jan 22 11:51:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947182 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FACCC02181 for ; Wed, 22 Jan 2025 11:51:40 +0000 (UTC) Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) by mx.groups.io with SMTP id smtpd.web11.41685.1737546690488884597 for ; Wed, 22 Jan 2025 03:51:30 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=E4nmaWHa; spf=pass (domain: tuxon.dev, ip: 209.85.128.43, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-43625c4a50dso47039095e9.0 for ; Wed, 22 Jan 2025 03:51:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737546689; x=1738151489; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2TDhDVdmrLyUjwA3Rd9ZKV50+C7dveaBYHkQzItSHlw=; b=E4nmaWHarOdjj/caDVH7keYUROHKcVyrLrJmdohadgm+s2bgs3u5UEZFo6rLTkdLaf KwBHcOMjJEVQmeWidvRHFa0q4ok3zaVyHFMy+vNzP3HDyKzZFalb/ImJgqvAyW77eggH EO9psxqYY1CecME63RcS2ppRVEr0ij0dH8CTjMN0CXGogXTKl/IrZ4UmQYmCL2VYj5rv XaYR1RJRv50fJ7RoiQ843Cxx1l9m1ZJIpFVMBCq0IeoXbRdCAWiMCT+KWLZw/a668d3l RMqGFaaYFVoDG60PhqU4YJcgnD2qxGBw+uVFvtGjzieN9aS5lA0+c0J104W8iepSFIvj i40Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737546689; x=1738151489; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2TDhDVdmrLyUjwA3Rd9ZKV50+C7dveaBYHkQzItSHlw=; b=wtw4cyo0KyZxXJzrZwL9hN8KhvAI9tstXgbj28UzMrxo4RHW4ggKhCkQv3yEHN+ogL Z3Qdsi7fJtZl5I0nqKmXiOQmIIcoF9i7/eZVJo32vXZabNBeJAp1Hfs4k5PUuzYNOqV6 5MPR6ERTZLCJjGHL1tTtAYeoelRnQGET12/D27PS1MscU6aDGokeutw23/Mh1aTq1+7r 0tQYtKvLdBJJCOUALmo6j/geUZazFvz8j/O/2TIekB3594KZBtgZ9Cb4XdT2GBL5TEqm v7VgOntwhGyW+8pKgKnupPo+quWZAKXWnCLDMqxXUznXhLBAgVZCLMqfAgrIa6RCpiJx dVYw== X-Forwarded-Encrypted: i=1; AJvYcCWh5ToKKfhSPIOVJo313PHw8Scjv2Ei9Yc/AjB9P75QdYSm4i7ziYFrJj53ceUbi07ASyOIALr/@lists.cip-project.org X-Gm-Message-State: AOJu0YyfNUr5cYAt2IvBuSOOu95mg3GHbFf/HZgS76/CYU/v3OpvHT2c Qbswk7/lkmK7gKgMvYa4w1NH0fFUf1X1HvwLEgHH6NohUAnhMgUhN4M8a0xAytk= X-Gm-Gg: ASbGncuNiEKVipFGz1ay0CQey6tz2H9JNHv2/Gdn2mYnO1o/N4CqvgWMvFnVW6uNgtE YbsCvgLBeZw11HoiEzX6iBSPb+gynlScza2v1XXzb5MJfNN+XvjwIOP0AjWeCT/E+C6sVGCchte +/Wx6i9InCxmCfEGoyLUY7XobzM9xRNCdFAHE4T+og8NcWlfSVGJVppi0f26wrSdNPshCgpDsk0 tep/bKpqwZgQLjXoJtwTJowqF8gNLD8auzCiaK/WgVTqoWx2HKLqiRZ8my/cKqvtFq+FM7tMG/j iX9tlpZztVZEBFbMXPhkwnKdllEIsGguqg== X-Google-Smtp-Source: AGHT+IGZw/YMLdHBzS+sWARaodE4BUemhOd/0xPNMnYLpxdaZiN3IhCcITP5wLHhgLKVZWqFWPl9xA== X-Received: by 2002:a05:600c:1f0b:b0:434:f270:a4f0 with SMTP id 5b1f17b1804b1-4389142e1a3mr166755615e9.21.1737546688883; Wed, 22 Jan 2025 03:51:28 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b31aea72sm21474765e9.21.2025.01.22.03.51.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:51:28 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip 05/14] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB Date: Wed, 22 Jan 2025 13:51:10 +0200 Message-ID: <20250122115120.2885015-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:51:40 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17568 From: Claudiu Beznea commit cdfd5daf90af8363fb1f58e08c829a775b2e2fc5 upstream. The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC, the tamper detector and a small general usage memory of 128B. The VBATTB controller controls the clock for the RTC on the Renesas RZ/G3S. The HW block diagram for the clock logic is as follows: +----------+ XC `\ RTXIN --->| |----->| \ +----+ VBATTCLK | 32K clock| | |----->|gate|-----------> | osc | XBYP | | +----+ RTXOUT --->| |----->| / +----------+ ,/ One could connect as input to this HW block either a crystal or an external clock device. This is board specific. After discussions w/ Stephen Boyd the clock tree associated with this hardware block was exported in Linux as: input-xtal xbyp xc mux vbattclk where: - input-xtal is the input clock (connected to RTXIN, RTXOUT pins) - xc, xbyp are mux inputs - mux is the internal mux - vbattclk is the gate clock that feeds in the end the RTC to allow selecting the input of the MUX though assigned-clock DT properties, using the already existing clock drivers and avoid adding other DT properties. This allows select the input of the mux based on the type of the connected input clock: - if the 32768 crystal is connected as input for the VBATTB, the input of the mux should be xc - if an external clock device is connected as input for the VBATTB the input of the mux should be xbyp Add bindings for the VBATTB controller. Reviewed-by: Geert Uytterhoeven Reviewed-by: Krzysztof Kozlowski Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- .../clock/renesas,r9a08g045-vbattb.yaml | 84 +++++++++++++++++++ .../clock/renesas,r9a08g045-vbattb.h | 13 +++ 2 files changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml create mode 100644 include/dt-bindings/clock/renesas,r9a08g045-vbattb.h diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml new file mode 100644 index 000000000000..3707e4118949 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Battery Backup Function (VBATTB) + +description: + Renesas VBATTB is an always on powered module (backed by battery) which + controls the RTC clock (VBATTCLK), tamper detection logic and a small + general usage memory (128B). + +maintainers: + - Claudiu Beznea + +properties: + compatible: + const: renesas,r9a08g045-vbattb + + reg: + maxItems: 1 + + interrupts: + items: + - description: tamper detector interrupt + + clocks: + items: + - description: VBATTB module clock + - description: RTC input clock (crystal or external clock device) + + clock-names: + items: + - const: bclk + - const: rtx + + '#clock-cells': + const: 1 + + power-domains: + maxItems: 1 + + resets: + items: + - description: VBATTB module reset + + quartz-load-femtofarads: + description: load capacitance of the on board crystal + enum: [ 4000, 7000, 9000, 12500 ] + default: 4000 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - '#clock-cells' + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + clock-controller@1005c000 { + compatible = "renesas,r9a08g045-vbattb"; + reg = <0x1005c000 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; + clock-names = "bclk", "rtx"; + assigned-clocks = <&vbattb VBATTB_MUX>; + assigned-clock-parents = <&vbattb VBATTB_XC>; + #clock-cells = <1>; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + quartz-load-femtofarads = <12500>; + }; diff --git a/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h new file mode 100644 index 000000000000..67774eafad06 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ +#define __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ + +#define VBATTB_XC 0 +#define VBATTB_XBYP 1 +#define VBATTB_MUX 2 +#define VBATTB_VBATTCLK 3 + +#endif /* __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ */ From patchwork Wed Jan 22 11:51:11 2025 Content-Type: text/plain; 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([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b31aea72sm21474765e9.21.2025.01.22.03.51.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:51:29 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip 06/14] clk: renesas: vbattb: Add VBATTB clock driver Date: Wed, 22 Jan 2025 13:51:11 +0200 Message-ID: <20250122115120.2885015-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:51:40 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17569 From: Claudiu Beznea commit be20a73e03e19005cfa5c1c4d6158af1ba02f056 upstream. The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used by the RTC. The input to the VBATTB could be a 32KHz crystal or an external clock device. The HW block diagram for the clock generator is as follows: +----------+ XC `\ RTXIN --->| |----->| \ +----+ VBATTCLK | 32K clock| | |----->|gate|-----------> | osc | XBYP | | +----+ RTXOUT --->| |----->| / +----------+ , After discussions w/ Stephen Boyd the clock tree associated with this hardware block was exported in Linux as: vbattb-xtal xbyp xc mux vbattbclk where: - input-xtal is the input clock (connected to RTXIN, RTXOUT pins) - xc, xbyp are mux inputs - mux is the internal mux - vbattclk is the gate clock that feeds in the end the RTC to allow selecting the input of the MUX though assigned-clock DT properties, using the already existing clock drivers and avoid adding other DT properties. If the crystal is connected on RTXIN, RTXOUT pins the XC will be selected as mux input. If an external clock device is connected on RTXIN, RTXOUT pins the XBYP will be selected as mux input. The load capacitance of the internal crystal can be configured with renesas,vbattb-load-nanofarads DT property. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/Kconfig | 5 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/clk-vbattb.c | 205 +++++++++++++++++++++++++++++++ 3 files changed, 211 insertions(+) create mode 100644 drivers/clk/renesas/clk-vbattb.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 69396e197959..04593172392e 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -223,6 +223,11 @@ config CLK_RZG2L bool "Renesas RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST select RESET_CONTROLLER +config CLK_RENESAS_VBATTB + tristate "Renesas VBATTB clock controller" + depends on ARCH_RZG2L || COMPILE_TEST + select RESET_CONTROLLER + # Generic config CLK_RENESAS_CPG_MSSR bool "CPG/MSSR clock support" if COMPILE_TEST diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 879a07d445f9..46bdcbcbf183 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -50,3 +50,4 @@ obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o obj-$(CONFIG_CLK_RENESAS_CPG_MSTP) += clk-mstp.o obj-$(CONFIG_CLK_RENESAS_DIV6) += clk-div6.o +obj-$(CONFIG_CLK_RENESAS_VBATTB) += clk-vbattb.o diff --git a/drivers/clk/renesas/clk-vbattb.c b/drivers/clk/renesas/clk-vbattb.c new file mode 100644 index 000000000000..ff9d1ead455c --- /dev/null +++ b/drivers/clk/renesas/clk-vbattb.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * VBATTB clock driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define VBATTB_BKSCCR 0x1c +#define VBATTB_BKSCCR_SOSEL 6 +#define VBATTB_SOSCCR2 0x24 +#define VBATTB_SOSCCR2_SOSTP2 0 +#define VBATTB_XOSCCR 0x30 +#define VBATTB_XOSCCR_OUTEN 16 +#define VBATTB_XOSCCR_XSEL GENMASK(1, 0) +#define VBATTB_XOSCCR_XSEL_4_PF 0x0 +#define VBATTB_XOSCCR_XSEL_7_PF 0x1 +#define VBATTB_XOSCCR_XSEL_9_PF 0x2 +#define VBATTB_XOSCCR_XSEL_12_5_PF 0x3 + +/** + * struct vbattb_clk - VBATTB clock data structure + * @base: base address + * @lock: lock + */ +struct vbattb_clk { + void __iomem *base; + spinlock_t lock; +}; + +static int vbattb_clk_validate_load_capacitance(u32 *reg_lc, u32 of_lc) +{ + switch (of_lc) { + case 4000: + *reg_lc = VBATTB_XOSCCR_XSEL_4_PF; + break; + case 7000: + *reg_lc = VBATTB_XOSCCR_XSEL_7_PF; + break; + case 9000: + *reg_lc = VBATTB_XOSCCR_XSEL_9_PF; + break; + case 12500: + *reg_lc = VBATTB_XOSCCR_XSEL_12_5_PF; + break; + default: + return -EINVAL; + } + + return 0; +} + +static void vbattb_clk_action(void *data) +{ + struct device *dev = data; + struct reset_control *rstc = dev_get_drvdata(dev); + int ret; + + ret = reset_control_assert(rstc); + if (ret) + dev_err(dev, "Failed to de-assert reset!"); + + ret = pm_runtime_put_sync(dev); + if (ret < 0) + dev_err(dev, "Failed to runtime suspend!"); + + of_clk_del_provider(dev->of_node); +} + +static int vbattb_clk_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct clk_parent_data parent_data = {}; + struct clk_hw_onecell_data *clk_data; + const struct clk_hw *parent_hws[2]; + struct device *dev = &pdev->dev; + struct reset_control *rstc; + struct vbattb_clk *vbclk; + u32 of_lc, reg_lc; + struct clk_hw *hw; + /* 4 clocks are exported: VBATTB_XC, VBATTB_XBYP, VBATTB_MUX, VBATTB_VBATTCLK. */ + u8 num_clks = 4; + int ret; + + /* Default to 4pF as this is not needed if external clock device is connected. */ + of_lc = 4000; + of_property_read_u32(np, "quartz-load-femtofarads", &of_lc); + + ret = vbattb_clk_validate_load_capacitance(®_lc, of_lc); + if (ret) + return ret; + + vbclk = devm_kzalloc(dev, sizeof(*vbclk), GFP_KERNEL); + if (!vbclk) + return -ENOMEM; + + clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, num_clks), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + clk_data->num = num_clks; + + vbclk->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(vbclk->base)) + return PTR_ERR(vbclk->base); + + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; + + rstc = devm_reset_control_get_shared(dev, NULL); + if (IS_ERR(rstc)) + return PTR_ERR(rstc); + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + ret = reset_control_deassert(rstc); + if (ret) { + pm_runtime_put_sync(dev); + return ret; + } + + dev_set_drvdata(dev, rstc); + ret = devm_add_action_or_reset(dev, vbattb_clk_action, dev); + if (ret) + return ret; + + spin_lock_init(&vbclk->lock); + + parent_data.fw_name = "rtx"; + hw = devm_clk_hw_register_gate_parent_data(dev, "xc", &parent_data, 0, + vbclk->base + VBATTB_SOSCCR2, + VBATTB_SOSCCR2_SOSTP2, + CLK_GATE_SET_TO_DISABLE, &vbclk->lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_XC] = hw; + + hw = devm_clk_hw_register_fixed_factor_fwname(dev, np, "xbyp", "rtx", 0, 1, 1); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_XBYP] = hw; + + parent_hws[0] = clk_data->hws[VBATTB_XC]; + parent_hws[1] = clk_data->hws[VBATTB_XBYP]; + hw = devm_clk_hw_register_mux_parent_hws(dev, "mux", parent_hws, 2, 0, + vbclk->base + VBATTB_BKSCCR, + VBATTB_BKSCCR_SOSEL, + 1, 0, &vbclk->lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_MUX] = hw; + + /* Set load capacitance before registering the VBATTCLK clock. */ + scoped_guard(spinlock, &vbclk->lock) { + u32 val = readl_relaxed(vbclk->base + VBATTB_XOSCCR); + + val &= ~VBATTB_XOSCCR_XSEL; + val |= reg_lc; + writel_relaxed(val, vbclk->base + VBATTB_XOSCCR); + } + + /* This feeds the RTC counter clock and it needs to stay on. */ + hw = devm_clk_hw_register_gate_parent_hw(dev, "vbattclk", hw, CLK_IS_CRITICAL, + vbclk->base + VBATTB_XOSCCR, + VBATTB_XOSCCR_OUTEN, 0, + &vbclk->lock); + + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_VBATTCLK] = hw; + + return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); +} + +static const struct of_device_id vbattb_clk_match[] = { + { .compatible = "renesas,r9a08g045-vbattb" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, vbattb_clk_match); + +static struct platform_driver vbattb_clk_driver = { + .driver = { + .name = "renesas-vbattb-clk", + .of_match_table = vbattb_clk_match, + }, + .probe = vbattb_clk_probe, +}; +module_platform_driver(vbattb_clk_driver); + +MODULE_DESCRIPTION("Renesas VBATTB Clock Driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); From patchwork Wed Jan 22 11:51:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947186 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64740C0218F for ; Wed, 22 Jan 2025 11:51:40 +0000 (UTC) Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) by mx.groups.io with SMTP id smtpd.web10.41873.1737546693642615292 for ; Wed, 22 Jan 2025 03:51:33 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=IywmWmdl; spf=pass (domain: tuxon.dev, ip: 209.85.128.44, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-435f8f29f8aso48680665e9.2 for ; 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([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b31aea72sm21474765e9.21.2025.01.22.03.51.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:51:30 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip 07/14] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RTCA-3 IP Date: Wed, 22 Jan 2025 13:51:12 +0200 Message-ID: <20250122115120.2885015-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:51:40 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17570 From: Claudiu Beznea commit 71c61a45c951eca67dd2cbc4de9cdd687ece4ead upstream. Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC. The RTC IP available on Renesas RZ/V2H is almost identical with the one found on Renesas RZ/G3S (it misses the time capture functionality which is not yet implemented on proposed driver). For this, added also a generic compatible that will be used at the moment as fallback for both RZ/G3S and RZ/V2H. Reviewed-by: Rob Herring (Arm) Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20241030110120.332802-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Alexandre Belloni Signed-off-by: Claudiu Beznea --- .../bindings/rtc/renesas,rz-rtca3.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml diff --git a/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml new file mode 100644 index 000000000000..e70eeb66aa64 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/renesas,rz-rtca3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RTCA-3 Real Time Clock + +maintainers: + - Claudiu Beznea + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + items: + - enum: + - renesas,r9a08g045-rtca3 # RZ/G3S + - const: renesas,rz-rtca3 + + reg: + maxItems: 1 + + interrupts: + items: + - description: Alarm interrupt + - description: Periodic interrupt + - description: Carry interrupt + + interrupt-names: + items: + - const: alarm + - const: period + - const: carry + + clocks: + items: + - description: RTC bus clock + - description: RTC counter clock + + clock-names: + items: + - const: bus + - const: counter + + power-domains: + maxItems: 1 + + resets: + items: + - description: VBATTB module reset + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + rtc@1004ec00 { + compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; + reg = <0x1004ec00 0x400>; + interrupts = , + , + ; + interrupt-names = "alarm", "period", "carry"; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattclk VBATTB_VBATTCLK>; + clock-names = "bus", "counter"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + }; From patchwork Wed Jan 22 11:51:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947187 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4623FC0218D for ; Wed, 22 Jan 2025 11:51:40 +0000 (UTC) Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.groups.io with SMTP id smtpd.web10.41874.1737546695151288386 for ; Wed, 22 Jan 2025 03:51:35 -0800 Authentication-Results: mx.groups.io; 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([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b31aea72sm21474765e9.21.2025.01.22.03.51.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:51:32 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip 08/14] rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S SoC Date: Wed, 22 Jan 2025 13:51:13 +0200 Message-ID: <20250122115120.2885015-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:51:40 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17571 From: Claudiu Beznea commit d4488377609e36cd9785533c29ccea4b86c292b9 upstream. The RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC has calendar count mode and binary count mode (selectable though RCR2.CNTMD) capabilities, alarm capabilities, clock error correction capabilities. It can generate alarm, period, carry interrupts. Add a driver for RTCA-3 IP. The driver implements calendar count mode (as the conversion b/w RTC and system time is simpler, done with bcd2bin(), bin2bcd()), read and set time, read and set alarm, read and set an offset. Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20241030110120.332802-6-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Alexandre Belloni [claudiu.beznea: - dropped references to RTC_DRV_MA35D1 as it is not present in v6.1 cip - changed return type of rtca3_remove() to int and return 0] Signed-off-by: Claudiu Beznea --- MAINTAINERS | 8 + drivers/rtc/Kconfig | 10 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-renesas-rtca3.c | 901 ++++++++++++++++++++++++++++++++ 4 files changed, 920 insertions(+) create mode 100644 drivers/rtc/rtc-renesas-rtca3.c diff --git a/MAINTAINERS b/MAINTAINERS index 90366b990f11..4f5f924124d2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17629,6 +17629,14 @@ S: Supported F: Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml F: drivers/counter/rz-mtu3-cnt.c +RENESAS RTCA-3 RTC DRIVER +M: Claudiu Beznea +L: linux-rtc@vger.kernel.org +L: linux-renesas-soc@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml +F: drivers/rtc/rtc-renesas-rtca3.c + RENESAS RZ/N1 A5PSW SWITCH DRIVER M: Clément Léger L: linux-renesas-soc@vger.kernel.org diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 87dc050ca004..d0ae7f805c84 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1942,6 +1942,16 @@ config RTC_DRV_TI_K3 This driver can also be built as a module, if so, the module will be called "rtc-ti-k3". +config RTC_DRV_RENESAS_RTCA3 + tristate "Renesas RTCA-3 RTC" + depends on ARCH_RENESAS + help + If you say yes here you get support for the Renesas RTCA-3 RTC + available on the Renesas RZ/G3S SoC. + + This driver can also be built as a module, if so, the module + will be called "rtc-rtca3". + comment "HID Sensor RTC drivers" config RTC_DRV_HID_SENSOR_TIME diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index aab22bc63432..4fc1de1987f7 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -154,6 +154,7 @@ obj-$(CONFIG_RTC_DRV_RX8010) += rtc-rx8010.o obj-$(CONFIG_RTC_DRV_RX8025) += rtc-rx8025.o obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o obj-$(CONFIG_RTC_DRV_RZN1) += rtc-rzn1.o +obj-$(CONFIG_RTC_DRV_RENESAS_RTCA3) += rtc-renesas-rtca3.o obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o obj-$(CONFIG_RTC_DRV_S3C) += rtc-s3c.o obj-$(CONFIG_RTC_DRV_S5M) += rtc-s5m.o diff --git a/drivers/rtc/rtc-renesas-rtca3.c b/drivers/rtc/rtc-renesas-rtca3.c new file mode 100644 index 000000000000..7683df87eafa --- /dev/null +++ b/drivers/rtc/rtc-renesas-rtca3.c @@ -0,0 +1,901 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * On-Chip RTC Support available on RZ/G3S SoC + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Counter registers. */ +#define RTCA3_RSECCNT 0x2 +#define RTCA3_RSECCNT_SEC GENMASK(6, 0) +#define RTCA3_RMINCNT 0x4 +#define RTCA3_RMINCNT_MIN GENMASK(6, 0) +#define RTCA3_RHRCNT 0x6 +#define RTCA3_RHRCNT_HR GENMASK(5, 0) +#define RTCA3_RHRCNT_PM BIT(6) +#define RTCA3_RWKCNT 0x8 +#define RTCA3_RWKCNT_WK GENMASK(2, 0) +#define RTCA3_RDAYCNT 0xa +#define RTCA3_RDAYCNT_DAY GENMASK(5, 0) +#define RTCA3_RMONCNT 0xc +#define RTCA3_RMONCNT_MONTH GENMASK(4, 0) +#define RTCA3_RYRCNT 0xe +#define RTCA3_RYRCNT_YEAR GENMASK(7, 0) + +/* Alarm registers. */ +#define RTCA3_RSECAR 0x10 +#define RTCA3_RSECAR_SEC GENMASK(6, 0) +#define RTCA3_RMINAR 0x12 +#define RTCA3_RMINAR_MIN GENMASK(6, 0) +#define RTCA3_RHRAR 0x14 +#define RTCA3_RHRAR_HR GENMASK(5, 0) +#define RTCA3_RHRAR_PM BIT(6) +#define RTCA3_RWKAR 0x16 +#define RTCA3_RWKAR_DAYW GENMASK(2, 0) +#define RTCA3_RDAYAR 0x18 +#define RTCA3_RDAYAR_DATE GENMASK(5, 0) +#define RTCA3_RMONAR 0x1a +#define RTCA3_RMONAR_MON GENMASK(4, 0) +#define RTCA3_RYRAR 0x1c +#define RTCA3_RYRAR_YR GENMASK(7, 0) +#define RTCA3_RYRAREN 0x1e + +/* Alarm enable bit (for all alarm registers). */ +#define RTCA3_AR_ENB BIT(7) + +/* Control registers. */ +#define RTCA3_RCR1 0x22 +#define RTCA3_RCR1_AIE BIT(0) +#define RTCA3_RCR1_CIE BIT(1) +#define RTCA3_RCR1_PIE BIT(2) +#define RTCA3_RCR1_PES GENMASK(7, 4) +#define RTCA3_RCR1_PES_1_64_SEC 0x8 +#define RTCA3_RCR2 0x24 +#define RTCA3_RCR2_START BIT(0) +#define RTCA3_RCR2_RESET BIT(1) +#define RTCA3_RCR2_AADJE BIT(4) +#define RTCA3_RCR2_ADJP BIT(5) +#define RTCA3_RCR2_HR24 BIT(6) +#define RTCA3_RCR2_CNTMD BIT(7) +#define RTCA3_RSR 0x20 +#define RTCA3_RSR_AF BIT(0) +#define RTCA3_RSR_CF BIT(1) +#define RTCA3_RSR_PF BIT(2) +#define RTCA3_RADJ 0x2e +#define RTCA3_RADJ_ADJ GENMASK(5, 0) +#define RTCA3_RADJ_ADJ_MAX 0x3f +#define RTCA3_RADJ_PMADJ GENMASK(7, 6) +#define RTCA3_RADJ_PMADJ_NONE 0 +#define RTCA3_RADJ_PMADJ_ADD 1 +#define RTCA3_RADJ_PMADJ_SUB 2 + +/* Polling operation timeouts. */ +#define RTCA3_DEFAULT_TIMEOUT_US 150 +#define RTCA3_IRQSET_TIMEOUT_US 5000 +#define RTCA3_START_TIMEOUT_US 150000 +#define RTCA3_RESET_TIMEOUT_US 200000 + +/** + * enum rtca3_alrm_set_step - RTCA3 alarm set steps + * @RTCA3_ALRM_SSTEP_DONE: alarm setup done step + * @RTCA3_ALRM_SSTEP_IRQ: two 1/64 periodic IRQs were generated step + * @RTCA3_ALRM_SSTEP_INIT: alarm setup initialization step + */ +enum rtca3_alrm_set_step { + RTCA3_ALRM_SSTEP_DONE = 0, + RTCA3_ALRM_SSTEP_IRQ = 1, + RTCA3_ALRM_SSTEP_INIT = 3, +}; + +/** + * struct rtca3_ppb_per_cycle - PPB per cycle + * @ten_sec: PPB per cycle in 10 seconds adjutment mode + * @sixty_sec: PPB per cycle in 60 seconds adjustment mode + */ +struct rtca3_ppb_per_cycle { + int ten_sec; + int sixty_sec; +}; + +/** + * struct rtca3_priv - RTCA3 private data structure + * @base: base address + * @rtc_dev: RTC device + * @rstc: reset control + * @set_alarm_completion: alarm setup completion + * @alrm_sstep: alarm setup step (see enum rtca3_alrm_set_step) + * @lock: device lock + * @ppb: ppb per cycle for each the available adjustment modes + * @wakeup_irq: wakeup IRQ + */ +struct rtca3_priv { + void __iomem *base; + struct rtc_device *rtc_dev; + struct reset_control *rstc; + struct completion set_alarm_completion; + atomic_t alrm_sstep; + spinlock_t lock; + struct rtca3_ppb_per_cycle ppb; + int wakeup_irq; +}; + +static void rtca3_byte_update_bits(struct rtca3_priv *priv, u8 off, u8 mask, u8 val) +{ + u8 tmp; + + tmp = readb(priv->base + off); + tmp &= ~mask; + tmp |= (val & mask); + writeb(tmp, priv->base + off); +} + +static u8 rtca3_alarm_handler_helper(struct rtca3_priv *priv) +{ + u8 val, pending; + + val = readb(priv->base + RTCA3_RSR); + pending = val & RTCA3_RSR_AF; + writeb(val & ~pending, priv->base + RTCA3_RSR); + + if (pending) + rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF); + + return pending; +} + +static irqreturn_t rtca3_alarm_handler(int irq, void *dev_id) +{ + struct rtca3_priv *priv = dev_id; + u8 pending; + + guard(spinlock)(&priv->lock); + + pending = rtca3_alarm_handler_helper(priv); + + return IRQ_RETVAL(pending); +} + +static irqreturn_t rtca3_periodic_handler(int irq, void *dev_id) +{ + struct rtca3_priv *priv = dev_id; + u8 val, pending; + + guard(spinlock)(&priv->lock); + + val = readb(priv->base + RTCA3_RSR); + pending = val & RTCA3_RSR_PF; + + if (pending) { + writeb(val & ~pending, priv->base + RTCA3_RSR); + + if (atomic_read(&priv->alrm_sstep) > RTCA3_ALRM_SSTEP_IRQ) { + /* Alarm setup in progress. */ + atomic_dec(&priv->alrm_sstep); + + if (atomic_read(&priv->alrm_sstep) == RTCA3_ALRM_SSTEP_IRQ) { + /* + * We got 2 * 1/64 periodic interrupts. Disable + * interrupt and let alarm setup continue. + */ + rtca3_byte_update_bits(priv, RTCA3_RCR1, + RTCA3_RCR1_PIE, 0); + readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, val, + !(val & RTCA3_RCR1_PIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + complete(&priv->set_alarm_completion); + } + } + } + + return IRQ_RETVAL(pending); +} + +static void rtca3_prepare_cntalrm_regs_for_read(struct rtca3_priv *priv, bool cnt) +{ + /* Offset b/w time and alarm registers. */ + u8 offset = cnt ? 0 : 0xe; + + /* + * According to HW manual (section 22.6.4. Notes on writing to and + * reading from registers) after writing to count registers, alarm + * registers, year alarm enable register, bits RCR2.AADJE, AADJP, + * and HR24 register, we need to do 3 empty reads before being + * able to fetch the registers content. + */ + for (u8 i = 0; i < 3; i++) { + readb(priv->base + RTCA3_RSECCNT + offset); + readb(priv->base + RTCA3_RMINCNT + offset); + readb(priv->base + RTCA3_RHRCNT + offset); + readb(priv->base + RTCA3_RWKCNT + offset); + readb(priv->base + RTCA3_RDAYCNT + offset); + readw(priv->base + RTCA3_RYRCNT + offset); + if (!cnt) + readb(priv->base + RTCA3_RYRAREN); + } +} + +static int rtca3_read_time(struct device *dev, struct rtc_time *tm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + u8 sec, min, hour, wday, mday, month, tmp; + u8 trials = 0; + u32 year100; + u16 year; + + guard(spinlock_irqsave)(&priv->lock); + + tmp = readb(priv->base + RTCA3_RCR2); + if (!(tmp & RTCA3_RCR2_START)) + return -EINVAL; + + do { + /* Clear carry interrupt. */ + rtca3_byte_update_bits(priv, RTCA3_RSR, RTCA3_RSR_CF, 0); + + /* Read counters. */ + sec = readb(priv->base + RTCA3_RSECCNT); + min = readb(priv->base + RTCA3_RMINCNT); + hour = readb(priv->base + RTCA3_RHRCNT); + wday = readb(priv->base + RTCA3_RWKCNT); + mday = readb(priv->base + RTCA3_RDAYCNT); + month = readb(priv->base + RTCA3_RMONCNT); + year = readw(priv->base + RTCA3_RYRCNT); + + tmp = readb(priv->base + RTCA3_RSR); + + /* + * We cannot generate carries due to reading 64Hz counter as + * the driver doesn't implement carry, thus, carries will be + * generated once per seconds. Add a timeout of 5 trials here + * to avoid infinite loop, if any. + */ + } while ((tmp & RTCA3_RSR_CF) && ++trials < 5); + + if (trials >= 5) + return -ETIMEDOUT; + + tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECCNT_SEC, sec)); + tm->tm_min = bcd2bin(FIELD_GET(RTCA3_RMINCNT_MIN, min)); + tm->tm_hour = bcd2bin(FIELD_GET(RTCA3_RHRCNT_HR, hour)); + tm->tm_wday = bcd2bin(FIELD_GET(RTCA3_RWKCNT_WK, wday)); + tm->tm_mday = bcd2bin(FIELD_GET(RTCA3_RDAYCNT_DAY, mday)); + tm->tm_mon = bcd2bin(FIELD_GET(RTCA3_RMONCNT_MONTH, month)) - 1; + year = FIELD_GET(RTCA3_RYRCNT_YEAR, year); + year100 = bcd2bin((year == 0x99) ? 0x19 : 0x20); + tm->tm_year = (year100 * 100 + bcd2bin(year)) - 1900; + + return 0; +} + +static int rtca3_set_time(struct device *dev, struct rtc_time *tm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + u8 rcr2, tmp; + int ret; + + guard(spinlock_irqsave)(&priv->lock); + + /* Stop the RTC. */ + rcr2 = readb(priv->base + RTCA3_RCR2); + writeb(rcr2 & ~RTCA3_RCR2_START, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + !(tmp & RTCA3_RCR2_START), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* Update time. */ + writeb(bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECCNT); + writeb(bin2bcd(tm->tm_min), priv->base + RTCA3_RMINCNT); + writeb(bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRCNT); + writeb(bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKCNT); + writeb(bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYCNT); + writeb(bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONCNT); + writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRCNT); + + /* Make sure we can read back the counters. */ + rtca3_prepare_cntalrm_regs_for_read(priv, true); + + /* Start RTC. */ + writeb(rcr2 | RTCA3_RCR2_START, priv->base + RTCA3_RCR2); + return readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + (tmp & RTCA3_RCR2_START), + 10, RTCA3_DEFAULT_TIMEOUT_US); +} + +static int rtca3_alarm_irq_set_helper(struct rtca3_priv *priv, + u8 interrupts, + unsigned int enabled) +{ + u8 tmp, val; + + if (enabled) { + /* + * AIE, CIE, PIE bit indexes in RSR corresponds with + * those on RCR1. Same interrupts mask can be used. + */ + rtca3_byte_update_bits(priv, RTCA3_RSR, interrupts, 0); + val = interrupts; + } else { + val = 0; + } + + rtca3_byte_update_bits(priv, RTCA3_RCR1, interrupts, val); + return readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + ((tmp & interrupts) == val), + 10, RTCA3_IRQSET_TIMEOUT_US); +} + +static int rtca3_alarm_irq_enable(struct device *dev, unsigned int enabled) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + + guard(spinlock_irqsave)(&priv->lock); + + return rtca3_alarm_irq_set_helper(priv, RTCA3_RCR1_AIE, enabled); +} + +static int rtca3_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + u8 sec, min, hour, wday, mday, month; + struct rtc_time *tm = &wkalrm->time; + u32 year100; + u16 year; + + guard(spinlock_irqsave)(&priv->lock); + + sec = readb(priv->base + RTCA3_RSECAR); + min = readb(priv->base + RTCA3_RMINAR); + hour = readb(priv->base + RTCA3_RHRAR); + wday = readb(priv->base + RTCA3_RWKAR); + mday = readb(priv->base + RTCA3_RDAYAR); + month = readb(priv->base + RTCA3_RMONAR); + year = readw(priv->base + RTCA3_RYRAR); + + tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECAR_SEC, sec)); + tm->tm_min = bcd2bin(FIELD_GET(RTCA3_RMINAR_MIN, min)); + tm->tm_hour = bcd2bin(FIELD_GET(RTCA3_RHRAR_HR, hour)); + tm->tm_wday = bcd2bin(FIELD_GET(RTCA3_RWKAR_DAYW, wday)); + tm->tm_mday = bcd2bin(FIELD_GET(RTCA3_RDAYAR_DATE, mday)); + tm->tm_mon = bcd2bin(FIELD_GET(RTCA3_RMONAR_MON, month)) - 1; + year = FIELD_GET(RTCA3_RYRAR_YR, year); + year100 = bcd2bin((year == 0x99) ? 0x19 : 0x20); + tm->tm_year = (year100 * 100 + bcd2bin(year)) - 1900; + + wkalrm->enabled = !!(readb(priv->base + RTCA3_RCR1) & RTCA3_RCR1_AIE); + + return 0; +} + +static int rtca3_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + struct rtc_time *tm = &wkalrm->time; + u8 rcr1, tmp; + int ret; + + scoped_guard(spinlock_irqsave, &priv->lock) { + tmp = readb(priv->base + RTCA3_RCR2); + if (!(tmp & RTCA3_RCR2_START)) + return -EPERM; + + /* Disable AIE to prevent false interrupts. */ + rcr1 = readb(priv->base + RTCA3_RCR1); + rcr1 &= ~RTCA3_RCR1_AIE; + writeb(rcr1, priv->base + RTCA3_RCR1); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + !(tmp & RTCA3_RCR1_AIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* Set the time and enable the alarm. */ + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_min), priv->base + RTCA3_RMINAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONAR); + + writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRAR); + writeb(RTCA3_AR_ENB, priv->base + RTCA3_RYRAREN); + + /* Make sure we can read back the counters. */ + rtca3_prepare_cntalrm_regs_for_read(priv, false); + + /* Need to wait for 2 * 1/64 periodic interrupts to be generated. */ + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_INIT); + reinit_completion(&priv->set_alarm_completion); + + /* Enable periodic interrupt. */ + rcr1 |= RTCA3_RCR1_PIE; + writeb(rcr1, priv->base + RTCA3_RCR1); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + (tmp & RTCA3_RCR1_PIE), + 10, RTCA3_IRQSET_TIMEOUT_US); + } + + if (ret) + goto setup_failed; + + /* Wait for the 2 * 1/64 periodic interrupts. */ + ret = wait_for_completion_interruptible_timeout(&priv->set_alarm_completion, + msecs_to_jiffies(500)); + if (ret <= 0) { + ret = -ETIMEDOUT; + goto setup_failed; + } + + scoped_guard(spinlock_irqsave, &priv->lock) { + ret = rtca3_alarm_irq_set_helper(priv, RTCA3_RCR1_AIE, wkalrm->enabled); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); + } + + return ret; + +setup_failed: + scoped_guard(spinlock_irqsave, &priv->lock) { + /* + * Disable PIE to avoid interrupt storm in case HW needed more than + * specified timeout for setup. + */ + writeb(rcr1 & ~RTCA3_RCR1_PIE, priv->base + RTCA3_RCR1); + readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, !(tmp & ~RTCA3_RCR1_PIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); + } + + return ret; +} + +static int rtca3_read_offset(struct device *dev, long *offset) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + u8 val, radj, cycles; + u32 ppb_per_cycle; + + scoped_guard(spinlock_irqsave, &priv->lock) { + radj = readb(priv->base + RTCA3_RADJ); + val = readb(priv->base + RTCA3_RCR2); + } + + cycles = FIELD_GET(RTCA3_RADJ_ADJ, radj); + + if (!cycles) { + *offset = 0; + return 0; + } + + if (val & RTCA3_RCR2_ADJP) + ppb_per_cycle = priv->ppb.ten_sec; + else + ppb_per_cycle = priv->ppb.sixty_sec; + + *offset = cycles * ppb_per_cycle; + val = FIELD_GET(RTCA3_RADJ_PMADJ, radj); + if (val == RTCA3_RADJ_PMADJ_SUB) + *offset = -(*offset); + + return 0; +} + +static int rtca3_set_offset(struct device *dev, long offset) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + int cycles, cycles10, cycles60; + u8 radj, adjp, tmp; + int ret; + + /* + * Automatic time error adjustment could be set at intervals of 10 + * or 60 seconds. + */ + cycles10 = DIV_ROUND_CLOSEST(offset, priv->ppb.ten_sec); + cycles60 = DIV_ROUND_CLOSEST(offset, priv->ppb.sixty_sec); + + /* We can set b/w 1 and 63 clock cycles. */ + if (cycles60 >= -RTCA3_RADJ_ADJ_MAX && + cycles60 <= RTCA3_RADJ_ADJ_MAX) { + cycles = cycles60; + adjp = 0; + } else if (cycles10 >= -RTCA3_RADJ_ADJ_MAX && + cycles10 <= RTCA3_RADJ_ADJ_MAX) { + cycles = cycles10; + adjp = RTCA3_RCR2_ADJP; + } else { + return -ERANGE; + } + + radj = FIELD_PREP(RTCA3_RADJ_ADJ, abs(cycles)); + if (!cycles) + radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_NONE); + else if (cycles > 0) + radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_ADD); + else + radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_SUB); + + guard(spinlock_irqsave)(&priv->lock); + + tmp = readb(priv->base + RTCA3_RCR2); + + if ((tmp & RTCA3_RCR2_ADJP) != adjp) { + /* RADJ.PMADJ need to be set to zero before setting RCR2.ADJP. */ + writeb(0, priv->base + RTCA3_RADJ); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, !tmp, + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + rtca3_byte_update_bits(priv, RTCA3_RCR2, RTCA3_RCR2_ADJP, adjp); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + ((tmp & RTCA3_RCR2_ADJP) == adjp), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + } + + writeb(radj, priv->base + RTCA3_RADJ); + return readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, (tmp == radj), + 10, RTCA3_DEFAULT_TIMEOUT_US); +} + +static const struct rtc_class_ops rtca3_ops = { + .read_time = rtca3_read_time, + .set_time = rtca3_set_time, + .read_alarm = rtca3_read_alarm, + .set_alarm = rtca3_set_alarm, + .alarm_irq_enable = rtca3_alarm_irq_enable, + .set_offset = rtca3_set_offset, + .read_offset = rtca3_read_offset, +}; + +static int rtca3_initial_setup(struct clk *clk, struct rtca3_priv *priv) +{ + unsigned long osc32k_rate; + u8 val, tmp, mask; + u32 sleep_us; + int ret; + + osc32k_rate = clk_get_rate(clk); + if (!osc32k_rate) + return -EINVAL; + + sleep_us = DIV_ROUND_UP_ULL(1000000ULL, osc32k_rate) * 6; + + priv->ppb.ten_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 10)); + priv->ppb.sixty_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 60)); + + /* + * According to HW manual (section 22.4.2. Clock and count mode setting procedure) + * we need to wait at least 6 cycles of the 32KHz clock after clock was enabled. + */ + usleep_range(sleep_us, sleep_us + 10); + + /* Disable all interrupts. */ + mask = RTCA3_RCR1_AIE | RTCA3_RCR1_CIE | RTCA3_RCR1_PIE; + ret = rtca3_alarm_irq_set_helper(priv, mask, 0); + if (ret) + return ret; + + mask = RTCA3_RCR2_START | RTCA3_RCR2_HR24; + val = readb(priv->base + RTCA3_RCR2); + /* Nothing to do if already started in 24 hours and calendar count mode. */ + if ((val & mask) == mask) + return 0; + + /* Reconfigure the RTC in 24 hours and calendar count mode. */ + mask = RTCA3_RCR2_START | RTCA3_RCR2_CNTMD; + writeb(0, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* + * Set 24 hours mode. According to HW manual (section 22.3.19. RTC Control + * Register 2) this needs to be done separate from stop operation. + */ + mask = RTCA3_RCR2_HR24; + val = RTCA3_RCR2_HR24; + writeb(val, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, (tmp & mask), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* Execute reset. */ + mask = RTCA3_RCR2_RESET; + writeb(val | RTCA3_RCR2_RESET, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask), + 10, RTCA3_RESET_TIMEOUT_US); + if (ret) + return ret; + + /* + * According to HW manual (section 22.6.3. Notes on writing to and reading + * from registers) after reset we need to wait 6 clock cycles before + * writing to RTC registers. + */ + usleep_range(sleep_us, sleep_us + 10); + + /* Set no adjustment. */ + writeb(0, priv->base + RTCA3_RADJ); + ret = readb_poll_timeout(priv->base + RTCA3_RADJ, tmp, !tmp, 10, + RTCA3_DEFAULT_TIMEOUT_US); + + /* Start the RTC and enable automatic time error adjustment. */ + mask = RTCA3_RCR2_START | RTCA3_RCR2_AADJE; + val |= RTCA3_RCR2_START | RTCA3_RCR2_AADJE; + writeb(val, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, ((tmp & mask) == mask), + 10, RTCA3_START_TIMEOUT_US); + if (ret) + return ret; + + /* + * According to HW manual (section 22.6.4. Notes on writing to and reading + * from registers) we need to wait 1/128 seconds while the clock is operating + * (RCR2.START bit = 1) to be able to read the counters after a return from + * reset. + */ + usleep_range(8000, 9000); + + /* Set period interrupt to 1/64 seconds. It is necessary for alarm setup. */ + val = FIELD_PREP(RTCA3_RCR1_PES, RTCA3_RCR1_PES_1_64_SEC); + rtca3_byte_update_bits(priv, RTCA3_RCR1, RTCA3_RCR1_PES, val); + return readb_poll_timeout(priv->base + RTCA3_RCR1, tmp, ((tmp & RTCA3_RCR1_PES) == val), + 10, RTCA3_DEFAULT_TIMEOUT_US); +} + +static int rtca3_request_irqs(struct platform_device *pdev, struct rtca3_priv *priv) +{ + struct device *dev = &pdev->dev; + int ret, irq; + + irq = platform_get_irq_byname(pdev, "alarm"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get alarm IRQ!\n"); + + ret = devm_request_irq(dev, irq, rtca3_alarm_handler, 0, "rtca3-alarm", priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to request alarm IRQ!\n"); + priv->wakeup_irq = irq; + + irq = platform_get_irq_byname(pdev, "period"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get period IRQ!\n"); + + ret = devm_request_irq(dev, irq, rtca3_periodic_handler, 0, "rtca3-period", priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to request period IRQ!\n"); + + /* + * Driver doesn't implement carry handler. Just get the IRQ here + * for backward compatibility, in case carry support will be added later. + */ + irq = platform_get_irq_byname(pdev, "carry"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get carry IRQ!\n"); + + return 0; +} + +static void rtca3_action(void *data) +{ + struct device *dev = data; + struct rtca3_priv *priv = dev_get_drvdata(dev); + int ret; + + ret = reset_control_assert(priv->rstc); + if (ret) + dev_err(dev, "Failed to de-assert reset!"); + + ret = pm_runtime_put_sync(dev); + if (ret < 0) + dev_err(dev, "Failed to runtime suspend!"); +} + +static int rtca3_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rtca3_priv *priv; + struct clk *clk; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; + + priv->rstc = devm_reset_control_get_shared(dev, NULL); + if (IS_ERR(priv->rstc)) + return PTR_ERR(priv->rstc); + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + ret = reset_control_deassert(priv->rstc); + if (ret) { + pm_runtime_put_sync(dev); + return ret; + } + + dev_set_drvdata(dev, priv); + ret = devm_add_action_or_reset(dev, rtca3_action, dev); + if (ret) + return ret; + + /* + * This must be an always-on clock to keep the RTC running even after + * driver is unbinded. + */ + clk = devm_clk_get_enabled(dev, "counter"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + spin_lock_init(&priv->lock); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); + init_completion(&priv->set_alarm_completion); + + ret = rtca3_initial_setup(clk, priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to setup the RTC!\n"); + + ret = rtca3_request_irqs(pdev, priv); + if (ret) + return ret; + + device_init_wakeup(&pdev->dev, 1); + + priv->rtc_dev = devm_rtc_allocate_device(&pdev->dev); + if (IS_ERR(priv->rtc_dev)) + return PTR_ERR(priv->rtc_dev); + + priv->rtc_dev->ops = &rtca3_ops; + priv->rtc_dev->max_user_freq = 256; + priv->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000; + priv->rtc_dev->range_max = RTC_TIMESTAMP_END_2099; + + return devm_rtc_register_device(priv->rtc_dev); +} + +static int rtca3_remove(struct platform_device *pdev) +{ + struct rtca3_priv *priv = platform_get_drvdata(pdev); + + guard(spinlock_irqsave)(&priv->lock); + + /* + * Disable alarm, periodic interrupts. The RTC device cannot + * power up the system. + */ + rtca3_alarm_irq_set_helper(priv, RTCA3_RCR1_AIE | RTCA3_RCR1_PIE, 0); + + return 0; +} + +static int rtca3_suspend(struct device *dev) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + + if (!device_may_wakeup(dev)) + return 0; + + /* Alarm setup in progress. */ + if (atomic_read(&priv->alrm_sstep) != RTCA3_ALRM_SSTEP_DONE) + return -EBUSY; + + enable_irq_wake(priv->wakeup_irq); + + return 0; +} + +static int rtca3_clean_alarm(struct rtca3_priv *priv) +{ + struct rtc_device *rtc_dev = priv->rtc_dev; + time64_t alarm_time, now; + struct rtc_wkalrm alarm; + struct rtc_time tm; + u8 pending; + int ret; + + ret = rtc_read_alarm(rtc_dev, &alarm); + if (ret) + return ret; + + if (!alarm.enabled) + return 0; + + ret = rtc_read_time(rtc_dev, &tm); + if (ret) + return ret; + + alarm_time = rtc_tm_to_time64(&alarm.time); + now = rtc_tm_to_time64(&tm); + if (alarm_time >= now) + return 0; + + /* + * Heuristically, it has been determined that when returning from deep + * sleep state the RTCA3_RSR.AF is zero even though the alarm expired. + * Call again the rtc_update_irq() if alarm helper detects this. + */ + + guard(spinlock_irqsave)(&priv->lock); + + pending = rtca3_alarm_handler_helper(priv); + if (!pending) + rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF); + + return 0; +} + +static int rtca3_resume(struct device *dev) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + + if (!device_may_wakeup(dev)) + return 0; + + disable_irq_wake(priv->wakeup_irq); + + /* + * According to the HW manual (section 22.6.4 Notes on writing to + * and reading from registers) we need to wait 1/128 seconds while + * RCR2.START = 1 to be able to read the counters after a return from low + * power consumption state. + */ + mdelay(8); + + /* + * The alarm cannot wake the system from deep sleep states. In case + * we return from deep sleep states and the alarm expired we need + * to disable it to avoid failures when setting another alarm. + */ + return rtca3_clean_alarm(priv); +} + +static DEFINE_SIMPLE_DEV_PM_OPS(rtca3_pm_ops, rtca3_suspend, rtca3_resume); + +static const struct of_device_id rtca3_of_match[] = { + { .compatible = "renesas,rz-rtca3", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rtca3_of_match); + +static struct platform_driver rtca3_platform_driver = { + .driver = { + .name = "rtc-rtca3", + .pm = pm_ptr(&rtca3_pm_ops), + .of_match_table = rtca3_of_match, + }, + .probe = rtca3_probe, + .remove = rtca3_remove, +}; +module_platform_driver(rtca3_platform_driver); + +MODULE_DESCRIPTION("Renesas RTCA-3 RTC driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); From patchwork Wed Jan 22 11:51:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947181 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4563BC0218C for ; Wed, 22 Jan 2025 11:51:40 +0000 (UTC) Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) by mx.groups.io with SMTP id smtpd.web10.41875.1737546695784171279 for ; Wed, 22 Jan 2025 03:51:36 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=j6dMI5PZ; spf=pass (domain: tuxon.dev, ip: 209.85.128.51, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-43624b2d453so74268275e9.2 for ; Wed, 22 Jan 2025 03:51:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737546694; x=1738151494; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9zy5Ld7NGydwRu6FAuloMv9y+mc+qqkUcwb3dRcSgM4=; b=j6dMI5PZCTlUhqglFX9R6gmMJ22O0Jd8mVCKWrHaAYPMiJjmNu7q5iMRc5lv5yw9YX FflP1U+ZvCL7U1iE1gTXuOc9C2eamC48c/Us8JhOJ7a5v0K+9YnnybO0vEJaFCJdUmbz 1mXE0JRHdJMb5gJteRROrCRg9PNfatFHEvikqSsueZt83e/msIxquOJ7OtCXNtkVyMha d/0zA8OKta0nSwhnc19fB8wOgmBmqTdKLnzq3xuizsQ+Cg5ucTupXNqx1yXhtcS8RUm4 dODzZxmn4+oLZfImUhjX/rf7ifPec8U3uVpQDTz8iiLuAGcNEtANEwGKn21mv0oIJmA1 JfWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737546694; x=1738151494; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9zy5Ld7NGydwRu6FAuloMv9y+mc+qqkUcwb3dRcSgM4=; b=F24sPSsNeCZTLffWT60jRqF/cVpD6vYS1RXRwS4C93GYsh/cke96w9mU5Wec/xp3u3 OgZ8eY10eD2rhY3NqfWZFgVXaYzRaSO7bWtBr9UwepqcYFdvrmNCgTlJUIBUG3olWomt VIcHcScRR48b/83CKtmz9rLDrZyi3EPPzwk8jpVPlfGSQv7j8cHvYInDAKUlJ04xOFUH +NpS25DbCQ6TwV5ntHSwXvswVtYCvkHKbE8YfxtaqNFYENGNbTP+Caj412xtSJMdLgsa uRlqsEAF43s3Aei7En2kDRzaI0FV31+e+qzEqS8dUxkLx2lrvlPMKJMai+1TCI6CON4w wclg== X-Forwarded-Encrypted: i=1; AJvYcCVc8WT26GETBNo7/tQsaKNZ8hOSUZl5Rg/QanRm+2THKff+8jiDVNR6Lp7uUa6NgDehGpg6tjFv@lists.cip-project.org X-Gm-Message-State: AOJu0Yx3lDWHyLRFuC80Y1XF3lia8u8kYNq5cgICoRBHNceFEpvivC/N /+cxm/fhqlYaZ7WP6pSZ5vqDolh+4PAUN1Z/XHXlbFO4EEtT6GbolW1P3z1VmyY= X-Gm-Gg: ASbGnctmOIBsVIQEwL28/KwX3fXrdoSj8AXcxha09XzvqGXDA/51PH/Uq49Q5sFtTEH LmsMAKtR/JfiKs5R/M3vQYnUmH5XH+mi1N4oXUf8hzg1Hcnn8ZnWpaua3L3YPx5eyI6TUAgP0xO kzzJuXflOQzozKL3++HBitXz84UMpar8zMtSo/NqU28y3+k9jAuY6gt+HMEF2p7/2B4l6Ens5FM /p4deDfUL8ZDmv3ykQMQQV3cTCsFY6it4DdwBv46BgEso4GkL+45lCR8EAcjJCDdfWWISRAJM3/ Eh4b4IMr+62V0Bh1tAv4fRjIyyvss8W21A== X-Google-Smtp-Source: AGHT+IEIVad2LLZxOF/EZpp7ogaRu0TSKk1siGYUxappoq8TPl6+Vj3pcWt8oC3NnhVRc8IZRRqUDg== X-Received: by 2002:a05:600c:4253:b0:436:18d0:aa6e with SMTP id 5b1f17b1804b1-43894744f5amr212454725e9.5.1737546694179; Wed, 22 Jan 2025 03:51:34 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b31aea72sm21474765e9.21.2025.01.22.03.51.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:51:33 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip 09/14] rtc: renesas-rtca3: Fix compilation error on RISC-V Date: Wed, 22 Jan 2025 13:51:14 +0200 Message-ID: <20250122115120.2885015-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:51:40 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17572 From: Claudiu Beznea commit 8f315a5c7376b2bc324d62a8400184da77f25e28 upstream. Fix the following compilation errors when building the RTCA3 for RISCV: ../drivers/rtc/rtc-renesas-rtca3.c:270:23: error: call to undeclared function 'FIELD_GET'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 270 | tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECCNT_SEC, sec)); | ^ ../drivers/rtc/rtc-renesas-rtca3.c:369:23: error: call to undeclared function 'FIELD_GET'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 369 | tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECAR_SEC, sec)); | ^ ../drivers/rtc/rtc-renesas-rtca3.c:476:11: error: call to undeclared function 'FIELD_GET'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 476 | cycles = FIELD_GET(RTCA3_RADJ_ADJ, radj); | ^ ../drivers/rtc/rtc-renesas-rtca3.c:523:9: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 523 | radj = FIELD_PREP(RTCA3_RADJ_ADJ, abs(cycles)); | ^ ../drivers/rtc/rtc-renesas-rtca3.c:658:8: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 658 | val = FIELD_PREP(RTCA3_RCR1_PES, RTCA3_RCR1_PES_1_64_SEC); | ^ Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20241101095720.2247815-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Alexandre Belloni Signed-off-by: Claudiu Beznea --- drivers/rtc/rtc-renesas-rtca3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/rtc/rtc-renesas-rtca3.c b/drivers/rtc/rtc-renesas-rtca3.c index 7683df87eafa..4bc28680f650 100644 --- a/drivers/rtc/rtc-renesas-rtca3.c +++ b/drivers/rtc/rtc-renesas-rtca3.c @@ -5,6 +5,7 @@ * Copyright (C) 2024 Renesas Electronics Corp. */ #include +#include #include #include #include From patchwork Wed Jan 22 11:51:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947183 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53EFEC02182 for ; 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([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b31aea72sm21474765e9.21.2025.01.22.03.51.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:51:34 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip 10/14] arm64: dts: renesas: r9a08g045: Add VBATTB node Date: Wed, 22 Jan 2025 13:51:15 +0200 Message-ID: <20250122115120.2885015-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:51:40 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17573 From: Claudiu Beznea commit 23c44956bce5aa79c060fc3e5d51843735e6eda6 upstream. Add the DT node for the VBATTB IP along with DT bindings for the clock it provides. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-6-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [claudiu.beznea: the backported patch has references for i2c nodes; the i2c nodes are not available in v6.1 cip, thus fixed conflict by dropping the i2c nodes] Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index f5f3f4f4c8d6..7bc8969a7b5a 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -72,6 +72,18 @@ scif0: serial@1004b800 { status = "disabled"; }; + vbattb: clock-controller@1005c000 { + compatible = "renesas,r9a08g045-vbattb"; + reg = <0 0x1005c000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; + clock-names = "bclk", "rtx"; + #clock-cells = <1>; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + status = "disabled"; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a08g045-cpg"; reg = <0 0x11010000 0 0x10000>; @@ -296,4 +308,11 @@ timer { <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; + + vbattb_xtal: vbattb-xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; }; From patchwork Wed Jan 22 11:51:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947184 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59406C0218E for ; Wed, 22 Jan 2025 11:51:40 +0000 (UTC) Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) by mx.groups.io with SMTP id smtpd.web11.41689.1737546698441085452 for ; Wed, 22 Jan 2025 03:51:38 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=CHgu8T+B; spf=pass (domain: tuxon.dev, ip: 209.85.128.47, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-4361815b96cso47380915e9.1 for ; Wed, 22 Jan 2025 03:51:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737546697; x=1738151497; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=avEm0xWoaPOuBqma5bKPsWNEysSf4Ic0Xdn9jpjXkLw=; b=CHgu8T+B+e+NfW/fIXcaFQDJJIcwXMsgOgkMVVxWx4KZgQEVG6g9rkaGv26nLURBu5 dOm5RnrGCIgtwWU0cFowyOOEycRvtbQyPYFhPFMNVIuLDtzSwWQyrXRxUJbzKRfflgej FB657qSaLbBdLZWcMRT9UUn+RONVGFN8gxz8HRKsybsK0OSaLzYSToo0UeFtUPvnua9u 14IeiVCWHFyvfGlLylr8EoYgfCUmpQuHWtCSSf2X+h+2AiiZr2ajNAOYguZGiBeSM2vJ IC9uVwCVK1Xje4mOaNgqPG94TF1mhwLASes8n7uVEqZVIUNT3n+G8u49pNZDN66CezTk Gf4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737546697; x=1738151497; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=avEm0xWoaPOuBqma5bKPsWNEysSf4Ic0Xdn9jpjXkLw=; b=dL1FXmUzcXHnMJrHtTzRSxFjUABtysz/yuOeiPWoDuttdFXQej5/jMlC68Nag4K18K gVOHk+yTtTXeDwLylcK5CgwiplbKlPzZiUI08QhBPrw7pmA6cewJU507z8mQ14Enet0r 7H0Foi4EzKJsml5hvs1qHwiKOoXJ5vMM1CtPIFYxP8+/2ojZqMMxDg0BkRjWSf9WplcS ghFlUYqQeVu7tLtCFK1IwBmyQ14HTk6smXM9HQoV9vGrZDIk9G0KdTRX5OWw1IFMA5uV cUeTk4AvYsE7wv4x7+EXmX0/CzFFZFTNMTpM4Poboq9P27+3ehWIDuLKxAqQI3/o3Jvk 4ODg== X-Forwarded-Encrypted: i=1; AJvYcCWMUJjRsI7eILCF/xY4q0VJWFR/QphnAxIvw8fIfdMCc0SVoFNDBvZjqDoUn2GMcxGYa6AfpeUF@lists.cip-project.org X-Gm-Message-State: AOJu0YxGLIet2fdkMZ8xKvB5mMvL55IYXG9Y8g8biuxA4VgXM5iXWpRS RS01+GOepm2b1SnqChzOcfG7GYiTafPKTI/lExhRylvJKAganGT4uOfHXFIhEuE8thi4eyWHx42 G X-Gm-Gg: ASbGnct/Lfac+2Ma4mxQ65H+Z2pW18IRO6yMd+YOniARYSt9Qcyo9fES/B0kPbK4KFx JMan7OhsLVj1yKtvG6gj+JGtPflXSVu8x/JlHWBWln5yc6osbrjxaoSULMlWOLE0i37SfcEqmRY a+6BiMTSGTZ7WH2gMUHZPz8TDzhwJIonbmVGFp/HgUbECWdXNmzkvB3a2AR2eyeVAzt3Waa+UIK 7hV6yYWWyl5oexzF5UDh+PW40y9c5lfFrMXkqjju7+iaZRk4OZ8eH8A11U6MrjlteprymvVIvch mJfVOZcZPaECyUaEkylygcpv3ojz9Jgv9Q== X-Google-Smtp-Source: AGHT+IH8y6dZSl17jTQX2xsMeGRSQ+uOlTlnL/Hz3EDr+iLg8eLPThk/xjdl73KTTjpUFcz+jew2bg== X-Received: by 2002:a05:600c:63d5:b0:438:a46b:1a6 with SMTP id 5b1f17b1804b1-438a46b0388mr136574905e9.18.1737546696882; Wed, 22 Jan 2025 03:51:36 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b31aea72sm21474765e9.21.2025.01.22.03.51.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:51:36 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip 11/14] arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB Date: Wed, 22 Jan 2025 13:51:16 +0200 Message-ID: <20250122115120.2885015-12-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:51:40 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17574 From: Claudiu Beznea commit ac948eb8ead1265ff034955bdbbb081744f1e7ed upstream. Enable the VBATTB controller. It provides the clock for RTC. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-8-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index acac4666ae59..67178d8c4108 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2023 Renesas Electronics Corp. */ +#include #include #include @@ -341,6 +342,17 @@ mux { }; }; +&vbattb { + assigned-clocks = <&vbattb VBATTB_MUX>; + assigned-clock-parents = <&vbattb VBATTB_XC>; + quartz-load-femtofarads = <12500>; + status = "okay"; +}; + +&vbattb_xtal { + clock-frequency = <32768>; +}; + &wdt0 { timeout-sec = <60>; status = "okay"; From patchwork Wed Jan 22 11:51:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947189 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 636F7C02181 for ; Wed, 22 Jan 2025 11:51:50 +0000 (UTC) Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) by mx.groups.io with SMTP id smtpd.web11.41691.1737546702018119164 for ; Wed, 22 Jan 2025 03:51:42 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=ixq5ugGd; spf=pass (domain: tuxon.dev, ip: 209.85.128.45, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-436ce2ab251so46968635e9.1 for ; Wed, 22 Jan 2025 03:51:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737546700; x=1738151500; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QT9gIUiudDAAdT7+/KwLCRVApT8O0rjggfgBvSy6a4o=; b=ixq5ugGdZ2XjLklNZonLEcYE0U563YnuFrg0dxKFrGKogxB9XQD2ZhhyhgdGSGWQdP CpotU/xvtKHQg6GujLCE7/ZjUmkmIcJlix1uRSOeqD0ClHJCjIfCQT7lmU5UjqeRRSJV M5QAMY7KTFaVmu+1TldIvuGfz+QptkxRjIE8D7g1iMAj6uatlsspF8cRvoPbheM5zsHS 2p4vZa2F1DCrlj/wHN8+T9a9kBtvoRDFbamw0KvwKpi6Y+UEI6/E9bsIqKx3Axcavh5h w3Dwvtu0FiuyZWPORKQ0Jt1BZYfeh8hhOBc3GclP6DtlVVM+kKH3QmAN5a/n6b9UzSU1 e5mQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737546700; x=1738151500; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QT9gIUiudDAAdT7+/KwLCRVApT8O0rjggfgBvSy6a4o=; b=on+K/IaknGtlPhiGCY8eLZ4wxpeIDJiDalaCbK66r0gnEYD6W+hsF9VModd/gyRTg0 2PmKa+ecKUA11yoS2aFNUVhDtkfsZumQniRY2LLayHTJ3Ty6EgCBdFYbP3Z0LIX8P8N7 j42T1YCh8aKbqsM4DH20Co/XunGHLkYZnA5OBYvqFoNcU6e1H+nxew0LvaRNJ6+wQR+D 7fMQ5ixa2MGkWPgVH/ryaVKdKIE97TNB4Xcv1w8VSVr54bl5/GqvAgIugzlm4TqLmbGV 7hflXTMgRkM8kO6MPx1Vc4+5GZbygO2r1fYzrYzwsnngNWUQA0C8qI73GBpx+VPpz9Tb XLBA== X-Forwarded-Encrypted: i=1; AJvYcCUZkgjtAZRDfyul0I7YmNzUxj8qeVANtI0bREitRgMRliXacfGfP9VJFfk1Dz+IXTa7kGl98980@lists.cip-project.org X-Gm-Message-State: AOJu0Yw4lo/PvPkKt0Yv44XMWhJa4VDAxmVU3Bq7Qr5DTzAcruhTcV6u KAs//G2N0VLmwDXy8F98IEhcnVR2Q1CY8AoStCznYNaprCefEV3Df3fn51AIZvg= X-Gm-Gg: ASbGnctJMdGQasSjavIX2U73+WbhdDg+/ZJfL/+yOk9YXHmZ4zAILgECL7bQwvAjpel zfgT7jKwUs25zoa3F1ss2Ds3hYcrLwPd9mLh3PmsRID9HYDDf4Ey9aHRGeQpOCSlkOrjCuhOI1p PhBTrWspWhu73MKAlIv/eKKFGVbZpMrO3Gfonf//TxOv+EB386HLYz9zwUMx87dJRfWkO5Uaww2 /zLmykr0Cw6rXFoWCoauVE0EHTQHcE7DQuDa10XNctY8Rt5B7b0H5xm0ffqtn5iZjJlfEJ2N7bi quXfPGUJdRlGVoXRLV8MnVU= X-Google-Smtp-Source: AGHT+IEAfS4u+OqHRQELjnzyT9xR8YhgdEa4gQqmKWnMgOT46fGkaluiFha/v+bdZtUQMKUwo5C+lA== X-Received: by 2002:a05:600c:3b94:b0:434:e2ea:fc94 with SMTP id 5b1f17b1804b1-438913cb620mr227322105e9.11.1737546700502; Wed, 22 Jan 2025 03:51:40 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b31aea72sm21474765e9.21.2025.01.22.03.51.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:51:37 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip 12/14] arm64: dts: renesas: r9a08g045: Add RTC node Date: Wed, 22 Jan 2025 13:51:17 +0200 Message-ID: <20250122115120.2885015-13-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:51:50 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17575 From: Claudiu Beznea commit 2d768aee9f5294d2023e824c0906e2e7d1414629 upstream. Add the DT node for the RTC IP available on the Renesas RZ/G3S SoC. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-7-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 7bc8969a7b5a..3401c1200a1c 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -7,6 +7,7 @@ #include #include +#include / { compatible = "renesas,r9a08g045"; @@ -72,6 +73,20 @@ scif0: serial@1004b800 { status = "disabled"; }; + rtc: rtc@1004ec00 { + compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; + reg = <0 0x1004ec00 0 0x400>; + interrupts = , + , + ; + interrupt-names = "alarm", "period", "carry"; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb VBATTB_VBATTCLK>; + clock-names = "bus", "counter"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + status = "disabled"; + }; + vbattb: clock-controller@1005c000 { compatible = "renesas,r9a08g045-vbattb"; reg = <0 0x1005c000 0 0x1000>; From patchwork Wed Jan 22 11:51:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947190 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63D61C02182 for ; Wed, 22 Jan 2025 11:51:50 +0000 (UTC) Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.groups.io with SMTP id smtpd.web10.41877.1737546703274535699 for ; Wed, 22 Jan 2025 03:51:43 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=Mx2GKKLd; spf=pass (domain: tuxon.dev, ip: 209.85.128.49, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-43625c4a50dso47041005e9.0 for ; Wed, 22 Jan 2025 03:51:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737546702; x=1738151502; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rZ/lXKoSkUmuSxtM2ry8mqYHW2bCm5mIiSIX1gifECs=; b=Mx2GKKLd4V7V2Hzg33KbUVNFhgK4hSU8WlrV3OFKuI8fb4O9H8TDUBJIAMcoCAbp+e 9KmJtdmqyAajDLriHcO8n6+k5vVDJ+dvlLEDdgrIvpXWHBdE/uLGn7oQkiuQSjoaN0vU PIpbYJHffY9iKZCcVrymW0wLZkR1nRpLHLA0Bva+llJ1oqhn/PyYRqr7+12PdPPv8T5e cUOMOdy4A8bgYCj4/tv7YMtUPP9rE2lggJXkrZqhYdtiXOXHjXF/5SYNclj4IHizFdee 1QMAfIughF/1VdYFccH/SBO9rVeTD3AIsuSAP5AYLOTmJwT21Rp7EEGqQRBgkjyzeAXN Gucg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737546702; x=1738151502; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rZ/lXKoSkUmuSxtM2ry8mqYHW2bCm5mIiSIX1gifECs=; b=pvqsfmwDCN9CMp0i3pfhIuqJRQxxYw2Num6VQGw9+dtKq7HmBGjgc5edKb055onfKD GpxRajoVk1yBRJyxFgZ9kB+zJbdiP6vXjIedwUaO1/WOnGOw8Ur5ZUc209ELarAu7hGA 3JZILL+AxpI3xKLjkELS4A/xPRdXfqWXxVISr/Csqlj/g2AOVf5RWk9zHsdHRx+PhPXO XkwGN6YcaemJyGp5qh6GcIhVt9xnd9k8xtVmT7xh2T2+ps342DK0UuISayv5pZMuaeKm gUTS/O3VYvByfNi5+tsvSoAg//q+RtFh10KbdBVOIfi+8r4VC5fQKcw5MVLX2yYCHhvG USgQ== X-Forwarded-Encrypted: i=1; AJvYcCUOnDaHHwbcaANJn2gsFKMiBFCH/derz1t3JVpKnYmAWft1tpWRi0dBQ3kvpR823Fx6Y/fb2Zkz@lists.cip-project.org X-Gm-Message-State: AOJu0YyRFBaZFV7sjQZLkiX4aLqFpUveGCIxDQ2y9TtMOuqDPmmkQMfl lkCSZI6JRgmEzkzrxEqU0bYwaNksG+L6DDnYkKpw9L2lU8H/5P8W7h+xjZ7Ll6U= X-Gm-Gg: ASbGncuE4B+X6Kcjw+8hf2WxPHjXSyP+iuB1c5+zJ73rnGoiJ0lzF0tqDkRvoPiwLjH Lqu+8ICEXgqf+8u73rP4YOST+ulBUBRdg82+p6+Qwu/x4yVuTdH1gbA3qJ1IyfAqMsv6TGPuPVg SRGta6gc8zTcLPjm8IulC4f2yXjDZ64ly4LDeA9JBQWiuLEox/ehy0DKTMmPWCvmqTlB2af/txd wvPTazhrrURZ58Ueopt93CgUQTV5tY99PiR39HiQYF+CEsPYePUkAZMPlX/d9SqT+38lHwKeksD j3YKperhv0yNFAxmE9qZXmU= X-Google-Smtp-Source: AGHT+IG3GsErIsa5IWdS5f1dEWJKtwesHaKt6Z4qLG9rKLhY4IOjqECdq74LckbMtM3VNK+pkq/rcQ== X-Received: by 2002:a05:600c:138f:b0:436:ed50:4f8a with SMTP id 5b1f17b1804b1-438913caeb9mr224241905e9.10.1737546701712; Wed, 22 Jan 2025 03:51:41 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b31aea72sm21474765e9.21.2025.01.22.03.51.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:51:41 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip 13/14] arm64: dts: renesas: rzg3s-smarc-som: Enable RTC Date: Wed, 22 Jan 2025 13:51:18 +0200 Message-ID: <20250122115120.2885015-14-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:51:50 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17576 From: Claudiu Beznea commit 0cd647cd53db0315361e41056e10739a5ee1e668 upstream. Enable RTC. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-9-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 67178d8c4108..b07d9251d182 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -342,6 +342,10 @@ mux { }; }; +&rtc { + status = "okay"; +}; + &vbattb { assigned-clocks = <&vbattb VBATTB_MUX>; assigned-clock-parents = <&vbattb VBATTB_XC>; From patchwork Wed Jan 22 11:51:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947188 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67E99C0218D for ; Wed, 22 Jan 2025 11:51:50 +0000 (UTC) Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) by mx.groups.io with SMTP id smtpd.web10.41878.1737546704427151869 for ; Wed, 22 Jan 2025 03:51:44 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=kUc1i9P6; spf=pass (domain: tuxon.dev, ip: 209.85.128.47, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-43622267b2eso67278965e9.0 for ; Wed, 22 Jan 2025 03:51:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737546703; x=1738151503; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pdoaaBkruq8UaBR6aG2nxEBiJ4gLHmsErL0xCb1P+ys=; b=kUc1i9P6dc+zF2l/Y2JI+onnoQJeAS5xbXC4nD0IfqpN8pqFiTjs3sz0qfqi9IQWMi mA48x/Y4JvpRNsI27fNnySgD2YqOJd1EnsSeLZvfhDVEqBhZXk9oHZV8uL6WAbJkSXWY fHvitjySBDWOwLFQ+AS7cTLWsGRtVZohVSc0aD9m6wXktTgAeWdfRdsIvtihG9uDOjQQ CChKVIP8D6jXp4D5uQUCZKuTdNmV9k8kxtiHG9hiOb37We+dMpAN3Oh5dJxJW7cjiAwV lOr0q+UIe6pJWqI6J8bBE3gv/7qtSuN3hyYd6sgYp5Kn7OsemORVlGuNNVKqnFH7ERTF s9Rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737546703; x=1738151503; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pdoaaBkruq8UaBR6aG2nxEBiJ4gLHmsErL0xCb1P+ys=; b=aMIHwNei1zeOweEpjFDyIoNLI9vQH2+CysSq8jKFTmgiMq+F8sAh9O4XzaG82RlqrW ztbWGwSomK1AqiNam246Zsnu+NDHJUuNUmr3vYvNmUWbDp18mvK5inuJosGQA0TJAUZv PjU9vyox654Pnv1/dghkFZ9tICCnBdfofrCLpwbbQ8385aq/DjaNq8M5GNvObpV6Otwm iLIi29meBAthOsISUx8la8UK1yT6fmVvfAPQ0TkXNEf8GGD+6Ls8mnVVm6lpUnwSu3ev KdXVipkpNFE8yXJf2Av9UT5b0dkDvffJoE1xajoAE5065/j2rgdo7JSt3CK6MrjE19ar S1iQ== X-Forwarded-Encrypted: i=1; AJvYcCV+svp4rIeT3qTbc0brqHakje7kAOtxIsAo4hmzYjX2V66Hzj1sheO8cRBYD8sg8lysxSDAw37Y@lists.cip-project.org X-Gm-Message-State: AOJu0YziKy6aVJwNgH3VqYw1xHAjEAE1YWT2S26sZBBR81bAK2+bPF3x KpTNEa29GRGejqw2hKMuDIqAtRTmne3Vrq3IL5gIH3wwNRCwp00NxUBNNGc4cKo= X-Gm-Gg: ASbGnctASOl7mB6DsSi0xiF3oZb6rBE00t7ouLTBpM1u9h/pqoyFm8LZ2AUdlslRf3+ /1Q2NpCkPSJ3dYgL9tHMZ5fv7KZr/9yfvr57CSW1EHzQ4r3stILeTqZi4lJyduXqlhUZuJcAwhq iS/nUHN3m9cgcY0/Z738YsXHmJBYsY//dagpu10tCRAZGZ1bGlYu9+/qqug0pLezEoqkm3pitem 4R2V7wjCthTMC4SCxx2S30nH4orlNiGjjTTAqOWQISP3zrD4v4lfYkCokWAO0uIz2+ZF+B8iDvM ud4RlcBfQLXKXDwi6LeXzVs= X-Google-Smtp-Source: AGHT+IEv0caoBtDaoqnPoQQkId4Sp5hpCHR+ZOUIkJujv/utaVpxgHVwMZkz7uv1moPKXtI6pwkRsw== X-Received: by 2002:a05:600c:6a94:b0:434:f753:600f with SMTP id 5b1f17b1804b1-438914376b1mr179381095e9.19.1737546702869; Wed, 22 Jan 2025 03:51:42 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b31aea72sm21474765e9.21.2025.01.22.03.51.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:51:42 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip 14/14] arm64: defconfig: Enable VBATTB clock and Renesas RTCA-3 Date: Wed, 22 Jan 2025 13:51:19 +0200 Message-ID: <20250122115120.2885015-15-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115120.2885015-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:51:50 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17577 From: Claudiu Beznea commit c520bbb523304ba98de9ffeeb0ef289921434125 upstream. Enable the Renesas VBATTB clock and RTCA-3 RTC drivers. These are available on the Renesas RZ/G3S SoC. VBATTB is the clock provider for the RTC counter. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-10-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [claudiu.beznea: fixed conflict by dropping CONFIG_RTC_DRV_TI_K3=m and CONFIG_TEGRA186_TIMER=y; although drivers for these are avaiable in the v6.1.y cip they were not enabled in the previous arm64 defconfig] Signed-off-by: Claudiu Beznea --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 6f644364b743..a15bfa82fe59 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1016,6 +1016,7 @@ CONFIG_RTC_DRV_SNVS=m CONFIG_RTC_DRV_IMX_SC=m CONFIG_RTC_DRV_MT6397=m CONFIG_RTC_DRV_XGENE=y +CONFIG_RTC_DRV_RENESAS_RTCA3=m CONFIG_DMADEVICES=y CONFIG_DMA_BCM2835=y CONFIG_DMA_SUN6I=m @@ -1104,6 +1105,7 @@ CONFIG_SM_VIDEOCC_8250=y CONFIG_QCOM_HFPLL=y CONFIG_CLK_GFM_LPASS_SM8250=m CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y +CONFIG_CLK_RENESAS_VBATTB=m CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y CONFIG_RENESAS_OSTM=y