From patchwork Wed Jan 22 11:52:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947191 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E260C0218C for ; Wed, 22 Jan 2025 11:52:40 +0000 (UTC) Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) by mx.groups.io with SMTP id smtpd.web11.41710.1737546755301197104 for ; Wed, 22 Jan 2025 03:52:35 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=bHqkMhfW; spf=pass (domain: tuxon.dev, ip: 209.85.128.43, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-4362f61757fso69878635e9.2 for ; Wed, 22 Jan 2025 03:52:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737546754; x=1738151554; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zsxyHYEIFzrPUxfeETGqg0hmG4mEeCV26g2ghkEEU2I=; b=bHqkMhfWH50RloWDXfiqJ6Nd5d9L8MEBxQ3/zzw8l9Mg7OiQz58tCHZ92PfU7qmeNd rvRDSe+x7DfZHQfOr7hDTdwKIGC2thQLmqBSSlW77/ijwByn3dL0E+ww050uYBqBuXQZ uBepaTMStWxu8XU2R4+sddnjIL+UNFQ+KOY9e9m0xDxrPA23p6aHSpV8g5YnRph8moeb ZTl4cKO4fR8tfDpoSI4jtGftJHuCmSmaiduwoOYnAdIgpWBg7xryA2WKF14rVytma1wG D8mux24w6OiI2/fxiXBsrHR+EOn7fjRrOSppZSvNBPCLKSQ92nPqAYa5Fv8QVnfP85wS UJ5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737546754; x=1738151554; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zsxyHYEIFzrPUxfeETGqg0hmG4mEeCV26g2ghkEEU2I=; b=Yb2tnr9glabgl4/pP663Pyjn99M1l8/B5xnl0nXpW80jqqYKDkMdnRFlbvSZVObgZU 0Qa8qhczJlQl7jLbClvFaEeKXuchxBWSlY2q8bssYu7+CbQU33k+380a0dmCVprn8WXP XWJpTA6fmKESG+6Vdp/4TZV3ao4W+vIy1WQR3oqBxMllYdx3YZaHqGkM1bR+ESBbkcb0 miA04urxVUVgQypptVxODm6rvD/uN7mc7D6iPngPL576eX+2F5yb9J2U1qPPiKEOm3ok EpXVu5yTKrmgCXzY1KeFfMCNIaJiZvZPr7YLSwwZN6omB4R4/90fDxUHrgbO498SNHnc Rzjw== X-Forwarded-Encrypted: i=1; AJvYcCWhCJoZeavPRV/WcNr/p3zsWs1HAGPdQDrasLavaCHJWe/7vOKDV+lI+f5+cz60JQGGFV7FMWnp@lists.cip-project.org X-Gm-Message-State: AOJu0YwVOse1YN2K0DCIpY0BOhuDZCHSFf2hUQv2Nl+7aeDs35T2Guta qHBiW9L+sQUieZxy1xhQPHZREgCgQhrS463zDwbatng6+DoT/88iBtg56p9QNdU= X-Gm-Gg: ASbGncts6sn6o7ipp9NkozxFsIzOAXlLlDsy0LtL7WucA5tTB12GbHvlMwy/iBoanJe P9VcBLRrNrMVjABEOjnpi+St9TBvCezCAXmjvbI17pCKSQXEc+7fMxDHzrFIyaVQEPASIkh9X+i yE0g0CekjcbR3uMuQTQjc4KmGjxwOxFp0+Ktmp43bm8ETJNzspf5nSjTqTt/0Au90s7nbkIx1Bl DdtvXTZP3eTuKoKBf+RJN58OxBfiLlMfm9upzigBTFkXhTatOnmsqW4KFC5gOwMMzZsafzqN7yT Nyiks6EIEnsIvwh1v9+C3PJHMyraF6g5yg== X-Google-Smtp-Source: AGHT+IHOdP0rGIh0VFc2nZOMX36Z9YR2CXWoAEV4uR7fj0Zuf4zXGyEDRBs8TQMacmeh63UEyF6YXQ== X-Received: by 2002:a05:600c:b8c:b0:435:330d:de86 with SMTP id 5b1f17b1804b1-438912d2c48mr204988705e9.0.1737546753717; Wed, 22 Jan 2025 03:52:33 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b318990esm22887415e9.7.2025.01.22.03.52.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:52:32 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip 01/16] clk: Add Sunplus SP7021 clock driver Date: Wed, 22 Jan 2025 13:52:15 +0200 Message-ID: <20250122115230.2885344-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:52:40 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17579 From: Qin Jian commit d54c1fd4a51e8fbc7f9da86b0cd338a4f7cd2bb2 upstream. Add clock driver for Sunplus SP7021 SoC. Signed-off-by: Qin Jian Link: https://lore.kernel.org/r/20221219015130.42621-1-qinjian@cqplus1.com Signed-off-by: Stephen Boyd [claudiu.beznea: kept only the code from include/linux/clk-provider.h] Signed-off-by: Claudiu Beznea --- include/linux/clk-provider.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 75cdef73e751..411f50478043 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -571,6 +571,25 @@ struct clk *clk_register_gate(struct device *dev, const char *name, __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \ (flags), (reg), (bit_idx), \ (clk_gate_flags), (lock)) +/** + * devm_clk_hw_register_gate_parent_data - register a gate clock with the + * clock framework + * @dev: device that is registering this clock + * @name: name of this clock + * @parent_data: parent clk data + * @flags: framework-specific flags for this clock + * @reg: register address to control gating of this clock + * @bit_idx: which bit in the register controls gating of this clock + * @clk_gate_flags: gate-specific flags for this clock + * @lock: shared register lock for this clock + */ +#define devm_clk_hw_register_gate_parent_data(dev, name, parent_data, flags, \ + reg, bit_idx, clk_gate_flags, \ + lock) \ + __devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL, \ + (parent_data), (flags), (reg), (bit_idx), \ + (clk_gate_flags), (lock)) + void clk_unregister_gate(struct clk *clk); void clk_hw_unregister_gate(struct clk_hw *hw); int clk_gate_is_enabled(struct clk_hw *hw); From patchwork Wed Jan 22 11:52:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947195 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8437BC0218E for ; Wed, 22 Jan 2025 11:52:40 +0000 (UTC) Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) by mx.groups.io with SMTP id smtpd.web10.41903.1737546756591169013 for ; Wed, 22 Jan 2025 03:52:36 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=LS49xGdy; spf=pass (domain: tuxon.dev, ip: 209.85.128.42, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-437a92d7b96so67090045e9.2 for ; Wed, 22 Jan 2025 03:52:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737546755; x=1738151555; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=czx0n57GKQ7ADNwcZUfpgZU8QtxHfQn25Ov/x51VkGk=; b=LS49xGdyHXKODFaqa30bTzBRF/NQV/LbmmFS+LXOr9eBc7JNcUoZGpVFq1RaEQnhcl +7/LIIklRhNKZf/G99hGYNDVj45WygA8QLSsasi2ZY+xct/kXNb2evJRV0AGIMzRQ62a x7EHWMrhgkMYtzSUjE486BBpg1ME0HDmReATqZ73rEYTuMs5dqufZs//9723pmm3V/uz YH+2/XpXXAizBDmSSqPL/bgyC5i5ORSReqKrb0ebHGPTHhzdiQZNmMMnTczZKdJy+uQ4 K67p6lr6LTz8YjoGlJ6YdoSlcysqPaL0+q/l5cgLbbt2bMsrVTEufBnVBTgQ+DVm7WEw 9OuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737546755; x=1738151555; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=czx0n57GKQ7ADNwcZUfpgZU8QtxHfQn25Ov/x51VkGk=; b=GNjpK500QNtNMdY4jmFILAYOLaxxDP27Is1hK1kP7sozztOgRtm0Bs2bOzOC4wy1c9 MmxHeJ+WX2962VpFwC/nz8vGD7ca3QFb4Ay0GPE2uztsAoMalEoO/A446OhHMlk8zdBe iUNW8yQxCBK8GCwwfoXP0FkkGj29VU4AmKJ3B3X89sik6OJBkPW/1PVxJubd5zm7FMAJ F8MPGi0h+hLsMXjnnhecjAyg4c6N8LBzyBoC6umClmDu5eEIjty3tH2bdmrJCbw2tQBD i7av9j4ig0JdWz3jTG9/emn3Tw0wkYw7VZB6zyZ3w/CgkNCOeQrAinsMwpGIN4POli8C 3KYw== X-Forwarded-Encrypted: i=1; AJvYcCUhBC5egAK+zIB274BCK+6grWHTAC4QXzZLFS8k7v2H8UijxYQ57AhFFYjkudFVi71KGtFxtIU+@lists.cip-project.org X-Gm-Message-State: AOJu0Yz3Tjv6Vb+QMimpDE2B/ClvAUqodDfmPHDtlN76bak/gG3m4LYQ Fnx61SmHJRX2XUN3dbrqa6tzRdQjSWmkD3ZGWBv2x2KQty1y5ZmXF0QBQ2rV3iY= X-Gm-Gg: ASbGncvrlJatlhqiYXnGq0mAgydoI4Q0lmk2uK7659R2OEaXixF0v9sMUSana1mwLVW s/mTcn9ZrBLAueHRhAdFhNO6aBbBwGMaukiD3v/zdcvwfZ7frJ3bVKN9x9WIGGsTkXKH+rUhVIx khn8uJR8BT1bbuVjYuCV3ua15SBt/XGR92XhF+h9vDSt3VeWzptiQCPuptoW9feAbCgHPDD3hu1 kpkA4y+SIALbIlaovvObbZ63KQPF5YGaO+uFEtx6UUTzFKRBq8AATLcgonFL073bQhUJM+FbFtW gIvoRpccL9jgydf+e1oMdu8= X-Google-Smtp-Source: AGHT+IH98yYJmWs4NBfMW2vpzQs8bM4IvpdituCn1mljCMNkL0mRXr8dw4fUK7mQYmHowc8O27jd3w== X-Received: by 2002:a05:600c:6a94:b0:434:f753:600f with SMTP id 5b1f17b1804b1-438914376b1mr179408285e9.19.1737546754952; Wed, 22 Jan 2025 03:52:34 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b318990esm22887415e9.7.2025.01.22.03.52.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:52:34 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip 02/16] clk: fixed-factor: add fwname-based constructor functions Date: Wed, 22 Jan 2025 13:52:16 +0200 Message-ID: <20250122115230.2885344-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:52:40 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17580 From: Théo Lebrun commit ae156a3633d377d43990eb539f8a007c0c2bf769 upstream. Add four functions to register clk_hw based on the fw_name field in clk_parent_data, ie the value in the DT property `clock-names`. There are variants for devm or not and passing an accuracy or not passing one: - clk_hw_register_fixed_factor_fwname - clk_hw_register_fixed_factor_with_accuracy_fwname - devm_clk_hw_register_fixed_factor_fwname - devm_clk_hw_register_fixed_factor_with_accuracy_fwname The `struct clk_parent_data` init is extracted from __clk_hw_register_fixed_factor to each calling function. It is required to allow each function to pass whatever field they want, not only index. Signed-off-by: Théo Lebrun Link: https://lore.kernel.org/r/20240221-mbly-clk-v7-2-31d4ce3630c3@bootlin.com Signed-off-by: Stephen Boyd [claudiu.beznea: dropped the accuracy part] Signed-off-by: Claudiu Beznea --- drivers/clk/clk-fixed-factor.c | 59 ++++++++++++++++++++++++++-------- include/linux/clk-provider.h | 6 ++++ 2 files changed, 51 insertions(+), 14 deletions(-) diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index bf55b9b71c6a..97623e100d44 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -72,13 +72,12 @@ static void devm_clk_hw_register_fixed_factor_release(struct device *dev, void * static struct clk_hw * __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, const char *name, const char *parent_name, - const struct clk_hw *parent_hw, int index, + const struct clk_hw *parent_hw, const struct clk_parent_data *pdata, unsigned long flags, unsigned int mult, unsigned int div, bool devm) { struct clk_fixed_factor *fix; struct clk_init_data init = { }; - struct clk_parent_data pdata = { .index = index }; struct clk_hw *hw; int ret; @@ -107,7 +106,7 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, else if (parent_hw) init.parent_hws = &parent_hw; else - init.parent_data = &pdata; + init.parent_data = pdata; init.num_parents = 1; hw = &fix->hw; @@ -144,7 +143,9 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, const char *name, unsigned int index, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL, index, + const struct clk_parent_data pdata = { .index = index }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL, &pdata, flags, mult, div, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_index); @@ -166,8 +167,10 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev, const char *name, const struct clk_hw *parent_hw, unsigned long flags, unsigned int mult, unsigned int div) { + const struct clk_parent_data pdata = { .index = -1 }; + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw, - -1, flags, mult, div, true); + &pdata, flags, mult, div, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_parent_hw); @@ -175,9 +178,10 @@ struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev, const char *name, const struct clk_hw *parent_hw, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, - parent_hw, -1, flags, mult, div, - false); + const struct clk_parent_data pdata = { .index = -1 }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw, + &pdata, flags, mult, div, false); } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_parent_hw); @@ -185,11 +189,24 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1, - flags, mult, div, false); + const struct clk_parent_data pdata = { .index = -1 }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, + &pdata, flags, mult, div, false); } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor); +struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div) +{ + const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name }; + + return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL, + &pdata, flags, mult, div, false); +} +EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_fwname); + struct clk *clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) @@ -232,16 +249,30 @@ struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1, - flags, mult, div, true); + const struct clk_parent_data pdata = { .index = -1 }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, + &pdata, flags, mult, div, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor); +struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div) +{ + const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name }; + + return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL, + &pdata, flags, mult, div, true); +} +EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_fwname); + #ifdef CONFIG_OF static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node) { struct clk_hw *hw; const char *clk_name = node->name; + const struct clk_parent_data pdata = { .index = 0 }; u32 div, mult; int ret; @@ -259,8 +290,8 @@ static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node) of_property_read_string(node, "clock-output-names", &clk_name); - hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, NULL, 0, - 0, mult, div, false); + hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, NULL, + &pdata, 0, mult, div, false); if (IS_ERR(hw)) { /* * Clear OF_POPULATED flag so that clock registration can be diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 411f50478043..b13ab221d653 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -985,10 +985,16 @@ void clk_unregister_fixed_factor(struct clk *clk); struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); +struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div); void clk_hw_unregister_fixed_factor(struct clk_hw *hw); struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); +struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div); struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, const char *name, unsigned int index, unsigned long flags, unsigned int mult, unsigned int div); From patchwork Wed Jan 22 11:52:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947192 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B676C02181 for ; Wed, 22 Jan 2025 11:52:40 +0000 (UTC) Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) by mx.groups.io with SMTP id smtpd.web10.41904.1737546757961158093 for ; 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([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b318990esm22887415e9.7.2025.01.22.03.52.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:52:35 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip 03/16] clk: gate: Add devm_clk_hw_register_gate() Date: Wed, 22 Jan 2025 13:52:17 +0200 Message-ID: <20250122115230.2885344-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:52:40 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17581 From: Horatiu Vultur commit 815f0e738a8d5663a02350e2580706829144a722 upstream. Add devm_clk_hw_register_gate() - devres-managed version of clk_hw_register_gate() Suggested-by: Stephen Boyd Signed-off-by: Horatiu Vultur Acked-by: Nicolas Ferre Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211103085102.1656081-2-horatiu.vultur@microchip.com [claudiu.beznea: fixed conflict] Signed-off-by: Claudiu Beznea --- drivers/clk/clk-gate.c | 35 +++++++++++++++++++++++++++++++++++ include/linux/clk-provider.h | 23 +++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 070dc47e95a1..64283807600b 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -222,3 +223,37 @@ void clk_hw_unregister_gate(struct clk_hw *hw) kfree(gate); } EXPORT_SYMBOL_GPL(clk_hw_unregister_gate); + +static void devm_clk_hw_release_gate(struct device *dev, void *res) +{ + clk_hw_unregister_gate(*(struct clk_hw **)res); +} + +struct clk_hw *__devm_clk_hw_register_gate(struct device *dev, + struct device_node *np, const char *name, + const char *parent_name, const struct clk_hw *parent_hw, + const struct clk_parent_data *parent_data, + unsigned long flags, + void __iomem *reg, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock) +{ + struct clk_hw **ptr, *hw; + + ptr = devres_alloc(devm_clk_hw_release_gate, sizeof(*ptr), GFP_KERNEL); + if (!ptr) + return ERR_PTR(-ENOMEM); + + hw = __clk_hw_register_gate(dev, np, name, parent_name, parent_hw, + parent_data, flags, reg, bit_idx, + clk_gate_flags, lock); + + if (!IS_ERR(hw)) { + *ptr = hw; + devres_add(dev, ptr); + } else { + devres_free(ptr); + } + + return hw; +} +EXPORT_SYMBOL_GPL(__devm_clk_hw_register_gate); diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index b13ab221d653..0e41b029f898 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -517,6 +517,13 @@ struct clk_hw *__clk_hw_register_gate(struct device *dev, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock); +struct clk_hw *__devm_clk_hw_register_gate(struct device *dev, + struct device_node *np, const char *name, + const char *parent_name, const struct clk_hw *parent_hw, + const struct clk_parent_data *parent_data, + unsigned long flags, + void __iomem *reg, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock); struct clk *clk_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, @@ -589,6 +596,22 @@ struct clk *clk_register_gate(struct device *dev, const char *name, __devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL, \ (parent_data), (flags), (reg), (bit_idx), \ (clk_gate_flags), (lock)) +/* + * devm_clk_hw_register_gate - register a gate clock with the clock framework + * @dev: device that is registering this clock + * @name: name of this clock + * @parent_name: name of this clock's parent + * @flags: framework-specific flags for this clock + * @reg: register address to control gating of this clock + * @bit_idx: which bit in the register controls gating of this clock + * @clk_gate_flags: gate-specific flags for this clock + * @lock: shared register lock for this clock + */ +#define devm_clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,\ + clk_gate_flags, lock) \ + __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ + NULL, (flags), (reg), (bit_idx), \ + (clk_gate_flags), (lock)) void clk_unregister_gate(struct clk *clk); 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([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b318990esm22887415e9.7.2025.01.22.03.52.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:52:36 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip 04/16] clk: Add devm_clk_hw_register_gate_parent_hw() Date: Wed, 22 Jan 2025 13:52:18 +0200 Message-ID: <20250122115230.2885344-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:52:40 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17582 From: Claudiu Beznea commit e1ef630c56d36770e180f0d0bf7b61b5289f5c48 upstream. Add devm_clk_hw_register_gate_parent_hw() macro to allow registering devres managed gate clocks providing struct clk_hw object as parent. Reviewed-by: Geert Uytterhoeven Acked-by: Stephen Boyd Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [claudiu.beznea: fixed conflict] Signed-off-by: Claudiu Beznea --- include/linux/clk-provider.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 0e41b029f898..9f34b4268e6a 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -578,6 +578,24 @@ struct clk *clk_register_gate(struct device *dev, const char *name, __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \ (flags), (reg), (bit_idx), \ (clk_gate_flags), (lock)) +/** + * devm_clk_hw_register_gate_parent_hw - register a gate clock with the clock + * framework + * @dev: device that is registering this clock + * @name: name of this clock + * @parent_hw: pointer to parent clk + * @flags: framework-specific flags for this clock + * @reg: register address to control gating of this clock + * @bit_idx: which bit in the register controls gating of this clock + * @clk_gate_flags: gate-specific flags for this clock + * @lock: shared register lock for this clock + */ +#define devm_clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, \ + reg, bit_idx, clk_gate_flags, \ + lock) \ + __devm_clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \ + NULL, (flags), (reg), (bit_idx), \ + (clk_gate_flags), (lock)) /** * devm_clk_hw_register_gate_parent_data - register a gate clock with the * clock framework From patchwork Wed Jan 22 11:52:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947196 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6893FC02181 for ; Wed, 22 Jan 2025 11:52:50 +0000 (UTC) Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) by mx.groups.io with SMTP id smtpd.web10.41907.1737546760152749210 for ; Wed, 22 Jan 2025 03:52:40 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=ZRigHlaq; spf=pass (domain: tuxon.dev, ip: 209.85.128.43, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-438a3216fc2so40030775e9.1 for ; Wed, 22 Jan 2025 03:52:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737546758; x=1738151558; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h/UPBktFKKZ2+4zFiQ8d88MTvMS3K0iI9Rt+Ln4Clbk=; b=ZRigHlaqnU9AfL8W4YbDp3lm9YhGZMGOdG5C5GhnxrMECej40yvO+iehMKwh038jGK 8ncI4GqkSKeZqBh7vepdOOsU0AURyaWGMjnUpntAKEJ+LmhT0Jg18eS2Yb+ugfdN0jfs K6AGlhqNqmU9oSOAJLxfVs9iq9sO3ZWme20nLUT797H9lHdaWus9YMH0UQJONDDpVlrB aw+bEFM4ltQSw88oWwW/kJO042JC/kNc9nxtdvElIyjQR0NgalayZ7lIBHNxYSeTU7Ec ngApbCDkYs5kXvOk7+BpqtPlyAGcBS8Dv9jNaAekAwFrp5FJJlVsI9IfoZXbMDHE/bx9 K8PQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737546758; x=1738151558; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h/UPBktFKKZ2+4zFiQ8d88MTvMS3K0iI9Rt+Ln4Clbk=; b=k5On3tlXS/5IHAl91OLNz+nziOSrNghWR0nEYP3SXFOWYHjBk2EJKzflwdg9Szuo4/ WfWeBAjZVXD1n0A1kOyFPGhs8Mo/LKrQJHvF+3BGpTjRhbvcluQlguuPewVYETty2O9Z QhVmlfaN0AQhJcpTf1sgbWYmCRh+uYBYbeTE2DKKSm+V4fXMhIc/0bA5xiE4jxrN0ByC 2sNeVtrVGODX9xh20wu7aM+DP6Wh11t2AbkTIA+O9OVnSJYRSBPZlLmpFWHK0JP3pPE8 hAwSU0j5zA8T3itMZN71FGb7nYjG5hoYQ/6qsrmlb+Tw4QhNc1F4vvRexcfp9JqtOONe NN9w== X-Forwarded-Encrypted: i=1; AJvYcCVC9Ww/x5MtJjBb3vTBWtwz2OaownWmPMfC8gKsG88/NIeB5uphWbO8SsR54riv3PQ1su2UUTsu@lists.cip-project.org X-Gm-Message-State: AOJu0YxbOHz5zKWYsb1C5ymCl0V+DR8p7LGJCQIJ53EkXzpm5SnvVP1f h1VTkYsUc4tmWNqblkes6eTgX61htDZgftJ7Dl03437CHSYIeiIbE/lCxDx9hhM= X-Gm-Gg: ASbGncuVIV4yMwqMsqP5CQutHyxaLa3405M140gUfFpp5aSSpl1i/BHUOS5B9IZrhIW b8Eq7XWQL7jJ/kwfbuUzpwb6K13xAZXTygv2HzZ2PvXBpEdC85rqTUtVzrIxxayxmKyEAuCQO6c 19wNZO4qpb8k/0HqJnZW4TLVd6jnE2vemM8mvcCDytJ05oPOtbM4ei19kRRqFnrk06mcA3ACzC7 rgG5zIom1QiU/THC9vas3pJFtt0hq/iMh17sZMGHiskciURbdUkMJ3ijnhirIkT5IKeyLCl0bcU RPsFI5irqKMOfoKTRjG77oM= X-Google-Smtp-Source: AGHT+IErrMYwsfYLcxjLYF/R+btUrsP6XZOP61Cv7aX6l/9gJAKPaHSzj/o4ggY+WK7Y0Qi53O8uXw== X-Received: by 2002:a05:600c:1f8c:b0:436:fb02:e90 with SMTP id 5b1f17b1804b1-438913cdaa8mr230411635e9.10.1737546758581; Wed, 22 Jan 2025 03:52:38 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b318990esm22887415e9.7.2025.01.22.03.52.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:52:38 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip 05/16] clk: mux: Introduce devm_clk_hw_register_mux_parent_hws() Date: Wed, 22 Jan 2025 13:52:19 +0200 Message-ID: <20250122115230.2885344-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:52:50 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17583 From: Marijn Suijten commit df63af17f3375239e0be124844f304b4a4b60665 upstream. Add the devres variant of clk_hw_register_mux_hws() for registering a mux clock with clk_hw parent pointers instead of parent names. Signed-off-by: Marijn Suijten Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220629225331.357308-3-marijn.suijten@somainline.org Signed-off-by: Stephen Boyd Signed-off-by: Claudiu Beznea --- include/linux/clk-provider.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 9f34b4268e6a..50eaf1946009 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -988,6 +988,13 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name, (parent_names), NULL, NULL, (flags), (reg), \ (shift), BIT((width)) - 1, (clk_mux_flags), \ NULL, (lock)) +#define devm_clk_hw_register_mux_parent_hws(dev, name, parent_hws, \ + num_parents, flags, reg, shift, \ + width, clk_mux_flags, lock) \ + __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ + (parent_hws), NULL, (flags), (reg), \ + (shift), BIT((width)) - 1, \ + (clk_mux_flags), NULL, (lock)) int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, unsigned int val); From patchwork Wed Jan 22 11:52:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947201 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BCD6C0218F for ; Wed, 22 Jan 2025 11:52:50 +0000 (UTC) Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) by mx.groups.io with SMTP id smtpd.web11.41712.1737546761453391369 for ; Wed, 22 Jan 2025 03:52:41 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=Mv6ZxM17; spf=pass (domain: tuxon.dev, ip: 209.85.128.47, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-4362f61757fso69879815e9.2 for ; Wed, 22 Jan 2025 03:52:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737546760; x=1738151560; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2TDhDVdmrLyUjwA3Rd9ZKV50+C7dveaBYHkQzItSHlw=; b=Mv6ZxM176sGauquhQg/U7rD4vbWDi0xsu2qD3zvtN6ligjOawP2EpePbGhZcI0mCO/ cEbzsaGyekijmRKvRA6ZHDTWqCoquZsI76Ab/ruMYTeNaerX5Ks/KmNavxWH9gHBxLC/ ooVzNQElZifIjYCdvnQcclDfLrALUrkDcSDZJin0UsXckmlcK8Z9kW/phoNgUhxUxNUO 9ew6VsBXIwPJZfYTXQaxUfoPKz+RdFb0U7FTT4hw29b5f3ZDIGa5DBMGWSqFCbUwIV1Q kgxyzBq4PkCtRQLhPM2KA5ZmJTK3VrU/gLUNvn17+Du/+PHJCx1oQNimLwlCNIokodxX V75w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737546760; x=1738151560; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2TDhDVdmrLyUjwA3Rd9ZKV50+C7dveaBYHkQzItSHlw=; b=WhmSYjShlEU5WmJG7de+fCPlEiA9yIK71qKXYh8LIqlXfNCbX6uet5+nuIpb4vMKp/ 2gVFJew4cplHzfMs8A2wenGknvAmifm8SHqqw7+BdAg+Dj1xB0ZfjIDi8Ok+ViHp6O+5 btJj3RmIqBef9VNYgDVnonH5g1rW2Y4vorkwBastQpP9VbuXJ2D/CrJrsR6+CT9eAZPZ AoQkbIA7p3j41prDnspLs4EkKTDmYqYV1EmBmK1la2tdG9D2RRXlJxE84z5//jizLBQ8 ykltfF4ZZCESjZQafhIkG/XDuqGfALbextuCKO+GKRbg6vVGIz8W9mUbRpuovElrGW4X Tbuw== X-Forwarded-Encrypted: i=1; AJvYcCX3iUu6T5Xyj66jNeLJ9mi2AyZXShyoq4G3A7G95677kJn9UkCc7eyTvfXVQWJ12q6QZHxkTlHX@lists.cip-project.org X-Gm-Message-State: AOJu0Yxwrwc3W5RJOX6XIbw2LdhCdPYsHs6HPtUFmIB4/zYEgSc8nTqW xLWPmN3dZHOhb7VFbpVedggJKigyEJ5KP67kHcoHoThKkTrND+Yu7VDo3LC1uDg= X-Gm-Gg: ASbGnctoYOa/cG+Am+QuHZJeVREmBPlaXLkW16VO2Wjhp/zIP1UZWOwaWVwK7GsPNDq eKmfQLXyJyv8s8DmJcC4jlC2afAacLHK+/oUQ/n2X6Z4jYA/pSIGpshIYIoQhhATaOvJGLaI3Os t/Hhd2D/p7xOudEXQX/ax3gahSxKHhySJNpYogMZQf59NlEpD5Eu+dlDNGfF315PK0bw0kNhmrY kvL/o0TMJqeaOcn9YOO1Thcyjs+5tlCzYpXIWcFwpJbYm0+a+eeMzBNA94MmGliJuQSXC66cGod nOOfZGRaiam5wIJ+uhGybtU= X-Google-Smtp-Source: AGHT+IE8camX+bLd2Jf/XoZM7mN2ErTsszytxIIZe5yp9mipEPWFMMvPJegeP37nA5S52hEhdNqRog== X-Received: by 2002:a05:600c:4e12:b0:42c:b9c8:2bb0 with SMTP id 5b1f17b1804b1-438913bdcd2mr179760515e9.4.1737546759861; Wed, 22 Jan 2025 03:52:39 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b318990esm22887415e9.7.2025.01.22.03.52.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:52:39 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip 06/16] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB Date: Wed, 22 Jan 2025 13:52:20 +0200 Message-ID: <20250122115230.2885344-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:52:50 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17584 From: Claudiu Beznea commit cdfd5daf90af8363fb1f58e08c829a775b2e2fc5 upstream. The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC, the tamper detector and a small general usage memory of 128B. The VBATTB controller controls the clock for the RTC on the Renesas RZ/G3S. The HW block diagram for the clock logic is as follows: +----------+ XC `\ RTXIN --->| |----->| \ +----+ VBATTCLK | 32K clock| | |----->|gate|-----------> | osc | XBYP | | +----+ RTXOUT --->| |----->| / +----------+ ,/ One could connect as input to this HW block either a crystal or an external clock device. This is board specific. After discussions w/ Stephen Boyd the clock tree associated with this hardware block was exported in Linux as: input-xtal xbyp xc mux vbattclk where: - input-xtal is the input clock (connected to RTXIN, RTXOUT pins) - xc, xbyp are mux inputs - mux is the internal mux - vbattclk is the gate clock that feeds in the end the RTC to allow selecting the input of the MUX though assigned-clock DT properties, using the already existing clock drivers and avoid adding other DT properties. This allows select the input of the mux based on the type of the connected input clock: - if the 32768 crystal is connected as input for the VBATTB, the input of the mux should be xc - if an external clock device is connected as input for the VBATTB the input of the mux should be xbyp Add bindings for the VBATTB controller. Reviewed-by: Geert Uytterhoeven Reviewed-by: Krzysztof Kozlowski Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- .../clock/renesas,r9a08g045-vbattb.yaml | 84 +++++++++++++++++++ .../clock/renesas,r9a08g045-vbattb.h | 13 +++ 2 files changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml create mode 100644 include/dt-bindings/clock/renesas,r9a08g045-vbattb.h diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml new file mode 100644 index 000000000000..3707e4118949 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Battery Backup Function (VBATTB) + +description: + Renesas VBATTB is an always on powered module (backed by battery) which + controls the RTC clock (VBATTCLK), tamper detection logic and a small + general usage memory (128B). + +maintainers: + - Claudiu Beznea + +properties: + compatible: + const: renesas,r9a08g045-vbattb + + reg: + maxItems: 1 + + interrupts: + items: + - description: tamper detector interrupt + + clocks: + items: + - description: VBATTB module clock + - description: RTC input clock (crystal or external clock device) + + clock-names: + items: + - const: bclk + - const: rtx + + '#clock-cells': + const: 1 + + power-domains: + maxItems: 1 + + resets: + items: + - description: VBATTB module reset + + quartz-load-femtofarads: + description: load capacitance of the on board crystal + enum: [ 4000, 7000, 9000, 12500 ] + default: 4000 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - '#clock-cells' + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + clock-controller@1005c000 { + compatible = "renesas,r9a08g045-vbattb"; + reg = <0x1005c000 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; + clock-names = "bclk", "rtx"; + assigned-clocks = <&vbattb VBATTB_MUX>; + assigned-clock-parents = <&vbattb VBATTB_XC>; + #clock-cells = <1>; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + quartz-load-femtofarads = <12500>; + }; diff --git a/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h new file mode 100644 index 000000000000..67774eafad06 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ +#define __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ + +#define VBATTB_XC 0 +#define VBATTB_XBYP 1 +#define VBATTB_MUX 2 +#define VBATTB_VBATTCLK 3 + +#endif /* __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ */ From patchwork Wed Jan 22 11:52:21 2025 Content-Type: text/plain; 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([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b318990esm22887415e9.7.2025.01.22.03.52.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:52:40 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip 07/16] clk: renesas: vbattb: Add VBATTB clock driver Date: Wed, 22 Jan 2025 13:52:21 +0200 Message-ID: <20250122115230.2885344-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:52:50 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17585 From: Claudiu Beznea commit be20a73e03e19005cfa5c1c4d6158af1ba02f056 upstream. The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used by the RTC. The input to the VBATTB could be a 32KHz crystal or an external clock device. The HW block diagram for the clock generator is as follows: +----------+ XC `\ RTXIN --->| |----->| \ +----+ VBATTCLK | 32K clock| | |----->|gate|-----------> | osc | XBYP | | +----+ RTXOUT --->| |----->| / +----------+ , After discussions w/ Stephen Boyd the clock tree associated with this hardware block was exported in Linux as: vbattb-xtal xbyp xc mux vbattbclk where: - input-xtal is the input clock (connected to RTXIN, RTXOUT pins) - xc, xbyp are mux inputs - mux is the internal mux - vbattclk is the gate clock that feeds in the end the RTC to allow selecting the input of the MUX though assigned-clock DT properties, using the already existing clock drivers and avoid adding other DT properties. If the crystal is connected on RTXIN, RTXOUT pins the XC will be selected as mux input. If an external clock device is connected on RTXIN, RTXOUT pins the XBYP will be selected as mux input. The load capacitance of the internal crystal can be configured with renesas,vbattb-load-nanofarads DT property. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [claudiu.beznea: dropped cleanup.h helpers, include to fix compilation errors] Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/Kconfig | 5 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/clk-vbattb.c | 204 +++++++++++++++++++++++++++++++ 3 files changed, 210 insertions(+) create mode 100644 drivers/clk/renesas/clk-vbattb.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 8e03eab59115..de7db5fa07de 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -206,6 +206,11 @@ config CLK_RZG2L bool "Renesas RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST select RESET_CONTROLLER +config CLK_RENESAS_VBATTB + tristate "Renesas VBATTB clock controller" + depends on ARCH_RZG2L || COMPILE_TEST + select RESET_CONTROLLER + # Generic config CLK_RENESAS_CPG_MSSR bool "CPG/MSSR clock support" if COMPILE_TEST diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 34815dd77f58..f40b8233eac5 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -46,3 +46,4 @@ obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o obj-$(CONFIG_CLK_RENESAS_CPG_MSTP) += clk-mstp.o obj-$(CONFIG_CLK_RENESAS_DIV6) += clk-div6.o +obj-$(CONFIG_CLK_RENESAS_VBATTB) += clk-vbattb.o diff --git a/drivers/clk/renesas/clk-vbattb.c b/drivers/clk/renesas/clk-vbattb.c new file mode 100644 index 000000000000..a5f9b736ef2c --- /dev/null +++ b/drivers/clk/renesas/clk-vbattb.c @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * VBATTB clock driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define VBATTB_BKSCCR 0x1c +#define VBATTB_BKSCCR_SOSEL 6 +#define VBATTB_SOSCCR2 0x24 +#define VBATTB_SOSCCR2_SOSTP2 0 +#define VBATTB_XOSCCR 0x30 +#define VBATTB_XOSCCR_OUTEN 16 +#define VBATTB_XOSCCR_XSEL GENMASK(1, 0) +#define VBATTB_XOSCCR_XSEL_4_PF 0x0 +#define VBATTB_XOSCCR_XSEL_7_PF 0x1 +#define VBATTB_XOSCCR_XSEL_9_PF 0x2 +#define VBATTB_XOSCCR_XSEL_12_5_PF 0x3 + +/** + * struct vbattb_clk - VBATTB clock data structure + * @base: base address + * @lock: lock + */ +struct vbattb_clk { + void __iomem *base; + spinlock_t lock; +}; + +static int vbattb_clk_validate_load_capacitance(u32 *reg_lc, u32 of_lc) +{ + switch (of_lc) { + case 4000: + *reg_lc = VBATTB_XOSCCR_XSEL_4_PF; + break; + case 7000: + *reg_lc = VBATTB_XOSCCR_XSEL_7_PF; + break; + case 9000: + *reg_lc = VBATTB_XOSCCR_XSEL_9_PF; + break; + case 12500: + *reg_lc = VBATTB_XOSCCR_XSEL_12_5_PF; + break; + default: + return -EINVAL; + } + + return 0; +} + +static void vbattb_clk_action(void *data) +{ + struct device *dev = data; + struct reset_control *rstc = dev_get_drvdata(dev); + int ret; + + ret = reset_control_assert(rstc); + if (ret) + dev_err(dev, "Failed to de-assert reset!"); + + ret = pm_runtime_put_sync(dev); + if (ret < 0) + dev_err(dev, "Failed to runtime suspend!"); + + of_clk_del_provider(dev->of_node); +} + +static int vbattb_clk_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct clk_parent_data parent_data = {}; + struct clk_hw_onecell_data *clk_data; + const struct clk_hw *parent_hws[2]; + struct device *dev = &pdev->dev; + struct reset_control *rstc; + struct vbattb_clk *vbclk; + u32 of_lc, reg_lc, val; + struct clk_hw *hw; + /* 4 clocks are exported: VBATTB_XC, VBATTB_XBYP, VBATTB_MUX, VBATTB_VBATTCLK. */ + u8 num_clks = 4; + int ret; + + /* Default to 4pF as this is not needed if external clock device is connected. */ + of_lc = 4000; + of_property_read_u32(np, "quartz-load-femtofarads", &of_lc); + + ret = vbattb_clk_validate_load_capacitance(®_lc, of_lc); + if (ret) + return ret; + + vbclk = devm_kzalloc(dev, sizeof(*vbclk), GFP_KERNEL); + if (!vbclk) + return -ENOMEM; + + clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, num_clks), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + clk_data->num = num_clks; + + vbclk->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(vbclk->base)) + return PTR_ERR(vbclk->base); + + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; + + rstc = devm_reset_control_get_shared(dev, NULL); + if (IS_ERR(rstc)) + return PTR_ERR(rstc); + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + ret = reset_control_deassert(rstc); + if (ret) { + pm_runtime_put_sync(dev); + return ret; + } + + dev_set_drvdata(dev, rstc); + ret = devm_add_action_or_reset(dev, vbattb_clk_action, dev); + if (ret) + return ret; + + spin_lock_init(&vbclk->lock); + + parent_data.fw_name = "rtx"; + hw = devm_clk_hw_register_gate_parent_data(dev, "xc", &parent_data, 0, + vbclk->base + VBATTB_SOSCCR2, + VBATTB_SOSCCR2_SOSTP2, + CLK_GATE_SET_TO_DISABLE, &vbclk->lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_XC] = hw; + + hw = devm_clk_hw_register_fixed_factor_fwname(dev, np, "xbyp", "rtx", 0, 1, 1); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_XBYP] = hw; + + parent_hws[0] = clk_data->hws[VBATTB_XC]; + parent_hws[1] = clk_data->hws[VBATTB_XBYP]; + hw = devm_clk_hw_register_mux_parent_hws(dev, "mux", parent_hws, 2, 0, + vbclk->base + VBATTB_BKSCCR, + VBATTB_BKSCCR_SOSEL, + 1, 0, &vbclk->lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_MUX] = hw; + + /* Set load capacitance before registering the VBATTCLK clock. */ + spin_lock(&vbclk->lock); + val = readl_relaxed(vbclk->base + VBATTB_XOSCCR); + val &= ~VBATTB_XOSCCR_XSEL; + val |= reg_lc; + writel_relaxed(val, vbclk->base + VBATTB_XOSCCR); + spin_unlock(&vbclk->lock); + + /* This feeds the RTC counter clock and it needs to stay on. */ + hw = devm_clk_hw_register_gate_parent_hw(dev, "vbattclk", hw, CLK_IS_CRITICAL, + vbclk->base + VBATTB_XOSCCR, + VBATTB_XOSCCR_OUTEN, 0, + &vbclk->lock); + + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_VBATTCLK] = hw; + + return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); +} + +static const struct of_device_id vbattb_clk_match[] = { + { .compatible = "renesas,r9a08g045-vbattb" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, vbattb_clk_match); + +static struct platform_driver vbattb_clk_driver = { + .driver = { + .name = "renesas-vbattb-clk", + .of_match_table = vbattb_clk_match, + }, + .probe = vbattb_clk_probe, +}; +module_platform_driver(vbattb_clk_driver); + +MODULE_DESCRIPTION("Renesas VBATTB Clock Driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); From patchwork Wed Jan 22 11:52:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947197 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69F56C02182 for ; Wed, 22 Jan 2025 11:52:50 +0000 (UTC) Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) by mx.groups.io with SMTP id smtpd.web10.41908.1737546763983940664 for ; Wed, 22 Jan 2025 03:52:44 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=miittreu; spf=pass (domain: tuxon.dev, ip: 209.85.128.45, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-43618283d48so48739395e9.1 for ; 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([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b318990esm22887415e9.7.2025.01.22.03.52.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:52:41 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip 08/16] clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP Date: Wed, 22 Jan 2025 13:52:22 +0200 Message-ID: <20250122115230.2885344-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:52:50 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17586 From: Claudiu Beznea commit c8bd9bd6446fa034a1877b553bf118606b37c025 upstream. The Renesas RZ/G3S SoC has an IP named Battery Backup Function (VBATTB) that generates the RTC clock. Add clock, reset and power domain support for it. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240614071932.1014067-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [claudiu.beznea: dropped PM domain part as it is not ready yet] Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/r9a08g045-cpg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index c3e6da2de197..55e7d42dc472 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -215,6 +215,7 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9), DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0), DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0), + DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0), }; static const struct rzg2l_reset r9a08g045_resets[] = { @@ -231,6 +232,7 @@ static const struct rzg2l_reset r9a08g045_resets[] = { DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0), DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1), DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2), + DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0), }; static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { @@ -238,6 +240,7 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { MOD_CLK_BASE + R9A08G045_IA55_PCLK, MOD_CLK_BASE + R9A08G045_IA55_CLK, MOD_CLK_BASE + R9A08G045_DMAC_ACLK, + MOD_CLK_BASE + R9A08G045_VBAT_BCLK, }; const struct rzg2l_cpg_info r9a08g045_cpg_info = { From patchwork Wed Jan 22 11:52:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947200 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BC66C0218D for ; Wed, 22 Jan 2025 11:52:50 +0000 (UTC) Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) by mx.groups.io with SMTP id smtpd.web10.41909.1737546765161151298 for ; Wed, 22 Jan 2025 03:52:45 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=W6wMJNm/; spf=pass (domain: tuxon.dev, ip: 209.85.128.44, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-4361dc6322fso47324905e9.3 for ; Wed, 22 Jan 2025 03:52:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737546763; x=1738151563; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OjtRyfTgZS3PaUggTQ0LoCLu4U5xv/Jge0GwFBL9qQY=; b=W6wMJNm/Zr7Xi9IMRw9FZaGaYlJziOS77LF4S1tNYJNsKhw+d5zBrTw6bJf8kLS20M hlm4jV17J8WIQJPXi04iaJr0g/t670/lYhPXJxWRoYXynKIT0UdInfxVUl2Q8gbXc1aU rSmXwt5IncetHTuZANJIXFki2NF7N6JicWkNWQUQ9oebZ9fSR05vm5vnk3q6o/J51Ekk sPBtvX8F8OMELV77Kv5xC/8ZkS0THJSVEGg5+ZTN81q86IZ8o6T0lq82TxuggSSF9phV 3fnJA4fdGhi3Ud1u+7dFUv/OvyJ8EIdVx6ctxT91jPqzWBVDHAU0KaXvOXVI+FiZ7blo zB8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737546763; x=1738151563; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OjtRyfTgZS3PaUggTQ0LoCLu4U5xv/Jge0GwFBL9qQY=; b=Lxue+3F8+6kQEhZeRuq4lIYRchEtsAmc+pfSOmvkX3eAg5UFr/sQL40S8cGCwNbUt6 d72f9uQx/fz1MR1r22spPoIvZsi0chmUkNNMv77wPoWI3mZMBJh/pwW0Cxg+RpFoz3JW PoB+yCCsbiW+66cEdq6q8O24TQpFZMLFtzE4eCJ78p3JiMTvR/Vip8c6I0fxsLyuAcfD t4YVEPrpzhQH+uSn7zqgDiSUymrjelw5Bbzs5KSOG28rxLYeFhTOwrPokjgioGxka7vT kTcdUy0oICEO7m7/bAPmoTz9LR/RjdY5hQ079zspScYsOx+trWrs9l92tso2rzdz5XCH 0pHg== X-Forwarded-Encrypted: i=1; AJvYcCWCz8KlG7G+C8IzBw5MNjPJkOcrEPSCXlgAeQTMHrQRAhfZmEriPCoU0XIbV3HoFGjZAulsevEM@lists.cip-project.org X-Gm-Message-State: AOJu0YzipIaBZvpW8vrUrOVfB5Caw0+JX/Rb8KzbKF2K94WDd8m24prF hkP0adi94xzDpGLrSzoxleOARgsltvMAYw7Gc0s6GPUCxPzOcIDDeDS6/7tfE0w= X-Gm-Gg: ASbGncuB/AyucaHw4wA+yG6bNhc3WkWKZ6Gg6dnqSa8lO6u3YaryCZ9GvxEJyOj5TZo dm9pAnlSbXNICmklsWLQuElxXaVh/2pz7X5J8bgDx3hCNdwRYhoRE/ehjUNfWZsiE9py6aiMdHt BEB/r4SAH9TJdN56pT4DKMSggtqu3Sp4Q6qrRh6JDR2/3HkPGKxGkzIR7GGi29Zn36YHbQOEkxj ke+o+v+f42B+livPtzq6Zt77Nu+z/1x+DfpT8Sk0XTa87kyYuMC4aKn60/m6HEiVg8lpNS0KXJs 3rP82almsfUIQXH8a4CQRU4= X-Google-Smtp-Source: AGHT+IHkGoSnVwHPLEr4UKyS0eMUACjt9+/RQztSb8FS4Gk5vDuJmKG2FsjsdglG5HBxhMjBQoy/CA== X-Received: by 2002:a05:600c:1e23:b0:434:f335:83b with SMTP id 5b1f17b1804b1-4389fa653e9mr183992365e9.5.1737546763623; Wed, 22 Jan 2025 03:52:43 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b318990esm22887415e9.7.2025.01.22.03.52.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:52:42 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip 09/16] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RTCA-3 IP Date: Wed, 22 Jan 2025 13:52:23 +0200 Message-ID: <20250122115230.2885344-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:52:50 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17587 From: Claudiu Beznea commit 71c61a45c951eca67dd2cbc4de9cdd687ece4ead upstream. Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC. The RTC IP available on Renesas RZ/V2H is almost identical with the one found on Renesas RZ/G3S (it misses the time capture functionality which is not yet implemented on proposed driver). For this, added also a generic compatible that will be used at the moment as fallback for both RZ/G3S and RZ/V2H. Reviewed-by: Rob Herring (Arm) Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20241030110120.332802-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Alexandre Belloni Signed-off-by: Claudiu Beznea --- .../bindings/rtc/renesas,rz-rtca3.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml diff --git a/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml new file mode 100644 index 000000000000..e70eeb66aa64 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/renesas,rz-rtca3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RTCA-3 Real Time Clock + +maintainers: + - Claudiu Beznea + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + items: + - enum: + - renesas,r9a08g045-rtca3 # RZ/G3S + - const: renesas,rz-rtca3 + + reg: + maxItems: 1 + + interrupts: + items: + - description: Alarm interrupt + - description: Periodic interrupt + - description: Carry interrupt + + interrupt-names: + items: + - const: alarm + - const: period + - const: carry + + clocks: + items: + - description: RTC bus clock + - description: RTC counter clock + + clock-names: + items: + - const: bus + - const: counter + + power-domains: + maxItems: 1 + + resets: + items: + - description: VBATTB module reset + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + rtc@1004ec00 { + compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; + reg = <0x1004ec00 0x400>; + interrupts = , + , + ; + interrupt-names = "alarm", "period", "carry"; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattclk VBATTB_VBATTCLK>; + clock-names = "bus", "counter"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + }; From patchwork Wed Jan 22 11:52:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947203 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82018C0218E for ; Wed, 22 Jan 2025 11:52:50 +0000 (UTC) Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) by mx.groups.io with SMTP id smtpd.web10.41911.1737546766664231357 for ; Wed, 22 Jan 2025 03:52:47 -0800 Authentication-Results: mx.groups.io; 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([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b318990esm22887415e9.7.2025.01.22.03.52.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:52:44 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip 10/16] rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S SoC Date: Wed, 22 Jan 2025 13:52:24 +0200 Message-ID: <20250122115230.2885344-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:52:50 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17588 From: Claudiu Beznea commit d4488377609e36cd9785533c29ccea4b86c292b9 upstream. The RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC has calendar count mode and binary count mode (selectable though RCR2.CNTMD) capabilities, alarm capabilities, clock error correction capabilities. It can generate alarm, period, carry interrupts. Add a driver for RTCA-3 IP. The driver implements calendar count mode (as the conversion b/w RTC and system time is simpler, done with bcd2bin(), bin2bcd()), read and set time, read and set alarm, read and set an offset. Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20241030110120.332802-6-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Alexandre Belloni [claudiu.beznea: - fixed conflicts - dropped cleanup.h helpers - fix "loop initial declarations are only allowed in C99 or C11 mode" compilation error - use rtc_register_device() instead of devres helper for registration and dropped the driver's remove with it - use SIMPLE_DEV_PM_OPS() - include ] Signed-off-by: Claudiu Beznea --- MAINTAINERS | 8 + drivers/rtc/Kconfig | 10 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-renesas-rtca3.c | 922 ++++++++++++++++++++++++++++++++ 4 files changed, 941 insertions(+) create mode 100644 drivers/rtc/rtc-renesas-rtca3.c diff --git a/MAINTAINERS b/MAINTAINERS index 4e2d9ed016ab..bb6f787ea461 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14945,6 +14945,14 @@ S: Supported F: Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml F: drivers/iio/adc/rzg2l_adc.c +RENESAS RTCA-3 RTC DRIVER +M: Claudiu Beznea +L: linux-rtc@vger.kernel.org +L: linux-renesas-soc@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml +F: drivers/rtc/rtc-renesas-rtca3.c + RESET CONTROLLER FRAMEWORK M: Philipp Zabel S: Maintained diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 8ddd334e049e..6b876bad9143 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1921,6 +1921,16 @@ config RTC_DRV_ASPEED This driver can also be built as a module, if so, the module will be called "rtc-aspeed". +config RTC_DRV_RENESAS_RTCA3 + tristate "Renesas RTCA-3 RTC" + depends on ARCH_RENESAS + help + If you say yes here you get support for the Renesas RTCA-3 RTC + available on the Renesas RZ/G3S SoC. + + This driver can also be built as a module, if so, the module + will be called "rtc-rtca3". + comment "HID Sensor RTC drivers" config RTC_DRV_HID_SENSOR_TIME diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index bfb57464118d..e17d71c129ad 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -148,6 +148,7 @@ obj-$(CONFIG_RTC_DRV_RX6110) += rtc-rx6110.o obj-$(CONFIG_RTC_DRV_RX8010) += rtc-rx8010.o obj-$(CONFIG_RTC_DRV_RX8025) += rtc-rx8025.o obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o +obj-$(CONFIG_RTC_DRV_RENESAS_RTCA3) += rtc-renesas-rtca3.o obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o obj-$(CONFIG_RTC_DRV_S3C) += rtc-s3c.o obj-$(CONFIG_RTC_DRV_S5M) += rtc-s5m.o diff --git a/drivers/rtc/rtc-renesas-rtca3.c b/drivers/rtc/rtc-renesas-rtca3.c new file mode 100644 index 000000000000..5a8dd2ad6b60 --- /dev/null +++ b/drivers/rtc/rtc-renesas-rtca3.c @@ -0,0 +1,922 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * On-Chip RTC Support available on RZ/G3S SoC + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Counter registers. */ +#define RTCA3_RSECCNT 0x2 +#define RTCA3_RSECCNT_SEC GENMASK(6, 0) +#define RTCA3_RMINCNT 0x4 +#define RTCA3_RMINCNT_MIN GENMASK(6, 0) +#define RTCA3_RHRCNT 0x6 +#define RTCA3_RHRCNT_HR GENMASK(5, 0) +#define RTCA3_RHRCNT_PM BIT(6) +#define RTCA3_RWKCNT 0x8 +#define RTCA3_RWKCNT_WK GENMASK(2, 0) +#define RTCA3_RDAYCNT 0xa +#define RTCA3_RDAYCNT_DAY GENMASK(5, 0) +#define RTCA3_RMONCNT 0xc +#define RTCA3_RMONCNT_MONTH GENMASK(4, 0) +#define RTCA3_RYRCNT 0xe +#define RTCA3_RYRCNT_YEAR GENMASK(7, 0) + +/* Alarm registers. */ +#define RTCA3_RSECAR 0x10 +#define RTCA3_RSECAR_SEC GENMASK(6, 0) +#define RTCA3_RMINAR 0x12 +#define RTCA3_RMINAR_MIN GENMASK(6, 0) +#define RTCA3_RHRAR 0x14 +#define RTCA3_RHRAR_HR GENMASK(5, 0) +#define RTCA3_RHRAR_PM BIT(6) +#define RTCA3_RWKAR 0x16 +#define RTCA3_RWKAR_DAYW GENMASK(2, 0) +#define RTCA3_RDAYAR 0x18 +#define RTCA3_RDAYAR_DATE GENMASK(5, 0) +#define RTCA3_RMONAR 0x1a +#define RTCA3_RMONAR_MON GENMASK(4, 0) +#define RTCA3_RYRAR 0x1c +#define RTCA3_RYRAR_YR GENMASK(7, 0) +#define RTCA3_RYRAREN 0x1e + +/* Alarm enable bit (for all alarm registers). */ +#define RTCA3_AR_ENB BIT(7) + +/* Control registers. */ +#define RTCA3_RCR1 0x22 +#define RTCA3_RCR1_AIE BIT(0) +#define RTCA3_RCR1_CIE BIT(1) +#define RTCA3_RCR1_PIE BIT(2) +#define RTCA3_RCR1_PES GENMASK(7, 4) +#define RTCA3_RCR1_PES_1_64_SEC 0x8 +#define RTCA3_RCR2 0x24 +#define RTCA3_RCR2_START BIT(0) +#define RTCA3_RCR2_RESET BIT(1) +#define RTCA3_RCR2_AADJE BIT(4) +#define RTCA3_RCR2_ADJP BIT(5) +#define RTCA3_RCR2_HR24 BIT(6) +#define RTCA3_RCR2_CNTMD BIT(7) +#define RTCA3_RSR 0x20 +#define RTCA3_RSR_AF BIT(0) +#define RTCA3_RSR_CF BIT(1) +#define RTCA3_RSR_PF BIT(2) +#define RTCA3_RADJ 0x2e +#define RTCA3_RADJ_ADJ GENMASK(5, 0) +#define RTCA3_RADJ_ADJ_MAX 0x3f +#define RTCA3_RADJ_PMADJ GENMASK(7, 6) +#define RTCA3_RADJ_PMADJ_NONE 0 +#define RTCA3_RADJ_PMADJ_ADD 1 +#define RTCA3_RADJ_PMADJ_SUB 2 + +/* Polling operation timeouts. */ +#define RTCA3_DEFAULT_TIMEOUT_US 150 +#define RTCA3_IRQSET_TIMEOUT_US 5000 +#define RTCA3_START_TIMEOUT_US 150000 +#define RTCA3_RESET_TIMEOUT_US 200000 + +/** + * enum rtca3_alrm_set_step - RTCA3 alarm set steps + * @RTCA3_ALRM_SSTEP_DONE: alarm setup done step + * @RTCA3_ALRM_SSTEP_IRQ: two 1/64 periodic IRQs were generated step + * @RTCA3_ALRM_SSTEP_INIT: alarm setup initialization step + */ +enum rtca3_alrm_set_step { + RTCA3_ALRM_SSTEP_DONE = 0, + RTCA3_ALRM_SSTEP_IRQ = 1, + RTCA3_ALRM_SSTEP_INIT = 3, +}; + +/** + * struct rtca3_ppb_per_cycle - PPB per cycle + * @ten_sec: PPB per cycle in 10 seconds adjutment mode + * @sixty_sec: PPB per cycle in 60 seconds adjustment mode + */ +struct rtca3_ppb_per_cycle { + int ten_sec; + int sixty_sec; +}; + +/** + * struct rtca3_priv - RTCA3 private data structure + * @base: base address + * @rtc_dev: RTC device + * @rstc: reset control + * @set_alarm_completion: alarm setup completion + * @alrm_sstep: alarm setup step (see enum rtca3_alrm_set_step) + * @lock: device lock + * @ppb: ppb per cycle for each the available adjustment modes + * @wakeup_irq: wakeup IRQ + */ +struct rtca3_priv { + void __iomem *base; + struct rtc_device *rtc_dev; + struct reset_control *rstc; + struct completion set_alarm_completion; + atomic_t alrm_sstep; + spinlock_t lock; + struct rtca3_ppb_per_cycle ppb; + int wakeup_irq; +}; + +static void rtca3_byte_update_bits(struct rtca3_priv *priv, u8 off, u8 mask, u8 val) +{ + u8 tmp; + + tmp = readb(priv->base + off); + tmp &= ~mask; + tmp |= (val & mask); + writeb(tmp, priv->base + off); +} + +static u8 rtca3_alarm_handler_helper(struct rtca3_priv *priv) +{ + u8 val, pending; + + val = readb(priv->base + RTCA3_RSR); + pending = val & RTCA3_RSR_AF; + writeb(val & ~pending, priv->base + RTCA3_RSR); + + if (pending) + rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF); + + return pending; +} + +static irqreturn_t rtca3_alarm_handler(int irq, void *dev_id) +{ + struct rtca3_priv *priv = dev_id; + u8 pending; + + spin_lock(&priv->lock); + pending = rtca3_alarm_handler_helper(priv); + spin_unlock(&priv->lock); + + return IRQ_RETVAL(pending); +} + +static irqreturn_t rtca3_periodic_handler(int irq, void *dev_id) +{ + struct rtca3_priv *priv = dev_id; + u8 val, pending; + + spin_lock(&priv->lock); + + val = readb(priv->base + RTCA3_RSR); + pending = val & RTCA3_RSR_PF; + + if (pending) { + writeb(val & ~pending, priv->base + RTCA3_RSR); + + if (atomic_read(&priv->alrm_sstep) > RTCA3_ALRM_SSTEP_IRQ) { + /* Alarm setup in progress. */ + atomic_dec(&priv->alrm_sstep); + + if (atomic_read(&priv->alrm_sstep) == RTCA3_ALRM_SSTEP_IRQ) { + /* + * We got 2 * 1/64 periodic interrupts. Disable + * interrupt and let alarm setup continue. + */ + rtca3_byte_update_bits(priv, RTCA3_RCR1, + RTCA3_RCR1_PIE, 0); + readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, val, + !(val & RTCA3_RCR1_PIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + complete(&priv->set_alarm_completion); + } + } + } + + spin_unlock(&priv->lock); + + return IRQ_RETVAL(pending); +} + +static void rtca3_prepare_cntalrm_regs_for_read(struct rtca3_priv *priv, bool cnt) +{ + /* Offset b/w time and alarm registers. */ + u8 offset = cnt ? 0 : 0xe; + u8 i; + + /* + * According to HW manual (section 22.6.4. Notes on writing to and + * reading from registers) after writing to count registers, alarm + * registers, year alarm enable register, bits RCR2.AADJE, AADJP, + * and HR24 register, we need to do 3 empty reads before being + * able to fetch the registers content. + */ + for (i = 0; i < 3; i++) { + readb(priv->base + RTCA3_RSECCNT + offset); + readb(priv->base + RTCA3_RMINCNT + offset); + readb(priv->base + RTCA3_RHRCNT + offset); + readb(priv->base + RTCA3_RWKCNT + offset); + readb(priv->base + RTCA3_RDAYCNT + offset); + readw(priv->base + RTCA3_RYRCNT + offset); + if (!cnt) + readb(priv->base + RTCA3_RYRAREN); + } +} + +static int rtca3_read_time(struct device *dev, struct rtc_time *tm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + u8 sec, min, hour, wday, mday, month, tmp; + unsigned long flags; + u8 trials = 0; + u32 year100; + int ret = 0; + u16 year; + + spin_lock_irqsave(&priv->lock, flags); + + tmp = readb(priv->base + RTCA3_RCR2); + if (!(tmp & RTCA3_RCR2_START)) { + ret = -EINVAL; + goto unlock; + } + + do { + /* Clear carry interrupt. */ + rtca3_byte_update_bits(priv, RTCA3_RSR, RTCA3_RSR_CF, 0); + + /* Read counters. */ + sec = readb(priv->base + RTCA3_RSECCNT); + min = readb(priv->base + RTCA3_RMINCNT); + hour = readb(priv->base + RTCA3_RHRCNT); + wday = readb(priv->base + RTCA3_RWKCNT); + mday = readb(priv->base + RTCA3_RDAYCNT); + month = readb(priv->base + RTCA3_RMONCNT); + year = readw(priv->base + RTCA3_RYRCNT); + + tmp = readb(priv->base + RTCA3_RSR); + + /* + * We cannot generate carries due to reading 64Hz counter as + * the driver doesn't implement carry, thus, carries will be + * generated once per seconds. Add a timeout of 5 trials here + * to avoid infinite loop, if any. + */ + } while ((tmp & RTCA3_RSR_CF) && ++trials < 5); + + if (trials >= 5) { + ret = -ETIMEDOUT; + goto unlock; + } + + tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECCNT_SEC, sec)); + tm->tm_min = bcd2bin(FIELD_GET(RTCA3_RMINCNT_MIN, min)); + tm->tm_hour = bcd2bin(FIELD_GET(RTCA3_RHRCNT_HR, hour)); + tm->tm_wday = bcd2bin(FIELD_GET(RTCA3_RWKCNT_WK, wday)); + tm->tm_mday = bcd2bin(FIELD_GET(RTCA3_RDAYCNT_DAY, mday)); + tm->tm_mon = bcd2bin(FIELD_GET(RTCA3_RMONCNT_MONTH, month)) - 1; + year = FIELD_GET(RTCA3_RYRCNT_YEAR, year); + year100 = bcd2bin((year == 0x99) ? 0x19 : 0x20); + tm->tm_year = (year100 * 100 + bcd2bin(year)) - 1900; + +unlock: + spin_unlock_irqrestore(&priv->lock, flags); + return ret; +} + +static int rtca3_set_time(struct device *dev, struct rtc_time *tm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + unsigned long flags; + u8 rcr2, tmp; + int ret; + + spin_lock_irqsave(&priv->lock, flags); + + /* Stop the RTC. */ + rcr2 = readb(priv->base + RTCA3_RCR2); + writeb(rcr2 & ~RTCA3_RCR2_START, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + !(tmp & RTCA3_RCR2_START), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + goto unlock; + + /* Update time. */ + writeb(bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECCNT); + writeb(bin2bcd(tm->tm_min), priv->base + RTCA3_RMINCNT); + writeb(bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRCNT); + writeb(bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKCNT); + writeb(bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYCNT); + writeb(bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONCNT); + writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRCNT); + + /* Make sure we can read back the counters. */ + rtca3_prepare_cntalrm_regs_for_read(priv, true); + + /* Start RTC. */ + writeb(rcr2 | RTCA3_RCR2_START, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + (tmp & RTCA3_RCR2_START), + 10, RTCA3_DEFAULT_TIMEOUT_US); +unlock: + spin_unlock_irqrestore(&priv->lock, flags); + return ret; +} + +static int rtca3_alarm_irq_set_helper(struct rtca3_priv *priv, + u8 interrupts, + unsigned int enabled) +{ + u8 tmp, val; + + if (enabled) { + /* + * AIE, CIE, PIE bit indexes in RSR corresponds with + * those on RCR1. Same interrupts mask can be used. + */ + rtca3_byte_update_bits(priv, RTCA3_RSR, interrupts, 0); + val = interrupts; + } else { + val = 0; + } + + rtca3_byte_update_bits(priv, RTCA3_RCR1, interrupts, val); + return readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + ((tmp & interrupts) == val), + 10, RTCA3_IRQSET_TIMEOUT_US); +} + +static int rtca3_alarm_irq_enable(struct device *dev, unsigned int enabled) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + unsigned long flags; + int ret; + + spin_lock_irqsave(&priv->lock, flags); + ret = rtca3_alarm_irq_set_helper(priv, RTCA3_RCR1_AIE, enabled); + spin_unlock_irqrestore(&priv->lock, flags); + + return ret; +} + +static int rtca3_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + u8 sec, min, hour, wday, mday, month; + struct rtc_time *tm = &wkalrm->time; + unsigned long flags; + u32 year100; + u16 year; + + spin_lock_irqsave(&priv->lock, flags); + + sec = readb(priv->base + RTCA3_RSECAR); + min = readb(priv->base + RTCA3_RMINAR); + hour = readb(priv->base + RTCA3_RHRAR); + wday = readb(priv->base + RTCA3_RWKAR); + mday = readb(priv->base + RTCA3_RDAYAR); + month = readb(priv->base + RTCA3_RMONAR); + year = readw(priv->base + RTCA3_RYRAR); + + tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECAR_SEC, sec)); + tm->tm_min = bcd2bin(FIELD_GET(RTCA3_RMINAR_MIN, min)); + tm->tm_hour = bcd2bin(FIELD_GET(RTCA3_RHRAR_HR, hour)); + tm->tm_wday = bcd2bin(FIELD_GET(RTCA3_RWKAR_DAYW, wday)); + tm->tm_mday = bcd2bin(FIELD_GET(RTCA3_RDAYAR_DATE, mday)); + tm->tm_mon = bcd2bin(FIELD_GET(RTCA3_RMONAR_MON, month)) - 1; + year = FIELD_GET(RTCA3_RYRAR_YR, year); + year100 = bcd2bin((year == 0x99) ? 0x19 : 0x20); + tm->tm_year = (year100 * 100 + bcd2bin(year)) - 1900; + + wkalrm->enabled = !!(readb(priv->base + RTCA3_RCR1) & RTCA3_RCR1_AIE); + + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int rtca3_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + struct rtc_time *tm = &wkalrm->time; + unsigned long flags; + u8 rcr1, tmp; + int ret; + + spin_lock_irqsave(&priv->lock, flags); + + tmp = readb(priv->base + RTCA3_RCR2); + if (!(tmp & RTCA3_RCR2_START)) { + ret = -EPERM; + goto unlock; + } + + /* Disable AIE to prevent false interrupts. */ + rcr1 = readb(priv->base + RTCA3_RCR1); + rcr1 &= ~RTCA3_RCR1_AIE; + writeb(rcr1, priv->base + RTCA3_RCR1); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + !(tmp & RTCA3_RCR1_AIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + goto unlock; + + /* Set the time and enable the alarm. */ + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_min), priv->base + RTCA3_RMINAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONAR); + + writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRAR); + writeb(RTCA3_AR_ENB, priv->base + RTCA3_RYRAREN); + + /* Make sure we can read back the counters. */ + rtca3_prepare_cntalrm_regs_for_read(priv, false); + + /* Need to wait for 2 * 1/64 periodic interrupts to be generated. */ + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_INIT); + reinit_completion(&priv->set_alarm_completion); + + /* Enable periodic interrupt. */ + rcr1 |= RTCA3_RCR1_PIE; + writeb(rcr1, priv->base + RTCA3_RCR1); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + (tmp & RTCA3_RCR1_PIE), + 10, RTCA3_IRQSET_TIMEOUT_US); + + spin_unlock_irqrestore(&priv->lock, flags); + + if (ret) + goto setup_failed; + + /* Wait for the 2 * 1/64 periodic interrupts. */ + ret = wait_for_completion_interruptible_timeout(&priv->set_alarm_completion, + msecs_to_jiffies(500)); + if (ret <= 0) { + ret = -ETIMEDOUT; + goto setup_failed; + } + + spin_lock_irqsave(&priv->lock, flags); + ret = rtca3_alarm_irq_set_helper(priv, RTCA3_RCR1_AIE, wkalrm->enabled); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); + spin_unlock_irqrestore(&priv->lock, flags); + + return ret; + +setup_failed: + spin_lock_irqsave(&priv->lock, flags); + /* + * Disable PIE to avoid interrupt storm in case HW needed more than + * specified timeout for setup. + */ + writeb(rcr1 & ~RTCA3_RCR1_PIE, priv->base + RTCA3_RCR1); + readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, !(tmp & ~RTCA3_RCR1_PIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); +unlock: + spin_unlock_irqrestore(&priv->lock, flags); + + return ret; +} + +static int rtca3_read_offset(struct device *dev, long *offset) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + u8 val, radj, cycles; + unsigned long flags; + u32 ppb_per_cycle; + + spin_lock_irqsave(&priv->lock, flags); + radj = readb(priv->base + RTCA3_RADJ); + val = readb(priv->base + RTCA3_RCR2); + spin_unlock_irqrestore(&priv->lock, flags); + + cycles = FIELD_GET(RTCA3_RADJ_ADJ, radj); + + if (!cycles) { + *offset = 0; + return 0; + } + + if (val & RTCA3_RCR2_ADJP) + ppb_per_cycle = priv->ppb.ten_sec; + else + ppb_per_cycle = priv->ppb.sixty_sec; + + *offset = cycles * ppb_per_cycle; + val = FIELD_GET(RTCA3_RADJ_PMADJ, radj); + if (val == RTCA3_RADJ_PMADJ_SUB) + *offset = -(*offset); + + return 0; +} + +static int rtca3_set_offset(struct device *dev, long offset) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + int cycles, cycles10, cycles60; + unsigned long flags; + u8 radj, adjp, tmp; + int ret; + + /* + * Automatic time error adjustment could be set at intervals of 10 + * or 60 seconds. + */ + cycles10 = DIV_ROUND_CLOSEST(offset, priv->ppb.ten_sec); + cycles60 = DIV_ROUND_CLOSEST(offset, priv->ppb.sixty_sec); + + /* We can set b/w 1 and 63 clock cycles. */ + if (cycles60 >= -RTCA3_RADJ_ADJ_MAX && + cycles60 <= RTCA3_RADJ_ADJ_MAX) { + cycles = cycles60; + adjp = 0; + } else if (cycles10 >= -RTCA3_RADJ_ADJ_MAX && + cycles10 <= RTCA3_RADJ_ADJ_MAX) { + cycles = cycles10; + adjp = RTCA3_RCR2_ADJP; + } else { + return -ERANGE; + } + + radj = FIELD_PREP(RTCA3_RADJ_ADJ, abs(cycles)); + if (!cycles) + radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_NONE); + else if (cycles > 0) + radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_ADD); + else + radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_SUB); + + spin_lock_irqsave(&priv->lock, flags); + + tmp = readb(priv->base + RTCA3_RCR2); + + if ((tmp & RTCA3_RCR2_ADJP) != adjp) { + /* RADJ.PMADJ need to be set to zero before setting RCR2.ADJP. */ + writeb(0, priv->base + RTCA3_RADJ); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, !tmp, + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + goto unlock; + + rtca3_byte_update_bits(priv, RTCA3_RCR2, RTCA3_RCR2_ADJP, adjp); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + ((tmp & RTCA3_RCR2_ADJP) == adjp), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + goto unlock; + } + + writeb(radj, priv->base + RTCA3_RADJ); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, (tmp == radj), + 10, RTCA3_DEFAULT_TIMEOUT_US); + +unlock: + spin_unlock_irqrestore(&priv->lock, flags); + return ret; +} + +static const struct rtc_class_ops rtca3_ops = { + .read_time = rtca3_read_time, + .set_time = rtca3_set_time, + .read_alarm = rtca3_read_alarm, + .set_alarm = rtca3_set_alarm, + .alarm_irq_enable = rtca3_alarm_irq_enable, + .set_offset = rtca3_set_offset, + .read_offset = rtca3_read_offset, +}; + +static int rtca3_initial_setup(struct clk *clk, struct rtca3_priv *priv) +{ + unsigned long osc32k_rate; + u8 val, tmp, mask; + u32 sleep_us; + int ret; + + osc32k_rate = clk_get_rate(clk); + if (!osc32k_rate) + return -EINVAL; + + sleep_us = DIV_ROUND_UP_ULL(1000000ULL, osc32k_rate) * 6; + + priv->ppb.ten_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 10)); + priv->ppb.sixty_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 60)); + + /* + * According to HW manual (section 22.4.2. Clock and count mode setting procedure) + * we need to wait at least 6 cycles of the 32KHz clock after clock was enabled. + */ + usleep_range(sleep_us, sleep_us + 10); + + /* Disable all interrupts. */ + mask = RTCA3_RCR1_AIE | RTCA3_RCR1_CIE | RTCA3_RCR1_PIE; + ret = rtca3_alarm_irq_set_helper(priv, mask, 0); + if (ret) + return ret; + + mask = RTCA3_RCR2_START | RTCA3_RCR2_HR24; + val = readb(priv->base + RTCA3_RCR2); + /* Nothing to do if already started in 24 hours and calendar count mode. */ + if ((val & mask) == mask) + return 0; + + /* Reconfigure the RTC in 24 hours and calendar count mode. */ + mask = RTCA3_RCR2_START | RTCA3_RCR2_CNTMD; + writeb(0, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* + * Set 24 hours mode. According to HW manual (section 22.3.19. RTC Control + * Register 2) this needs to be done separate from stop operation. + */ + mask = RTCA3_RCR2_HR24; + val = RTCA3_RCR2_HR24; + writeb(val, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, (tmp & mask), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* Execute reset. */ + mask = RTCA3_RCR2_RESET; + writeb(val | RTCA3_RCR2_RESET, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask), + 10, RTCA3_RESET_TIMEOUT_US); + if (ret) + return ret; + + /* + * According to HW manual (section 22.6.3. Notes on writing to and reading + * from registers) after reset we need to wait 6 clock cycles before + * writing to RTC registers. + */ + usleep_range(sleep_us, sleep_us + 10); + + /* Set no adjustment. */ + writeb(0, priv->base + RTCA3_RADJ); + ret = readb_poll_timeout(priv->base + RTCA3_RADJ, tmp, !tmp, 10, + RTCA3_DEFAULT_TIMEOUT_US); + + /* Start the RTC and enable automatic time error adjustment. */ + mask = RTCA3_RCR2_START | RTCA3_RCR2_AADJE; + val |= RTCA3_RCR2_START | RTCA3_RCR2_AADJE; + writeb(val, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, ((tmp & mask) == mask), + 10, RTCA3_START_TIMEOUT_US); + if (ret) + return ret; + + /* + * According to HW manual (section 22.6.4. Notes on writing to and reading + * from registers) we need to wait 1/128 seconds while the clock is operating + * (RCR2.START bit = 1) to be able to read the counters after a return from + * reset. + */ + usleep_range(8000, 9000); + + /* Set period interrupt to 1/64 seconds. It is necessary for alarm setup. */ + val = FIELD_PREP(RTCA3_RCR1_PES, RTCA3_RCR1_PES_1_64_SEC); + rtca3_byte_update_bits(priv, RTCA3_RCR1, RTCA3_RCR1_PES, val); + return readb_poll_timeout(priv->base + RTCA3_RCR1, tmp, ((tmp & RTCA3_RCR1_PES) == val), + 10, RTCA3_DEFAULT_TIMEOUT_US); +} + +static int rtca3_request_irqs(struct platform_device *pdev, struct rtca3_priv *priv) +{ + struct device *dev = &pdev->dev; + int ret, irq; + + irq = platform_get_irq_byname(pdev, "alarm"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get alarm IRQ!\n"); + + ret = devm_request_irq(dev, irq, rtca3_alarm_handler, 0, "rtca3-alarm", priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to request alarm IRQ!\n"); + priv->wakeup_irq = irq; + + irq = platform_get_irq_byname(pdev, "period"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get period IRQ!\n"); + + ret = devm_request_irq(dev, irq, rtca3_periodic_handler, 0, "rtca3-period", priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to request period IRQ!\n"); + + /* + * Driver doesn't implement carry handler. Just get the IRQ here + * for backward compatibility, in case carry support will be added later. + */ + irq = platform_get_irq_byname(pdev, "carry"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get carry IRQ!\n"); + + return 0; +} + +static void rtca3_action(void *data) +{ + struct device *dev = data; + struct rtca3_priv *priv = dev_get_drvdata(dev); + int ret; + + ret = reset_control_assert(priv->rstc); + if (ret) + dev_err(dev, "Failed to de-assert reset!"); + + ret = pm_runtime_put_sync(dev); + if (ret < 0) + dev_err(dev, "Failed to runtime suspend!"); +} + +static int rtca3_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rtca3_priv *priv; + struct clk *clk; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; + + priv->rstc = devm_reset_control_get_shared(dev, NULL); + if (IS_ERR(priv->rstc)) + return PTR_ERR(priv->rstc); + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + ret = reset_control_deassert(priv->rstc); + if (ret) { + pm_runtime_put_sync(dev); + return ret; + } + + dev_set_drvdata(dev, priv); + ret = devm_add_action_or_reset(dev, rtca3_action, dev); + if (ret) + return ret; + + /* + * This must be an always-on clock to keep the RTC running even after + * driver is unbinded. + */ + clk = devm_clk_get_enabled(dev, "counter"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + spin_lock_init(&priv->lock); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); + init_completion(&priv->set_alarm_completion); + + ret = rtca3_initial_setup(clk, priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to setup the RTC!\n"); + + ret = rtca3_request_irqs(pdev, priv); + if (ret) + return ret; + + device_init_wakeup(&pdev->dev, 1); + + priv->rtc_dev = devm_rtc_allocate_device(&pdev->dev); + if (IS_ERR(priv->rtc_dev)) + return PTR_ERR(priv->rtc_dev); + + priv->rtc_dev->ops = &rtca3_ops; + priv->rtc_dev->max_user_freq = 256; + priv->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000; + priv->rtc_dev->range_max = RTC_TIMESTAMP_END_2099; + + return rtc_register_device(priv->rtc_dev); +} + +static int rtca3_suspend(struct device *dev) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + + if (!device_may_wakeup(dev)) + return 0; + + /* Alarm setup in progress. */ + if (atomic_read(&priv->alrm_sstep) != RTCA3_ALRM_SSTEP_DONE) + return -EBUSY; + + enable_irq_wake(priv->wakeup_irq); + + return 0; +} + +static int rtca3_clean_alarm(struct rtca3_priv *priv) +{ + struct rtc_device *rtc_dev = priv->rtc_dev; + time64_t alarm_time, now; + struct rtc_wkalrm alarm; + unsigned long flags; + struct rtc_time tm; + u8 pending; + int ret; + + ret = rtc_read_alarm(rtc_dev, &alarm); + if (ret) + return ret; + + if (!alarm.enabled) + return 0; + + ret = rtc_read_time(rtc_dev, &tm); + if (ret) + return ret; + + alarm_time = rtc_tm_to_time64(&alarm.time); + now = rtc_tm_to_time64(&tm); + if (alarm_time >= now) + return 0; + + /* + * Heuristically, it has been determined that when returning from deep + * sleep state the RTCA3_RSR.AF is zero even though the alarm expired. + * Call again the rtc_update_irq() if alarm helper detects this. + */ + + spin_lock_irqsave(&priv->lock, flags); + + pending = rtca3_alarm_handler_helper(priv); + if (!pending) + rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF); + + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int rtca3_resume(struct device *dev) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + + if (!device_may_wakeup(dev)) + return 0; + + disable_irq_wake(priv->wakeup_irq); + + /* + * According to the HW manual (section 22.6.4 Notes on writing to + * and reading from registers) we need to wait 1/128 seconds while + * RCR2.START = 1 to be able to read the counters after a return from low + * power consumption state. + */ + mdelay(8); + + /* + * The alarm cannot wake the system from deep sleep states. In case + * we return from deep sleep states and the alarm expired we need + * to disable it to avoid failures when setting another alarm. + */ + return rtca3_clean_alarm(priv); +} + +static SIMPLE_DEV_PM_OPS(rtca3_pm_ops, rtca3_suspend, rtca3_resume); + +static const struct of_device_id rtca3_of_match[] = { + { .compatible = "renesas,rz-rtca3", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rtca3_of_match); + +static struct platform_driver rtca3_platform_driver = { + .driver = { + .name = "rtc-rtca3", + .pm = pm_ptr(&rtca3_pm_ops), + .of_match_table = rtca3_of_match, + }, + .probe = rtca3_probe, +}; +module_platform_driver(rtca3_platform_driver); + +MODULE_DESCRIPTION("Renesas RTCA-3 RTC driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); From patchwork Wed Jan 22 11:52:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947198 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8760DC0218C for ; Wed, 22 Jan 2025 11:52:50 +0000 (UTC) Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) by mx.groups.io with SMTP id smtpd.web10.41913.1737546767994711193 for ; Wed, 22 Jan 2025 03:52:48 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=Wb4wlZsl; spf=pass (domain: tuxon.dev, ip: 209.85.128.43, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-4361f65ca01so69948605e9.1 for ; Wed, 22 Jan 2025 03:52:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737546766; x=1738151566; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7HPzZZCLSVbtc4np5bDYcl3oLJxIAIKhjbJRvMNwAW0=; b=Wb4wlZslTV6njyzpsmwbSYexXPhprLgo4EUD9PPSI8ESsSel3dXdMEObFgVHRHKlvO owakedk52cHlroE0uiYJC/uf4/+tqRR0S4dKwKo/m2J5AlDr7hkbRHyFdtgEFHCa7miS 6XrWABVcQ3zsuJFo/Z7414D2t7iJupnstIywX5VvX2IzFqG+CqWv0t4ZON9rI4Sj7+aM Tzg7GA/pMMol7Tflp/iWxBvYBxG+aRILdEAmB0MCSREEf+7tqazTlMZ5UmtoWO9cgHEl AV7ISuGAMLgpqwKJO8Dp2FX9WxGiPpR+LgpMKWIZLUIXKUjZ87xXstThfRFvwySJyxbb WMIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737546766; x=1738151566; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7HPzZZCLSVbtc4np5bDYcl3oLJxIAIKhjbJRvMNwAW0=; b=LLFIfpbcV3MZ/epb4KqfFVQZH9r4NXgCdKqEkRmc4sZlF8SYNWPz0C0dx2XsgvjbYJ Wwr3i1mRCRav4p/kl6gRTUptTOCXbe3nqBh1+Yxo0Cy5HjA7bR3Oalk0/X4O0A5uVyHx vqjelbEhKlZ2yBlIKHEiuqdyZ2nGcju4PYUuVXyO5Mz2EEXGCCVMJ9QavfkEWY1a12ky 7bFclC07bWDk3HnSoS8AnPD74ftYM9hPo+a62GcqGIMmZ9H4ktYRKMl8/NG5bwqhjWIP cnSFjHkS8n3IZRhqj63rYWFnq1cLmFdwEgvT6CL8v2NjJTelaZ/o2RImgYJUngnJNVMa mpUA== X-Forwarded-Encrypted: i=1; AJvYcCUWYJb6H+q9HiUS4/UcvZinlE9eqwAUrGcoJj4ACV/CyRyZa5a8VO6Eu1b2hvPChP0Jo8YoA5QC@lists.cip-project.org X-Gm-Message-State: AOJu0YzDSGHpKykXz2fhQmIP3Tpq1GF2cdzHgJg5aZhkcv0PminYx4yL GrufSopX05IpBvJQla2PP/elInW41T1ytfx4RoI9QyoLarzI4DZTphUjcHCK/hM= X-Gm-Gg: ASbGncvTIj7xwDIsLNPgr585XCC3MQJTc3BR086LpvPM5CFBIhxP6w0R6q50Wxoqbix boCQspbL6N5363peWNAJ6WfnzWqUDKgl8u8qDGvZOlug44jnAJSAcgxv/e8Qa1kxCZp9BzYbydC sPMA2ooH1NlIfS6Ars6Vj680081vWNLAwwvpDzkMRDnLu/jN0r6veeO1+8ljCjjZBezzSfgQ3qZ wMXE7Flzu4e54P08HKswipO70gg/FEOSoTwtR879MRpb8a3N5wCUse5MuOL5HYhNfw7wJDzFO8T HITXCOm9C6FNQaAoBb0+lZo= X-Google-Smtp-Source: AGHT+IGuQISCj7D0unMOLbt091WOqEYOutAXEKjhTGCDumCXxDah78RiHXd+3mC5MlIsHUFLtsvfBA== X-Received: by 2002:a05:600c:468e:b0:436:5165:f1ec with SMTP id 5b1f17b1804b1-4389143145bmr202336945e9.30.1737546766391; Wed, 22 Jan 2025 03:52:46 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b318990esm22887415e9.7.2025.01.22.03.52.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:52:45 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip 11/16] rtc: renesas-rtca3: Fix compilation error on RISC-V Date: Wed, 22 Jan 2025 13:52:25 +0200 Message-ID: <20250122115230.2885344-12-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:52:50 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17589 From: Claudiu Beznea commit 8f315a5c7376b2bc324d62a8400184da77f25e28 upstream. Fix the following compilation errors when building the RTCA3 for RISCV: ../drivers/rtc/rtc-renesas-rtca3.c:270:23: error: call to undeclared function 'FIELD_GET'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 270 | tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECCNT_SEC, sec)); | ^ ../drivers/rtc/rtc-renesas-rtca3.c:369:23: error: call to undeclared function 'FIELD_GET'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 369 | tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECAR_SEC, sec)); | ^ ../drivers/rtc/rtc-renesas-rtca3.c:476:11: error: call to undeclared function 'FIELD_GET'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 476 | cycles = FIELD_GET(RTCA3_RADJ_ADJ, radj); | ^ ../drivers/rtc/rtc-renesas-rtca3.c:523:9: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 523 | radj = FIELD_PREP(RTCA3_RADJ_ADJ, abs(cycles)); | ^ ../drivers/rtc/rtc-renesas-rtca3.c:658:8: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 658 | val = FIELD_PREP(RTCA3_RCR1_PES, RTCA3_RCR1_PES_1_64_SEC); | ^ Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20241101095720.2247815-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Alexandre Belloni [claudiu.beznea: fixed conflict] Signed-off-by: Claudiu Beznea --- drivers/rtc/rtc-renesas-rtca3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/rtc/rtc-renesas-rtca3.c b/drivers/rtc/rtc-renesas-rtca3.c index 5a8dd2ad6b60..e3a9bb16b1ec 100644 --- a/drivers/rtc/rtc-renesas-rtca3.c +++ b/drivers/rtc/rtc-renesas-rtca3.c @@ -5,6 +5,7 @@ * Copyright (C) 2024 Renesas Electronics Corp. */ #include +#include #include #include #include From patchwork Wed Jan 22 11:52:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947199 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94AE9C02191 for ; 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([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b318990esm22887415e9.7.2025.01.22.03.52.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:52:47 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip 12/16] arm64: dts: renesas: r9a08g045: Add VBATTB node Date: Wed, 22 Jan 2025 13:52:26 +0200 Message-ID: <20250122115230.2885344-13-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:52:50 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17590 From: Claudiu Beznea commit 23c44956bce5aa79c060fc3e5d51843735e6eda6 upstream. Add the DT node for the VBATTB IP along with DT bindings for the clock it provides. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-6-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [claudiu.beznea: the backported patch has references for i2c nodes; the i2c nodes are not available in v5.10 cip, thus fixed conflict by dropping the i2c nodes] Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index f5f3f4f4c8d6..7bc8969a7b5a 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -72,6 +72,18 @@ scif0: serial@1004b800 { status = "disabled"; }; + vbattb: clock-controller@1005c000 { + compatible = "renesas,r9a08g045-vbattb"; + reg = <0 0x1005c000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; + clock-names = "bclk", "rtx"; + #clock-cells = <1>; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + status = "disabled"; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a08g045-cpg"; reg = <0 0x11010000 0 0x10000>; @@ -296,4 +308,11 @@ timer { <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; + + vbattb_xtal: vbattb-xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; }; From patchwork Wed Jan 22 11:52:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947204 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 909A0C02181 for ; Wed, 22 Jan 2025 11:53:00 +0000 (UTC) Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) by mx.groups.io with SMTP id smtpd.web11.41716.1737546770537758660 for ; Wed, 22 Jan 2025 03:52:50 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=Fo4j5HB8; spf=pass (domain: tuxon.dev, ip: 209.85.128.50, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-43618283d48so48740235e9.1 for ; Wed, 22 Jan 2025 03:52:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737546769; x=1738151569; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=avEm0xWoaPOuBqma5bKPsWNEysSf4Ic0Xdn9jpjXkLw=; b=Fo4j5HB8XZ3ngO3qmCfaC2mXY4j6FR/airBupD74Kz1K5hd/9DlDIH92JbKhqVVH+K acqbkX5d16C83MikdOWSsIRyTGUjlTerorRy14rHsc/IpTo/LkBaB4VbzdrIvgy63ra5 X7DArPFHK0KLGVyaU6BvILypkVzbFeNWCeTiINOI4kk+U+QrU4NIJc0wq/avGyfcly9d sFxwHVe2VTpjxXA0zGabzygJ51u3OfnauQECeRWHqXpCS+Mo47K8az7x1D9TkU/XgSOj B0gKSADPxh366hPt1i5woC5FZjjzmZPwdKOh0PkrOZ86PLSwYH9lHyuj07sJ/CUpftPU I30w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737546769; x=1738151569; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=avEm0xWoaPOuBqma5bKPsWNEysSf4Ic0Xdn9jpjXkLw=; b=bTMm3gf4XrIuJ9Xgwx3wsNdCvdliCzM1ZYg0bh7rOl7Zt76gsWCsYUANJfHWSsHfQx cIhHFy4mFmRpy6Ms4CB6kqE47ZiJ6iyhFKW5ieD5DFutWSWW++RQ4sW4Rjj81Q1TOgCG rK/IqrCrueBFDyQAz1Ewsae9/kbIE5eBVcykNQQIP4Gji94YaXf0ZHbi/UiV1Qh3vBQu rE0sUpADY1iT1aZKpKCLDhDoDPy5toj2eGDNbEEXL6ZYCKVYzbmDesMYJFVHX5se4EGG MqGqDEltMC8fICygtr6drkPPipLbCrYlj2z+nJKwcUbmN0eG2GwyzZs6L8mbDy2+QTX+ UjkQ== X-Forwarded-Encrypted: i=1; AJvYcCU2QWRDQVaffcmGH/mkSgtCWBeonEn6R9seQiT7hsqD2o+HlUIBiizF+qSx2rROE0eq/LPtew1p@lists.cip-project.org X-Gm-Message-State: AOJu0YyDDfT8zokIAI+oOM7A46Zlpf/vAbKzbfkxyTpN2B4VwueBmIv2 HjjaDnwN+c0R2HAqx0qv9efDzqI/8BfMIqf/1B853OZptBDUoGB+1CtfYb2tBGM= X-Gm-Gg: ASbGnctpTW5CwgSGQc//2CPjN0Y56x82kurfVFDYfDoeWuz7okS3+klPGuTA9jHoPxk /Wy1+wSFVGM+nXRNbEhkHeh1SQ5G9r4HSatxy4UkAczrwUAoc/j0hEkde89/v2hLwihEmX1S5y9 Q7h2Dz+pXfN1v45h0Mf/dQBlq9lj3wGE9Gw7nX5VV5bb6KTE8IGyrQdokBm3xYk/88iMZEyNhJh aHY/32g/OtwZngvVf/888hjxiApI2krQz6Wag7m0nTdYhMk1QuPQsex2HcX/s2ehw4J3P49iSMS u8qbOexmpUWD7mdCzDgpXMY= X-Google-Smtp-Source: AGHT+IHgrl8GicoUYf+PQ5aXmXNuuno74Fo+6b5NVLzvjXpHKWJrsJoVDyzSe+rwrI/FJKZOZuTJ3A== X-Received: by 2002:a05:600c:3420:b0:436:f3f6:9582 with SMTP id 5b1f17b1804b1-438913cb729mr206286335e9.8.1737546768989; Wed, 22 Jan 2025 03:52:48 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b318990esm22887415e9.7.2025.01.22.03.52.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:52:48 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip 13/16] arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB Date: Wed, 22 Jan 2025 13:52:27 +0200 Message-ID: <20250122115230.2885344-14-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:53:00 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17591 From: Claudiu Beznea commit ac948eb8ead1265ff034955bdbbb081744f1e7ed upstream. Enable the VBATTB controller. It provides the clock for RTC. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-8-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index acac4666ae59..67178d8c4108 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2023 Renesas Electronics Corp. */ +#include #include #include @@ -341,6 +342,17 @@ mux { }; }; +&vbattb { + assigned-clocks = <&vbattb VBATTB_MUX>; + assigned-clock-parents = <&vbattb VBATTB_XC>; + quartz-load-femtofarads = <12500>; + status = "okay"; +}; + +&vbattb_xtal { + clock-frequency = <32768>; +}; + &wdt0 { timeout-sec = <60>; status = "okay"; From patchwork Wed Jan 22 11:52:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947205 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97EE8C0218D for ; Wed, 22 Jan 2025 11:53:00 +0000 (UTC) Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) by mx.groups.io with SMTP id smtpd.web11.41717.1737546771791624648 for ; Wed, 22 Jan 2025 03:52:52 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=hI3RV+t0; spf=pass (domain: tuxon.dev, ip: 209.85.128.51, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-43621d27adeso46603165e9.2 for ; Wed, 22 Jan 2025 03:52:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737546770; x=1738151570; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QT9gIUiudDAAdT7+/KwLCRVApT8O0rjggfgBvSy6a4o=; b=hI3RV+t0nGPa4NwnZKWSgOlPLA5f0RltzXKGzySgJmYJChEYddf07S3Hr/AOo8TKc6 v4I2XvrBf3g7+9jvNMtu8EbeLAKtqHG4Kp1LhsZgJFAQNdCyAUwYAzl8DeP7IXIMxHJI uPXplcoM4HvteCYAnUOWHl1+3bnJFTb8XhdkSRyclP5zs6PhpYmUsaCYbqH3EaEGi4ay L2FeESdq6Y6iQIFFttnHklBN4f1/8dx3iWd02OlOhe+evA0Ns/uWAGKV2gx6JNR/CIQh cVSdtTgJM0r8uqg0GeLZAizDGfUUic16/AbLFKSzXWu7LJN7TCkToRuydEAYDARzu4jB V79w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737546770; x=1738151570; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QT9gIUiudDAAdT7+/KwLCRVApT8O0rjggfgBvSy6a4o=; b=jTfxUMXPeYwlcogAaqY8/J/a8+NP0CZFfH59KgS1l2pXXcyPaDAyAMHUpFcE+Qz/Gw nee1osNXEIR+kfDiGvb2yXd5puwjr6aXMuxvU5XEhthOxN891axvSAvZZIflf9HyUvRR bX0XS5nvgvxvPKn+9cLqcr/Nm180+IJ6VVaO4SbnlJUdVqPLipAqttG5KkT3pHhYfNPX q+pvQiVRTJarJHsScM+YTW+16tZmtIGUyq8f7Qvk7zmQKh1mJsBTkIm4r81Rjcoh4AMW aKgKbL3n/oampbHH71RlqIbLnljfluxK2AnWDii2Km6R1e6C6lQkunhqRFIxMPvdStnq W8yA== X-Forwarded-Encrypted: i=1; AJvYcCUEgcnvZF9Vaavp/32kvXNctcXR67onvo4UxYWKdaEG1VGphF7/Hfr0bnfjRClCqxoov2iHIwlv@lists.cip-project.org X-Gm-Message-State: AOJu0Yy95SwkADZ1o7tC1zhXwpHm3/BvSIJQIZP+vaeIEqAUZOqFX3Wu tZyYg3j34auX1JVufW3nkq9Ee0NLBOZ9m27LV31D+6h1pe1VZDJAwTb9cSn2kYVRr5WAAVzmDDX k X-Gm-Gg: ASbGnctWzJDqU7vbKjFxDJ3X2sfrc5cFDJ7ExWJ//+TZbcg4YR2eBr2sIvSVhwxA1Ma B1zqn3Lj8Z8spmPV7dV/EAbns4KpQFRqifijYsICfH5OLn+lQ12+RKdQdcU9jSsHflio7PkpFUg gFBzk3HMKJ34wjqkCsZ1mlAahjAyghNyrAO9/+QmhWlFyCOo1waBPGz7leLXQlW7lWUuQCC29dP ISd+2EGKH/HxrCTr/SWveLMCjUl23hINqIWB1VRWmQ+NVGeljcHgRztmvS383tglnV/7gJQTP0z Ap9XUxV9qgoRJS1VURvELAQ= X-Google-Smtp-Source: AGHT+IFR+U5oP4L1kFyCNZhfsDHBTpYE5eY7ZYsP/zGjFqnEiQZBxHoB3gNmyxc6iVbN+p5L+k1OXA== X-Received: by 2002:a05:600c:450d:b0:436:840b:261c with SMTP id 5b1f17b1804b1-438914340afmr177955635e9.19.1737546770228; Wed, 22 Jan 2025 03:52:50 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b318990esm22887415e9.7.2025.01.22.03.52.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:52:49 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip 14/16] arm64: dts: renesas: r9a08g045: Add RTC node Date: Wed, 22 Jan 2025 13:52:28 +0200 Message-ID: <20250122115230.2885344-15-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:53:00 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17592 From: Claudiu Beznea commit 2d768aee9f5294d2023e824c0906e2e7d1414629 upstream. Add the DT node for the RTC IP available on the Renesas RZ/G3S SoC. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-7-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 7bc8969a7b5a..3401c1200a1c 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -7,6 +7,7 @@ #include #include +#include / { compatible = "renesas,r9a08g045"; @@ -72,6 +73,20 @@ scif0: serial@1004b800 { status = "disabled"; }; + rtc: rtc@1004ec00 { + compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; + reg = <0 0x1004ec00 0 0x400>; + interrupts = , + , + ; + interrupt-names = "alarm", "period", "carry"; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb VBATTB_VBATTCLK>; + clock-names = "bus", "counter"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + status = "disabled"; + }; + vbattb: clock-controller@1005c000 { compatible = "renesas,r9a08g045-vbattb"; reg = <0 0x1005c000 0 0x1000>; From patchwork Wed Jan 22 11:52:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947207 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0F04C0218C for ; Wed, 22 Jan 2025 11:53:00 +0000 (UTC) Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) by mx.groups.io with SMTP id smtpd.web11.41718.1737546772836929301 for ; Wed, 22 Jan 2025 03:52:53 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=gbCT/GDd; spf=pass (domain: tuxon.dev, ip: 209.85.128.41, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-4368a293339so77917665e9.3 for ; Wed, 22 Jan 2025 03:52:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737546771; x=1738151571; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rZ/lXKoSkUmuSxtM2ry8mqYHW2bCm5mIiSIX1gifECs=; b=gbCT/GDdG2cPk0Ua6sIvUmby2cPTtIdbnGsgRFz7BRZRqQnYo1LZ1tZ2/1Wxk54OfP 1BOhqFfmiQl6j1sMFz96/jKxQwy8EDhoJJqrgDoQkupwrHY69ZO66GmM4MMZA1Xk5OXP XbapYUj0XHv61xC9hrb7lc1WifMVLyG7X8+f8hCTX+PaYM9K0D5oZgtF90faUYpT+4Cn v29PosQTfG5FuEK7I9YHTyb44HgMWgD8T021Y1AA8g+eWZPEDrA/9Zd1GI3GvCr/gsXR ij6NGdA4URemoG1ErmGE6GZkUXc0oJWIphURylakKUYrAu3BvGRffpm/MS0/hJ9JBG4L vmKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737546771; x=1738151571; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rZ/lXKoSkUmuSxtM2ry8mqYHW2bCm5mIiSIX1gifECs=; b=uanAA9vSKe0bemFlcOMCcA2PZ3Br553JREL+YqED0x+BD/qYTr3fQxK3HdbNrEOM3y aJ5wVncw7fvYUjOD3s6PFYS1sMDUV0CA2gT++iVot6uoJ3SOPr5zsiden8jBeYG/7KuX Q4N5fvKE0DNnWOtI5S215vlJSs8E+5vSG9VDNH5izv3bUvQ1NL0CHwqbUTkeqW6MUoSU NPjNsY+J3yfHdmsmfYueH6u+schG9j31/fIA9gWSWeFOLTJPFc49mNLOSk24FUdQjZlD pUIraej2iavSWY7EimthtYQQuqenGGWlTzzFjgMuMQuXJnPxsMkuQSGtB9moEVOBGGLh hHqA== X-Forwarded-Encrypted: i=1; AJvYcCX3RN2dFM2WHHYyPgcuvqanFksxrm2PyLKzC17o57s1ayt3Xy7ti+cV/4krFO2/fRr8hhfCRbTM@lists.cip-project.org X-Gm-Message-State: AOJu0Yy3j26LCf+Qr+nqAWjZwdQbN3dvHwbc+9hP3b7t+pHekHhPigEb PacEMhgbHBpbxJgaT+jk4YT/uzleLHOdu8AK3jVR7lkVXjWpMGINbkMSiYRXbM2odRZI/eHne4W t X-Gm-Gg: ASbGncsFs05CSiyonUQDW8dlBe2ZHT3dfQC82Q/2d5m24aeczZIaeiM1R1yeI0BT+1Q otFMuoTfIg5uNlzRolUC2nZfcEnEy3SNcai7eNjODbgqcpEA30QT8LdTEdkP7L7fZvpewQ5ypsl 91w11XSTXdyNJQ6QDI5P/EwerQnYkwPMm0Wmc1vkKvf0togLtexvtJtAv5UNgiYpgA79nBBbJMi y8HmFhNc8jzLm21z5RcrkMXf0pUqGxlsv8TnBnF8itoBjUfD0bxjxLfHRnT27f7VYnBxHRlUNNN ppXmrfX/L4iRO4G/Gse2IAI= X-Google-Smtp-Source: AGHT+IGypMvfvxMefeHG3AOQJme8FWutTvv+a+kEgV0QSm9qilFwgraYggo1GGMpfSDn/YOyx4cZ5Q== X-Received: by 2002:a05:600c:1988:b0:434:fddf:5bfa with SMTP id 5b1f17b1804b1-438913bf072mr190379275e9.2.1737546771293; Wed, 22 Jan 2025 03:52:51 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b318990esm22887415e9.7.2025.01.22.03.52.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:52:50 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip 15/16] arm64: dts: renesas: rzg3s-smarc-som: Enable RTC Date: Wed, 22 Jan 2025 13:52:29 +0200 Message-ID: <20250122115230.2885344-16-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:53:00 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17593 From: Claudiu Beznea commit 0cd647cd53db0315361e41056e10739a5ee1e668 upstream. Enable RTC. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-9-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 67178d8c4108..b07d9251d182 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -342,6 +342,10 @@ mux { }; }; +&rtc { + status = "okay"; +}; + &vbattb { assigned-clocks = <&vbattb VBATTB_MUX>; assigned-clock-parents = <&vbattb VBATTB_XC>; From patchwork Wed Jan 22 11:52:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13947206 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90D46C02182 for ; Wed, 22 Jan 2025 11:53:00 +0000 (UTC) Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) by mx.groups.io with SMTP id smtpd.web11.41719.1737546774104889205 for ; Wed, 22 Jan 2025 03:52:54 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=jjTKkGbl; spf=pass (domain: tuxon.dev, ip: 209.85.128.47, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-43634b570c1so49589425e9.0 for ; Wed, 22 Jan 2025 03:52:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737546772; x=1738151572; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KiWwby+0nhz5r1URk4IPI41lZP5NmYIaMigly9M0E/E=; b=jjTKkGbli8BAqF9e39KfTVuDmxQZdEjNfqo7DOwOofK62huaVQfLHh6mWpd0QxadzO WE+/alo8F7ib3riQpKI38yZ+zqptG0jGSfls4JvOXAfaYWqovXzPlZLHbLwb58Gb2FS/ 8V4mBMKh7JYnCqwPIHhglEdkjVfZkwWik8lBP8Hd4lRXeQiHVOCNyidyiwk4GJi795Uc 4oRYXGHAycPpQ8MzchhEWWqPTdRjPQCSJU9GfBaZaIyK2q2bW6oEzQDyInTZLP+xF/gh EOREVhKgdevp9JvfuOf1zOfASksUAMxuPa7XqSMDGAr8aN+nS1wNIZbI87U6q76DGAqS mXBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737546772; x=1738151572; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KiWwby+0nhz5r1URk4IPI41lZP5NmYIaMigly9M0E/E=; b=cjpMpqVx1ZshN1kCsDhuO3Oljg/kUgBqhrw5/c4K+dGzDWEDWG/UjZJjy62RaOuyrh baAIGqZ9X5fX7TxYSvVGrYk7vjwReo7pSwg+zZ8I7GFM1qaof+RUmyuEthUTliNV+Z+c RKeH8FHPar4+xXMVRezAPm65mfS3hHBU/eN4KCUtyEsWGhERhFsxSMuIp02HLTksrKIQ 2yXbogxS0MKjQO3Mum4PabWnWw05MNOACsiCt7C20xKU/isF46tqcmBWTFiLb0Ug3/Md kN/Daj5/H1hkTodhgUT97NYXqCi15BeczncOOHrmdoL67QPuDkQesJs7AAVlrsmNHCTC PVrg== X-Forwarded-Encrypted: i=1; AJvYcCUjd7owzaq2WAc5Dl38jZa/M1CPaIxG7V8k6Z5vzEqxraRy2rA3PQqB1Hi1/quw0rH33px1eo2r@lists.cip-project.org X-Gm-Message-State: AOJu0YwlBDFPeVv91qkGg0t3RY42stcYoiKgDAsHeD7GFzZOfWkvewrW dbQ9BS7tiXECRWnRhuuG4NMAaiVngTaBzP8Ecv+bVMS8ozKxfi5aI6aWUiiO/w8= X-Gm-Gg: ASbGncs6y1P16FFmy1JLPtMBS7bjir9bsGnlmms3M84MMOFTVrDA+2VGNcgL4hgySwU 9jYIHWMzvFFpO3Js1in/m3+sw4iz2ml+di40yFudu4Wh/mdnFQcycivXM/7I0h+NZoNunX7pV3N VUA+96xGm0fk5yam0I0z5yMtZF7ZuymezPSCw8HaWqIgxV8zZ+lAA3Sk5GSsS1yCID+mn7qvc6j USJt2d9xpHbGa7Ot039hoKCsvRM/FBA9G3kbHhTwQhqGuM5F7ol7o8zg0jETmILNgKESoSheesK ueSAMAUe11HXi8RDBiQrTeI= X-Google-Smtp-Source: AGHT+IGZlVBqhuKqMflo0EoiEMPy/uQusgp2X/zmywzZyO1oiBvxSyzKcpvkHhKqCG2F70v4FciCaA== X-Received: by 2002:a05:600c:4f42:b0:434:fa55:eb56 with SMTP id 5b1f17b1804b1-438913cf805mr206261185e9.7.1737546772490; Wed, 22 Jan 2025 03:52:52 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438b318990esm22887415e9.7.2025.01.22.03.52.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 03:52:51 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip 16/16] arm64: defconfig: Enable VBATTB clock and Renesas RTCA-3 Date: Wed, 22 Jan 2025 13:52:30 +0200 Message-ID: <20250122115230.2885344-17-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> References: <20250122115230.2885344-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 22 Jan 2025 11:53:00 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17594 From: Claudiu Beznea commit c520bbb523304ba98de9ffeeb0ef289921434125 upstream. Enable the Renesas VBATTB clock and RTCA-3 RTC drivers. These are available on the Renesas RZ/G3S SoC. VBATTB is the clock provider for the RTC counter. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-10-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [claudiu.beznea: fixed conflict by keeping only RTC and VBATTB flags] Signed-off-by: Claudiu Beznea --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 297d671306ce..14a6a6978714 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -854,6 +854,7 @@ CONFIG_RTC_DRV_TEGRA=y CONFIG_RTC_DRV_SNVS=m CONFIG_RTC_DRV_IMX_SC=m CONFIG_RTC_DRV_XGENE=y +CONFIG_RTC_DRV_RENESAS_RTCA3=m CONFIG_DMADEVICES=y CONFIG_DMA_BCM2835=y CONFIG_DMA_SUN6I=m @@ -926,6 +927,7 @@ CONFIG_SM_GCC_8250=y CONFIG_SM_GPUCC_8150=y CONFIG_SM_GPUCC_8250=y CONFIG_QCOM_HFPLL=y +CONFIG_CLK_RENESAS_VBATTB=m CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y CONFIG_RENESAS_OSTM=y