From patchwork Wed Jan 22 15:17:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13947417 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A89EFC0218C for ; Wed, 22 Jan 2025 15:18:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 536B310E6FF; Wed, 22 Jan 2025 15:18:02 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="SsXY6CAN"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2F22E10E6FF; Wed, 22 Jan 2025 15:18:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737559081; x=1769095081; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zCazrzVqMuxDVcgaZqw5QSHfuCjqMp68vWHbHVMEQtU=; b=SsXY6CANXl2SpwxFZG2Bz1slkPKQtkY00dhxB2mfGIjSBJW/3YRuKogk Abb57RxJ/jo1asckFa0fqnoimp55lXJTDIcytnFZo3UpDsaEKeZtefR0H zaCoI5gwrQNIQsDFqOZLNMJXpebBEkE98HX2OtSnSf1KV1Rv/mxIGZybN ypT3Mfq1FXp18uSEH7eBl3+XFCOy0enRhi+S4ZJe5XDOkT3CzSLhJUHmo FHrGWaEbFqb9CWts2TKaL5LIg0ik2j446e1VlMRx41qVaOTm7jxHkcnsD 19kwn+P4GJgzbIjkJSllvkuKoCdLO6/YomTqgLie0muPIPzzg5U529mut w==; X-CSE-ConnectionGUID: iWKVv8TJQWW840OkoP7eqA== X-CSE-MsgGUID: ba2B0cUPTJ+0lENspTJBug== X-IronPort-AV: E=McAfee;i="6700,10204,11323"; a="40841178" X-IronPort-AV: E=Sophos;i="6.13,225,1732608000"; d="scan'208";a="40841178" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2025 07:18:01 -0800 X-CSE-ConnectionGUID: +tcDhNDBRLWuaePBNVhjkw== X-CSE-MsgGUID: fVe6b2vCSBq86i6GnR23Dg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,225,1732608000"; d="scan'208";a="107274688" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 22 Jan 2025 07:17:59 -0800 Received: by stinkbox (sSMTP sendmail emulation); Wed, 22 Jan 2025 17:17:58 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH 1/5] drm/i915: Move VT-d alignment into plane->min_alignment() Date: Wed, 22 Jan 2025 17:17:51 +0200 Message-ID: <20250122151755.6928-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250122151755.6928-1-ville.syrjala@linux.intel.com> References: <20250122151755.6928-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Currently we don't account for the VT-d alignment w/a in plane->min_alignment() which means that panning inside a larger framebuffer can still cause the plane SURF to be misaligned. Fix the issue by moving the VT-d alignment w/a into plane->min_alignment() itself (for the affected platforms). Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/i9xx_plane.c | 10 ++++++++++ drivers/gpu/drm/i915/display/intel_cursor.c | 5 +++++ drivers/gpu/drm/i915/display/intel_fb_pin.c | 8 -------- drivers/gpu/drm/i915/display/intel_sprite.c | 5 +++++ drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++++ 5 files changed, 24 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index ed171fbf8720..19cc34babef3 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -780,9 +780,14 @@ unsigned int vlv_plane_min_alignment(struct intel_plane *plane, const struct drm_framebuffer *fb, int color_plane) { + struct drm_i915_private *i915 = to_i915(plane->base.dev); + if (intel_plane_can_async_flip(plane, fb->modifier)) return 256 * 1024; + if (intel_scanout_needs_vtd_wa(i915)) + return 256 * 1024; + switch (fb->modifier) { case I915_FORMAT_MOD_X_TILED: return 4 * 1024; @@ -798,9 +803,14 @@ static unsigned int g4x_primary_min_alignment(struct intel_plane *plane, const struct drm_framebuffer *fb, int color_plane) { + struct drm_i915_private *i915 = to_i915(plane->base.dev); + if (intel_plane_can_async_flip(plane, fb->modifier)) return 256 * 1024; + if (intel_scanout_needs_vtd_wa(i915)) + return 256 * 1024; + switch (fb->modifier) { case I915_FORMAT_MOD_X_TILED: case DRM_FORMAT_MOD_LINEAR: diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index ae7243ad6e0c..9157825e370b 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -372,6 +372,11 @@ static unsigned int i9xx_cursor_min_alignment(struct intel_plane *plane, const struct drm_framebuffer *fb, int color_plane) { + struct drm_i915_private *i915 = to_i915(plane->base.dev); + + if (intel_scanout_needs_vtd_wa(i915)) + return 256 * 1024; + return 4 * 1024; /* physical for i915/i945 */ } diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c index dd3ac7f98dfc..2b9ad46eaef7 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -126,14 +126,6 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment))) return ERR_PTR(-EINVAL); - /* Note that the w/a also requires 64 PTE of padding following the - * bo. We currently fill all unused PTE with the shadow page and so - * we should always have valid PTE following the scanout preventing - * the VT-d warning. - */ - if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) - alignment = 256 * 1024; - /* * Global gtt pte registers are special registers which actually forward * writes to a chunk of system memory. Which means that there is no risk diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 13996d7059ad..d63e71fe469e 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -980,6 +980,11 @@ static unsigned int g4x_sprite_min_alignment(struct intel_plane *plane, const struct drm_framebuffer *fb, int color_plane) { + struct drm_i915_private *i915 = to_i915(plane->base.dev); + + if (intel_scanout_needs_vtd_wa(i915)) + return 256 * 1024; + return 4 * 1024; } diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 450dd8c64e0c..5cec2df0baca 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -649,6 +649,10 @@ static u32 skl_plane_min_alignment(struct intel_plane *plane, if (color_plane != 0) return 4 * 1024; + /* + * VT-d needs at least 256k alignment, + * but that's already covered below. + */ switch (fb->modifier) { case DRM_FORMAT_MOD_LINEAR: case I915_FORMAT_MOD_X_TILED: From patchwork Wed Jan 22 15:17:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13947418 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A9264C02181 for ; Wed, 22 Jan 2025 15:18:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4B46210E706; Wed, 22 Jan 2025 15:18:05 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="mJh4nYCJ"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1CE7810E706; Wed, 22 Jan 2025 15:18:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737559084; x=1769095084; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=O2l444ttznRZ4LiqqrCajE0NB7ee01oJU+H9zotsvTs=; b=mJh4nYCJM+PiFvj2FooTkxuvNNE70pkNzHAPA7urODPOaqYDXlPE8h7T RTdHsgvh7i/G7qFUVrryriiBSPJpBB6p40tJ+5ZWum0L6oTaDRXPOh2QQ aPBuCNlhNnAPPFGeBxdhCZztNqFh2tyWonQ4AdXImASDGPqKkLsZvT1tH 6COJt0LRAR13UnSjjs9BSld3PbvFgOC0W8khPvSVKgMUcQCoZ4pTvGEMn /BZaUJlxnGjrfoVAc8SljFUIsq36hsuK5ZOQ0/DiUvEmMY+MP+dMtiMMA 9EU26sUPGA0U5BpXDXnKpgX39OJeHngAPx9il/w1b+1aXBguVZQNF/RMG Q==; X-CSE-ConnectionGUID: 1Tk5P8wZTv2cX4rUkStS+w== X-CSE-MsgGUID: 3hA6zkS6RuGaB70zmmXrEA== X-IronPort-AV: E=McAfee;i="6700,10204,11323"; a="40841188" X-IronPort-AV: E=Sophos;i="6.13,225,1732608000"; d="scan'208";a="40841188" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2025 07:18:04 -0800 X-CSE-ConnectionGUID: 8/RrxtXOTwqh71TTm4r1Yg== X-CSE-MsgGUID: 2CQPDgNlSVScrVwKYY2kYg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,225,1732608000"; d="scan'208";a="107274689" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 22 Jan 2025 07:18:02 -0800 Received: by stinkbox (sSMTP sendmail emulation); Wed, 22 Jan 2025 17:18:01 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH 2/5] drm/i915: Use more optimal VTd alignment for planes Date: Wed, 22 Jan 2025 17:17:52 +0200 Message-ID: <20250122151755.6928-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250122151755.6928-1-ville.syrjala@linux.intel.com> References: <20250122151755.6928-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Depending on the platform and/or plane type we can get away with a bit less alignment in the VT-d w/a. Reduce the numbers accordingly. Note that it's not actually clear in VLV/CHV need this w/a, and if they do we don't actually know what kind of alignment is sufficient. Leave the 256k alignment in place for now, but toss in a FIXME. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/i9xx_plane.c | 1 + drivers/gpu/drm/i915/display/intel_cursor.c | 2 +- drivers/gpu/drm/i915/display/intel_sprite.c | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 19cc34babef3..65a2eb9e92c4 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -785,6 +785,7 @@ unsigned int vlv_plane_min_alignment(struct intel_plane *plane, if (intel_plane_can_async_flip(plane, fb->modifier)) return 256 * 1024; + /* FIXME undocumented so not sure what's actually needed */ if (intel_scanout_needs_vtd_wa(i915)) return 256 * 1024; diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 9157825e370b..ea7cd7b5093c 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -375,7 +375,7 @@ static unsigned int i9xx_cursor_min_alignment(struct intel_plane *plane, struct drm_i915_private *i915 = to_i915(plane->base.dev); if (intel_scanout_needs_vtd_wa(i915)) - return 256 * 1024; + return 64 * 1024; return 4 * 1024; /* physical for i915/i945 */ } diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index d63e71fe469e..af121c720b89 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -983,7 +983,7 @@ static unsigned int g4x_sprite_min_alignment(struct intel_plane *plane, struct drm_i915_private *i915 = to_i915(plane->base.dev); if (intel_scanout_needs_vtd_wa(i915)) - return 256 * 1024; + return 128 * 1024; return 4 * 1024; } From patchwork Wed Jan 22 15:17:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13947419 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B58F0C02181 for ; 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X-CSE-ConnectionGUID: G9UsCBf0Tp2+rTe+owyHgg== X-CSE-MsgGUID: Y7nNM2/kS4egXWSarplhlA== X-IronPort-AV: E=McAfee;i="6700,10204,11323"; a="40841193" X-IronPort-AV: E=Sophos;i="6.13,225,1732608000"; d="scan'208";a="40841193" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2025 07:18:07 -0800 X-CSE-ConnectionGUID: kwtV1IqqR9GFImZLBgRSRA== X-CSE-MsgGUID: R38z3KoXTw6vXYecatK/lQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,225,1732608000"; d="scan'208";a="107274694" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 22 Jan 2025 07:18:05 -0800 Received: by stinkbox (sSMTP sendmail emulation); Wed, 22 Jan 2025 17:18:04 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH 3/5] drm/i915: Calculate the VT-d guard size in the display code Date: Wed, 22 Jan 2025 17:17:53 +0200 Message-ID: <20250122151755.6928-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250122151755.6928-1-ville.syrjala@linux.intel.com> References: <20250122151755.6928-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Currently i915_gem_object_pin_to_display_plane() uses i915_gem_object_get_tile_row_size() to calculate the tile row size for the VT-d guard w/a. That's not really proper since i915_gem_object_get_tile_row_size() only works for fenced BOs, nor does it take rotation into account. Remedy the situation by calculating the VT-d guard size in the display code where we have more information readily available. Although the default guard size (168 PTEs now) should cover the more typical fb size use cases anyway, and only very large Y/Yf-tiled framebuffers might have tile row size that exceeds it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fb.c | 33 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_fb.h | 3 ++ drivers/gpu/drm/i915/display/intel_fb_pin.c | 12 ++++++- drivers/gpu/drm/i915/display/intel_fb_pin.h | 1 + drivers/gpu/drm/i915/display/intel_fbdev.c | 2 ++ drivers/gpu/drm/i915/display/intel_overlay.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 15 ++------- drivers/gpu/drm/i915/gem/i915_gem_object.h | 2 +- drivers/gpu/drm/xe/display/xe_fb_pin.c | 1 + drivers/gpu/drm/xe/display/xe_plane_initial.c | 2 +- 10 files changed, 57 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 9f7f1b9f3275..ea8c8a99c5c7 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -1761,6 +1761,39 @@ int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer * return 0; } +unsigned int intel_fb_view_vtd_guard(const struct drm_framebuffer *fb, + const struct intel_fb_view *view, + unsigned int rotation) +{ + struct drm_i915_private *i915 = to_i915(fb->dev); + unsigned int vtd_guard; + int color_plane; + + if (!intel_scanout_needs_vtd_wa(i915)) + return 0; + + vtd_guard = 168; + + for (color_plane = 0; color_plane < fb->format->num_planes; color_plane++) { + unsigned int stride, tile; + + if (intel_fb_is_ccs_aux_plane(fb, color_plane) || + is_gen12_ccs_cc_plane(fb, color_plane)) + continue; + + stride = view->color_plane[color_plane].mapping_stride; + + if (drm_rotation_90_or_270(rotation)) + tile = intel_tile_height(fb, color_plane); + else + tile = intel_tile_width_bytes(fb, color_plane); + + vtd_guard = max(vtd_guard, DIV_ROUND_UP(stride, tile)); + } + + return vtd_guard; +} + static void intel_plane_remap_gtt(struct intel_plane_state *plane_state) { struct drm_i915_private *i915 = diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index d78993e5eb62..026e9f7f98f7 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -83,6 +83,9 @@ bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb); int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *fb); void intel_fb_fill_view(const struct intel_framebuffer *fb, unsigned int rotation, struct intel_fb_view *view); +unsigned int intel_fb_view_vtd_guard(const struct drm_framebuffer *fb, + const struct intel_fb_view *view, + unsigned int rotation); int intel_plane_compute_gtt(struct intel_plane_state *plane_state); int intel_framebuffer_init(struct intel_framebuffer *ifb, diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c index 2b9ad46eaef7..204e7e3e48ca 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -107,6 +107,7 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, const struct i915_gtt_view *view, unsigned int alignment, unsigned int phys_alignment, + unsigned int vtd_guard, bool uses_fence, unsigned long *out_flags) { @@ -162,7 +163,7 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, goto err; vma = i915_gem_object_pin_to_display_plane(obj, &ww, alignment, - view, pinctl); + vtd_guard, view, pinctl); if (IS_ERR(vma)) { ret = PTR_ERR(vma); goto err_unpin; @@ -244,6 +245,14 @@ intel_plane_fb_min_phys_alignment(const struct intel_plane_state *plane_state) return plane->min_alignment(plane, fb, 0); } +static unsigned int +intel_plane_fb_vtd_guard(const struct intel_plane_state *plane_state) +{ + return intel_fb_view_vtd_guard(plane_state->hw.fb, + &plane_state->view, + plane_state->hw.rotation); +} + int intel_plane_pin_fb(struct intel_plane_state *plane_state, const struct intel_plane_state *old_plane_state) { @@ -256,6 +265,7 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state, vma = intel_fb_pin_to_ggtt(&fb->base, &plane_state->view.gtt, intel_plane_fb_min_alignment(plane_state), intel_plane_fb_min_phys_alignment(plane_state), + intel_plane_fb_vtd_guard(plane_state), intel_plane_uses_fence(plane_state), &plane_state->flags); if (IS_ERR(vma)) diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.h b/drivers/gpu/drm/i915/display/intel_fb_pin.h index 0fc6d9044638..01770dbba2e0 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.h +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.h @@ -18,6 +18,7 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, const struct i915_gtt_view *view, unsigned int alignment, unsigned int phys_alignment, + unsigned int vtd_guard, bool uses_fence, unsigned long *out_flags); diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c index 6c0808133397..833cded53d37 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -228,6 +228,8 @@ static int intelfb_create(struct drm_fb_helper *helper, */ vma = intel_fb_pin_to_ggtt(&fb->base, &view, fb->min_alignment, 0, + intel_fb_view_vtd_guard(&fb->base, &fb->normal_view, + DRM_MODE_ROTATE_0), false, &flags); if (IS_ERR(vma)) { ret = PTR_ERR(vma); diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c index ca30fff61876..e519a021ea39 100644 --- a/drivers/gpu/drm/i915/display/intel_overlay.c +++ b/drivers/gpu/drm/i915/display/intel_overlay.c @@ -772,7 +772,7 @@ static struct i915_vma *intel_overlay_pin_fb(struct drm_i915_gem_object *new_bo) retry: ret = i915_gem_object_lock(new_bo, &ww); if (!ret) { - vma = i915_gem_object_pin_to_display_plane(new_bo, &ww, 0, + vma = i915_gem_object_pin_to_display_plane(new_bo, &ww, 0, 0, NULL, PIN_MAPPABLE); ret = PTR_ERR_OR_ZERO(vma); } diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c index 3770828f2eaf..cd865149b068 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c @@ -18,8 +18,6 @@ #include "i915_gem_object_frontbuffer.h" #include "i915_vma.h" -#define VTD_GUARD (168u * I915_GTT_PAGE_SIZE) /* 168 or tile-row PTE padding */ - static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj) { struct drm_i915_private *i915 = to_i915(obj->base.dev); @@ -424,7 +422,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, struct i915_vma * i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, struct i915_gem_ww_ctx *ww, - u32 alignment, + u32 alignment, unsigned int guard, const struct i915_gtt_view *view, unsigned int flags) { @@ -453,15 +451,8 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, return ERR_PTR(ret); /* VT-d may overfetch before/after the vma, so pad with scratch */ - if (intel_scanout_needs_vtd_wa(i915)) { - unsigned int guard = VTD_GUARD; - - if (i915_gem_object_is_tiled(obj)) - guard = max(guard, - i915_gem_object_get_tile_row_size(obj)); - - flags |= PIN_OFFSET_GUARD | guard; - } + if (guard) + flags |= PIN_OFFSET_GUARD | (guard * I915_GTT_PAGE_SIZE); /* * As the user may map the buffer once pinned in the display plane diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h index bb713e096db2..a5f34542135c 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -776,7 +776,7 @@ i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); struct i915_vma * __must_check i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, struct i915_gem_ww_ctx *ww, - u32 alignment, + u32 alignment, unsigned int guard, const struct i915_gtt_view *view, unsigned int flags); diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index 25ce032bb293..11a6b996d739 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -369,6 +369,7 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, const struct i915_gtt_view *view, unsigned int alignment, unsigned int phys_alignment, + unsigned int vtd_guard, bool uses_fence, unsigned long *out_flags) { diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c b/drivers/gpu/drm/xe/display/xe_plane_initial.c index 2a2f250fa495..25c80dd6d386 100644 --- a/drivers/gpu/drm/xe/display/xe_plane_initial.c +++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c @@ -215,7 +215,7 @@ intel_find_initial_plane_obj(struct intel_crtc *crtc, plane_state->uapi.rotation, &plane_state->view); vma = intel_fb_pin_to_ggtt(fb, &plane_state->view.gtt, - 0, 0, false, &plane_state->flags); + 0, 0, 0, false, &plane_state->flags); if (IS_ERR(vma)) goto nofb; From patchwork Wed Jan 22 15:17:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13947420 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E792DC02182 for ; Wed, 22 Jan 2025 15:18:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 90C8A10E712; Wed, 22 Jan 2025 15:18:11 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; 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a="40841204" X-IronPort-AV: E=Sophos;i="6.13,225,1732608000"; d="scan'208";a="40841204" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2025 07:18:10 -0800 X-CSE-ConnectionGUID: PuPh2HCxQrGEzf97iWCJpA== X-CSE-MsgGUID: 0CaEaiF5TzqP7lJ9+CIA3A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,225,1732608000"; d="scan'208";a="107274696" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 22 Jan 2025 07:18:08 -0800 Received: by stinkbox (sSMTP sendmail emulation); Wed, 22 Jan 2025 17:18:07 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH 4/5] drm/i915: Use per-plane VT-d guard numbers Date: Wed, 22 Jan 2025 17:17:54 +0200 Message-ID: <20250122151755.6928-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250122151755.6928-1-ville.syrjala@linux.intel.com> References: <20250122151755.6928-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Bspec lists different VT-d guard numbers (the number of dummy padding PTEs) for different platforms and plane types. Use those instead of just assuming the max glk+ number for everything. This could avoid a bit of overhead on older platforms due to reduced padding, and it makes it easier to cross check with the spec. Note that VLV/CHV do not document this w/a at all, so not sure if it's actually needed or not. Nor do we actually know how much padding is required if it is needed. For now use the same 128 PTEs that we use for snb-bdw primary planes. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/i9xx_plane.c | 4 ++++ drivers/gpu/drm/i915/display/intel_cursor.c | 3 +++ .../drm/i915/display/intel_display_types.h | 2 ++ drivers/gpu/drm/i915/display/intel_fb.c | 23 +++++++++++++++---- drivers/gpu/drm/i915/display/intel_sprite.c | 10 ++++++++ .../drm/i915/display/skl_universal_plane.c | 3 +++ 6 files changed, 41 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 65a2eb9e92c4..bd3f8db13700 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -958,6 +958,10 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) else plane->min_alignment = i9xx_plane_min_alignment; + /* FIXME undocumented for VLV/CHV so not sure what's actually needed */ + if (intel_scanout_needs_vtd_wa(dev_priv)) + plane->vtd_guard = 128; + if (IS_I830(dev_priv) || IS_I845G(dev_priv)) { plane->update_arm = i830_plane_update_arm; } else { diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index ea7cd7b5093c..911388d0c9b5 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -1019,6 +1019,9 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, else cursor->min_alignment = i9xx_cursor_min_alignment; + if (intel_scanout_needs_vtd_wa(dev_priv)) + cursor->vtd_guard = 2; + cursor->update_arm = i9xx_cursor_update_arm; cursor->disable_arm = i9xx_cursor_disable_arm; cursor->get_hw_state = i9xx_cursor_get_hw_state; diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 083eb86f0904..db8685465b23 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -144,6 +144,7 @@ struct intel_framebuffer { struct i915_address_space *dpt_vm; unsigned int min_alignment; + unsigned int vtd_guard; }; enum intel_hotplug_state { @@ -1445,6 +1446,7 @@ struct intel_plane { enum plane_id id; enum pipe pipe; bool need_async_flip_toggle_wa; + u8 vtd_guard; u32 frontbuffer_bit; struct { diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index ea8c8a99c5c7..d9328877cc6d 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -1660,6 +1660,22 @@ static unsigned int intel_fb_min_alignment(const struct drm_framebuffer *fb) return min_alignment; } +static unsigned int intel_fb_vtd_guard(const struct drm_framebuffer *fb) +{ + struct drm_i915_private *i915 = to_i915(fb->dev); + struct intel_plane *plane; + unsigned int vtd_guard = 0; + + for_each_intel_plane(&i915->drm, plane) { + if (!drm_plane_has_format(&plane->base, fb->format->format, fb->modifier)) + continue; + + vtd_guard = max_t(unsigned int, vtd_guard, plane->vtd_guard); + } + + return vtd_guard; +} + int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *fb) { struct drm_gem_object *obj = intel_fb_bo(&fb->base); @@ -1757,6 +1773,7 @@ int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer * } fb->min_alignment = intel_fb_min_alignment(&fb->base); + fb->vtd_guard = intel_fb_vtd_guard(&fb->base); return 0; } @@ -1765,15 +1782,13 @@ unsigned int intel_fb_view_vtd_guard(const struct drm_framebuffer *fb, const struct intel_fb_view *view, unsigned int rotation) { - struct drm_i915_private *i915 = to_i915(fb->dev); unsigned int vtd_guard; int color_plane; - if (!intel_scanout_needs_vtd_wa(i915)) + vtd_guard = to_intel_framebuffer(fb)->vtd_guard; + if (!vtd_guard) return 0; - vtd_guard = 168; - for (color_plane = 0; color_plane < fb->format->num_planes; color_plane++) { unsigned int stride, tile; diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index af121c720b89..a6b27798fdc3 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -1609,6 +1609,10 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->min_alignment = vlv_plane_min_alignment; plane->min_cdclk = vlv_plane_min_cdclk; + /* FIXME undocumented for VLV/CHV so not sure what's actually needed */ + if (intel_scanout_needs_vtd_wa(dev_priv)) + plane->vtd_guard = 128; + if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { formats = chv_pipe_b_sprite_formats; num_formats = ARRAY_SIZE(chv_pipe_b_sprite_formats); @@ -1635,6 +1639,9 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->min_alignment = g4x_sprite_min_alignment; + if (intel_scanout_needs_vtd_wa(dev_priv)) + plane->vtd_guard = 64; + formats = snb_sprite_formats; num_formats = ARRAY_SIZE(snb_sprite_formats); @@ -1649,6 +1656,9 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->min_alignment = g4x_sprite_min_alignment; plane->min_cdclk = g4x_sprite_min_cdclk; + if (intel_scanout_needs_vtd_wa(dev_priv)) + plane->vtd_guard = 64; + if (IS_SANDYBRIDGE(dev_priv)) { formats = snb_sprite_formats; num_formats = ARRAY_SIZE(snb_sprite_formats); diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 5cec2df0baca..7b49309a6d8c 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2754,6 +2754,9 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, else plane->min_alignment = skl_plane_min_alignment; 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a="40841213" X-IronPort-AV: E=Sophos;i="6.13,225,1732608000"; d="scan'208";a="40841213" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2025 07:18:12 -0800 X-CSE-ConnectionGUID: Bp9sQYzkRyC5tatcOKsYWw== X-CSE-MsgGUID: gD7wZHo4TEG2jCOP8wCMwg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,225,1732608000"; d="scan'208";a="107274698" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 22 Jan 2025 07:18:11 -0800 Received: by stinkbox (sSMTP sendmail emulation); Wed, 22 Jan 2025 17:18:10 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH 5/5] drm/i915/fbdev: Use fb->normal_view.gtt Date: Wed, 22 Jan 2025 17:17:55 +0200 Message-ID: <20250122151755.6928-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250122151755.6928-1-ville.syrjala@linux.intel.com> References: <20250122151755.6928-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Grab the GTT view for the fbdev fb pinning from fb->normal_view.gtt instead of having and extra one on the stack. Seems safer in case we ever put any new information into normal GTT views. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbdev.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c index 833cded53d37..301b5fd301a2 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -177,9 +177,6 @@ static int intelfb_create(struct drm_fb_helper *helper, struct intel_framebuffer *fb = ifbdev->fb; struct drm_device *dev = helper->dev; struct drm_i915_private *dev_priv = to_i915(dev); - const struct i915_gtt_view view = { - .type = I915_GTT_VIEW_NORMAL, - }; intel_wakeref_t wakeref; struct fb_info *info; struct i915_vma *vma; @@ -226,7 +223,7 @@ static int intelfb_create(struct drm_fb_helper *helper, * This also validates that any existing fb inherited from the * BIOS is suitable for own access. */ - vma = intel_fb_pin_to_ggtt(&fb->base, &view, + vma = intel_fb_pin_to_ggtt(&fb->base, &fb->normal_view.gtt, fb->min_alignment, 0, intel_fb_view_vtd_guard(&fb->base, &fb->normal_view, DRM_MODE_ROTATE_0),