From patchwork Thu Jan 23 05:51:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jiwei Sun X-Patchwork-Id: 13947951 X-Patchwork-Delegate: bhelgaas@google.com Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.5]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D5472C2FD; Thu, 23 Jan 2025 05:52:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737611552; cv=none; b=SRZC3f/EeuThmWtcArOFmnV6VTTecsbPwQaDLhb04Sr0uCpj2WmZ6pXnx8t1kUdd1VDka9JaLOdvHNvhjKfJycoLOn8uQhfXxUCYQKglXv4CGjA/4xOSE+91EAX+5OdY90UMBZjHzL4fvDbMBagmX1l8tqxbjPokgHA5eMCvJZk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737611552; c=relaxed/simple; bh=zPfd2wsYvCHUkuP7O8rme07rC0QW8LHh5xBKN9/yqRA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=EcfzpPQ1HyjZ7EW/hytgKibIJBj5S5ur9TCQoR41V9qVWg00oyLlFPwb+t8ky8Ga3EVVr0Qqtb37esdeeGACMmNAvbwQGAvLDPPRFNE/i/QMv1CkEP4StXy0vw9Of32CPbm+fG4A3ED5rfc6hgnd5LGmcwuaJQWTHG/brk4NlDQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=fuoDHjAL; arc=none smtp.client-ip=220.197.31.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="fuoDHjAL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version: Content-Type; bh=m2D3TK/wDGpgftow+9dKzgwXIks/NmyWWEukqak6kfU=; b=fuoDHjAL+pXnW8UaL91wJy1m0qMVEi8EfZN6nv2pUR+iOrNgUMsd6oyruTMbBY 4O1xV26O+PZ9HakEIathEDU5Cyyky1vnR33TGxfNe2XOUaEk/Rd31QyiDujh7SX6 bgWzlccGa6l/zP+YVpeBY3AgpwBVyuezx5GqDiV/QWx3s= Received: from jiwei-VirtualBox.lenovo.com (unknown []) by gzga-smtp-mtada-g1-2 (Coremail) with SMTP id _____wDXxy392JFnt3jOHw--.51666S3; Thu, 23 Jan 2025 13:52:00 +0800 (CST) From: Jiwei Sun To: macro@orcam.me.uk, ilpo.jarvinen@linux.intel.com, bhelgaas@google.com Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, helgaas@kernel.org, lukas@wunner.de, ahuang12@lenovo.com, sunjw10@lenovo.com, jiwei.sun.bj@qq.com, sunjw10@outlook.com Subject: [PATCH v4 1/2] PCI: Fix the wrong reading of register fields Date: Thu, 23 Jan 2025 13:51:54 +0800 Message-Id: <20250123055155.22648-2-sjiwei@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250123055155.22648-1-sjiwei@163.com> References: <20250123055155.22648-1-sjiwei@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: _____wDXxy392JFnt3jOHw--.51666S3 X-Coremail-Antispam: 1Uf129KBjvJXoWxuF4rtFWDWw15uF1DGw4Uurg_yoW5uFyxp3 W3ur90yrW8Gw47u3s5Gas7Xa4xXFn3GF129rnrWrn0qFyrJ34kAF10k3sIqry7Ar40kry8 X3srZr45G3W2kFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jzYLkUUUUU= X-CM-SenderInfo: 5vml4vrl6rljoofrz/1tbiWx3dmWeR07BWzwAAsO From: Jiwei Sun The macro PCIE_LNKCTL2_TLS2SPEED() and PCIE_LNKCAP_SLS2SPEED() just use the link speed field of the registers. However, there are many other different function fields in the Link Control 2 Register or the Link Capabilities Register. If the register value is directly used by the two macros, it may cause getting an error link speed value (PCI_SPEED_UNKNOWN). In order to avoid the above-mentioned potential issue, only keep link speed field of the two registers before using. Fixes: de9a6c8d5dbf ("PCI/bwctrl: Add pcie_set_target_speed() to set PCIe Link Speed") Suggested-by: Maciej W. Rozycki Suggested-by: Ilpo Järvinen Signed-off-by: Jiwei Sun Reviewed-by: Ilpo Järvinen --- drivers/pci/pci.h | 32 +++++++++++++++++++------------- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 2e40fc63ba31..aeca10ce2028 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -337,12 +337,14 @@ void pci_bus_put(struct pci_bus *bus); #define PCIE_LNKCAP_SLS2SPEED(lnkcap) \ ({ \ - ((lnkcap) == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ - (lnkcap) == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ - (lnkcap) == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ - (lnkcap) == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ - (lnkcap) == PCI_EXP_LNKCAP_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ - (lnkcap) == PCI_EXP_LNKCAP_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ + u32 lnkcap_sls = (lnkcap) & PCI_EXP_LNKCAP_SLS; \ + \ + (lnkcap_sls == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ + lnkcap_sls == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ + lnkcap_sls == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ + lnkcap_sls == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ + lnkcap_sls == PCI_EXP_LNKCAP_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ + lnkcap_sls == PCI_EXP_LNKCAP_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ PCI_SPEED_UNKNOWN); \ }) @@ -357,13 +359,17 @@ void pci_bus_put(struct pci_bus *bus); PCI_SPEED_UNKNOWN) #define PCIE_LNKCTL2_TLS2SPEED(lnkctl2) \ - ((lnkctl2) == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT : \ - (lnkctl2) == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT : \ - (lnkctl2) == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT : \ - (lnkctl2) == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT : \ - (lnkctl2) == PCI_EXP_LNKCTL2_TLS_5_0GT ? PCIE_SPEED_5_0GT : \ - (lnkctl2) == PCI_EXP_LNKCTL2_TLS_2_5GT ? PCIE_SPEED_2_5GT : \ - PCI_SPEED_UNKNOWN) +({ \ + u16 lnkctl2_tls = (lnkctl2) & PCI_EXP_LNKCTL2_TLS; \ + \ + (lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT : \ + lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT : \ + lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT : \ + lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT : \ + lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_5_0GT ? PCIE_SPEED_5_0GT : \ + lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_2_5GT ? PCIE_SPEED_2_5GT : \ + PCI_SPEED_UNKNOWN); \ +}) /* PCIe speed to Mb/s reduced by encoding overhead */ #define PCIE_SPEED2MBS_ENC(speed) \ From patchwork Thu Jan 23 05:51:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jiwei Sun X-Patchwork-Id: 13947953 X-Patchwork-Delegate: bhelgaas@google.com Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.2]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F006F1C3BE3; Thu, 23 Jan 2025 05:52:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737611574; cv=none; b=fpWw2+cJ/UN2a8l4jLvbeEIJh0yMfQsbkWG4IaT22YWoWRtQjCx8QQEoXdiaocFiVG3Atwk92dJ3AVxkT/po5Qh6xVSfuhxqzfCCb2yoLD4JfTjj4o91467x42HyqFIHSbS4ctY4VyDNk4Jkn/lffN4FC1dtRwh5HLzftWA/bLE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737611574; c=relaxed/simple; bh=YJcYy6FvcSP7a5L9SPKEAovX+VDxR/9OmnxzR18avRc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=mMhd8w/NXFFrW+XmWiJdi12OCh+vhEUDW3w/ScSEE6CAzMa8sSRKTfZC4mq4JJj+L6jnp35HnMIWCM+YtV73nCify0/QAOlBzo+E5gcdxt1J/f2a2g+C9Dqp4GK1h+1auExeqxnsrRzcJtYqyzKlCYaik0L/0z7t6z3kvmYiKTg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=Q5zc2V49; arc=none smtp.client-ip=220.197.31.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="Q5zc2V49" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version: Content-Type; bh=HZPg+6roJ7x4xUK2gSmzafnHFMqskHkdEYTKOCV7+vc=; b=Q5zc2V49ZZqwR9LpWUsbF3j4hGglg9o+i4zTy8nhhs/aT+8uy/cWE6t1haC5yq u6QYxTnGyPVEfagCga7A2zrfBXv6yJP2exlqNgHQ9r4RYe0qg53RvgrATLuxboK7 sb52TSzQkNpo7L/uA4H4W5HiGHMzvFjl/yWKBOnNMrEp4= Received: from jiwei-VirtualBox.lenovo.com (unknown []) by gzga-smtp-mtada-g1-2 (Coremail) with SMTP id _____wDXxy392JFnt3jOHw--.51666S4; Thu, 23 Jan 2025 13:52:00 +0800 (CST) From: Jiwei Sun To: macro@orcam.me.uk, ilpo.jarvinen@linux.intel.com, bhelgaas@google.com Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, helgaas@kernel.org, lukas@wunner.de, ahuang12@lenovo.com, sunjw10@lenovo.com, jiwei.sun.bj@qq.com, sunjw10@outlook.com Subject: [PATCH v4 2/2] PCI: Adjust the position of reading the Link Control 2 register Date: Thu, 23 Jan 2025 13:51:55 +0800 Message-Id: <20250123055155.22648-3-sjiwei@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250123055155.22648-1-sjiwei@163.com> References: <20250123055155.22648-1-sjiwei@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: _____wDXxy392JFnt3jOHw--.51666S4 X-Coremail-Antispam: 1Uf129KBjvJXoW7uryDXF45uFW3urykAF47Jwb_yoW8Kw15pF WfWry7tr1kGr47Z3yDWayfXFyDu3ZxCay7G3y7W3s8ZFy3tws5XF4FkF43t3W5Zrs7u34U XFW5trWkAa1YgFJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07j7J5rUUUUU= X-CM-SenderInfo: 5vml4vrl6rljoofrz/xtbBDwXdmWeRy1vXuQAAsG From: Jiwei Sun In the commit a89c82249c37 ("PCI: Work around PCIe link training failures"), if the speed limit is set to 2.5 GT/s and the retraining is successful, an attempt will be made to lift the speed limit. One condition for lifting the speed limit is to check whether the link speed field of the Link Control 2 register is PCI_EXP_LNKCTL2_TLS_2_5GT. However, since the commit de9a6c8d5dbf ("PCI/bwctrl: Add pcie_set_target_speed() to set PCIe Link Speed"), the `lnkctl2` local variable does not undergo any changes during the speed limit setting and retraining process. As a result, the code intended to lift the speed limit is not executed. To address this issue, adjust the position of the Link Control 2 register read operation in the code and place it before its use. Fixes: de9a6c8d5dbf ("PCI/bwctrl: Add pcie_set_target_speed() to set PCIe Link Speed") Suggested-by: Maciej W. Rozycki Suggested-by: Ilpo Järvinen Signed-off-by: Jiwei Sun --- drivers/pci/quirks.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 76f4df75b08a..c2344706ba61 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -108,13 +108,13 @@ int pcie_failed_link_retrain(struct pci_dev *dev) !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) return ret; - pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2); pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); if (!(lnksta & PCI_EXP_LNKSTA_DLLLA) && pcie_lbms_seen(dev, lnksta)) { - u16 oldlnkctl2 = lnkctl2; + u16 oldlnkctl2; pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); + pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &oldlnkctl2); ret = pcie_set_target_speed(dev, PCIE_SPEED_2_5GT, false); if (ret) { pci_info(dev, "retraining failed\n"); @@ -126,6 +126,8 @@ int pcie_failed_link_retrain(struct pci_dev *dev) pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); } + pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2); + if ((lnksta & PCI_EXP_LNKSTA_DLLLA) && (lnkctl2 & PCI_EXP_LNKCTL2_TLS) == PCI_EXP_LNKCTL2_TLS_2_5GT && pci_match_id(ids, dev)) {