From patchwork Thu Jan 23 06:47:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Langyan Ye X-Patchwork-Id: 13947957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 41205C02182 for ; Thu, 23 Jan 2025 06:48:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B15E510E402; Thu, 23 Jan 2025 06:48:15 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=huaqin-corp-partner-google-com.20230601.gappssmtp.com header.i=@huaqin-corp-partner-google-com.20230601.gappssmtp.com header.b="lHVjuvR6"; dkim-atps=neutral Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3A1A810E3E4 for ; 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Wed, 22 Jan 2025 22:48:13 -0800 (PST) Received: from dgp100339560-01.huaqin.com ([116.66.212.162]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-a9bcc323777sm11923454a12.20.2025.01.22.22.48.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 22:48:13 -0800 (PST) From: Langyan Ye To: neil.armstrong@linaro.org, quic_jesszhan@quicinc.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, thierry.reding@gmail.com, sam@ravnborg.org, dianders@chromium.org Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Langyan Ye Subject: [PATCH v4 1/3] dt-bindings: display: panel: Add compatible for KD110N11-51IE and 2082109QFH040022-50E Date: Thu, 23 Jan 2025 14:47:56 +0800 Message-Id: <20250123064758.743798-2-yelangyan@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250123064758.743798-1-yelangyan@huaqin.corp-partner.google.com> References: <20250123064758.743798-1-yelangyan@huaqin.corp-partner.google.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" KINGDISPLAY KD110N11-51IE and STARRY 2082109QFH040022-50E are 10.95-inch WUXGA TFT LCD panels, which fits in nicely with the existing panel-boe-tv101wum-nl6 driver. Hence, we add a new compatible with panel specific config. Signed-off-by: Langyan Ye --- .../devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml index 7a9f49e40e75..b740681605f8 100644 --- a/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml +++ b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml @@ -30,8 +30,12 @@ properties: - boe,tv110c9m-ll3 # INX HJ110IZ-01A 10.95" WUXGA TFT LCD panel - innolux,hj110iz-01a + # KINGDISPLAY KD110N11-51IE 10.95" WUXGA TFT LCD panel + - kingdisplay,kd110n11-51ie # STARRY 2081101QFH032011-53G 10.1" WUXGA TFT LCD panel - starry,2081101qfh032011-53g + # STARRY 2082109QFH040022-50E 10.95" WUXGA TFT LCD panel + - starry,2082109qfh040022-50e # STARRY ili9882t 10.51" WUXGA TFT LCD panel - starry,ili9882t From patchwork Thu Jan 23 06:47:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Langyan Ye X-Patchwork-Id: 13947958 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 210FDC02182 for ; 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Wed, 22 Jan 2025 22:48:17 -0800 (PST) Received: from dgp100339560-01.huaqin.com ([116.66.212.162]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-a9bcc323777sm11923454a12.20.2025.01.22.22.48.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 22:48:17 -0800 (PST) From: Langyan Ye To: neil.armstrong@linaro.org, quic_jesszhan@quicinc.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, thierry.reding@gmail.com, sam@ravnborg.org, dianders@chromium.org Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Langyan Ye Subject: [PATCH v4 2/3] drm/panel: boe-tv101wum-nl6: support for kingdisplay-kd110n11-51ie MIPI-DSI panel Date: Thu, 23 Jan 2025 14:47:57 +0800 Message-Id: <20250123064758.743798-3-yelangyan@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250123064758.743798-1-yelangyan@huaqin.corp-partner.google.com> References: <20250123064758.743798-1-yelangyan@huaqin.corp-partner.google.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The kingdisplay-kd110n11-51ie is a 10.95" TFT panel. which fits in nicely with the existing panel-boe-tv101wum-nl6 driver. From the datasheet, MIPI needs to keep the LP11 state before the lcm_reset pin is pulled high, so increase lp11_before_reset flag. Signed-off-by: Langyan Ye Reviewed-by: Neil Armstrong --- .../gpu/drm/panel/panel-boe-tv101wum-nl6.c | 122 ++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c index 3e5b0d8636d0..2a84ce3a33ed 100644 --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c @@ -1205,6 +1205,97 @@ static int auo_b101uan08_3_init(struct boe_panel *boe) return 0; }; +static int kingdisplay_kd110n11_51ie_init(struct boe_panel *boe) +{ + struct mipi_dsi_multi_context ctx = { .dsi = boe->dsi }; + + msleep(50); + + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB9, 0x83, 0x10, 0x21, 0x55, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xC4); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD9, 0xD1); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB1, 0x2C, 0xB3, 0xB3, 0x31, 0xF1, 0x33, 0xE0, 0x54, + 0x36, 0x36, 0x3A, 0x3A, 0x32, 0x8B, 0x11, 0xE5, 0x98); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xD9); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB1, 0x8B, 0x33); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB2, 0x00, 0x47, 0xB0, 0x80, 0x00, 0x2C, 0x80, 0x3C, + 0x9F, 0x22, 0x20, 0x00, 0x00, 0x98, 0x51); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB4, 0x64, 0x64, 0x64, 0x64, 0x64, 0x64, 0x40, 0x84, + 0x64, 0x84, 0x01, 0x9D, 0x01, 0x02, 0x01, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBC, 0x1B, 0x04); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBE, 0x20); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBF, 0xFC, 0xC4, 0x80, 0x9C, 0x36, 0x00, 0x0D, 0x04); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xC0, 0x32, 0x32, 0x22, 0x11, 0x22, 0xA0, 0x31, 0x08, + 0xF5, 0x03); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xCC); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xC7, 0x80); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xC6); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xC8, 0x97); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xC9, 0x00, 0x1E, 0x13, 0x88, 0x01); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xCB, 0x08, 0x13, 0x07, 0x00, 0x0F, 0x36); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xCC, 0x02, 0x03, 0x44); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD1, 0x07, 0x06, 0x00, 0x02, 0x04, 0x2C, 0xFF); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD3, 0x06, 0x00, 0x00, 0x00, 0x40, 0x04, 0x08, 0x04, + 0x08, 0x37, 0x07, 0x44, 0x37, 0x2B, 0x2B, 0x03, 0x03, 0x32, + 0x10, 0x22, 0x00, 0x25, 0x32, 0x10, 0x29, 0x00, 0x29, 0x32, + 0x10, 0x08, 0x00, 0x08, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD5, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, + 0x18, 0x18, 0x07, 0x06, 0x07, 0x06, 0x05, 0x04, 0x05, 0x04, + 0x03, 0x02, 0x03, 0x02, 0x01, 0x00, 0x01, 0x00, 0x18, 0x18, + 0x25, 0x24, 0x25, 0x24, 0x1F, 0x1F, 0x1F, 0x1F, 0x1E, 0x1E, + 0x1E, 0x1E, 0x20, 0x20, 0x20, 0x20); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD8, 0x0A, 0x2A, 0xAA, 0x8A, 0xAA, 0xA0, 0x0A, 0x2A, + 0xAA, 0x8A, 0xAA, 0xA0); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE7, 0xE0, 0x10, 0x10, 0x0D, 0x1E, 0x9D, 0x02, 0x52, + 0x9D, 0x14, 0x14); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBD, 0x01); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB1, 0x01, 0x7F, 0x11, 0xFD); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xC5); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBA, 0x4F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xCB, 0x86); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD2, 0x64); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xC5); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD3, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD8, 0x0A, 0x2A, 0xAA, 0x8A, 0xAA, 0xA0, 0x0A, 0x2A, + 0xAA, 0x8A, 0xAA, 0xA0, 0x05, 0x15, 0x55, 0x45, 0x55, 0x50, + 0x05, 0x15, 0x55, 0x45, 0x55, 0x50); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE7, 0x02, 0x00, 0x24, 0x01, 0x7E, 0x0F, 0x7C, 0x10, + 0xA0, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBD, 0x02); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xCB, 0x03, 0x07, 0x00, 0x10, 0x7B); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD8, 0x0F, 0x3F, 0xFF, 0xCF, 0xFF, 0xF0, 0x0F, 0x3F, + 0xFF, 0xCF, 0xFF, 0xF0); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE7, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0x00, 0x00, + 0x00, 0x23, 0x00, 0x23, 0x81, 0x02, 0x40, 0x00, 0x20, 0x9D, + 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBD, 0x03); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB2, 0x66, 0x81); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xC6); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB4, 0x03, 0xFF, 0xF8); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD8, 0x0A, 0x2A, 0xAA, 0x8A, 0xAA, 0xA0, 0x0A, 0x2A, + 0xAA, 0x8A, 0xAA, 0xA0, 0x0F, 0x2A, 0xAA, 0x8A, 0xAA, 0xF0, + 0x0F, 0x2A, 0xAA, 0x8A, 0xAA, 0xF0, 0x0A, 0x2A, 0xAA, 0x8A, + 0xAA, 0xA0, 0x0A, 0x2A, 0xAA, 0x8A, 0xAA, 0xA0); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBD, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB9, 0x00, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0x11); + + mipi_dsi_msleep(&ctx, 120); + + mipi_dsi_dcs_write_seq_multi(&ctx, 0x29); + + mipi_dsi_msleep(&ctx, 20); + + return 0; +} + static int starry_qfh032011_53g_init(struct boe_panel *boe) { struct mipi_dsi_multi_context ctx = { .dsi = boe->dsi }; @@ -1615,6 +1706,34 @@ static const struct panel_desc boe_tv105wum_nw0_desc = { .lp11_before_reset = true, }; +static const struct drm_display_mode kingdisplay_kd110n11_51ie_default_mode = { + .clock = 182888, + .hdisplay = 1200, + .hsync_start = 1200 + 124, + .hsync_end = 1200 + 124 + 80, + .htotal = 1200 + 124 + 80 + 80, + .vdisplay = 1920, + .vsync_start = 1920 + 88, + .vsync_end = 1920 + 88 + 8, + .vtotal = 1920 + 88 + 8 + 38, + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct panel_desc kingdisplay_kd110n11_51ie_desc = { + .modes = &kingdisplay_kd110n11_51ie_default_mode, + .bpc = 8, + .size = { + .width_mm = 147, + .height_mm = 235, + }, + .lanes = 4, + .format = MIPI_DSI_FMT_RGB888, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM, + .init = kingdisplay_kd110n11_51ie_init, + .lp11_before_reset = true, +}; + static const struct drm_display_mode starry_qfh032011_53g_default_mode = { .clock = 165731, .hdisplay = 1200, @@ -1804,6 +1923,9 @@ static const struct of_device_id boe_of_match[] = { { .compatible = "innolux,hj110iz-01a", .data = &inx_hj110iz_desc }, + { .compatible = "kingdisplay,kd110n11-51ie", + .data = &kingdisplay_kd110n11_51ie_desc + }, { .compatible = "starry,2081101qfh032011-53g", .data = &starry_qfh032011_53g_desc }, From patchwork Thu Jan 23 06:47:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Langyan Ye X-Patchwork-Id: 13947959 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 27D18C02182 for ; Thu, 23 Jan 2025 06:48:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9BECA10E772; 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Wed, 22 Jan 2025 22:48:21 -0800 (PST) Received: from dgp100339560-01.huaqin.com ([116.66.212.162]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-a9bcc323777sm11923454a12.20.2025.01.22.22.48.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 22:48:20 -0800 (PST) From: Langyan Ye To: neil.armstrong@linaro.org, quic_jesszhan@quicinc.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, thierry.reding@gmail.com, sam@ravnborg.org, dianders@chromium.org Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Langyan Ye Subject: [PATCH v4 3/3] drm/panel: boe-tv101wum-nl6: support for starry-2082109qfh040022-50e MIPI-DSI panel Date: Thu, 23 Jan 2025 14:47:58 +0800 Message-Id: <20250123064758.743798-4-yelangyan@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250123064758.743798-1-yelangyan@huaqin.corp-partner.google.com> References: <20250123064758.743798-1-yelangyan@huaqin.corp-partner.google.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The starry-2082109qfh040022-50e is a 10.95" TFT panel. which fits in nicely with the existing panel-boe-tv101wum-nl6 driver. From the datasheet, MIPI needs to keep the LP11 state before the lcm_reset pin is pulled high, so increase lp11_before_reset flag. Signed-off-by: Langyan Ye Reviewed-by: Neil Armstrong --- .../gpu/drm/panel/panel-boe-tv101wum-nl6.c | 148 ++++++++++++++++++ 1 file changed, 148 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c index 2a84ce3a33ed..ba8921c13942 100644 --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c @@ -1400,6 +1400,123 @@ static int starry_qfh032011_53g_init(struct boe_panel *boe) return 0; }; +static int starry_2082109qfh040022_50e_init(struct boe_panel *boe) +{ + struct mipi_dsi_multi_context ctx = { .dsi = boe->dsi }; + + msleep(50); + + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB9, 0x83, 0x10, 0x21, 0x55, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xC4); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD9, 0xD1); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB1, 0x2C, 0xB5, 0xB5, 0x31, 0xF1, 0x33, 0xC3, 0x57, + 0x36, 0x36, 0x36, 0x36, 0x1A, 0x8B, 0x11, 0x65, 0x00, 0x88, 0xFA, 0xFF, 0xFF, + 0x8F, 0xFF, 0x08, 0x3C, 0x33); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB2, 0x00, 0x47, 0xB0, 0x80, 0x00, 0x22, 0x70, 0x3C, + 0xA1, 0x22, 0x00, 0x00, 0x00, 0x88, 0xF4); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB4, 0x14, 0x16, 0x14, 0x50, 0x14, 0x50, 0x0D, 0x6A, + 0x0D, 0x6A, 0x01, 0x9E); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB6, 0x34, 0x34, 0x03); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB8, 0x40); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xCD); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBA, 0x84); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBC, 0x1B, 0x04); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBE, 0x20); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBF, 0xFC, 0xC4); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xC0, 0x38, 0x38, 0x22, 0x11, 0x33, 0xA0, 0x61, 0x08, + 0xF5, 0x03); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xCC); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xC7, 0x80); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xC6); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xC8, 0x97); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xC9, 0x00, 0x1E, 0x30, 0xD4, 0x01); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xCB, 0x08, 0x13, 0x07, 0x00, 0x0F, 0x16); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xCC, 0x02, 0x03, 0x44); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xC4); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD0, 0x03); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD1, 0x37, 0x06, 0x00, 0x02, 0x04, 0x2C, 0xFF); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD3, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x3B, 0x03, 0x73, 0x3B, 0x21, 0x21, 0x03, 0x03, 0x98, 0x10, 0x1D, 0x00, + 0x1D, 0x32, 0x17, 0xA1, 0x07, 0xA1, 0x43, 0x17, 0xA6, 0x07, 0xA6, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD5, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x40, 0x40, + 0x18, 0x18, 0x18, 0x18, 0x2A, 0x2B, 0x1F, 0x1F, 0x1E, 0x1E, 0x24, 0x25, 0x26, + 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x20, 0x21, 0x18, 0x18, 0x18, 0x18); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD8, 0x02, 0xAA, 0xEA, 0xAA, 0xAA, 0x00, 0x02, 0xAA, + 0xEA, 0xAA, 0xAA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE7, 0x07, 0x10, 0x10, 0x2A, 0x32, 0x9F, 0x01, 0x5A, + 0x91, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12, 0x05, 0x02, 0x02, 0x10, 0x33, + 0x02, 0x04, 0x18, 0x01); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBD, 0x01); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB1, 0x01, 0x7F, 0x11, 0xFD); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xCB, 0x86); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD2, 0x3D); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xC5); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD3, 0x00, 0x00, 0x00, 0x80, 0x80, 0x0C, 0xA1); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD8, 0x03, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x03, 0xFF, + 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE7, 0x02, 0x00, 0x2D, 0x01, 0x7F, 0x0F, 0x7C, 0x10, + 0xA0, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBD, 0x02); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBF, 0xF2); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xCB, 0x02, 0x00, 0x00, 0x10, 0x58); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD2, 0x0A, 0x0A, 0x05, 0x03, 0x0A, 0x0A, 0x01, 0x03, + 0x01, 0x01, 0x05, 0x0E); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xCC); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD3, 0x03, 0x1F, 0xE0, 0x11, 0x70); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD8, 0xAB, 0xFF, 0xFF, 0xFF, 0xFF, 0xA0, 0xAB, 0xFF, + 0xFF, 0xFF, 0xFF, 0xA0); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE7, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0x00, 0x00, + 0x00, 0x03, 0x00, 0x03, 0x81, 0x02, 0x40, 0x00, 0x20, 0x9E, 0x02, 0x01, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBD, 0x03); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xC6); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB4, 0x03, 0xFF, 0xF8); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD8, 0xAA, 0xAB, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xAB, + 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBF, 0xFF, 0xFF, 0xFE, 0xA0, 0xAA, 0xBF, 0xFF, + 0xFF, 0xFE, 0xA0, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0, 0xAA, 0xAA, 0xAA, 0xAA, + 0xAA, 0xA0); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE1, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBD, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xC4); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBA, 0x96); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBD, 0x01); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xC5); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBA, 0x4F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBD, 0x02); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xCC); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBA, 0x84); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBD, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB9, 0x00, 0x00, 0x00, 0x00); + + msleep(110); + + mipi_dsi_dcs_write_seq_multi(&ctx, 0x11); + + mipi_dsi_msleep(&ctx, 120); + + mipi_dsi_dcs_write_seq_multi(&ctx, 0x29); + + mipi_dsi_msleep(&ctx, 20); + + return 0; +} + static inline struct boe_panel *to_boe_panel(struct drm_panel *panel) { return container_of(panel, struct boe_panel, base); @@ -1761,6 +1878,34 @@ static const struct panel_desc starry_qfh032011_53g_desc = { .lp11_before_reset = true, }; +static const struct drm_display_mode starry_2082109qfh040022_50e_default_mode = { + .clock = 192105, + .hdisplay = 1200, + .hsync_start = 1200 + 160, + .hsync_end = 1200 + 160 + 66, + .htotal = 1200 + 160 + 66 + 120, + .vdisplay = 1920, + .vsync_start = 1920 + 115, + .vsync_end = 1920 + 115 + 8, + .vtotal = 1920 + 115 + 8 + 28, + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct panel_desc starry_2082109qfh040022_50e_desc = { + .modes = &starry_2082109qfh040022_50e_default_mode, + .bpc = 8, + .size = { + .width_mm = 147, + .height_mm = 235, + }, + .lanes = 4, + .format = MIPI_DSI_FMT_RGB888, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM, + .init = starry_2082109qfh040022_50e_init, + .lp11_before_reset = true, +}; + static int boe_panel_get_modes(struct drm_panel *panel, struct drm_connector *connector) { @@ -1929,6 +2074,9 @@ static const struct of_device_id boe_of_match[] = { { .compatible = "starry,2081101qfh032011-53g", .data = &starry_qfh032011_53g_desc }, + { .compatible = "starry,2082109qfh040022-50e", + .data = &starry_2082109qfh040022_50e_desc + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, boe_of_match);