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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a1764c8sm979124f8f.3.2025.01.23.15.44.20 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Jan 2025 15:44:21 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Igor Mammedov , =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, David Hildenbrand , qemu-s390x@nongnu.org, xen-devel@lists.xenproject.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Pierrick Bouvier , Kevin Wolf Subject: [PATCH 01/20] qemu/compiler: Absorb 'clang-tsa.h' Date: Fri, 24 Jan 2025 00:43:55 +0100 Message-ID: <20250123234415.59850-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250123234415.59850-1-philmd@linaro.org> References: <20250123234415.59850-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We already have "qemu/compiler.h" for compiler-specific arrangements, automatically included by "qemu/osdep.h" for each source file. No need to explicitly include a header for a Clang particularity. Suggested-by: Pierrick Bouvier Reviewed-by: Pierrick Bouvier Reviewed-by: Alex Bennée Reviewed-by: Kevin Wolf Signed-off-by: Philippe Mathieu-Daudé --- bsd-user/qemu.h | 1 - include/block/block_int-common.h | 1 - include/block/graph-lock.h | 2 - include/exec/page-protection.h | 2 - include/qemu/clang-tsa.h | 114 ------------------------------- include/qemu/compiler.h | 87 +++++++++++++++++++++++ include/qemu/thread.h | 1 - block/create.c | 1 - tests/unit/test-bdrv-drain.c | 1 - tests/unit/test-block-iothread.c | 1 - util/qemu-thread-posix.c | 1 - 11 files changed, 87 insertions(+), 125 deletions(-) delete mode 100644 include/qemu/clang-tsa.h diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index 3eaa14f3f56..4e97c796318 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -40,7 +40,6 @@ extern char **environ; #include "target.h" #include "exec/gdbstub.h" #include "exec/page-protection.h" -#include "qemu/clang-tsa.h" #include "accel/tcg/vcpu-state.h" #include "qemu-os.h" diff --git a/include/block/block_int-common.h b/include/block/block_int-common.h index bb91a0f62fa..ebb4e56a503 100644 --- a/include/block/block_int-common.h +++ b/include/block/block_int-common.h @@ -28,7 +28,6 @@ #include "block/block-common.h" #include "block/block-global-state.h" #include "block/snapshot.h" -#include "qemu/clang-tsa.h" #include "qemu/iov.h" #include "qemu/rcu.h" #include "qemu/stats64.h" diff --git a/include/block/graph-lock.h b/include/block/graph-lock.h index dc8d9491843..2c26c721081 100644 --- a/include/block/graph-lock.h +++ b/include/block/graph-lock.h @@ -20,8 +20,6 @@ #ifndef GRAPH_LOCK_H #define GRAPH_LOCK_H -#include "qemu/clang-tsa.h" - /** * Graph Lock API * This API provides a rwlock used to protect block layer diff --git a/include/exec/page-protection.h b/include/exec/page-protection.h index bae3355f62c..3e0a8a03331 100644 --- a/include/exec/page-protection.h +++ b/include/exec/page-protection.h @@ -40,8 +40,6 @@ #ifdef CONFIG_USER_ONLY -#include "qemu/clang-tsa.h" - void TSA_NO_TSA mmap_lock(void); void TSA_NO_TSA mmap_unlock(void); bool have_mmap_lock(void); diff --git a/include/qemu/clang-tsa.h b/include/qemu/clang-tsa.h deleted file mode 100644 index ba06fb8c924..00000000000 --- a/include/qemu/clang-tsa.h +++ /dev/null @@ -1,114 +0,0 @@ -#ifndef CLANG_TSA_H -#define CLANG_TSA_H - -/* - * Copyright 2018 Jarkko Hietaniemi - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without - * limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -/* http://clang.llvm.org/docs/ThreadSafetyAnalysis.html - * - * TSA is available since clang 3.6-ish. - */ -#ifdef __clang__ -# define TSA(x) __attribute__((x)) -#else -# define TSA(x) /* No TSA, make TSA attributes no-ops. */ -#endif - -/* TSA_CAPABILITY() is used to annotate typedefs: - * - * typedef pthread_mutex_t TSA_CAPABILITY("mutex") tsa_mutex; - */ -#define TSA_CAPABILITY(x) TSA(capability(x)) - -/* TSA_GUARDED_BY() is used to annotate global variables, - * the data is guarded: - * - * Foo foo TSA_GUARDED_BY(mutex); - */ -#define TSA_GUARDED_BY(x) TSA(guarded_by(x)) - -/* TSA_PT_GUARDED_BY() is used to annotate global pointers, the data - * behind the pointer is guarded. - * - * Foo* ptr TSA_PT_GUARDED_BY(mutex); - */ -#define TSA_PT_GUARDED_BY(x) TSA(pt_guarded_by(x)) - -/* The TSA_REQUIRES() is used to annotate functions: the caller of the - * function MUST hold the resource, the function will NOT release it. - * - * More than one mutex may be specified, comma-separated. - * - * void Foo(void) TSA_REQUIRES(mutex); - */ -#define TSA_REQUIRES(...) TSA(requires_capability(__VA_ARGS__)) -#define TSA_REQUIRES_SHARED(...) TSA(requires_shared_capability(__VA_ARGS__)) - -/* TSA_EXCLUDES() is used to annotate functions: the caller of the - * function MUST NOT hold resource, the function first acquires the - * resource, and then releases it. - * - * More than one mutex may be specified, comma-separated. - * - * void Foo(void) TSA_EXCLUDES(mutex); - */ -#define TSA_EXCLUDES(...) TSA(locks_excluded(__VA_ARGS__)) - -/* TSA_ACQUIRE() is used to annotate functions: the caller of the - * function MUST NOT hold the resource, the function will acquire the - * resource, but NOT release it. - * - * More than one mutex may be specified, comma-separated. - * - * void Foo(void) TSA_ACQUIRE(mutex); - */ -#define TSA_ACQUIRE(...) TSA(acquire_capability(__VA_ARGS__)) -#define TSA_ACQUIRE_SHARED(...) TSA(acquire_shared_capability(__VA_ARGS__)) - -/* TSA_RELEASE() is used to annotate functions: the caller of the - * function MUST hold the resource, but the function will then release it. - * - * More than one mutex may be specified, comma-separated. - * - * void Foo(void) TSA_RELEASE(mutex); - */ -#define TSA_RELEASE(...) TSA(release_capability(__VA_ARGS__)) -#define TSA_RELEASE_SHARED(...) TSA(release_shared_capability(__VA_ARGS__)) - -/* TSA_NO_TSA is used to annotate functions. Use only when you need to. - * - * void Foo(void) TSA_NO_TSA; - */ -#define TSA_NO_TSA TSA(no_thread_safety_analysis) - -/* - * TSA_ASSERT() is used to annotate functions: This function will assert that - * the lock is held. When it returns, the caller of the function is assumed to - * already hold the resource. - * - * More than one mutex may be specified, comma-separated. - */ -#define TSA_ASSERT(...) TSA(assert_capability(__VA_ARGS__)) -#define TSA_ASSERT_SHARED(...) TSA(assert_shared_capability(__VA_ARGS__)) - -#endif /* #ifndef CLANG_TSA_H */ diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h index d904408e5ed..af0a9b17ff9 100644 --- a/include/qemu/compiler.h +++ b/include/qemu/compiler.h @@ -207,6 +207,93 @@ # define QEMU_USED #endif +/* http://clang.llvm.org/docs/ThreadSafetyAnalysis.html + * + * TSA is available since clang 3.6-ish. + */ +#ifdef __clang__ +# define TSA(x) __attribute__((x)) +#else +# define TSA(x) /* No TSA, make TSA attributes no-ops. */ +#endif + +/* TSA_CAPABILITY() is used to annotate typedefs: + * + * typedef pthread_mutex_t TSA_CAPABILITY("mutex") tsa_mutex; + */ +#define TSA_CAPABILITY(x) TSA(capability(x)) + +/* TSA_GUARDED_BY() is used to annotate global variables, + * the data is guarded: + * + * Foo foo TSA_GUARDED_BY(mutex); + */ +#define TSA_GUARDED_BY(x) TSA(guarded_by(x)) + +/* TSA_PT_GUARDED_BY() is used to annotate global pointers, the data + * behind the pointer is guarded. + * + * Foo* ptr TSA_PT_GUARDED_BY(mutex); + */ +#define TSA_PT_GUARDED_BY(x) TSA(pt_guarded_by(x)) + +/* The TSA_REQUIRES() is used to annotate functions: the caller of the + * function MUST hold the resource, the function will NOT release it. + * + * More than one mutex may be specified, comma-separated. + * + * void Foo(void) TSA_REQUIRES(mutex); + */ +#define TSA_REQUIRES(...) TSA(requires_capability(__VA_ARGS__)) +#define TSA_REQUIRES_SHARED(...) TSA(requires_shared_capability(__VA_ARGS__)) + +/* TSA_EXCLUDES() is used to annotate functions: the caller of the + * function MUST NOT hold resource, the function first acquires the + * resource, and then releases it. + * + * More than one mutex may be specified, comma-separated. + * + * void Foo(void) TSA_EXCLUDES(mutex); + */ +#define TSA_EXCLUDES(...) TSA(locks_excluded(__VA_ARGS__)) + +/* TSA_ACQUIRE() is used to annotate functions: the caller of the + * function MUST NOT hold the resource, the function will acquire the + * resource, but NOT release it. + * + * More than one mutex may be specified, comma-separated. + * + * void Foo(void) TSA_ACQUIRE(mutex); + */ +#define TSA_ACQUIRE(...) TSA(acquire_capability(__VA_ARGS__)) +#define TSA_ACQUIRE_SHARED(...) TSA(acquire_shared_capability(__VA_ARGS__)) + +/* TSA_RELEASE() is used to annotate functions: the caller of the + * function MUST hold the resource, but the function will then release it. + * + * More than one mutex may be specified, comma-separated. + * + * void Foo(void) TSA_RELEASE(mutex); + */ +#define TSA_RELEASE(...) TSA(release_capability(__VA_ARGS__)) +#define TSA_RELEASE_SHARED(...) TSA(release_shared_capability(__VA_ARGS__)) + +/* TSA_NO_TSA is used to annotate functions. Use only when you need to. + * + * void Foo(void) TSA_NO_TSA; + */ +#define TSA_NO_TSA TSA(no_thread_safety_analysis) + +/* + * TSA_ASSERT() is used to annotate functions: This function will assert that + * the lock is held. When it returns, the caller of the function is assumed to + * already hold the resource. + * + * More than one mutex may be specified, comma-separated. + */ +#define TSA_ASSERT(...) TSA(assert_capability(__VA_ARGS__)) +#define TSA_ASSERT_SHARED(...) TSA(assert_shared_capability(__VA_ARGS__)) + /* * Ugly CPP trick that is like "defined FOO", but also works in C * code. Useful to replace #ifdef with "if" statements; assumes diff --git a/include/qemu/thread.h b/include/qemu/thread.h index 7eba27a7049..6f800aad31a 100644 --- a/include/qemu/thread.h +++ b/include/qemu/thread.h @@ -3,7 +3,6 @@ #include "qemu/processor.h" #include "qemu/atomic.h" -#include "qemu/clang-tsa.h" typedef struct QemuCond QemuCond; typedef struct QemuSemaphore QemuSemaphore; diff --git a/block/create.c b/block/create.c index 72abafb4c12..6b23a216753 100644 --- a/block/create.c +++ b/block/create.c @@ -24,7 +24,6 @@ #include "qemu/osdep.h" #include "block/block_int.h" -#include "qemu/clang-tsa.h" #include "qemu/job.h" #include "qemu/main-loop.h" #include "qapi/qapi-commands-block-core.h" diff --git a/tests/unit/test-bdrv-drain.c b/tests/unit/test-bdrv-drain.c index 98ad89b390c..7410e6f3528 100644 --- a/tests/unit/test-bdrv-drain.c +++ b/tests/unit/test-bdrv-drain.c @@ -28,7 +28,6 @@ #include "system/block-backend.h" #include "qapi/error.h" #include "qemu/main-loop.h" -#include "qemu/clang-tsa.h" #include "iothread.h" static QemuEvent done_event; diff --git a/tests/unit/test-block-iothread.c b/tests/unit/test-block-iothread.c index 1de04a8a13d..26a6c051758 100644 --- a/tests/unit/test-block-iothread.c +++ b/tests/unit/test-block-iothread.c @@ -29,7 +29,6 @@ #include "system/block-backend.h" #include "qapi/error.h" #include "qapi/qmp/qdict.h" -#include "qemu/clang-tsa.h" #include "qemu/main-loop.h" #include "iothread.h" diff --git a/util/qemu-thread-posix.c b/util/qemu-thread-posix.c index 6fff4162ac6..b2e26e21205 100644 --- a/util/qemu-thread-posix.c +++ b/util/qemu-thread-posix.c @@ -17,7 +17,6 @@ #include "qemu-thread-common.h" #include "qemu/tsan.h" #include "qemu/bitmap.h" -#include "qemu/clang-tsa.h" #ifdef CONFIG_PTHREAD_SET_NAME_NP #include From patchwork Thu Jan 23 23:43:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13948738 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 786F7C02182 for ; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a17d6e2sm989811f8f.23.2025.01.23.15.44.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Jan 2025 15:44:26 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Igor Mammedov , =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, David Hildenbrand , qemu-s390x@nongnu.org, xen-devel@lists.xenproject.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 02/20] user: Extract common MMAP API to 'user/mmap.h' Date: Fri, 24 Jan 2025 00:43:56 +0100 Message-ID: <20250123234415.59850-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250123234415.59850-1-philmd@linaro.org> References: <20250123234415.59850-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Keep common MMAP-related declarations in a single place. Note, this disable ThreadSafetyAnalysis on Linux for: - mmap_fork_start() - mmap_fork_end(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/qemu.h | 12 +----------- include/user/mmap.h | 32 ++++++++++++++++++++++++++++++++ linux-user/user-mmap.h | 19 ++----------------- 3 files changed, 35 insertions(+), 28 deletions(-) create mode 100644 include/user/mmap.h diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index 4e97c796318..c1c508281a8 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -32,6 +32,7 @@ extern char **environ; #include "user/thunk.h" +#include "user/mmap.h" #include "target_arch.h" #include "syscall_defs.h" #include "target_syscall.h" @@ -233,19 +234,8 @@ void print_taken_signal(int target_signum, const target_siginfo_t *tinfo); extern int do_strace; /* mmap.c */ -int target_mprotect(abi_ulong start, abi_ulong len, int prot); -abi_long target_mmap(abi_ulong start, abi_ulong len, int prot, - int flags, int fd, off_t offset); -int target_munmap(abi_ulong start, abi_ulong len); -abi_long target_mremap(abi_ulong old_addr, abi_ulong old_size, - abi_ulong new_size, unsigned long flags, - abi_ulong new_addr); int target_msync(abi_ulong start, abi_ulong len, int flags); -extern abi_ulong mmap_next_start; -abi_ulong mmap_find_vma(abi_ulong start, abi_ulong size); void mmap_reserve(abi_ulong start, abi_ulong size); -void TSA_NO_TSA mmap_fork_start(void); -void TSA_NO_TSA mmap_fork_end(int child); /* main.c */ extern char qemu_proc_pathname[]; diff --git a/include/user/mmap.h b/include/user/mmap.h new file mode 100644 index 00000000000..4d004e6b822 --- /dev/null +++ b/include/user/mmap.h @@ -0,0 +1,32 @@ +/* + * MMAP declarations for QEMU user emulation + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef USER_MMAP_H +#define USER_MMAP_H + +#include "user/abitypes.h" + +/* + * mmap_next_start: The base address for the next mmap without hint, + * increased after each successful map, starting at task_unmapped_base. + * This is an optimization within QEMU and not part of ADDR_COMPAT_LAYOUT. + */ +extern abi_ulong mmap_next_start; + +int target_mprotect(abi_ulong start, abi_ulong len, int prot); + +abi_long target_mmap(abi_ulong start, abi_ulong len, int prot, + int flags, int fd, off_t offset); +int target_munmap(abi_ulong start, abi_ulong len); +abi_long target_mremap(abi_ulong old_addr, abi_ulong old_size, + abi_ulong new_size, unsigned long flags, + abi_ulong new_addr); + +abi_ulong mmap_find_vma(abi_ulong, abi_ulong, abi_ulong); + +void TSA_NO_TSA mmap_fork_start(void); +void TSA_NO_TSA mmap_fork_end(int child); + +#endif diff --git a/linux-user/user-mmap.h b/linux-user/user-mmap.h index b94bcdcf83c..dfc4477a720 100644 --- a/linux-user/user-mmap.h +++ b/linux-user/user-mmap.h @@ -18,6 +18,8 @@ #ifndef LINUX_USER_USER_MMAP_H #define LINUX_USER_USER_MMAP_H +#include "user/mmap.h" + /* * Guest parameters for the ADDR_COMPAT_LAYOUT personality * (at present this is the only layout supported by QEMU). @@ -39,24 +41,7 @@ extern abi_ulong task_unmapped_base; extern abi_ulong elf_et_dyn_base; -/* - * mmap_next_start: The base address for the next mmap without hint, - * increased after each successful map, starting at task_unmapped_base. - * This is an optimization within QEMU and not part of ADDR_COMPAT_LAYOUT. - */ -extern abi_ulong mmap_next_start; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a1c4006sm982952f8f.94.2025.01.23.15.44.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Jan 2025 15:44:32 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Igor Mammedov , =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, David Hildenbrand , qemu-s390x@nongnu.org, xen-devel@lists.xenproject.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 03/20] gdbstub: Check for TCG before calling tb_flush() Date: Fri, 24 Jan 2025 00:43:57 +0100 Message-ID: <20250123234415.59850-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250123234415.59850-1-philmd@linaro.org> References: <20250123234415.59850-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Use the tcg_enabled() check so the compiler can elide the call when TCG isn't available, allowing to remove the tb_flush() stub. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson --- accel/stubs/tcg-stub.c | 4 ---- gdbstub/system.c | 5 ++++- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c index 7f4208fddf2..b2b9881bdfb 100644 --- a/accel/stubs/tcg-stub.c +++ b/accel/stubs/tcg-stub.c @@ -14,10 +14,6 @@ #include "exec/tb-flush.h" #include "exec/exec-all.h" -void tb_flush(CPUState *cpu) -{ -} - G_NORETURN void cpu_loop_exit(CPUState *cpu) { g_assert_not_reached(); diff --git a/gdbstub/system.c b/gdbstub/system.c index 8ce79fa88cf..7f047a285c8 100644 --- a/gdbstub/system.c +++ b/gdbstub/system.c @@ -22,6 +22,7 @@ #include "system/cpus.h" #include "system/runstate.h" #include "system/replay.h" +#include "system/tcg.h" #include "hw/core/cpu.h" #include "hw/cpu/cluster.h" #include "hw/boards.h" @@ -171,7 +172,9 @@ static void gdb_vm_state_change(void *opaque, bool running, RunState state) } else { trace_gdbstub_hit_break(); } - tb_flush(cpu); + if (tcg_enabled()) { + tb_flush(cpu); + } ret = GDB_SIGNAL_TRAP; break; case RUN_STATE_PAUSED: From patchwork Thu Jan 23 23:43:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13948748 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 29921C0218B for ; Thu, 23 Jan 2025 23:48:08 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tb6sN-0006Eq-FX; Thu, 23 Jan 2025 18:44:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tb6sM-0006DY-Ak for qemu-devel@nongnu.org; Thu, 23 Jan 2025 18:44:42 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tb6sK-0003v6-6C for qemu-devel@nongnu.org; Thu, 23 Jan 2025 18:44:42 -0500 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-43635796b48so10273555e9.0 for ; Thu, 23 Jan 2025 15:44:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1737675878; x=1738280678; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JSvw35u1c/GeD9pKIKqf6WHVcOBbPhJhoq/j5sOwl2I=; b=GoRdQTBO60uisqPbsnCeaTXiqcwQ5VAL/Y/vqmdVvUMB93sGL3FBXU2mkaz5g1+AQ1 07JppaTzUfZ4YljrB3RzYn34yLc5dWPVkmC4m/3Zqn7sQLgBFZ6ImFig1CEyQD2xfRhc AtbObKo7A4Kwz6bYz12mqVpFu0QPgoJD8qVO2wOyWvh4nCv9hSCuOayoBRCBxeFGcvYS Kk0umoxokrBnUqX8SuA5ctRAP2hIQKg6aS1O8WNJU4jjWZUowTHrFi28aSFHIzxTBA+U J9L+WNS4RyBfcbPGhgkLXJ35nQiPhSNLqeSsWsj9Mh9BgmS3jzbQkOf9K/ZNNVt9yVZl 8zBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737675878; x=1738280678; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JSvw35u1c/GeD9pKIKqf6WHVcOBbPhJhoq/j5sOwl2I=; b=Wnf3F4KwCllpemmNB73YfgX1LUj7xm2ODDZJK+UsFumsQhl/2FezcsVY2lidrKxgqm sbrP47a8rc/1RUVq06+JW/rmsgXRrUdsR+E3od7ONTnXh4wg7KpfIwX7eKCMkTlsYMFR uOKhRNXpYTFpK3Q/JZnoQVY6EqfRUQwul+LljjJe1tkMRqwcqnjYbO5iQtIHfxPyejW7 2i1o94aWeOCvCbo/CW6tnao265qg4/CCJjnyKvzdRnS8pXivx2hu5Y+2msKFgNFkoews gQn68v2y788LxZ4S1kILyB/SxHDboumn/pni4QCUAnh2UNEsIDlOtfQ539OAHu9prcar p2bw== X-Gm-Message-State: AOJu0Yy3m4so1rS20WQDNcbZoihzwiFkop4FGG8fiDXF5Z7QscVidtBY ebn+pu7e3I6GdlpxMJaBK6syKhOy5LSQXjb9zvE22S2C8PdXl5PAzfq9Dbh8UGW2UpeMjWcketv F54s= X-Gm-Gg: ASbGncti4jL4rroGFnRfeapUfQHvnuyH6In7p17I0HFlw5Hij1MYOR42UQzcbsX+lO8 1r7AF5lBtxqjJHqCghA402kuYNbuk57pKjRI9PF2TC1JazAWmZxPVRliGRaiYomEbIIrAOBxwCi 4q/IjMDV/S382+aiaxCsA/tVxLvluTzF8uRdcuCoFP+ajlZ+SOGBQQYBxZC1wVgVeKC9Y3g+sID WFZlGmPlJpiLHbUiHKmkZDHyLbev29gSelgs5OsNCCpd2ZTn+XQRbE1WecHT5tNyBeFdnA9FpBW y0m6F+t9jWKQ7IrTXmHQObqTDHJ6eJGPw4tb9Qv7XeFVLR3od8zo5Mjw3fPyQ9bEGg== X-Google-Smtp-Source: AGHT+IGo8PNbuw90Bq4/JTfJj+icg7kmRyyI+cmqGdvUrpM4r/a237PZVlDOFDC6zvKvXQiH9M0QlA== X-Received: by 2002:a05:600c:3d05:b0:434:9e17:190c with SMTP id 5b1f17b1804b1-438b87f953fmr44596875e9.0.1737675878313; Thu, 23 Jan 2025 15:44:38 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd4857c3sm7081075e9.10.2025.01.23.15.44.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Jan 2025 15:44:37 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Igor Mammedov , =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, David Hildenbrand , qemu-s390x@nongnu.org, xen-devel@lists.xenproject.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 04/20] cpus: Cache CPUClass early in instance_init() handler Date: Fri, 24 Jan 2025 00:43:58 +0100 Message-ID: <20250123234415.59850-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250123234415.59850-1-philmd@linaro.org> References: <20250123234415.59850-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Cache CPUClass as early as possible, when the instance is initialized. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- cpu-target.c | 3 --- hw/core/cpu-common.c | 3 +++ 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/cpu-target.c b/cpu-target.c index 667688332c9..89874496a41 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -134,9 +134,6 @@ const VMStateDescription vmstate_cpu_common = { bool cpu_exec_realizefn(CPUState *cpu, Error **errp) { - /* cache the cpu class for the hotpath */ - cpu->cc = CPU_GET_CLASS(cpu); - if (!accel_cpu_common_realize(cpu, errp)) { return false; } diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index cb79566cc51..ff605059c15 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -238,6 +238,9 @@ static void cpu_common_initfn(Object *obj) { CPUState *cpu = CPU(obj); + /* cache the cpu class for the hotpath */ + cpu->cc = CPU_GET_CLASS(cpu); + gdb_init_cpu(cpu); cpu->cpu_index = UNASSIGNED_CPU_INDEX; cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX; From patchwork Thu Jan 23 23:43:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13948792 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 90476C02182 for ; Thu, 23 Jan 2025 23:49:34 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tb6sV-0006IQ-1C; Thu, 23 Jan 2025 18:44:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tb6sS-0006Gk-Gh for qemu-devel@nongnu.org; Thu, 23 Jan 2025 18:44:48 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tb6sP-0003wm-Pw for qemu-devel@nongnu.org; Thu, 23 Jan 2025 18:44:48 -0500 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-38a8b35e168so1073183f8f.1 for ; Thu, 23 Jan 2025 15:44:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1737675884; x=1738280684; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=89WHzW+ji4rB+60gFYzeRD9ADgUNDHjcXvYSPMINgc0=; b=IUCLje6AsykLpWFfkO2DPFz3e1nLIYD10d6w/vMvcWhKSLSKROfqvYPg4W3ifaK0sO z/txwjr0lY1M/oRcf3nk3Zf68DhZsZC4FOlCc8l4WzYUiHnsbEmGelRF1/wDm8mWzcZd 51wDyPdo0FDgTVMpxcnYN2eST92TE1eZUWCTUUe+dnJ0MGZNxkpraRCea5+aXUqyzlQ2 beA3qEuSULdpeCWrvqHc1gZ61g7zGXbMzkjFTehA1EpkND/LdO1ar5zyv6UzTUtUaGei K+wIJwN4i0k9ObTh2nqLB4MbtuMuUHz862nE+4aRjrFOGg+TGWDjWhhKRcCsKgo0U+nG XAXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737675884; x=1738280684; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=89WHzW+ji4rB+60gFYzeRD9ADgUNDHjcXvYSPMINgc0=; b=wuZ2wFf3ENMYotQ9oGqS11vLrlppECbtPQ66nL6HID4ZQfblZkEPi0O4d4XMmrx6RN NfCEh+oVkXuMHr6xUGaZojj7q6XRNCfnYrFucu7BQIWCWNByZAXq/pRmSZRJqIk1tNPz KszsE0qQnIXFy9hvPCTahxJ9N0ycx0hP8VBV1z8trjxaQyMwgqJrCR1L0wduGWECynbE staDYUkEoZSAPFL8ZUQFA/vTVmPFrlen6zOGoYsXbxApHucqDCglP8f/H2FxyKFowGSN 86agIB8BBwIZc5hy0H2KmEDSQeA6c38jcM5cGF5P/A/tNL1hJfok3Ud0qgE+G3bWAMlI RotQ== X-Gm-Message-State: AOJu0Yw9xLQrV4lr5Vbt5XHHv+2f7+vw3lLwEkNtIxs0L7vHmJlkyc6e EgncVs9tQ544Ppb3PvD4rVLlYYWMdXbtl36cGsrU1h1qjJ3BylxkBh88Mie0TEMGEX5kP9RheM/ YgjM= X-Gm-Gg: ASbGncsHPYio0cNrkwgHQbax6ZkBI9GeVsC2I8Bau7wl8FBrps8qubtYWsBR+ppd/q9 fw53zJhtKKAQIb1oYP+AV2SphOv3qDnoz5tDHEUpeWzJ2fx256PV488JUJOtsmjpWeWs8j/fghw mdO4z1YBq7j2MQuLlAI6Vh2hE88WjGRX1qvLaHf/CmwUspuuHPkLO+z0g/Y9z35PUYq1OmvcRDP re6DY0IRx8821a3MBEGiUEWhCVdx/hYus1YZZ9Ri3EBE7B44a+YJw3B0zaZqiJNedlGfNi2voY/ U6qRvEutrVYpyw85MZ8jiyeX4HmnZ+9LItAdE5+RdPlctaWg452wOYM= X-Google-Smtp-Source: AGHT+IHfcp2D5aSm8Sn0VT4IidLdBYhD/KSzWcZHka724j1qpNfMP/dVIsxPCprx8nPoBb5TgAtEpw== X-Received: by 2002:a05:6000:1fa9:b0:38b:f4dc:44ad with SMTP id ffacd0b85a97d-38c2b65ebf8mr997845f8f.5.1737675884076; Thu, 23 Jan 2025 15:44:44 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd4d29cesm6991745e9.35.2025.01.23.15.44.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Jan 2025 15:44:43 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Igor Mammedov , =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, David Hildenbrand , qemu-s390x@nongnu.org, xen-devel@lists.xenproject.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 05/20] cpus: Keep default fields initialization in cpu_common_initfn() Date: Fri, 24 Jan 2025 00:43:59 +0100 Message-ID: <20250123234415.59850-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250123234415.59850-1-philmd@linaro.org> References: <20250123234415.59850-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org cpu_common_initfn() is our target agnostic initializer, while cpu_exec_initfn() is the target specific one. The %as and %num_ases fields are not target specific, so initialize them in the common helper. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- cpu-target.c | 3 --- hw/core/cpu-common.c | 2 ++ 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/cpu-target.c b/cpu-target.c index 89874496a41..75501a909df 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -234,9 +234,6 @@ void cpu_class_init_props(DeviceClass *dc) void cpu_exec_initfn(CPUState *cpu) { - cpu->as = NULL; - cpu->num_ases = 0; - #ifndef CONFIG_USER_ONLY cpu->memory = get_system_memory(); object_ref(OBJECT(cpu->memory)); diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index ff605059c15..71425cb7422 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -244,6 +244,8 @@ static void cpu_common_initfn(Object *obj) gdb_init_cpu(cpu); cpu->cpu_index = UNASSIGNED_CPU_INDEX; cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX; + cpu->as = NULL; + cpu->num_ases = 0; /* user-mode doesn't have configurable SMP topology */ /* the default value is changed by qemu_init_vcpu() for system-mode */ cpu->nr_threads = 1; From patchwork Thu Jan 23 23:44:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13948737 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 78E19C0218B for ; Thu, 23 Jan 2025 23:45:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tb6sa-0006LR-3l; Thu, 23 Jan 2025 18:44:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tb6sY-0006JN-0Q for qemu-devel@nongnu.org; Thu, 23 Jan 2025 18:44:54 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tb6sV-0003yK-Gr for qemu-devel@nongnu.org; Thu, 23 Jan 2025 18:44:53 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-43622267b2eso15565265e9.0 for ; Thu, 23 Jan 2025 15:44:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1737675890; x=1738280690; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VK0JABDJF/QMP4ClWDlwjdLf62KvnH3DnM23ZO9feXo=; b=ymH3z41q7DT98Z3mTLQ3dPO8bRehaNOzLrCHVnYwJcHW1sc2cLZ7/JEwH68OQoeEEy Z5nFIwdFqJ6iCWugo66MKB+WvAaLkhIPd2FzXMlG1TgOSu3aQu2LE2mZ7V3sTSA8SaXv S0vLfct7eunB0hdb3qkN4Uj9QC9I7xa3BJJJlF7BF2ZuHeZo9ARiNWqV9N4d9Y9LLyAt eACRY+RyG8DhRy8Pc8SHrR93c1lMoBNf8gAvm8/M3TibwipQEeIrPoZPp41x8uHhnm5k g5jS/cn+JRcxcnu/KLqFugnycUX743zyuuLTLJ3CLv2IByGqsIz3gCtbToiSj3xU+h8L yhlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737675890; x=1738280690; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VK0JABDJF/QMP4ClWDlwjdLf62KvnH3DnM23ZO9feXo=; b=XQQRN1UTr9aqbOP3SKfnojlijCh3GYfEPoEcmCH7k4+NCSLy+nXJYzmk/13rJlzCiD rV2BMlRT0C08Epm7Uz1T40f9avUPnElTb/lJ7uD4X+NvwEPyCUXCi/SjfS4IOV9HdYSA a+79lr1JatJAAY5xrCIAaP4JIJyShsoCCHQwnPvriJvJO0gN55reoHhhOPfpuBbYqMRb sUFX5uRCq9J57HIAeGvV2Zmwfpko1TTJwAOYYtq5Lx60JiMTX3vIniGAGJbQPRlSOVyH Mj06UUMGAmAWpgbvo/5e/EVKDLG9FCUw8OKilBoOVRYc18ZCi4NNzTesZSVvONSOcwh2 XkFw== X-Gm-Message-State: AOJu0Yw710xUOWecKlLNM3RsAOywdhvZPm46beEszej5hDPxxECaUzpO bU+IPKbO3q+86J7zufVd26ZcEqE5MqcUMDoP6Wl32EzubviD41CTNDfyKYCzpMkgEAG3LOF0qCg OU9o= X-Gm-Gg: ASbGncu6IsduWuZUb3UCEt/bj/0VTKCirxvwv3rF/bUrxPyFyMaCYtGj+0tSx11wMxx vFQBbKMkG9xcariotJNViH2oY6g+bmZ/BxXVXshjv3KWRh33Hbmx5YqL9awcF7y9ISpfh9/+LpS aQ0TJwlc/buIr28AYzyyK1aeVqsqxexIYvoibluSzEAK/dAXExVyODLvE/aNjDVfFGepVQXYvOW BmTYa5vjfergRhfALPyBjYA5r2LJ+WqRTORvclEEqmYaB1fAYTjz0SREBQfm+DUb0p/UrWmx4L2 TL1DvW4sA14/4zI0PsbWLKPZhmYeXhGse6B5io6L9kgpPZb1qOD/v7A= X-Google-Smtp-Source: AGHT+IGSMRqXknIm20dxUVJ6YnBSj5qdwQEIsknPsDpqx1Ro9qYQKL2SDEG840LoeQHivalI7LVk8Q== X-Received: by 2002:a5d:64a1:0:b0:386:3262:28c6 with SMTP id ffacd0b85a97d-38bf5677c09mr24857649f8f.5.1737675889741; Thu, 23 Jan 2025 15:44:49 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a1c4161sm952291f8f.88.2025.01.23.15.44.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Jan 2025 15:44:48 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Igor Mammedov , =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, David Hildenbrand , qemu-s390x@nongnu.org, xen-devel@lists.xenproject.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 06/20] accel/kvm: Remove unused 'system/cpus.h' header in kvm-cpus.h Date: Fri, 24 Jan 2025 00:44:00 +0100 Message-ID: <20250123234415.59850-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250123234415.59850-1-philmd@linaro.org> References: <20250123234415.59850-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Missed in commit b86f59c7155 ("accel: replace struct CpusAccel with AccelOpsClass") which removed the single CpusAccel use. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- accel/kvm/kvm-cpus.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/accel/kvm/kvm-cpus.h b/accel/kvm/kvm-cpus.h index b5435286e42..688511151c8 100644 --- a/accel/kvm/kvm-cpus.h +++ b/accel/kvm/kvm-cpus.h @@ -10,8 +10,6 @@ #ifndef KVM_CPUS_H #define KVM_CPUS_H -#include "system/cpus.h" - int kvm_init_vcpu(CPUState *cpu, Error **errp); int kvm_cpu_exec(CPUState *cpu); void kvm_destroy_vcpu(CPUState *cpu); From patchwork Thu Jan 23 23:44:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13948740 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2F0BFC0218B for ; Thu, 23 Jan 2025 23:46:07 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tb6sl-0006Rd-1V; Thu, 23 Jan 2025 18:45:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tb6se-0006Nw-4W for qemu-devel@nongnu.org; Thu, 23 Jan 2025 18:45:00 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tb6sb-0003zl-B2 for qemu-devel@nongnu.org; Thu, 23 Jan 2025 18:44:59 -0500 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-43621d27adeso10192185e9.2 for ; Thu, 23 Jan 2025 15:44:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1737675895; x=1738280695; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zgM0qO1a7TmnAaVr92PdlZQNV8dbDE9Lo8CXyhKvg/4=; b=XRbsaPaW/Mjo1pMNwc4umgoghtu4Qy8WcsPBBfhFdo+xb1lmAOxV8cCd5fnnYGMDPy 5IUpKlcaE/GYE9IRaxsBIyj66D/9ZinJEFAPL5tUF9Xr1729EnrCZfUa1/iitQvJDxV/ jCPUeMLjz/01iAYwVxyNh/XfRyRe0hkRFYJe5y1oovwWZKS3Z6aF7xhLkwc1J7SmRehJ tyg8CfxxfatD/6k1Xoz0XIJGzLE44RoPcQMtgHnhIvkMKP5gzYXePL7VsL6D6Ovc+aLq Pme1tw6MVqN8aV4ptz8igF4LtnVNWUoc7VDA8mAIEh25Nmq2dNZ/4NLuzfYCADsb6pYB WMiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737675895; x=1738280695; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zgM0qO1a7TmnAaVr92PdlZQNV8dbDE9Lo8CXyhKvg/4=; b=aO4ChTAdAQ3yzHwLBciw/q+LOs9IrgNKtMRRe65yS045Qt6SHxByz7HvxYh7lUnoAv W2zmzDw/5o+K+rsGdKivGI29cWXJzfmac7YBrgUpP24Fno6Olm+r5ZMjv/UjV93qeR7v nMTp7SUUmK3Zdcs3bvA8UPKZ/3zQ6NMBHo19nceBy82Qdv1O+/8kI4BkoSiBZixq7bnM 6FIQaxapsVE49ZBzEvZr/Nz4sZbwKziPIRKzjrzc0EwfrQywsLP5EhiCHx5XDXsQfYpB IOHSYSZn5jAXK7lG0yOInI1dqDXv0MPmhAuGg5mmnffzSCzfz3QgbsZiadTI7OjltTID tHCg== X-Gm-Message-State: AOJu0Yw1snTyi0NWkWOet2pfTx68bwf8SCTEp7fK3x4IwvHdgaB95J10 4kC+c0jpeTshtpgvky4vzPEW2Jd6TqWbctQtegxlX67BekQ0Q5XgUHkRq1EOpIUBLKOqvD34TWo mkjw= X-Gm-Gg: ASbGncvD/9K8jnA5k1i7DzJ1iLHie5Bh9TAjjp8lBVuIwDx/ubQwiJI1U/1MVptuEwL TTtLNfdXTpaRoGV49vjTw6TcsStl2qgDdgO/1g2DhI6+zNlcc5iFuZVmWYV1KUhAbeUyVctRJjo 5sXxO+PtoaIgSjeF6o5VvXhzqmASpXlMhHt9wB6Lld5SXeQkfO6Q6JOZJrr3kx54OWedFAZjUyy oZ7Cbi3POsOrcXVG8RgDjJPagiFSK+4CdRG1POOEq8T1FHLRGdRIJjDeGB/etNYMZnqazVpSCBV UGJjQYGIfH4ntFHpILQnraUFJly0mBbYscvIdZdiTSPApLDP+0V1oVs= X-Google-Smtp-Source: AGHT+IFu3bGh+dR4gXvA0Xd23GoBCnM+yfw+G3EPNj4Vc2jg+fj1VnlHOFgKCDXygKj5XAozIyeBjA== X-Received: by 2002:a05:600c:a09:b0:435:9ed3:5688 with SMTP id 5b1f17b1804b1-438913f86dcmr267603485e9.18.1737675895459; Thu, 23 Jan 2025 15:44:55 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd48a94asm7141855e9.23.2025.01.23.15.44.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Jan 2025 15:44:54 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Igor Mammedov , =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, David Hildenbrand , qemu-s390x@nongnu.org, xen-devel@lists.xenproject.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 07/20] accel/tcg: Build tcg_flags helpers as common code Date: Fri, 24 Jan 2025 00:44:01 +0100 Message-ID: <20250123234415.59850-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250123234415.59850-1-philmd@linaro.org> References: <20250123234415.59850-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org While cpu-exec.c is build for each target,tcg_flags helpers aren't target specific. Move them to cpu-exec-common.c to build them once. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- accel/tcg/cpu-exec-common.c | 33 +++++++++++++++++++++++++++++++++ accel/tcg/cpu-exec.c | 32 -------------------------------- 2 files changed, 33 insertions(+), 32 deletions(-) diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c index 6ecfc4e7c21..100746d555a 100644 --- a/accel/tcg/cpu-exec-common.c +++ b/accel/tcg/cpu-exec-common.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" +#include "exec/log.h" #include "system/cpus.h" #include "system/tcg.h" #include "qemu/plugin.h" @@ -25,6 +26,38 @@ bool tcg_allowed; +bool tcg_cflags_has(CPUState *cpu, uint32_t flags) +{ + return cpu->tcg_cflags & flags; +} + +void tcg_cflags_set(CPUState *cpu, uint32_t flags) +{ + cpu->tcg_cflags |= flags; +} + +uint32_t curr_cflags(CPUState *cpu) +{ + uint32_t cflags = cpu->tcg_cflags; + + /* + * Record gdb single-step. We should be exiting the TB by raising + * EXCP_DEBUG, but to simplify other tests, disable chaining too. + * + * For singlestep and -d nochain, suppress goto_tb so that + * we can log -d cpu,exec after every TB. + */ + if (unlikely(cpu->singlestep_enabled)) { + cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR | CF_SINGLE_STEP | 1; + } else if (qatomic_read(&one_insn_per_tb)) { + cflags |= CF_NO_GOTO_TB | 1; + } else if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { + cflags |= CF_NO_GOTO_TB; + } + + return cflags; +} + /* exit the current TB, but without causing any exception to be raised */ void cpu_loop_exit_noexc(CPUState *cpu) { diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8b773d88478..be2ba199d3d 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -148,38 +148,6 @@ static void init_delay_params(SyncClocks *sc, const CPUState *cpu) } #endif /* CONFIG USER ONLY */ -bool tcg_cflags_has(CPUState *cpu, uint32_t flags) -{ - return cpu->tcg_cflags & flags; -} - -void tcg_cflags_set(CPUState *cpu, uint32_t flags) -{ - cpu->tcg_cflags |= flags; -} - -uint32_t curr_cflags(CPUState *cpu) -{ - uint32_t cflags = cpu->tcg_cflags; - - /* - * Record gdb single-step. We should be exiting the TB by raising - * EXCP_DEBUG, but to simplify other tests, disable chaining too. - * - * For singlestep and -d nochain, suppress goto_tb so that - * we can log -d cpu,exec after every TB. - */ - if (unlikely(cpu->singlestep_enabled)) { - cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR | CF_SINGLE_STEP | 1; - } else if (qatomic_read(&one_insn_per_tb)) { - cflags |= CF_NO_GOTO_TB | 1; - } else if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { - cflags |= CF_NO_GOTO_TB; - } - - return cflags; -} - struct tb_desc { vaddr pc; uint64_t cs_base; From patchwork Thu Jan 23 23:44:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13948749 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 67DF7C0218B for ; Thu, 23 Jan 2025 23:48:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tb6sq-0006Zd-Ei; Thu, 23 Jan 2025 18:45:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tb6sn-0006WC-3f for qemu-devel@nongnu.org; Thu, 23 Jan 2025 18:45:09 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tb6si-00043f-5s for qemu-devel@nongnu.org; Thu, 23 Jan 2025 18:45:07 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-4361c705434so10880025e9.3 for ; Thu, 23 Jan 2025 15:45:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1737675902; x=1738280702; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=b+Ptx+X+/4qytTYw1NRizSw3Es7j283R5duCMBs45So=; b=Ef2fc/Pj/OZOiYX1+9odviTVzxzRJ/vZNN8Me63W8E6TIyrDHT6zv6ahYuXGlIwDiw 8eRxo795JASt5yUnNJHTBetdA0hVcgkOITLWvnnwpNzRj9/hCN7Lkt6kmiJyGZRYlgH4 iGzzSwcmx2qJS0aJaAPQF4Ba5dxq8Tml9gmi2a27+LXVOPRoknJpWdtAWujstux7QwNh x7BLc2SDre7ya0+X2/otZGOWSiAheZo2NqL7sccd3Q4WsBEEc3tfbwYa38JubF7NyNVa NpngQeEnG6HvRLYcjZfDvJumPqnFEOWXMh5egUOXn08R6En5VciLj+v4uK5mseTzPoZk Ki/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737675902; x=1738280702; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b+Ptx+X+/4qytTYw1NRizSw3Es7j283R5duCMBs45So=; b=V6r7eDewvRIzQW+NlbchgJF3I1MeZrp4vadit8jaBifnn/tXvmeHHlJqUn/RM4oTES G5VUwFEN62JovITgZ2qbP8xFz59fqBMHJvjM8s8fCRT7pdmrthZFYiAtp6TbaODLqhYv 4EuobpjnkEMlUzufh07Sbhg/3jlSAKwIAwAp9DZU3pKSKJQs7rZnjsI0Kovg4+JKm/Oc Fw6N7ACjIEUbENyPP2lEkDIj/wT37+Lt5mRksFcvj4v8sIvRYFb+7O/GZ7m4JSEs1zrh ZsWCyb0Lv6kzhWJ6UVIaFz6VPXaJIHbERR/Q+/RIblppcnRex3/DMroFnC7mpvSNrToS 1Rqw== X-Gm-Message-State: AOJu0Yytloc5pRO3cOuDOdsXig5vxfCv5/zRk/XHg2KYn3XuwPh2hmRn mJpidplXx0BahJcScvghv5Z1kS3vif2cBvW+dKLoI7/4A1V+Qyxf4IZkZ3Mg/XS2tVNnXDu2RzF NlLw= X-Gm-Gg: ASbGncv5adFQBg+VfNa3tL9KWGSgkdIKy7sVYmuXpgeXzMtRgF2htzpEltCKU4jiYCB nvtShwPeeF3FC71s7ktnkS/9VMenugsLduuFBQygkZ/+bNAM9w+aJDtDbYEdfyuiYT+gESeKBmP ydf23vYbyMAG3G9l0ve4J70kSO9ggE4GUObq4Es+vPKhLem8O8hG662azqfXuBuY2bxu802vSNO w6RSred1c4Lagy3gJMTs5auDcAA8Sj+Z/c+2CKP0bdYocRGoGcAv9k97saUHyNc+RzJwChZxzS1 qIjKK6jI3ppJ6awRNj52Bqo35Kljzu90teNG0Xc/Sjnd+HsYsec7X+I= X-Google-Smtp-Source: AGHT+IGYKHSOUWuv3Z35/L1kDcj+xko6P82ABEfwOu6IFt4mwFRNrLSNCMYz6YlSXtAKxKsobnoAmQ== X-Received: by 2002:a05:600c:46ca:b0:434:a367:2bd9 with SMTP id 5b1f17b1804b1-438913dfd7fmr310320675e9.14.1737675901922; Thu, 23 Jan 2025 15:45:01 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd54c0ecsm6510925e9.30.2025.01.23.15.44.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Jan 2025 15:45:00 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Igor Mammedov , =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, David Hildenbrand , qemu-s390x@nongnu.org, xen-devel@lists.xenproject.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH 08/20] accel/tcg: Restrict tlb_init() / destroy() to TCG Date: Fri, 24 Jan 2025 00:44:02 +0100 Message-ID: <20250123234415.59850-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250123234415.59850-1-philmd@linaro.org> References: <20250123234415.59850-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Move CPU TLB related methods to accel/tcg/ scope, in "internal-common.h". Suggested-by: Richard Henderson Reviewed-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- accel/tcg/internal-common.h | 11 +++++++++++ include/exec/exec-all.h | 16 ---------------- accel/tcg/user-exec-stub.c | 11 +++++++++++ 3 files changed, 22 insertions(+), 16 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index c8d714256cb..d3186721839 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -53,6 +53,17 @@ TranslationBlock *tb_link_page(TranslationBlock *tb); void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, uintptr_t host_pc); +/** + * tlb_init - initialize a CPU's TLB + * @cpu: CPU whose TLB should be initialized + */ +void tlb_init(CPUState *cpu); +/** + * tlb_destroy - destroy a CPU's TLB + * @cpu: CPU whose TLB should be destroyed + */ +void tlb_destroy(CPUState *cpu); + bool tcg_exec_realizefn(CPUState *cpu, Error **errp); void tcg_exec_unrealizefn(CPUState *cpu); diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index d9045c9ac4c..8eb0df48f94 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -29,16 +29,6 @@ #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* cputlb.c */ -/** - * tlb_init - initialize a CPU's TLB - * @cpu: CPU whose TLB should be initialized - */ -void tlb_init(CPUState *cpu); -/** - * tlb_destroy - destroy a CPU's TLB - * @cpu: CPU whose TLB should be destroyed - */ -void tlb_destroy(CPUState *cpu); /** * tlb_flush_page: * @cpu: CPU whose TLB should be flushed @@ -223,12 +213,6 @@ void tlb_set_page(CPUState *cpu, vaddr addr, hwaddr paddr, int prot, int mmu_idx, vaddr size); #else -static inline void tlb_init(CPUState *cpu) -{ -} -static inline void tlb_destroy(CPUState *cpu) -{ -} static inline void tlb_flush_page(CPUState *cpu, vaddr addr) { } diff --git a/accel/tcg/user-exec-stub.c b/accel/tcg/user-exec-stub.c index 4fbe2dbdc88..1d52f48226a 100644 --- a/accel/tcg/user-exec-stub.c +++ b/accel/tcg/user-exec-stub.c @@ -1,6 +1,7 @@ #include "qemu/osdep.h" #include "hw/core/cpu.h" #include "exec/replay-core.h" +#include "internal-common.h" void cpu_resume(CPUState *cpu) { @@ -18,6 +19,16 @@ void cpu_exec_reset_hold(CPUState *cpu) { } +/* User mode emulation does not support softmmu yet. */ + +void tlb_init(CPUState *cpu) +{ +} + +void tlb_destroy(CPUState *cpu) +{ +} + /* User mode emulation does not support record/replay yet. */ bool replay_exception(void) From patchwork Thu Jan 23 23:44:03 2025 Content-Type: text/plain; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a17630asm997952f8f.6.2025.01.23.15.45.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Jan 2025 15:45:06 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Igor Mammedov , =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, David Hildenbrand , qemu-s390x@nongnu.org, xen-devel@lists.xenproject.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 09/20] accel/tcg: Restrict 'icount_align_option' global to TCG Date: Fri, 24 Jan 2025 00:44:03 +0100 Message-ID: <20250123234415.59850-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250123234415.59850-1-philmd@linaro.org> References: <20250123234415.59850-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Since commit 740b1759734 ("cpu-timers, icount: new modules") we don't need to expose icount_align_option to all the system code, we can restrict it to TCG. Since it is used as a boolean, declare it as 'bool' type. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- accel/tcg/internal-common.h | 2 ++ include/system/cpus.h | 2 -- accel/tcg/icount-common.c | 2 ++ system/globals.c | 1 - 4 files changed, 4 insertions(+), 3 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index d3186721839..7ef620d9631 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -17,6 +17,8 @@ extern int64_t max_advance; extern bool one_insn_per_tb; +extern bool icount_align_option; + /* * Return true if CS is not running in parallel with other cpus, either * because there are no other cpus or we are within an exclusive context. diff --git a/include/system/cpus.h b/include/system/cpus.h index 3d8fd368f32..1cffeaaf5c4 100644 --- a/include/system/cpus.h +++ b/include/system/cpus.h @@ -38,8 +38,6 @@ void resume_all_vcpus(void); void pause_all_vcpus(void); void cpu_stop_current(void); -extern int icount_align_option; - /* Unblock cpu */ void qemu_cpu_kick_self(void); diff --git a/accel/tcg/icount-common.c b/accel/tcg/icount-common.c index b178dccec45..402d3e3f4e8 100644 --- a/accel/tcg/icount-common.c +++ b/accel/tcg/icount-common.c @@ -48,6 +48,8 @@ static bool icount_sleep = true; /* Arbitrarily pick 1MIPS as the minimum allowable speed. */ #define MAX_ICOUNT_SHIFT 10 +bool icount_align_option; + /* Do not count executed instructions */ ICountMode use_icount = ICOUNT_DISABLED; diff --git a/system/globals.c b/system/globals.c index 4867c93ca6b..b968e552452 100644 --- a/system/globals.c +++ b/system/globals.c @@ -48,7 +48,6 @@ unsigned int nb_prom_envs; const char *prom_envs[MAX_PROM_ENVS]; uint8_t *boot_splash_filedata; int only_migratable; /* turn it off unless user states otherwise */ -int icount_align_option; /* The bytes in qemu_uuid are in the order specified by RFC4122, _not_ in the * little-endian "wire format" described in the SMBIOS 2.6 specification. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd54c04bsm6412735e9.27.2025.01.23.15.45.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Jan 2025 15:45:12 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Igor Mammedov , =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, David Hildenbrand , qemu-s390x@nongnu.org, xen-devel@lists.xenproject.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 10/20] accel/tcg: Rename 'hw/core/tcg-cpu-ops.h' -> 'accel/tcg/cpu-ops.h' Date: Fri, 24 Jan 2025 00:44:04 +0100 Message-ID: <20250123234415.59850-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250123234415.59850-1-philmd@linaro.org> References: <20250123234415.59850-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org TCGCPUOps structure makes more sense in the accelerator context rather than hardware emulation. Move it under the accel/tcg/ scope. Mechanical change doing: $ sed -i -e 's,hw/core/tcg-cpu-ops.h,accel/tcg/cpu-ops.h,g' \ $(git grep -l hw/core/tcg-cpu-ops.h) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- MAINTAINERS | 2 +- include/{hw/core/tcg-cpu-ops.h => accel/tcg/cpu-ops.h} | 0 accel/tcg/cpu-exec.c | 4 ++-- accel/tcg/cputlb.c | 2 +- accel/tcg/translate-all.c | 2 +- accel/tcg/user-exec.c | 2 +- accel/tcg/watchpoint.c | 2 +- bsd-user/signal.c | 2 +- hw/mips/jazz.c | 2 +- linux-user/signal.c | 2 +- system/physmem.c | 2 +- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/arm/tcg/cpu-v7m.c | 2 +- target/arm/tcg/cpu32.c | 2 +- target/arm/tcg/mte_helper.c | 2 +- target/arm/tcg/sve_helper.c | 2 +- target/avr/cpu.c | 2 +- target/avr/helper.c | 2 +- target/hexagon/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/loongarch/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/ppc/cpu_init.c | 2 +- target/riscv/tcg/tcg-cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/s390x/tcg/mem_helper.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- 36 files changed, 36 insertions(+), 36 deletions(-) rename include/{hw/core/tcg-cpu-ops.h => accel/tcg/cpu-ops.h} (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 7be3d8f431a..fa46d077d30 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -175,7 +175,7 @@ F: include/exec/helper-info.c.inc F: include/exec/page-protection.h F: include/system/cpus.h F: include/system/tcg.h -F: include/hw/core/tcg-cpu-ops.h +F: include/accel/tcg/cpu-ops.h F: host/include/*/host/cpuinfo.h F: util/cpuinfo-*.c F: include/tcg/ diff --git a/include/hw/core/tcg-cpu-ops.h b/include/accel/tcg/cpu-ops.h similarity index 100% rename from include/hw/core/tcg-cpu-ops.h rename to include/accel/tcg/cpu-ops.h diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index be2ba199d3d..8ee76e14b0d 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -22,7 +22,7 @@ #include "qapi/error.h" #include "qapi/type-helpers.h" #include "hw/core/cpu.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "trace.h" #include "disas/disas.h" #include "exec/cpu-common.h" @@ -39,7 +39,7 @@ #include "exec/replay-core.h" #include "system/tcg.h" #include "exec/helper-proto-common.h" -#include "tb-jmp-cache.h" +//#include "tb-jmp-cache.h" #include "tb-hash.h" #include "tb-context.h" #include "tb-internal.h" diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b4ccf0cdcb7..d68401b35c3 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -19,7 +19,7 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/memory.h" diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index d4189c73860..786e2f6f1a7 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -58,7 +58,7 @@ #include "system/cpu-timers.h" #include "system/tcg.h" #include "qapi/error.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "tb-jmp-cache.h" #include "tb-hash.h" #include "tb-context.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 0561c4f6dc7..c4454100ad7 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -17,7 +17,7 @@ * License along with this library; if not, see . */ #include "qemu/osdep.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "disas/disas.h" #include "exec/exec-all.h" #include "tcg/tcg.h" diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c index af57d182d5b..40112b2b2e7 100644 --- a/accel/tcg/watchpoint.c +++ b/accel/tcg/watchpoint.c @@ -26,7 +26,7 @@ #include "tb-internal.h" #include "system/tcg.h" #include "system/replay.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "hw/core/cpu.h" #include "internal-common.h" diff --git a/bsd-user/signal.c b/bsd-user/signal.c index b4e1458237a..088fe775c05 100644 --- a/bsd-user/signal.c +++ b/bsd-user/signal.c @@ -28,7 +28,7 @@ #include "gdbstub/user.h" #include "signal-common.h" #include "trace.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "host-signal.h" /* target_siginfo_t must fit in gdbstub's siginfo save area. */ diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index c89610639a9..1700c3765de 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -50,7 +50,7 @@ #include "qemu/error-report.h" #include "qemu/help_option.h" #ifdef CONFIG_TCG -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #endif /* CONFIG_TCG */ #include "cpu.h" diff --git a/linux-user/signal.c b/linux-user/signal.c index 087c4d270e4..b9e9b0a6c03 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -21,7 +21,7 @@ #include "qemu/cutils.h" #include "gdbstub/user.h" #include "exec/page-protection.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include #include diff --git a/system/physmem.c b/system/physmem.c index c76503aea82..8638f8817e6 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -28,7 +28,7 @@ #include "qemu/lockable.h" #ifdef CONFIG_TCG -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #endif /* CONFIG_TCG */ #include "exec/exec-all.h" diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index e1b898e5755..da21f99a6ac 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -220,7 +220,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops = { }; #endif -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps alpha_tcg_ops = { .initialize = alpha_translate_init, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index dc0231233a6..d59433e33fb 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -29,7 +29,7 @@ #include "cpu.h" #ifdef CONFIG_TCG #include "exec/translation-block.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #endif /* CONFIG_TCG */ #include "internals.h" #include "cpu-features.h" diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 03acdf83e00..29a41fde694 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -10,7 +10,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "internals.h" #if !defined(CONFIG_USER_ONLY) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 2ad21825255..c5913665d12 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -10,7 +10,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "internals.h" #include "target/arm/idau.h" #if !defined(CONFIG_USER_ONLY) diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index f72ce2ae0d4..5d6d8a17ae8 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -31,7 +31,7 @@ #endif #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "qapi/error.h" #include "qemu/guest-random.h" #include "mte_helper.h" diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index d0865dece35..2268fcd41b0 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -28,7 +28,7 @@ #include "tcg/tcg.h" #include "vec_internal.h" #include "sve_ldst_internal.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #ifdef CONFIG_USER_ONLY #include "user/page-protection.h" #endif diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 8a126ff3222..5a0e21465e5 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -203,7 +203,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = { .get_phys_page_debug = avr_cpu_get_phys_page_debug, }; -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps avr_tcg_ops = { .initialize = avr_cpu_tcg_init, diff --git a/target/avr/helper.c b/target/avr/helper.c index 345708a1b39..9ea6870e44d 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -22,7 +22,7 @@ #include "qemu/log.h" #include "qemu/error-report.h" #include "cpu.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 0b7fc98f6ce..238e63bcea4 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -321,7 +321,7 @@ static void hexagon_cpu_init(Object *obj) { } -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps hexagon_tcg_ops = { .initialize = hexagon_translate_init, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index b0bc9d35e4c..f2441d4d7fb 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -235,7 +235,7 @@ static const struct SysemuCPUOps hppa_sysemu_ops = { }; #endif -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps hppa_tcg_ops = { .initialize = hppa_translate_init, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 14ee038079a..f09ee813ac9 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -105,7 +105,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs) } #endif -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps x86_tcg_ops = { .initialize = tcg_x86_init, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index d611a604704..ecfd6edefbe 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -813,7 +813,7 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) } #ifdef CONFIG_TCG -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps loongarch_tcg_ops = { .initialize = loongarch_translate_init, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 41dfdf58045..5eac4a38c62 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -547,7 +547,7 @@ static const struct SysemuCPUOps m68k_sysemu_ops = { }; #endif /* !CONFIG_USER_ONLY */ -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps m68k_tcg_ops = { .initialize = m68k_tcg_init, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index f114789abd8..13d194cef88 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -419,7 +419,7 @@ static const struct SysemuCPUOps mb_sysemu_ops = { }; #endif -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps mb_tcg_ops = { .initialize = mb_tcg_init, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 47cd7cfdcef..0b267d2e507 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -544,7 +544,7 @@ static const Property mips_cpu_properties[] = { }; #ifdef CONFIG_TCG -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps mips_tcg_ops = { .initialize = mips_tcg_init, .translate_code = mips_translate_code, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b7bab0d7abf..0669ba2fd10 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -232,7 +232,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = { }; #endif -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps openrisc_tcg_ops = { .initialize = openrisc_translate_init, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index c05c2dc42dc..ed85448bc7d 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7427,7 +7427,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops = { #endif #ifdef CONFIG_TCG -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps ppc_tcg_ops = { .initialize = ppc_translate_init, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 0a137281de1..e40c8e85b26 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -31,7 +31,7 @@ #include "qemu/error-report.h" #include "qemu/log.h" #include "hw/core/accel-cpu.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" #ifndef CONFIG_USER_ONLY #include "hw/boards.h" diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 8c50c7a1bc8..d237d007023 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -192,7 +192,7 @@ static const struct SysemuCPUOps rx_sysemu_ops = { }; #endif -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps rx_tcg_ops = { .initialize = rx_translate_init, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 97d41c23de7..3bea014f9ee 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -322,7 +322,7 @@ static const Property s390x_cpu_properties[] = { #endif #ifdef CONFIG_TCG -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflags) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 32717acb7d1..4ce7aa8127f 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -28,7 +28,7 @@ #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "qemu/int128.h" #include "qemu/atomic128.h" diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 24a22724c61..e3c2aea1a64 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -247,7 +247,7 @@ static const struct SysemuCPUOps sh4_sysemu_ops = { }; #endif -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps superh_tcg_ops = { .initialize = sh4_translate_init, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index fbd38ec334a..e3b46137178 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -992,7 +992,7 @@ static const struct SysemuCPUOps sparc_sysemu_ops = { #endif #ifdef CONFIG_TCG -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps sparc_tcg_ops = { .initialize = sparc_tcg_init, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 95202fadbfd..eb794674c8d 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -168,7 +168,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops = { .get_phys_page_debug = tricore_cpu_get_phys_page_debug, }; -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps tricore_tcg_ops = { .initialize = tricore_tcg_init, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 4eb699d1f45..efbfe73fcfb 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -228,7 +228,7 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = { }; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd54c0f7sm6499935e9.28.2025.01.23.15.45.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Jan 2025 15:45:18 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Igor Mammedov , =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, David Hildenbrand , qemu-s390x@nongnu.org, xen-devel@lists.xenproject.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 11/20] accel: Rename 'hw/core/accel-cpu.h' -> 'accel/accel-cpu-target.h' Date: Fri, 24 Jan 2025 00:44:05 +0100 Message-ID: <20250123234415.59850-12-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250123234415.59850-1-philmd@linaro.org> References: <20250123234415.59850-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org AccelCPUClass is for accelerator to initialize target specific features of a vCPU. Not really related to hardware emulation, rename "hw/core/accel-cpu.h" as "accel/accel-cpu-target.h" (using the explicit -target suffix). More importantly, target specific header often access the target specific definitions which are in each target/FOO/cpu.h header, usually included generically as "cpu.h" relative to target/FOO/. However, there is already a "cpu.h" in hw/core/ which takes precedence. This change allows "accel-cpu-target.h" to include a target "cpu.h". Mechanical change doing: $ git mv include/hw/core/accel-cpu.h \ include/accel/accel-cpu-target.h $ sed -i -e 's,hw/core/accel-cpu.h,accel/accel-cpu-target.h,' \ $(git grep -l hw/core/accel-cpu.h) and renaming header guard 'ACCEL_CPU_TARGET_H'. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- MAINTAINERS | 2 +- include/{hw/core/accel-cpu.h => accel/accel-cpu-target.h} | 4 ++-- accel/accel-target.c | 2 +- cpu-target.c | 2 +- target/i386/hvf/hvf-cpu.c | 2 +- target/i386/kvm/kvm-cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/ppc/kvm.c | 2 +- target/riscv/kvm/kvm-cpu.c | 2 +- target/riscv/tcg/tcg-cpu.c | 2 +- 10 files changed, 11 insertions(+), 11 deletions(-) rename include/{hw/core/accel-cpu.h => accel/accel-cpu-target.h} (95%) diff --git a/MAINTAINERS b/MAINTAINERS index fa46d077d30..e4521852519 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -499,7 +499,7 @@ R: Paolo Bonzini S: Maintained F: include/qemu/accel.h F: include/system/accel-*.h -F: include/hw/core/accel-cpu.h +F: include/accel/accel-cpu-target.h F: accel/accel-*.c F: accel/Makefile.objs F: accel/stubs/Makefile.objs diff --git a/include/hw/core/accel-cpu.h b/include/accel/accel-cpu-target.h similarity index 95% rename from include/hw/core/accel-cpu.h rename to include/accel/accel-cpu-target.h index 24dad45ab9e..0a8e518600d 100644 --- a/include/hw/core/accel-cpu.h +++ b/include/accel/accel-cpu-target.h @@ -8,8 +8,8 @@ * See the COPYING file in the top-level directory. */ -#ifndef ACCEL_CPU_H -#define ACCEL_CPU_H +#ifndef ACCEL_CPU_TARGET_H +#define ACCEL_CPU_TARGET_H /* * This header is used to define new accelerator-specific target-specific diff --git a/accel/accel-target.c b/accel/accel-target.c index 08626c00c2d..09c1e1053e0 100644 --- a/accel/accel-target.c +++ b/accel/accel-target.c @@ -27,7 +27,7 @@ #include "qemu/accel.h" #include "cpu.h" -#include "hw/core/accel-cpu.h" +#include "accel/accel-cpu-target.h" #ifndef CONFIG_USER_ONLY #include "accel-system.h" diff --git a/cpu-target.c b/cpu-target.c index 75501a909df..f97f3a14751 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -44,7 +44,7 @@ #include "exec/tb-flush.h" #include "exec/translation-block.h" #include "exec/log.h" -#include "hw/core/accel-cpu.h" +#include "accel/accel-cpu-target.h" #include "trace/trace-root.h" #include "qemu/accel.h" diff --git a/target/i386/hvf/hvf-cpu.c b/target/i386/hvf/hvf-cpu.c index 560b5a05940..b5f4c80028f 100644 --- a/target/i386/hvf/hvf-cpu.c +++ b/target/i386/hvf/hvf-cpu.c @@ -14,7 +14,7 @@ #include "system/system.h" #include "hw/boards.h" #include "system/hvf.h" -#include "hw/core/accel-cpu.h" +#include "accel/accel-cpu-target.h" #include "hvf-i386.h" static void hvf_cpu_max_instance_init(X86CPU *cpu) diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c index 1bda403f88b..6269fa80452 100644 --- a/target/i386/kvm/kvm-cpu.c +++ b/target/i386/kvm/kvm-cpu.c @@ -15,7 +15,7 @@ #include "hw/boards.h" #include "kvm_i386.h" -#include "hw/core/accel-cpu.h" +#include "accel/accel-cpu-target.h" static void kvm_set_guest_phys_bits(CPUState *cs) { diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index f09ee813ac9..b8aff825eec 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "helper-tcg.h" #include "qemu/accel.h" -#include "hw/core/accel-cpu.h" +#include "accel/accel-cpu-target.h" #include "exec/translation-block.h" #include "tcg-cpu.h" diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 966c2c65723..216638dee40 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -49,7 +49,7 @@ #include "elf.h" #include "system/kvm_int.h" #include "system/kvm.h" -#include "hw/core/accel-cpu.h" +#include "accel/accel-cpu-target.h" #include CONFIG_DEVICES diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 23ce7793594..7e4443c5bda 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -32,7 +32,7 @@ #include "system/kvm_int.h" #include "cpu.h" #include "trace.h" -#include "hw/core/accel-cpu.h" +#include "accel/accel-cpu-target.h" #include "hw/pci/pci.h" #include "exec/memattrs.h" #include "exec/address-spaces.h" diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index e40c8e85b26..79345e4b89d 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -30,7 +30,7 @@ #include "qemu/accel.h" #include "qemu/error-report.h" #include "qemu/log.h" -#include "hw/core/accel-cpu.h" +#include "accel/accel-cpu-target.h" #include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" #ifndef CONFIG_USER_ONLY From patchwork Thu Jan 23 23:44:06 2025 Content-Type: text/plain; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd4fa416sm6932195e9.6.2025.01.23.15.45.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Jan 2025 15:45:24 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Igor Mammedov , =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, David Hildenbrand , qemu-s390x@nongnu.org, xen-devel@lists.xenproject.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 12/20] accel/accel-cpu-target.h: Include missing 'cpu.h' header Date: Fri, 24 Jan 2025 00:44:06 +0100 Message-ID: <20250123234415.59850-13-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250123234415.59850-1-philmd@linaro.org> References: <20250123234415.59850-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org CPU_RESOLVING_TYPE is declared per target in "cpu.h". Include it (along with "qom/object.h") to avoid when moving code around: include/accel/accel-cpu-target.h:26:50: error: expected ')' 26 | DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU) | ^ include/accel/accel-cpu-target.h:23:33: note: expanded from macro 'TYPE_ACCEL_CPU' 23 | #define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE | ^ include/accel/accel-cpu-target.h:26:1: note: to match this '(' 26 | DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU) | ^ include/qom/object.h:196:14: note: expanded from macro 'DECLARE_CLASS_CHECKERS' 196 | { return OBJECT_GET_CLASS(ClassType, obj, TYPENAME); } \ | ^ include/qom/object.h:558:5: note: expanded from macro 'OBJECT_GET_CLASS' 558 | OBJECT_CLASS_CHECK(class, object_get_class(OBJECT(obj)), name) | ^ include/qom/object.h:544:74: note: expanded from macro 'OBJECT_CLASS_CHECK' 544 | ((class_type *)object_class_dynamic_cast_assert(OBJECT_CLASS(class), (name), \ | ^ Signed-off-by: Philippe Mathieu-Daudé Acked-by: Richard Henderson --- include/accel/accel-cpu-target.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/accel/accel-cpu-target.h b/include/accel/accel-cpu-target.h index 0a8e518600d..37dde7fae3e 100644 --- a/include/accel/accel-cpu-target.h +++ b/include/accel/accel-cpu-target.h @@ -20,6 +20,9 @@ * subclasses in target/, or the accel implementation itself in accel/ */ +#include "qom/object.h" +#include "cpu.h" + #define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE #define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU) typedef struct AccelCPUClass AccelCPUClass; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd4b9990sm7076685e9.29.2025.01.23.15.45.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Jan 2025 15:45:28 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Igor Mammedov , =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, David Hildenbrand , qemu-s390x@nongnu.org, xen-devel@lists.xenproject.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 13/20] accel: Forward-declare AccelOpsClass in 'qemu/typedefs.h' Date: Fri, 24 Jan 2025 00:44:07 +0100 Message-ID: <20250123234415.59850-14-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250123234415.59850-1-philmd@linaro.org> References: <20250123234415.59850-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The heavily imported "system/cpus.h" header includes "accel-ops.h" to get AccelOpsClass type declaration. Reduce headers pressure by forward declaring it in "qemu/typedefs.h", where we already declare the AccelCPUState type. Reduce "system/cpus.h" inclusions by only including "system/accel-ops.h" when necessary. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/qemu/typedefs.h | 1 + include/system/accel-ops.h | 1 - include/system/cpus.h | 2 -- accel/accel-system.c | 1 + accel/hvf/hvf-accel-ops.c | 1 + accel/kvm/kvm-accel-ops.c | 1 + accel/qtest/qtest.c | 1 + accel/tcg/cpu-exec-common.c | 1 - accel/tcg/cpu-exec.c | 1 - accel/tcg/monitor.c | 1 - accel/tcg/tcg-accel-ops.c | 1 + accel/tcg/translate-all.c | 1 - accel/xen/xen-all.c | 1 + cpu-common.c | 1 - cpu-target.c | 1 + gdbstub/system.c | 1 + system/cpus.c | 1 + target/i386/nvmm/nvmm-accel-ops.c | 1 + target/i386/whpx/whpx-accel-ops.c | 1 + 19 files changed, 12 insertions(+), 8 deletions(-) diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 3d84efcac47..465cc501773 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -22,6 +22,7 @@ * Please keep this list in case-insensitive alphabetical order. */ typedef struct AccelCPUState AccelCPUState; +typedef struct AccelOpsClass AccelOpsClass; typedef struct AccelState AccelState; typedef struct AddressSpace AddressSpace; typedef struct AioContext AioContext; diff --git a/include/system/accel-ops.h b/include/system/accel-ops.h index 137fb96d444..4c99d25aeff 100644 --- a/include/system/accel-ops.h +++ b/include/system/accel-ops.h @@ -17,7 +17,6 @@ #define TYPE_ACCEL_OPS "accel" ACCEL_OPS_SUFFIX #define ACCEL_OPS_NAME(name) (name "-" TYPE_ACCEL_OPS) -typedef struct AccelOpsClass AccelOpsClass; DECLARE_CLASS_CHECKERS(AccelOpsClass, ACCEL_OPS, TYPE_ACCEL_OPS) /** diff --git a/include/system/cpus.h b/include/system/cpus.h index 1cffeaaf5c4..3226c765d01 100644 --- a/include/system/cpus.h +++ b/include/system/cpus.h @@ -1,8 +1,6 @@ #ifndef QEMU_CPUS_H #define QEMU_CPUS_H -#include "system/accel-ops.h" - /* register accel-specific operations */ void cpus_register_accel(const AccelOpsClass *i); diff --git a/accel/accel-system.c b/accel/accel-system.c index a7596aef59d..5df49fbe831 100644 --- a/accel/accel-system.c +++ b/accel/accel-system.c @@ -26,6 +26,7 @@ #include "qemu/osdep.h" #include "qemu/accel.h" #include "hw/boards.h" +#include "system/accel-ops.h" #include "system/cpus.h" #include "qemu/error-report.h" #include "accel-system.h" diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index 945ba720513..12fc30c2761 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -54,6 +54,7 @@ #include "exec/exec-all.h" #include "gdbstub/enums.h" #include "hw/boards.h" +#include "system/accel-ops.h" #include "system/cpus.h" #include "system/hvf.h" #include "system/hvf_int.h" diff --git a/accel/kvm/kvm-accel-ops.c b/accel/kvm/kvm-accel-ops.c index a81e8f3b03b..54ea60909e2 100644 --- a/accel/kvm/kvm-accel-ops.c +++ b/accel/kvm/kvm-accel-ops.c @@ -16,6 +16,7 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" +#include "system/accel-ops.h" #include "system/kvm.h" #include "system/kvm_int.h" #include "system/runstate.h" diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest.c index ad7e3441a5a..7fae80f6a1b 100644 --- a/accel/qtest/qtest.c +++ b/accel/qtest/qtest.c @@ -18,6 +18,7 @@ #include "qemu/option.h" #include "qemu/config-file.h" #include "qemu/accel.h" +#include "system/accel-ops.h" #include "system/qtest.h" #include "system/cpus.h" #include "qemu/guest-random.h" diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c index 100746d555a..c5c513f1e4a 100644 --- a/accel/tcg/cpu-exec-common.c +++ b/accel/tcg/cpu-exec-common.c @@ -19,7 +19,6 @@ #include "qemu/osdep.h" #include "exec/log.h" -#include "system/cpus.h" #include "system/tcg.h" #include "qemu/plugin.h" #include "internal-common.h" diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8ee76e14b0d..4070d532bf1 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -33,7 +33,6 @@ #include "qemu/rcu.h" #include "exec/log.h" #include "qemu/main-loop.h" -#include "system/cpus.h" #include "exec/cpu-all.h" #include "system/cpu-timers.h" #include "exec/replay-core.h" diff --git a/accel/tcg/monitor.c b/accel/tcg/monitor.c index ae1dbeb79f8..eeb38a4d9ce 100644 --- a/accel/tcg/monitor.c +++ b/accel/tcg/monitor.c @@ -13,7 +13,6 @@ #include "qapi/type-helpers.h" #include "qapi/qapi-commands-machine.h" #include "monitor/monitor.h" -#include "system/cpus.h" #include "system/cpu-timers.h" #include "system/tcg.h" #include "tcg/tcg.h" diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 6e3f1fa92b2..132c5d14613 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -26,6 +26,7 @@ */ #include "qemu/osdep.h" +#include "system/accel-ops.h" #include "system/tcg.h" #include "system/replay.h" #include "system/cpu-timers.h" diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 786e2f6f1a7..0914d6e98b2 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -54,7 +54,6 @@ #include "qemu/cacheinfo.h" #include "qemu/timer.h" #include "exec/log.h" -#include "system/cpus.h" #include "system/cpu-timers.h" #include "system/tcg.h" #include "qapi/error.h" diff --git a/accel/xen/xen-all.c b/accel/xen/xen-all.c index 852e9fbe5fe..7aa28b9ab93 100644 --- a/accel/xen/xen-all.c +++ b/accel/xen/xen-all.c @@ -18,6 +18,7 @@ #include "hw/xen/xen_igd.h" #include "chardev/char.h" #include "qemu/accel.h" +#include "system/accel-ops.h" #include "system/cpus.h" #include "system/xen.h" #include "system/runstate.h" diff --git a/cpu-common.c b/cpu-common.c index 4248b2d727e..f5dcc2d136b 100644 --- a/cpu-common.c +++ b/cpu-common.c @@ -21,7 +21,6 @@ #include "qemu/main-loop.h" #include "exec/cpu-common.h" #include "hw/core/cpu.h" -#include "system/cpus.h" #include "qemu/lockable.h" #include "trace/trace-root.h" diff --git a/cpu-target.c b/cpu-target.c index f97f3a14751..20933bde7d4 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -35,6 +35,7 @@ #include "exec/address-spaces.h" #include "exec/memory.h" #endif +#include "system/accel-ops.h" #include "system/cpus.h" #include "system/tcg.h" #include "exec/tswap.h" diff --git a/gdbstub/system.c b/gdbstub/system.c index 7f047a285c8..416c1dbe1e9 100644 --- a/gdbstub/system.c +++ b/gdbstub/system.c @@ -19,6 +19,7 @@ #include "gdbstub/commands.h" #include "exec/hwaddr.h" #include "exec/tb-flush.h" +#include "system/accel-ops.h" #include "system/cpus.h" #include "system/runstate.h" #include "system/replay.h" diff --git a/system/cpus.c b/system/cpus.c index 37e5892c240..2cc5f887ab5 100644 --- a/system/cpus.c +++ b/system/cpus.c @@ -31,6 +31,7 @@ #include "qapi/qapi-events-run-state.h" #include "qapi/qmp/qerror.h" #include "exec/gdbstub.h" +#include "system/accel-ops.h" #include "system/hw_accel.h" #include "exec/cpu-common.h" #include "qemu/thread.h" diff --git a/target/i386/nvmm/nvmm-accel-ops.c b/target/i386/nvmm/nvmm-accel-ops.c index e7b56662fee..4e4e63de78e 100644 --- a/target/i386/nvmm/nvmm-accel-ops.c +++ b/target/i386/nvmm/nvmm-accel-ops.c @@ -10,6 +10,7 @@ #include "qemu/osdep.h" #include "system/kvm_int.h" #include "qemu/main-loop.h" +#include "system/accel-ops.h" #include "system/cpus.h" #include "qemu/guest-random.h" diff --git a/target/i386/whpx/whpx-accel-ops.c b/target/i386/whpx/whpx-accel-ops.c index ab2e014c9ea..81fdd06e487 100644 --- a/target/i386/whpx/whpx-accel-ops.c +++ b/target/i386/whpx/whpx-accel-ops.c @@ -11,6 +11,7 @@ #include "qemu/osdep.h" #include "system/kvm_int.h" #include "qemu/main-loop.h" +#include "system/accel-ops.h" #include "system/cpus.h" #include "qemu/guest-random.h" From patchwork Thu Jan 23 23:44:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13948746 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd507d60sm6676495e9.18.2025.01.23.15.45.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Jan 2025 15:45:34 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Igor Mammedov , =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, David Hildenbrand , qemu-s390x@nongnu.org, xen-devel@lists.xenproject.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 14/20] accel/tcg: Move cpu_memory_rw_debug() user implementation to user-exec.c Date: Fri, 24 Jan 2025 00:44:08 +0100 Message-ID: <20250123234415.59850-15-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250123234415.59850-1-philmd@linaro.org> References: <20250123234415.59850-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org cpu_memory_rw_debug() system implementation is defined in system/physmem.c. Move the user one to accel/tcg/user-exec.c to simplify cpu-target.c maintenance. Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/user-exec.c | 92 +++++++++++++++++++++++++++++++++++++ cpu-target.c | 102 +----------------------------------------- 2 files changed, 94 insertions(+), 100 deletions(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index c4454100ad7..e7e99a46087 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -19,6 +19,8 @@ #include "qemu/osdep.h" #include "accel/tcg/cpu-ops.h" #include "disas/disas.h" +#include "exec/vaddr.h" +#include "exec/tswap.h" #include "exec/exec-all.h" #include "tcg/tcg.h" #include "qemu/bitops.h" @@ -35,6 +37,7 @@ #include "internal-common.h" #include "internal-target.h" #include "tb-internal.h" +#include "qemu.h" __thread uintptr_t helper_retaddr; @@ -969,6 +972,95 @@ static void *cpu_mmu_lookup(CPUState *cpu, vaddr addr, return ret; } +/* physical memory access (slow version, mainly for debug) */ +int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, + void *ptr, size_t len, bool is_write) +{ + int flags; + vaddr l, page; + void * p; + uint8_t *buf = ptr; + ssize_t written; + int ret = -1; + int fd = -1; + + while (len > 0) { + page = addr & TARGET_PAGE_MASK; + l = (page + TARGET_PAGE_SIZE) - addr; + if (l > len) + l = len; + flags = page_get_flags(page); + if (!(flags & PAGE_VALID)) { + goto out_close; + } + if (is_write) { + if (flags & PAGE_WRITE) { + /* XXX: this code should not depend on lock_user */ + p = lock_user(VERIFY_WRITE, addr, l, 0); + if (!p) { + goto out_close; + } + memcpy(p, buf, l); + unlock_user(p, addr, l); + } else { + /* Bypass the host page protection using ptrace. */ + if (fd == -1) { + fd = open("/proc/self/mem", O_WRONLY); + if (fd == -1) { + goto out; + } + } + /* + * If there is a TranslationBlock and we weren't bypassing the + * host page protection, the memcpy() above would SEGV, + * ultimately leading to page_unprotect(). So invalidate the + * translations manually. Both invalidation and pwrite() must + * be under mmap_lock() in order to prevent the creation of + * another TranslationBlock in between. + */ + mmap_lock(); + tb_invalidate_phys_range(addr, addr + l - 1); + written = pwrite(fd, buf, l, + (off_t)(uintptr_t)g2h_untagged(addr)); + mmap_unlock(); + if (written != l) { + goto out_close; + } + } + } else if (flags & PAGE_READ) { + /* XXX: this code should not depend on lock_user */ + p = lock_user(VERIFY_READ, addr, l, 1); + if (!p) { + goto out_close; + } + memcpy(buf, p, l); + unlock_user(p, addr, 0); + } else { + /* Bypass the host page protection using ptrace. */ + if (fd == -1) { + fd = open("/proc/self/mem", O_RDONLY); + if (fd == -1) { + goto out; + } + } + if (pread(fd, buf, l, + (off_t)(uintptr_t)g2h_untagged(addr)) != l) { + goto out_close; + } + } + len -= l; + buf += l; + addr += l; + } + ret = 0; +out_close: + if (fd != -1) { + close(fd); + } +out: + return ret; +} + #include "ldst_atomicity.c.inc" static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, diff --git a/cpu-target.c b/cpu-target.c index 20933bde7d4..6d8b7825746 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -19,18 +19,12 @@ #include "qemu/osdep.h" #include "qapi/error.h" - -#include "exec/target_page.h" -#include "exec/page-protection.h" #include "hw/qdev-core.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" #include "qemu/qemu-print.h" #include "migration/vmstate.h" -#ifdef CONFIG_USER_ONLY -#include "qemu.h" -#include "user/page-protection.h" -#else +#ifndef CONFIG_USER_ONLY #include "hw/core/sysemu-cpu-ops.h" #include "exec/address-spaces.h" #include "exec/memory.h" @@ -38,16 +32,15 @@ #include "system/accel-ops.h" #include "system/cpus.h" #include "system/tcg.h" -#include "exec/tswap.h" #include "exec/replay-core.h" #include "exec/cpu-common.h" #include "exec/exec-all.h" #include "exec/tb-flush.h" -#include "exec/translation-block.h" #include "exec/log.h" #include "accel/accel-cpu-target.h" #include "trace/trace-root.h" #include "qemu/accel.h" +#include "hw/core/cpu.h" #ifndef CONFIG_USER_ONLY static int cpu_common_post_load(void *opaque, int version_id) @@ -367,97 +360,6 @@ void cpu_abort(CPUState *cpu, const char *fmt, ...) abort(); } -/* physical memory access (slow version, mainly for debug) */ -#if defined(CONFIG_USER_ONLY) -int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, - void *ptr, size_t len, bool is_write) -{ - int flags; - vaddr l, page; - void * p; - uint8_t *buf = ptr; - ssize_t written; - int ret = -1; - int fd = -1; - - while (len > 0) { - page = addr & TARGET_PAGE_MASK; - l = (page + TARGET_PAGE_SIZE) - addr; - if (l > len) - l = len; - flags = page_get_flags(page); - if (!(flags & PAGE_VALID)) { - goto out_close; - } - if (is_write) { - if (flags & PAGE_WRITE) { - /* XXX: this code should not depend on lock_user */ - p = lock_user(VERIFY_WRITE, addr, l, 0); - if (!p) { - goto out_close; - } - memcpy(p, buf, l); - unlock_user(p, addr, l); - } else { - /* Bypass the host page protection using ptrace. */ - if (fd == -1) { - fd = open("/proc/self/mem", O_WRONLY); - if (fd == -1) { - goto out; - } - } - /* - * If there is a TranslationBlock and we weren't bypassing the - * host page protection, the memcpy() above would SEGV, - * ultimately leading to page_unprotect(). So invalidate the - * translations manually. Both invalidation and pwrite() must - * be under mmap_lock() in order to prevent the creation of - * another TranslationBlock in between. - */ - mmap_lock(); - tb_invalidate_phys_range(addr, addr + l - 1); - written = pwrite(fd, buf, l, - (off_t)(uintptr_t)g2h_untagged(addr)); - mmap_unlock(); - if (written != l) { - goto out_close; - } - } - } else if (flags & PAGE_READ) { - /* XXX: this code should not depend on lock_user */ - p = lock_user(VERIFY_READ, addr, l, 1); - if (!p) { - goto out_close; - } - memcpy(buf, p, l); - unlock_user(p, addr, 0); - } else { - /* Bypass the host page protection using ptrace. */ - if (fd == -1) { - fd = open("/proc/self/mem", O_RDONLY); - if (fd == -1) { - goto out; - } - } - if (pread(fd, buf, l, - (off_t)(uintptr_t)g2h_untagged(addr)) != l) { - goto out_close; - } - } - len -= l; - buf += l; - addr += l; - } - ret = 0; -out_close: - if (fd != -1) { - close(fd); - } -out: - return ret; -} -#endif - bool target_words_bigendian(void) { return TARGET_BIG_ENDIAN; From patchwork Thu Jan 23 23:44:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13948747 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9E2ADC02182 for ; Thu, 23 Jan 2025 23:47:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tb6tk-0008T9-VN; Thu, 23 Jan 2025 18:46:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tb6tR-0008Br-7K for qemu-devel@nongnu.org; Thu, 23 Jan 2025 18:45:49 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tb6tM-0004PK-4J for qemu-devel@nongnu.org; Thu, 23 Jan 2025 18:45:48 -0500 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-385de9f789cso1183755f8f.2 for ; Thu, 23 Jan 2025 15:45:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1737675942; x=1738280742; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GOf7cXhzVFnELwvvE/9oD0dVEdIwULgdsVx2rdQEX18=; b=y9cJ233jkEU2cGiX4rydtYd7iaCv5DVQkPevCFChp1S0C0KVzJuAEk6EL8NVS2Ybwr fw4tlRA4hoYwW3Vp+3mnwdol8qnGX3koIrOYLL8AIlr7DSGtQDxvE5J77CtOCtAhjiKr 9cMJZkFi9C99mO3W5fxZvrbfBt6BOYAAmBzmnk8KVtoNBwSgUq5miVijVjzyKjsgb9DI IWbdJInt3o4UT5Al3lYATYeI4lJOiyMYp7BbVo7OLIREWsGv+rrDLuzygqUCzzU3/2DH 9Q29QONNT59iaioLwVHIXkC+bPAmMKI9MMvkYP2azlRpFiQXYtBB3bLEjLBKI6TtC7cr cvZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737675942; x=1738280742; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GOf7cXhzVFnELwvvE/9oD0dVEdIwULgdsVx2rdQEX18=; b=T4YVFOBMxPbJozBP/a8pFRnbvAq/6i5LW5sn58LUT0ws/ezHpSYPoasgtnuMEluZ7a qem+Dej940gTGjvfsY7hIuxDTTbg4zr0/e5Bi/1MJ4cQD7eRP6EY054crVoff4RJFHey y+fRQ9WmYXJKdBD6wvk7/BB1TTbonDlbAu8pAbkxNV2bqr1judGZpSF35Zk4mDy0hSbY TAxaPrFVW3bpDksjtApsOHzEoCLmYhYd5sH1GcNQiIQT0K7FCsbH/Qq1TYAYVJb0FtmJ qfSEQmfDB5EzPjzRUl5jx2lboU8b19IpjWkOSyK4DFVkf3/prYFXd4jqmPK+Zec2qrwO oYjg== X-Gm-Message-State: AOJu0Ywd/kCg5vlVPD5jJK0AIGPWN0CNEG/msck03juw3OKbLodYlug3 3SJn+AlKIKeusZgLNwy/v8iYkUQW1K2FgXfvvf4dqU0/2Thaug1sr9FbKoqoVT4fqUZ448gzTYb gV+k= X-Gm-Gg: ASbGncvdzjohmKSuZ899WmqHXUTr5QdpLg8WoN1of0ceoQm5FVrjH+3aSj2CKwCVacz rIJsvwgkXojyA3mh3xN6eLHeh3ZNjOPKkCGAA/xY5OIoCokZ6ZvhMeQOvx0z2vfPBdo+PTCBkZQ bIn2sbCxU2oYHQDCmkFG89MXSpCEfRCtcxGakjG6wx1jKIUsl7BQWPbNcl8JNWC6a0uGaaAJ+IK OWYhYrjbpyaPpS59e215ESIk/ApwV7TPoWZJJLtjB/SJhE4aU9+FBwz6isRGjxT0H2ougkN26KG thLxwrzQ2N1A7eZrQC8jqjMlmoVCTIUZWwo2JqRul8JVGtylypSEDJU= X-Google-Smtp-Source: AGHT+IFFvdlRkBEFpuvRapz+0/bX2s0BjBYZ6M4itb1IiIpdMWapxxpC9ppUNuB95mK5m+Q7pE4GZw== X-Received: by 2002:a5d:47c9:0:b0:385:fb56:5596 with SMTP id ffacd0b85a97d-38bf5663956mr20431872f8f.19.1737675942270; Thu, 23 Jan 2025 15:45:42 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a1bad87sm971133f8f.74.2025.01.23.15.45.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Jan 2025 15:45:40 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Igor Mammedov , =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, David Hildenbrand , qemu-s390x@nongnu.org, xen-devel@lists.xenproject.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 15/20] cpus: Fix style in cpu-target.c Date: Fri, 24 Jan 2025 00:44:09 +0100 Message-ID: <20250123234415.59850-16-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250123234415.59850-1-philmd@linaro.org> References: <20250123234415.59850-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Fix style on code we are going to modify. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- cpu-target.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/cpu-target.c b/cpu-target.c index 6d8b7825746..a2999e7c3c0 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -47,12 +47,15 @@ static int cpu_common_post_load(void *opaque, int version_id) { CPUState *cpu = opaque; - /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the - version_id is increased. */ + /* + * 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the + * version_id is increased. + */ cpu->interrupt_request &= ~0x01; tlb_flush(cpu); - /* loadvm has just updated the content of RAM, bypassing the + /* + * loadvm has just updated the content of RAM, bypassing the * usual mechanisms that ensure we flush TBs for writes to * memory we've translated code from. So we must flush all TBs, * which will now be stale. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd47f355sm7138595e9.4.2025.01.23.15.45.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Jan 2025 15:45:46 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Igor Mammedov , =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, David Hildenbrand , qemu-s390x@nongnu.org, xen-devel@lists.xenproject.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 16/20] cpus: Restrict cpu_common_post_load() code to TCG Date: Fri, 24 Jan 2025 00:44:10 +0100 Message-ID: <20250123234415.59850-17-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250123234415.59850-1-philmd@linaro.org> References: <20250123234415.59850-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org CPU_INTERRUPT_EXIT was removed in commit 3098dba01c7 ("Use a dedicated function to request exit from execution loop"), tlb_flush() and tb_flush() are related to TCG accelerator. Signed-off-by: Philippe Mathieu-Daudé --- cpu-target.c | 33 +++++++++++++++++++-------------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/cpu-target.c b/cpu-target.c index a2999e7c3c0..c05ef1ff096 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -45,22 +45,27 @@ #ifndef CONFIG_USER_ONLY static int cpu_common_post_load(void *opaque, int version_id) { - CPUState *cpu = opaque; +#ifdef CONFIG_TCG + if (tcg_enabled()) { + CPUState *cpu = opaque; - /* - * 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the - * version_id is increased. - */ - cpu->interrupt_request &= ~0x01; - tlb_flush(cpu); + /* + * 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the + * version_id is increased. + */ + cpu->interrupt_request &= ~0x01; - /* - * loadvm has just updated the content of RAM, bypassing the - * usual mechanisms that ensure we flush TBs for writes to - * memory we've translated code from. So we must flush all TBs, - * which will now be stale. - */ - tb_flush(cpu); + tlb_flush(cpu); + + /* + * loadvm has just updated the content of RAM, bypassing the + * usual mechanisms that ensure we flush TBs for writes to + * memory we've translated code from. So we must flush all TBs, + * which will now be stale. + */ + tb_flush(cpu); + } +#endif return 0; } From patchwork Thu Jan 23 23:44:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13948752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39B0CC0218C for ; Thu, 23 Jan 2025 23:49:06 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tb6uH-0002B2-Lh; Thu, 23 Jan 2025 18:46:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tb6td-0008V7-Bf for qemu-devel@nongnu.org; Thu, 23 Jan 2025 18:46:05 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tb6tX-0004Sx-Nx for qemu-devel@nongnu.org; Thu, 23 Jan 2025 18:45:58 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-436341f575fso16147105e9.1 for ; Thu, 23 Jan 2025 15:45:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1737675953; x=1738280753; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MvtCakZyrGCXwv1NUluQigNUDDDoRJgD07DKcxozaAI=; b=YvKHHn5ZfVZi29RpK+uoYhF6jLID0zTCtwKGiGKjjeuMNTtCCATYrICRiEbjMD4Jea vikOePFYSrwXmYPlb6VhkIboq0NEwnopfaIC84G+s3ReY1Wbo9m65Tvlt6ECEziPIs7o KBtkRTJbFP6VDFBI+EtwJgfD2raK6F4bikwVHsDqPS5v9HLJx31oLBDkW+ywQLiEaxzz TjN9Unkng8pavhpSeBTWyRtsh6hDnGRGl66WHU1EDUvY6z8Hdw1JBzMoLIE3GdS04uVE dN9cGj7A7d4bo7rvXIIYP7IVytYQ6jiMPri/1//4xG1B39d3HKu/usgMzFXWsvlV+ArI YY9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737675953; x=1738280753; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MvtCakZyrGCXwv1NUluQigNUDDDoRJgD07DKcxozaAI=; b=P+koqzUU5MYRFHAZPk3vNAtrXJ5J14/0SPVSeVr915zqmjGy9zi+O4ZpAUUJ2DeF6u SNOoNe/0p2r7XI4r1SfiAbQCJKdmO6IGlguf79jTb0HRxwRranwR2d8Iqutq08izzUFX lr0XKN5u6LsO3Wcm1+/CwmAlqwTBJWpRAgcu/c/+ULtvgbjb6nVw0o1ispOV7QDuC5Ms B+sXWQ5Z0RDV81JOV0jHYrX/tg61VZWE2rIUtrVo27r+8e4gEDaON2bsX2mlaK8hYJ1k PTv+Nir2puWReNEplo/ePiFmq6l4Wy0yFEi1M34nkppehxzXmhfYmiuVIUD3zm16L9yq inXw== X-Gm-Message-State: AOJu0YwxQs8fQIK72fT3G7pTHXV+x0n4X3omTFJn6wUQP6E9Gi5AMDDK PWcW0Ey29odt/oBKJ4P/ZovF1iDTmXGZ4mWNwkb4r2Pc++yEe0EzcnD5WapaHsO6TALiIm8ox0B mc8w= X-Gm-Gg: ASbGncsMTp3nWy45Ou8FI9SMsrbr3SvLKbdn2Jvfl8klAdpXDeVW4s/LQmQqIGFD4Su ZZCV9rMh5pgV8THfIJdx4n46NLHB1zZMb4kc3WXwngXZfUcj6OG7mfOU9odIGwPkPjd+CdsPa13 3p4t+qnhQR8hLHUBEq3/CcEm93vP1QjmqZ36SehZpyu43+xYDzetZLLm5RFLTGaJ9q9Rx937WxZ dArB09aUL8GJslcwEJoooxRdT15f0mlv4UVtNi8kBBPkRveMgkR9oqM69loTygPOYHIDKJXApJk m39XfO3b8h2cZvxzdFqPHRYUVhr1LPDuvLPxru+BgUNbxDSKgjFZzos= X-Google-Smtp-Source: AGHT+IESHbhLNhi6WI+MIsv7kwcNIGaQJ9dXLlWxoyCR3XibduHPGVHiP0CzOiY9OItw0/7PMnFvyA== X-Received: by 2002:a05:600c:1987:b0:434:f753:6012 with SMTP id 5b1f17b1804b1-438913f2f4emr282730315e9.17.1737675953608; Thu, 23 Jan 2025 15:45:53 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd43cdbbsm7488805e9.0.2025.01.23.15.45.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Jan 2025 15:45:52 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Igor Mammedov , =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, David Hildenbrand , qemu-s390x@nongnu.org, xen-devel@lists.xenproject.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 17/20] cpus: Have cpu_class_init_props() per user / system emulation Date: Fri, 24 Jan 2025 00:44:11 +0100 Message-ID: <20250123234415.59850-18-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250123234415.59850-1-philmd@linaro.org> References: <20250123234415.59850-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Rather than maintaining a mix of system / user code for CPU class properties, move system properties to cpu-system.c and user ones to the new cpu-user.c unit. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- cpu-target.c | 58 -------------------------------------------- hw/core/cpu-system.c | 40 ++++++++++++++++++++++++++++++ hw/core/cpu-user.c | 27 +++++++++++++++++++++ hw/core/meson.build | 5 +++- 4 files changed, 71 insertions(+), 59 deletions(-) create mode 100644 hw/core/cpu-user.c diff --git a/cpu-target.c b/cpu-target.c index c05ef1ff096..dff8c0747f9 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -19,15 +19,12 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "hw/qdev-core.h" -#include "hw/qdev-properties.h" #include "qemu/error-report.h" #include "qemu/qemu-print.h" #include "migration/vmstate.h" #ifndef CONFIG_USER_ONLY #include "hw/core/sysemu-cpu-ops.h" #include "exec/address-spaces.h" -#include "exec/memory.h" #endif #include "system/accel-ops.h" #include "system/cpus.h" @@ -179,61 +176,6 @@ void cpu_exec_unrealizefn(CPUState *cpu) accel_cpu_common_unrealize(cpu); } -/* - * This can't go in hw/core/cpu.c because that file is compiled only - * once for both user-mode and system builds. - */ -static const Property cpu_common_props[] = { -#ifdef CONFIG_USER_ONLY - /* - * Create a property for the user-only object, so users can - * adjust prctl(PR_SET_UNALIGN) from the command-line. - * Has no effect if the target does not support the feature. - */ - DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState, - prctl_unalign_sigbus, false), -#else - /* - * Create a memory property for system CPU object, so users can - * wire up its memory. The default if no link is set up is to use - * the system address space. - */ - DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, - MemoryRegion *), -#endif -}; - -#ifndef CONFIG_USER_ONLY -static bool cpu_get_start_powered_off(Object *obj, Error **errp) -{ - CPUState *cpu = CPU(obj); - return cpu->start_powered_off; -} - -static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp) -{ - CPUState *cpu = CPU(obj); - cpu->start_powered_off = value; -} -#endif - -void cpu_class_init_props(DeviceClass *dc) -{ -#ifndef CONFIG_USER_ONLY - ObjectClass *oc = OBJECT_CLASS(dc); - - /* - * We can't use DEFINE_PROP_BOOL in the Property array for this - * property, because we want this to be settable after realize. - */ - object_class_property_add_bool(oc, "start-powered-off", - cpu_get_start_powered_off, - cpu_set_start_powered_off); -#endif - - device_class_set_props(dc, cpu_common_props); -} - void cpu_exec_initfn(CPUState *cpu) { #ifndef CONFIG_USER_ONLY diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c index 6aae28a349a..c63c984a803 100644 --- a/hw/core/cpu-system.c +++ b/hw/core/cpu-system.c @@ -20,7 +20,10 @@ #include "qemu/osdep.h" #include "qapi/error.h" +#include "exec/memory.h" #include "exec/tswap.h" +#include "hw/qdev-core.h" +#include "hw/qdev-properties.h" #include "hw/core/sysemu-cpu-ops.h" bool cpu_paging_enabled(const CPUState *cpu) @@ -142,3 +145,40 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) } return res; } + +static const Property cpu_system_props[] = { + /* + * Create a memory property for system CPU object, so users can + * wire up its memory. The default if no link is set up is to use + * the system address space. + */ + DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, + MemoryRegion *), +}; + +static bool cpu_get_start_powered_off(Object *obj, Error **errp) +{ + CPUState *cpu = CPU(obj); + return cpu->start_powered_off; +} + +static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp) +{ + CPUState *cpu = CPU(obj); + cpu->start_powered_off = value; +} + +void cpu_class_init_props(DeviceClass *dc) +{ + ObjectClass *oc = OBJECT_CLASS(dc); + + /* + * We can't use DEFINE_PROP_BOOL in the Property array for this + * property, because we want this to be settable after realize. + */ + object_class_property_add_bool(oc, "start-powered-off", + cpu_get_start_powered_off, + cpu_set_start_powered_off); + + device_class_set_props(dc, cpu_system_props); +} diff --git a/hw/core/cpu-user.c b/hw/core/cpu-user.c new file mode 100644 index 00000000000..e5ccf6bf13a --- /dev/null +++ b/hw/core/cpu-user.c @@ -0,0 +1,27 @@ +/* + * QEMU CPU model (user specific) + * + * Copyright (c) Linaro, Ltd. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/qdev-core.h" +#include "hw/qdev-properties.h" +#include "hw/core/cpu.h" + +static const Property cpu_user_props[] = { + /* + * Create a property for the user-only object, so users can + * adjust prctl(PR_SET_UNALIGN) from the command-line. + * Has no effect if the target does not support the feature. + */ + DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState, + prctl_unalign_sigbus, false), +}; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a17d79csm1009152f8f.39.2025.01.23.15.45.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Jan 2025 15:45:58 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Igor Mammedov , =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, David Hildenbrand , qemu-s390x@nongnu.org, xen-devel@lists.xenproject.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 18/20] cpus: Have cpu_exec_initfn() per user / system emulation Date: Fri, 24 Jan 2025 00:44:12 +0100 Message-ID: <20250123234415.59850-19-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250123234415.59850-1-philmd@linaro.org> References: <20250123234415.59850-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Slighly simplify cpu-target.c again by extracting cpu_exec_initfn() to cpu-{system,user}.c, adding an empty stub for user emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- Good enough for now... --- cpu-target.c | 9 --------- hw/core/cpu-system.c | 7 +++++++ hw/core/cpu-user.c | 5 +++++ 3 files changed, 12 insertions(+), 9 deletions(-) diff --git a/cpu-target.c b/cpu-target.c index dff8c0747f9..3d33d20b8c8 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -24,7 +24,6 @@ #include "migration/vmstate.h" #ifndef CONFIG_USER_ONLY #include "hw/core/sysemu-cpu-ops.h" -#include "exec/address-spaces.h" #endif #include "system/accel-ops.h" #include "system/cpus.h" @@ -176,14 +175,6 @@ void cpu_exec_unrealizefn(CPUState *cpu) accel_cpu_common_unrealize(cpu); } -void cpu_exec_initfn(CPUState *cpu) -{ -#ifndef CONFIG_USER_ONLY - cpu->memory = get_system_memory(); - object_ref(OBJECT(cpu->memory)); -#endif -} - char *cpu_model_from_type(const char *typename) { const char *suffix = "-" CPU_RESOLVING_TYPE; diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c index c63c984a803..0520c362db4 100644 --- a/hw/core/cpu-system.c +++ b/hw/core/cpu-system.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" +#include "exec/address-spaces.h" #include "exec/memory.h" #include "exec/tswap.h" #include "hw/qdev-core.h" @@ -182,3 +183,9 @@ void cpu_class_init_props(DeviceClass *dc) device_class_set_props(dc, cpu_system_props); } + +void cpu_exec_initfn(CPUState *cpu) +{ + cpu->memory = get_system_memory(); + object_ref(OBJECT(cpu->memory)); +} diff --git a/hw/core/cpu-user.c b/hw/core/cpu-user.c index e5ccf6bf13a..cdd8de2fefa 100644 --- a/hw/core/cpu-user.c +++ b/hw/core/cpu-user.c @@ -25,3 +25,8 @@ void cpu_class_init_props(DeviceClass *dc) { device_class_set_props(dc, cpu_user_props); } + +void cpu_exec_initfn(CPUState *cpu) +{ + /* nothing to do */ +} From patchwork Thu Jan 23 23:44:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13948753 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 83D1FC0218D for ; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a1c403asm989733f8f.93.2025.01.23.15.46.03 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Jan 2025 15:46:03 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Igor Mammedov , =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, David Hildenbrand , qemu-s390x@nongnu.org, xen-devel@lists.xenproject.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 19/20] cpus: Register VMState per user / system emulation Date: Fri, 24 Jan 2025 00:44:13 +0100 Message-ID: <20250123234415.59850-20-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250123234415.59850-1-philmd@linaro.org> References: <20250123234415.59850-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Simplify cpu-target.c by extracting mixed vmstate code into the cpu_vmstate_register() / cpu_vmstate_unregister() helpers, implemented in cpu-user.c and cpu-system.c. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- XXX: tlb_flush() temporary declared manually. Only 2 more CONFIG_USER_ONLY to go. --- include/hw/core/cpu.h | 2 + cpu-target.c | 122 +---------------------------------------- hw/core/cpu-system.c | 123 ++++++++++++++++++++++++++++++++++++++++++ hw/core/cpu-user.c | 12 +++++ 4 files changed, 139 insertions(+), 120 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index fb397cdfc53..aadbd2e1122 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1163,6 +1163,8 @@ G_NORETURN void cpu_abort(CPUState *cpu, const char *fmt, ...) /* $(top_srcdir)/cpu.c */ void cpu_class_init_props(DeviceClass *dc); void cpu_exec_initfn(CPUState *cpu); +void cpu_vmstate_register(CPUState *cpu); +void cpu_vmstate_unregister(CPUState *cpu); bool cpu_exec_realizefn(CPUState *cpu, Error **errp); void cpu_exec_unrealizefn(CPUState *cpu); void cpu_exec_reset_hold(CPUState *cpu); diff --git a/cpu-target.c b/cpu-target.c index 3d33d20b8c8..bfcd48f9ae2 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -21,115 +21,16 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/qemu-print.h" -#include "migration/vmstate.h" -#ifndef CONFIG_USER_ONLY -#include "hw/core/sysemu-cpu-ops.h" -#endif #include "system/accel-ops.h" #include "system/cpus.h" -#include "system/tcg.h" #include "exec/replay-core.h" #include "exec/cpu-common.h" -#include "exec/exec-all.h" -#include "exec/tb-flush.h" #include "exec/log.h" #include "accel/accel-cpu-target.h" #include "trace/trace-root.h" #include "qemu/accel.h" #include "hw/core/cpu.h" -#ifndef CONFIG_USER_ONLY -static int cpu_common_post_load(void *opaque, int version_id) -{ -#ifdef CONFIG_TCG - if (tcg_enabled()) { - CPUState *cpu = opaque; - - /* - * 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the - * version_id is increased. - */ - cpu->interrupt_request &= ~0x01; - - tlb_flush(cpu); - - /* - * loadvm has just updated the content of RAM, bypassing the - * usual mechanisms that ensure we flush TBs for writes to - * memory we've translated code from. So we must flush all TBs, - * which will now be stale. - */ - tb_flush(cpu); - } -#endif - - return 0; -} - -static int cpu_common_pre_load(void *opaque) -{ - CPUState *cpu = opaque; - - cpu->exception_index = -1; - - return 0; -} - -static bool cpu_common_exception_index_needed(void *opaque) -{ - CPUState *cpu = opaque; - - return tcg_enabled() && cpu->exception_index != -1; -} - -static const VMStateDescription vmstate_cpu_common_exception_index = { - .name = "cpu_common/exception_index", - .version_id = 1, - .minimum_version_id = 1, - .needed = cpu_common_exception_index_needed, - .fields = (const VMStateField[]) { - VMSTATE_INT32(exception_index, CPUState), - VMSTATE_END_OF_LIST() - } -}; - -static bool cpu_common_crash_occurred_needed(void *opaque) -{ - CPUState *cpu = opaque; - - return cpu->crash_occurred; -} - -static const VMStateDescription vmstate_cpu_common_crash_occurred = { - .name = "cpu_common/crash_occurred", - .version_id = 1, - .minimum_version_id = 1, - .needed = cpu_common_crash_occurred_needed, - .fields = (const VMStateField[]) { - VMSTATE_BOOL(crash_occurred, CPUState), - VMSTATE_END_OF_LIST() - } -}; - -const VMStateDescription vmstate_cpu_common = { - .name = "cpu_common", - .version_id = 1, - .minimum_version_id = 1, - .pre_load = cpu_common_pre_load, - .post_load = cpu_common_post_load, - .fields = (const VMStateField[]) { - VMSTATE_UINT32(halted, CPUState), - VMSTATE_UINT32(interrupt_request, CPUState), - VMSTATE_END_OF_LIST() - }, - .subsections = (const VMStateDescription * const []) { - &vmstate_cpu_common_exception_index, - &vmstate_cpu_common_crash_occurred, - NULL - } -}; -#endif - bool cpu_exec_realizefn(CPUState *cpu, Error **errp) { if (!accel_cpu_common_realize(cpu, errp)) { @@ -139,33 +40,14 @@ bool cpu_exec_realizefn(CPUState *cpu, Error **errp) /* Wait until cpu initialization complete before exposing cpu. */ cpu_list_add(cpu); -#ifdef CONFIG_USER_ONLY - assert(qdev_get_vmsd(DEVICE(cpu)) == NULL || - qdev_get_vmsd(DEVICE(cpu))->unmigratable); -#else - if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { - vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); - } - if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) { - vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy_vmsd, cpu); - } -#endif /* CONFIG_USER_ONLY */ + cpu_vmstate_register(cpu); return true; } void cpu_exec_unrealizefn(CPUState *cpu) { -#ifndef CONFIG_USER_ONLY - CPUClass *cc = CPU_GET_CLASS(cpu); - - if (cc->sysemu_ops->legacy_vmsd != NULL) { - vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu); - } - if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { - vmstate_unregister(NULL, &vmstate_cpu_common, cpu); - } -#endif + cpu_vmstate_unregister(cpu); cpu_list_remove(cpu); /* diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c index 0520c362db4..3e1f60f23df 100644 --- a/hw/core/cpu-system.c +++ b/hw/core/cpu-system.c @@ -22,10 +22,21 @@ #include "qapi/error.h" #include "exec/address-spaces.h" #include "exec/memory.h" +#include "exec/tb-flush.h" #include "exec/tswap.h" #include "hw/qdev-core.h" #include "hw/qdev-properties.h" #include "hw/core/sysemu-cpu-ops.h" +#include "migration/vmstate.h" +#include "system/tcg.h" + +/* + * XXX this series plan is to be applied on top on my exec/cputlb rework series, + * then tlb_flush() won't be declared target-specific in exec-all.h. + * Meanwhile, declare locally. + * XXX + */ +void tlb_flush(CPUState *cs); bool cpu_paging_enabled(const CPUState *cpu) { @@ -189,3 +200,115 @@ void cpu_exec_initfn(CPUState *cpu) cpu->memory = get_system_memory(); object_ref(OBJECT(cpu->memory)); } + +static int cpu_common_post_load(void *opaque, int version_id) +{ +#ifdef CONFIG_TCG + if (tcg_enabled()) { + CPUState *cpu = opaque; + + /* + * 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the + * version_id is increased. + */ + cpu->interrupt_request &= ~0x01; + + tlb_flush(cpu); + + /* + * loadvm has just updated the content of RAM, bypassing the + * usual mechanisms that ensure we flush TBs for writes to + * memory we've translated code from. So we must flush all TBs, + * which will now be stale. + */ + tb_flush(cpu); + } +#endif + + return 0; +} + +static int cpu_common_pre_load(void *opaque) +{ + CPUState *cpu = opaque; + + cpu->exception_index = -1; + + return 0; +} + +static bool cpu_common_exception_index_needed(void *opaque) +{ + CPUState *cpu = opaque; + + return tcg_enabled() && cpu->exception_index != -1; +} + +static const VMStateDescription vmstate_cpu_common_exception_index = { + .name = "cpu_common/exception_index", + .version_id = 1, + .minimum_version_id = 1, + .needed = cpu_common_exception_index_needed, + .fields = (const VMStateField[]) { + VMSTATE_INT32(exception_index, CPUState), + VMSTATE_END_OF_LIST() + } +}; + +static bool cpu_common_crash_occurred_needed(void *opaque) +{ + CPUState *cpu = opaque; + + return cpu->crash_occurred; +} + +static const VMStateDescription vmstate_cpu_common_crash_occurred = { + .name = "cpu_common/crash_occurred", + .version_id = 1, + .minimum_version_id = 1, + .needed = cpu_common_crash_occurred_needed, + .fields = (const VMStateField[]) { + VMSTATE_BOOL(crash_occurred, CPUState), + VMSTATE_END_OF_LIST() + } +}; + +const VMStateDescription vmstate_cpu_common = { + .name = "cpu_common", + .version_id = 1, + .minimum_version_id = 1, + .pre_load = cpu_common_pre_load, + .post_load = cpu_common_post_load, + .fields = (const VMStateField[]) { + VMSTATE_UINT32(halted, CPUState), + VMSTATE_UINT32(interrupt_request, CPUState), + VMSTATE_END_OF_LIST() + }, + .subsections = (const VMStateDescription * const []) { + &vmstate_cpu_common_exception_index, + &vmstate_cpu_common_crash_occurred, + NULL + } +}; + +void cpu_vmstate_register(CPUState *cpu) +{ + if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { + vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); + } + if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) { + vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy_vmsd, cpu); + } +} + +void cpu_vmstate_unregister(CPUState *cpu) +{ + CPUClass *cc = CPU_GET_CLASS(cpu); + + if (cc->sysemu_ops->legacy_vmsd != NULL) { + vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu); + } + if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { + vmstate_unregister(NULL, &vmstate_cpu_common, cpu); + } +} diff --git a/hw/core/cpu-user.c b/hw/core/cpu-user.c index cdd8de2fefa..1892acdee0f 100644 --- a/hw/core/cpu-user.c +++ b/hw/core/cpu-user.c @@ -10,6 +10,7 @@ #include "hw/qdev-core.h" #include "hw/qdev-properties.h" #include "hw/core/cpu.h" +#include "migration/vmstate.h" static const Property cpu_user_props[] = { /* @@ -30,3 +31,14 @@ void cpu_exec_initfn(CPUState *cpu) { /* nothing to do */ } + +void cpu_vmstate_register(CPUState *cpu) +{ + assert(qdev_get_vmsd(DEVICE(cpu)) == NULL || + qdev_get_vmsd(DEVICE(cpu))->unmigratable); +} + +void cpu_vmstate_unregister(CPUState *cpu) +{ + /* nothing to do */ +} From patchwork Thu Jan 23 23:44:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13948755 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8645BC0218C for ; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd4d34e3sm6953255e9.39.2025.01.23.15.46.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Jan 2025 15:46:10 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, Igor Mammedov , =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, David Hildenbrand , qemu-s390x@nongnu.org, xen-devel@lists.xenproject.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 20/20] cpus: Build cpu_exec_[un]realizefn() methods once Date: Fri, 24 Jan 2025 00:44:14 +0100 Message-ID: <20250123234415.59850-21-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250123234415.59850-1-philmd@linaro.org> References: <20250123234415.59850-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now that cpu_exec_realizefn() and cpu_exec_unrealizefn() methods don't use any target specific definition anymore, we can move them to cpu-common.c to be able to build them once. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- Eventually they'll be absorbed within cpu_common_[un]realizefn(). --- cpu-target.c | 30 ------------------------------ hw/core/cpu-common.c | 26 ++++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 30 deletions(-) diff --git a/cpu-target.c b/cpu-target.c index bfcd48f9ae2..8f4477be417 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -19,43 +19,13 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "qemu/error-report.h" #include "qemu/qemu-print.h" #include "system/accel-ops.h" #include "system/cpus.h" #include "exec/replay-core.h" -#include "exec/cpu-common.h" #include "exec/log.h" #include "accel/accel-cpu-target.h" #include "trace/trace-root.h" -#include "qemu/accel.h" -#include "hw/core/cpu.h" - -bool cpu_exec_realizefn(CPUState *cpu, Error **errp) -{ - if (!accel_cpu_common_realize(cpu, errp)) { - return false; - } - - /* Wait until cpu initialization complete before exposing cpu. */ - cpu_list_add(cpu); - - cpu_vmstate_register(cpu); - - return true; -} - -void cpu_exec_unrealizefn(CPUState *cpu) -{ - cpu_vmstate_unregister(cpu); - - cpu_list_remove(cpu); - /* - * Now that the vCPU has been removed from the RCU list, we can call - * accel_cpu_common_unrealize, which may free fields using call_rcu. - */ - accel_cpu_common_unrealize(cpu); -} char *cpu_model_from_type(const char *typename) { diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 71425cb7422..c5382a350fc 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -193,6 +193,20 @@ static void cpu_common_parse_features(const char *typename, char *features, } } +bool cpu_exec_realizefn(CPUState *cpu, Error **errp) +{ + if (!accel_cpu_common_realize(cpu, errp)) { + return false; + } + + /* Wait until cpu initialization complete before exposing cpu. */ + cpu_list_add(cpu); + + cpu_vmstate_register(cpu); + + return true; +} + static void cpu_common_realizefn(DeviceState *dev, Error **errp) { CPUState *cpu = CPU(dev); @@ -234,6 +248,18 @@ static void cpu_common_unrealizefn(DeviceState *dev) cpu_exec_unrealizefn(cpu); } +void cpu_exec_unrealizefn(CPUState *cpu) +{ + cpu_vmstate_unregister(cpu); + + cpu_list_remove(cpu); + /* + * Now that the vCPU has been removed from the RCU list, we can call + * accel_cpu_common_unrealize, which may free fields using call_rcu. + */ + accel_cpu_common_unrealize(cpu); +} + static void cpu_common_initfn(Object *obj) { CPUState *cpu = CPU(obj);