From patchwork Fri Jan 24 06:41:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tamizh Chelvam Raja X-Patchwork-Id: 13948978 X-Patchwork-Delegate: kvalo@adurom.com Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC14E1D6DC8 for ; Fri, 24 Jan 2025 06:41:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737700895; cv=none; b=peSHABzxZ83blHlTJAAB9y6B88MUoXlcPVlldeJWC+K9Vl/Euw0x/UPnUOmYOhbq9I2i/nH6+H0mXoKWBTXsF5VCrq9JVVaHjjBReH5zbYq9HGkVrND2xxQWmbV/q3yABrblprbiRccxpdACT6B0L+ZE+p6gvhp3LcZCYuBK8BU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737700895; c=relaxed/simple; bh=JV56mn64EUCbvCf7IxRxUu/Rht+ZWT7AxFFJTsDCr7k=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=iCaP0Ukverfet0a0BPyNdIVm7E/RhhvXMrCdKrbrVuhP6wLV7f32+BJvX0LKabOeDuqdnUTV1cDM7jaajCIYHEQDu8eNXdeuaCXb29L8Qr6FCkBJo8AKK9CC0vqjkiFcns6P5M5xofTDyQgih6g0Hed+UmjxBPjleeH47HtNpE4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=IVhUOAea; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="IVhUOAea" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 50O1KvEl021872; Fri, 24 Jan 2025 06:41:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=qcppdkim1; bh=+VdPkH8MNd89kH0DDEnn48 8Yrtdw3TlkM78HIsLDW/s=; b=IVhUOAeaJE5g86LtM2/K921VEVknP82zCIjkQk 7juR3drVGrjwPU4jXuMeCNAP5qRsNkGVFO3CLIJ/5oIzp17erj7RvyIc5ca1BlH6 xsSTNMFittgTYa8u1KrX9CRlQia3ZAh3AbsxtihZUuMYaV7DkgLsw7NQ0t1HRkgQ +ttsk8Eu/Vys4hrrWmrZyw56Nmo4uQET9PeURbvIb6Gj8Hx3otaFgM177lpHbjQl Kudy8dR3jDdGvcKaBZt+imn2Q+r3xvxZOAuxTJ5juzP8qOlZP3cHRZ5FUs2JQ/eA ogA5t/sDR0MS8h5B2+/1eYY5ubIeCWObXaqdnGEbbOef0Q0g== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44c147rkbt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 24 Jan 2025 06:41:30 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50O6fTBi014391 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 24 Jan 2025 06:41:29 GMT Received: from hu-tamizhr-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 23 Jan 2025 22:41:27 -0800 From: Tamizh Chelvam Raja To: CC: , Avula Sri Charan , Tamizh Chelvam Raja Subject: [PATCH] wifi: ath12k: Avoid napi_sync before napi_enable Date: Fri, 24 Jan 2025 12:11:06 +0530 Message-ID: <20250124064106.3066564-1-quic_tamizhr@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-wireless@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: tnZ318iFMZJqQ2pEm14Mpj5X5GnwyqMS X-Proofpoint-GUID: tnZ318iFMZJqQ2pEm14Mpj5X5GnwyqMS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-24_02,2025-01-23_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=999 bulkscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 suspectscore=0 priorityscore=1501 spamscore=0 malwarescore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501240047 From: Avula Sri Charan In case of MHI error a reset work will be queued which will try napi_disable after napi_synchronize. As the napi will be only enabled after qmi_firmware_ready event trying napi_synchronize before napi_enable will result in indefinite sleep in case of a firmware crash in QMI init sequence. To avoid this introduce napi_enabled flag to check if napi is enabled or not before calling napi_synchronize. Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.3.1-00173-QCAHKSWPL_SILICONZ-1 Signed-off-by: Avula Sri Charan Signed-off-by: Tamizh Chelvam Raja --- drivers/net/wireless/ath/ath12k/core.h | 1 + drivers/net/wireless/ath/ath12k/pci.c | 13 ++++++++++--- 2 files changed, 11 insertions(+), 3 deletions(-) base-commit: 376673aa393c1c232299be3e910d7f2e6d974b2f prerequisite-patch-id: 07c9ff6fcaf4ba464be993caa19eb49113eedbdf diff --git a/drivers/net/wireless/ath/ath12k/core.h b/drivers/net/wireless/ath/ath12k/core.h index 86a1eeec64a6..b5adbb21315a 100644 --- a/drivers/net/wireless/ath/ath12k/core.h +++ b/drivers/net/wireless/ath/ath12k/core.h @@ -166,6 +166,7 @@ struct ath12k_ext_irq_grp { u32 num_irq; u32 grp_id; u64 timestamp; + bool napi_enabled; struct napi_struct napi; struct net_device *napi_ndev; }; diff --git a/drivers/net/wireless/ath/ath12k/pci.c b/drivers/net/wireless/ath/ath12k/pci.c index 4a50d7118b3e..24c5ef96baf6 100644 --- a/drivers/net/wireless/ath/ath12k/pci.c +++ b/drivers/net/wireless/ath/ath12k/pci.c @@ -483,8 +483,11 @@ static void __ath12k_pci_ext_irq_disable(struct ath12k_base *ab) ath12k_pci_ext_grp_disable(irq_grp); - napi_synchronize(&irq_grp->napi); - napi_disable(&irq_grp->napi); + if (irq_grp->napi_enabled) { + napi_synchronize(&irq_grp->napi); + napi_disable(&irq_grp->napi); + irq_grp->napi_enabled = false; + } } } @@ -1114,7 +1117,11 @@ void ath12k_pci_ext_irq_enable(struct ath12k_base *ab) for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; - napi_enable(&irq_grp->napi); + if (!irq_grp->napi_enabled) { + napi_enable(&irq_grp->napi); + irq_grp->napi_enabled = true; + } + ath12k_pci_ext_grp_enable(irq_grp); }