From patchwork Fri Jan 24 08:59:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949112 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BE24C0218C for ; Fri, 24 Jan 2025 09:00:21 +0000 (UTC) Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) by mx.groups.io with SMTP id smtpd.web10.7423.1737709213628221883 for ; Fri, 24 Jan 2025 01:00:13 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=YBf8IQBz; spf=pass (domain: tuxon.dev, ip: 209.85.128.50, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-438a39e659cso11546525e9.2 for ; Fri, 24 Jan 2025 01:00:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709212; x=1738314012; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DrRBnKcgXqxrStIRsxwt5XKoQfgDG5P+3dvITQgP9pM=; b=YBf8IQBzpi8WuHAzOVgYvplW2Cgx5n8PMho/nl7MKzQjuXm+b7XHapLTo1iH5jpMXI OviEfohQP2RaAzfC894vqR5zUr0j3NgFQF5Rf1tUd994aprVSfpaPGmiI6WF1F7L0ujw uU0v1JVAh8PSr3VzMAsTMZo0bfwRpPStwa0TFFf2e0guHpt9uTRClVbgzzT7gXmLnUZa MyOQGzeILYugLEDu52qZGFRqW9r8UiHF//BS1Cbnnlu4tkLbQMyIcouSl9PJxl5INBNN DbiQPXYGoFgB5c98nP/c5I7a5/NgzrAMgu6ljbZOE4h5XtPHhNYCMtA0dGzURVdRNoHO oJIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709212; x=1738314012; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DrRBnKcgXqxrStIRsxwt5XKoQfgDG5P+3dvITQgP9pM=; b=u1dXlHozC41LGGFNfaqXgLJG0Za7K7ZKt4CDo4DCKlHZHaMgVeamA1Yg+bZkQQv7kY ZbZ62T/PWl/yV+ALEMvXl2RBXpnN4dh7kcvTCozE75e3Pu1UrHN5hc2a0nFud02x0AOJ 5D3/3J+mg4eE+PDxFIvrR5x3G5fkYpERVPW8X8TvSClFlFO5IaRpuE3zBlsENYRpfdmc L27FRuNjXdo4ttKgdDFjP5mCeZ2anNZMHm0YWMM4Zjw3RGWbIjUsXr3mjhfH/NBL2clH a4S5RkSGonRefEBmlbCu8YSj+Tu/BcEoRUN4fSnAsfQr2Is5crXevUREK028AbeeZb+P iWag== X-Forwarded-Encrypted: i=1; AJvYcCUQBS20quUI3jpvRYCfG9d6O5d844YJvw3TSYlx9D2qzc09/WRXLD2Ko/oGVY1F9dGVk6OsWVP8@lists.cip-project.org X-Gm-Message-State: AOJu0YyUWkNFA7t/OaxjE8xLsxZnv1tFrwh4nH1ijU/TesFUrZUH/KF5 GfOKxXPC4K64VK+JgM2DbGXUEGpfk5J9/ivl9TBtXjp9zSL4DNEisbRdXr+m8vQ= X-Gm-Gg: ASbGncuMZSRAfxhmIgTnjs0M1jHNN8OuTWDbG7nacChfW5YI5aRbTic923jg6qoCf93 TfQoIaYIUeSCeMWW33By4h9zCRrrl+vOmVTgCDXAkZJ9nHhQpZ7Gi27HrJEC0HjHdSg0/SFRn1A g12LGr/v+8sc/P9IRinhOl8NOTvTakNr0z9Bb89q9TixrMgpYJrqsJLgB8udu/mk55x+pP3aiTk YOfyM76O40WB/TVWDwXbNsazYfyR69FAcqQZyXSvsWDNnJCQPKi7HE7JK6mwy6TSDEJe1atnTyM zo2O5SuRuu3HIaivO/GB1ZBe3GwmpQoARg== X-Google-Smtp-Source: AGHT+IF64M7rRMllY/S/3UQs+862UjI7huFE2teaXa7sJsSOi6iOafpkNKBNJ6l1XmCfXvDbgip9lw== X-Received: by 2002:a05:600c:1d16:b0:436:a3a3:a70c with SMTP id 5b1f17b1804b1-438914390dbmr243973575e9.28.1737709212027; Fri, 24 Jan 2025 01:00:12 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd47f25csm19410935e9.1.2025.01.24.01.00.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:11 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip v2 01/14] clk: Add devm_clk_hw_register_gate_parent_data() Date: Fri, 24 Jan 2025 10:59:52 +0200 Message-ID: <20250124090008.1401077-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:00:21 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17623 From: Claudiu Beznea Add devm_clk_hw_register_gate_parent_data() macro to be used in the Renesas VBATTB clock driver. This macro originates from the upstream commit d54c1fd4a51e ("Add clock driver for Sunplus SP7021 SoC"). Signed-off-by: Claudiu Beznea --- include/linux/clk-provider.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index d2c799595d5e..53dd7c9dcc94 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -606,6 +606,25 @@ struct clk *clk_register_gate(struct device *dev, const char *name, __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ NULL, (flags), (reg), (bit_idx), \ (clk_gate_flags), (lock)) +/** + * devm_clk_hw_register_gate_parent_data - register a gate clock with the + * clock framework + * @dev: device that is registering this clock + * @name: name of this clock + * @parent_data: parent clk data + * @flags: framework-specific flags for this clock + * @reg: register address to control gating of this clock + * @bit_idx: which bit in the register controls gating of this clock + * @clk_gate_flags: gate-specific flags for this clock + * @lock: shared register lock for this clock + */ +#define devm_clk_hw_register_gate_parent_data(dev, name, parent_data, flags, \ + reg, bit_idx, clk_gate_flags, \ + lock) \ + __devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL, \ + (parent_data), (flags), (reg), (bit_idx), \ + (clk_gate_flags), (lock)) + void clk_unregister_gate(struct clk *clk); void clk_hw_unregister_gate(struct clk_hw *hw); int clk_gate_is_enabled(struct clk_hw *hw); From patchwork Fri Jan 24 08:59:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949116 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52E5CC0218F for ; Fri, 24 Jan 2025 09:00:21 +0000 (UTC) Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) by mx.groups.io with SMTP id smtpd.web11.7423.1737709214733621273 for ; Fri, 24 Jan 2025 01:00:15 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=Rufh8NYF; spf=pass (domain: tuxon.dev, ip: 209.85.128.53, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-436ce2ab251so11615435e9.1 for ; Fri, 24 Jan 2025 01:00:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709213; x=1738314013; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8AGIwR5dix3cBevysVkNwWGSAXw1Uxe87cB4A40YKpQ=; b=Rufh8NYFvOs2Fs8fZw9iGJDXnyAv8nlksLGOA7zwDfXRum5LFt7lgMNvGYTkWEJHAh cPB1mq5hc2VQ5M1VhoZUJa+BBjwGsDx2FFf9uGSvRSLfYD7aOp3PtJq7q3nLw9K8ZK8K lYy1TO5xPGC6YQzEymPnHxBWbFfUNwqAT+AZs+UZW3us+N7h3h39m6Nmdbw0/9PPqXfK lulLeTW68vBjqH661Ks/FkEPt3Jn8pWVZqzN9TtHBOz4VC80suJre2FTMG9ycTHE9sKR xhvCvbmTGW+XNrZ42NJ0Lk8l3xCeT6uPaNrsTCvFb+wYoXKKp66YdWpX29zSaI5YrI54 LThA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709213; x=1738314013; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8AGIwR5dix3cBevysVkNwWGSAXw1Uxe87cB4A40YKpQ=; b=npx2IjSGgDS0hOgQeXt4m4vkxl0/NTSH2MUNSIGQvqGUsVwZWyj20E/y9V0wxKVdh1 gzhxn7L9l6bLAxfAWsIKIF+S7qYbulQ41eLviRzSBygw1i0PF3XaVUK7hvXuidGxHQ6a 9cRvDqz9PR7ACkUnWietKvCPvzKLeThdHHgwvby/EwoR3IRQhlaxrKhIBrMM7An1uvGF fXUGeh86ry6y/ctqE0nYZRmwXAW9VL7kJEdWDtug98AuLFO0CytMhJbuItbJRV1DLB0B lzjU0uAkh/EEh1SWB0cDOaGddb1ajl+Cw65tcFB1GJDgAjLRnRqzj8YEDen5X+N3t/5J KFZA== X-Forwarded-Encrypted: i=1; AJvYcCUye1LgqojTyXLd3/k15r1VWJT4hK9XayGKrBzgEZtJB3RtXqEVNUvAuZDVTlNqJvGhhQ4bY8QJ@lists.cip-project.org X-Gm-Message-State: AOJu0Yy/3g+z44Ultls/cIdy7t4plbOqqINmFdd5EIPltho2QfTDsuFc 5nw2utezEkc/CznKh03XwRkEDqrFX1K8nuRyyucbMn+tE1DUhZc/BRLKL3C228g= X-Gm-Gg: ASbGncuw5Cksods2C4/gdKTf2ucq9Sk2hAHhrMQ+uZyuKJE+EzwJ0U0d7BwE2vQ+Hie 1rzKS7vQcaCRfbZP4TRE1n2hD9yGHqHx3LZ9hvgfku6YFzn/ZHIkYkZC15o4jG8YdsIzmivAAZx JcFCBM4C7OfPHgR5pN5YZ9W3KgPguo89a/LFjo+i5CXJIcKbEU7DRx325SUGuC0T6qMcbQe8rmi lsU++cKki6EuUuWCPzBn1Mwm6sc+fmB+EulUcAivK0YJl7Zxw+yNFs5tchhKLx6AcguoZvzHu8m odZ0PDB/uqBnSifG0F4KtaUVSIyFw356Wg== X-Google-Smtp-Source: AGHT+IGTXRHVzcFFcOctYNvN58+noNtE2IVj/O5waUOfPOx0UcJjj/GpPbe8QVXcdkOb5H+KrdkF3A== X-Received: by 2002:a05:600c:a03:b0:434:f7e3:bfbd with SMTP id 5b1f17b1804b1-4389142e8b5mr263417155e9.23.1737709213134; Fri, 24 Jan 2025 01:00:13 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd47f25csm19410935e9.1.2025.01.24.01.00.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:12 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip v2 02/14] clk: fixed-factor: add fwname-based constructor functions Date: Fri, 24 Jan 2025 10:59:53 +0200 Message-ID: <20250124090008.1401077-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:00:21 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17624 From: Théo Lebrun commit ae156a3633d377d43990eb539f8a007c0c2bf769 upstream. Add four functions to register clk_hw based on the fw_name field in clk_parent_data, ie the value in the DT property `clock-names`. There are variants for devm or not and passing an accuracy or not passing one: - clk_hw_register_fixed_factor_fwname - clk_hw_register_fixed_factor_with_accuracy_fwname - devm_clk_hw_register_fixed_factor_fwname - devm_clk_hw_register_fixed_factor_with_accuracy_fwname The `struct clk_parent_data` init is extracted from __clk_hw_register_fixed_factor to each calling function. It is required to allow each function to pass whatever field they want, not only index. Signed-off-by: Théo Lebrun Link: https://lore.kernel.org/r/20240221-mbly-clk-v7-2-31d4ce3630c3@bootlin.com Signed-off-by: Stephen Boyd [claudiu.beznea: dropped accuracy part] Signed-off-by: Claudiu Beznea --- drivers/clk/clk-fixed-factor.c | 59 ++++++++++++++++++++++++++-------- include/linux/clk-provider.h | 6 ++++ 2 files changed, 51 insertions(+), 14 deletions(-) diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index f734e34735a9..6b30f6a05613 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -79,13 +79,12 @@ static void devm_clk_hw_register_fixed_factor_release(struct device *dev, void * static struct clk_hw * __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, const char *name, const char *parent_name, - const struct clk_hw *parent_hw, int index, + const struct clk_hw *parent_hw, const struct clk_parent_data *pdata, unsigned long flags, unsigned int mult, unsigned int div, bool devm) { struct clk_fixed_factor *fix; struct clk_init_data init = { }; - struct clk_parent_data pdata = { .index = index }; struct clk_hw *hw; int ret; @@ -114,7 +113,7 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, else if (parent_hw) init.parent_hws = &parent_hw; else - init.parent_data = &pdata; + init.parent_data = pdata; init.num_parents = 1; hw = &fix->hw; @@ -151,7 +150,9 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, const char *name, unsigned int index, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL, index, + const struct clk_parent_data pdata = { .index = index }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL, &pdata, flags, mult, div, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_index); @@ -173,8 +174,10 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev, const char *name, const struct clk_hw *parent_hw, unsigned long flags, unsigned int mult, unsigned int div) { + const struct clk_parent_data pdata = { .index = -1 }; + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw, - -1, flags, mult, div, true); + &pdata, flags, mult, div, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_parent_hw); @@ -182,9 +185,10 @@ struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev, const char *name, const struct clk_hw *parent_hw, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, - parent_hw, -1, flags, mult, div, - false); + const struct clk_parent_data pdata = { .index = -1 }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw, + &pdata, flags, mult, div, false); } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_parent_hw); @@ -192,11 +196,24 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1, - flags, mult, div, false); + const struct clk_parent_data pdata = { .index = -1 }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, + &pdata, flags, mult, div, false); } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor); +struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div) +{ + const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name }; + + return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL, + &pdata, flags, mult, div, false); +} +EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_fwname); + struct clk *clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) @@ -239,16 +256,30 @@ struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1, - flags, mult, div, true); + const struct clk_parent_data pdata = { .index = -1 }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, + &pdata, flags, mult, div, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor); +struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div) +{ + const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name }; + + return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL, + &pdata, flags, mult, div, true); +} +EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_fwname); + #ifdef CONFIG_OF static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node) { struct clk_hw *hw; const char *clk_name = node->name; + const struct clk_parent_data pdata = { .index = 0 }; u32 div, mult; int ret; @@ -266,8 +297,8 @@ static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node) of_property_read_string(node, "clock-output-names", &clk_name); - hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, NULL, 0, - 0, mult, div, false); + hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, NULL, + &pdata, 0, mult, div, false); if (IS_ERR(hw)) { /* * Clear OF_POPULATED flag so that clock registration can be diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 53dd7c9dcc94..19bd0ad70b08 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -1104,10 +1104,16 @@ void clk_unregister_fixed_factor(struct clk *clk); struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); +struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div); void clk_hw_unregister_fixed_factor(struct clk_hw *hw); struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); +struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div); struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, const char *name, unsigned int index, unsigned long flags, unsigned int mult, unsigned int div); From patchwork Fri Jan 24 08:59:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949114 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3ABADC0218E for ; Fri, 24 Jan 2025 09:00:21 +0000 (UTC) Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.groups.io with SMTP id smtpd.web10.7425.1737709215747363814 for ; Fri, 24 Jan 2025 01:00:16 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=M+TLbbOS; spf=pass (domain: tuxon.dev, ip: 209.85.128.49, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-4361b6f9faeso11920025e9.1 for ; Fri, 24 Jan 2025 01:00:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709214; x=1738314014; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Pyh/eCeUAKyxfgbv4E+U4BbnwMoXJ6eA0t8m+1CZZmQ=; b=M+TLbbOSgCieHURNGNB7YRvEEbeXCJyze8psbII0Uym714hSPEEAH0Cw+WxoYPNvFo wTJ9J0h+FjCMeX047sx72+o8+5zWhgGP9pd/XNeWhcVcuSrpAWdIvn/XAAeHkQ2gZbUS 02R7bjwE3l0TcRghqu8EJU47kYnRlYKoTGaQ6qXNgN4zbsawnGpzBNHOv/CDpNxHAdl5 hKBzw5Gr+0jzFfPbkwgzP0DOsi6JAUSdz9oBwoQ+uU158Dkab/lXfxdKdgyiOG0E+R+3 vfSDema+a5e9P1rcmFMu1pfdQCg8Cby/i5aODks2fch/ZexDM3guexPYNWl6nFjx47eB I7TA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709214; x=1738314014; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Pyh/eCeUAKyxfgbv4E+U4BbnwMoXJ6eA0t8m+1CZZmQ=; b=fzjn036eeZIJ924cT/R90q041FLp3YJpbK3XNDjgGyWqajRlDIusJpaS7+JR/MAEXb pDv2lHp18XscL7Fd2TSUVkr8441clCX9EKQqbb6RCZZGYh+fl7lvCPS71DiVx95ulWO+ 2+kXoB5FkIDTPFQowA9Vpm+8YxOZvzCZNphP2Y5b1ShvM8UStVbjHpLrLp5iiGtI2aWg A9fVEiM6dGq1E1LdzwVu4fNPWMRzSdjOGYVLYPDh5zVI5DAUd1hZLS3/rXiPASvSVV8J 90YjszlNq0kXiHs9Xr5VnNap1z5+Z7JKud7ZRCrESSDRb+dlpmxQXqGNwISHrVCwPvpi sxVA== X-Forwarded-Encrypted: i=1; AJvYcCXRN/6Rxr3Q9xlNjNa0N2vd349L9lIQvlbWao8f98kLzCdtVxCfKSCyPEAwi1r3bp45iPvquEf1@lists.cip-project.org X-Gm-Message-State: AOJu0Yypj17J4lT3GqXPcyLmEVPfyn0Hmt+jA/L/s5Z6LfIQG+OY9kfU kv2O8EfyLnEFfmnW5zYEt+erX8Dg0GPreYrzFUgrsyMPJYiPvfJ+ntp3B7zbqLL3lMXEDzMwW3U j X-Gm-Gg: ASbGnctDDLNr5evfsQ7QEMwKAJ8aWcOY4Oodda087ZqJ0ow7vTFxkqw4ZXQtiMJtlbj NtH01un+zA0h6sPqsDVE2GTItRQQbisjvum3XY5Zsms8qVh4gOEMO6JE1ouGqRBSl4S0uKq/yiU C8gxH3K/p0Uc6GgYMXdUCe5sO2iKKVuvkyGhHDee3F7XfFFCSOI1MPIiFvV0aUSS5jCXUXfu2Cl oBaVf9G0tttOjl+OFNV577pD3/giMYmJOmFuYaSzvcy75BoIEA0sWEvhtMXR7pxvIsDZPVhlvbb 9MfGFvGFlhY6Su9OvN9Nks0nHT+Z/eN1VA== X-Google-Smtp-Source: AGHT+IFe7KKJlE/8pIQktghnMMYR3CdDjrylsYfEnNGeU5lYi2D/Uf7s/gXBp+k76Fwf762yB1Ox2w== X-Received: by 2002:a05:600c:1c14:b0:434:fddf:5c06 with SMTP id 5b1f17b1804b1-438b8841d5amr58998875e9.1.1737709214147; Fri, 24 Jan 2025 01:00:14 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd47f25csm19410935e9.1.2025.01.24.01.00.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:13 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip v2 03/14] clk: Add devm_clk_hw_register_gate_parent_hw() Date: Fri, 24 Jan 2025 10:59:54 +0200 Message-ID: <20250124090008.1401077-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:00:21 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17625 From: Claudiu Beznea commit e1ef630c56d36770e180f0d0bf7b61b5289f5c48 upstream. Add devm_clk_hw_register_gate_parent_hw() macro to allow registering devres managed gate clocks providing struct clk_hw object as parent. Reviewed-by: Geert Uytterhoeven Acked-by: Stephen Boyd Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- include/linux/clk-provider.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 19bd0ad70b08..a0c7ff8d8928 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -606,6 +606,24 @@ struct clk *clk_register_gate(struct device *dev, const char *name, __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ NULL, (flags), (reg), (bit_idx), \ (clk_gate_flags), (lock)) +/** + * devm_clk_hw_register_gate_parent_hw - register a gate clock with the clock + * framework + * @dev: device that is registering this clock + * @name: name of this clock + * @parent_hw: pointer to parent clk + * @flags: framework-specific flags for this clock + * @reg: register address to control gating of this clock + * @bit_idx: which bit in the register controls gating of this clock + * @clk_gate_flags: gate-specific flags for this clock + * @lock: shared register lock for this clock + */ +#define devm_clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, \ + reg, bit_idx, clk_gate_flags, \ + lock) \ + __devm_clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \ + NULL, (flags), (reg), (bit_idx), \ + (clk_gate_flags), (lock)) /** * devm_clk_hw_register_gate_parent_data - register a gate clock with the * clock framework From patchwork Fri Jan 24 08:59:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949113 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A63CC02181 for ; Fri, 24 Jan 2025 09:00:21 +0000 (UTC) Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) by mx.groups.io with SMTP id smtpd.web10.7427.1737709217400105111 for ; Fri, 24 Jan 2025 01:00:17 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=CEMbd1Rg; spf=pass (domain: tuxon.dev, ip: 209.85.128.48, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-4368a293339so20393005e9.3 for ; Fri, 24 Jan 2025 01:00:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709216; x=1738314016; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VwTM5alHxiV99WoSjSGaeY10FKz85c0VVLpWvkRdO+c=; b=CEMbd1Rgm9Qb8MlieGZHCLBbEa/ptJ05SUFYpRW152UyaIGLl/wueez0f7ePew4x0N mYRE4enhM8Eui+aGRGfcvRzkk/9sWMsWVH+YUwcOEsfSfAs5uQYcAQSkDUowLpuI6SEU i2AxLg8vF3rEER0l4z6R56MS81HbDfYFjGBqaQXde3yUBRYTHady/uoxBl0txDZXD9ag 4U10w/+ie+tDNMT2Ke4jUuxeSucxCwtRcznkfRRW1DXRDhKXDAhIwpryTrGq6kA8zLUn 2ImmbGby1wAr3hZReHcadcf7gaX1P99xR0aJ3YJ6BZ7ulbDJ3kuNUi781tMOG80KFhpk 3JpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709216; x=1738314016; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VwTM5alHxiV99WoSjSGaeY10FKz85c0VVLpWvkRdO+c=; b=lU/fE6MQisW8QW/SphEah2VTcn6kkGIJtTIcmOFiwlbUf+jalHJKnjEsFKw2nZM2Xn qh9B78zENpBrT028y5zEKzAldNWnhC3KgF/RD16P6a0nh6u+pVBcnQTHEJam6mmL984/ sSvf+x2Cz8qfRfzSElZQzXjpjVSk6iZUhJJsd+RSPV6xzTnerojBgTUu5DLngDkW2N6h ZU7sriudPJn2KuEWecXFa7IwCEXGFBKE14s/03bystRt4P25asBhjzYCQ/UAoIutX70d t0hxJZfZQW1ydSQZ8EFMcMhiF+pzZt0d7mWFZC/IDZoJfDv804AecyCqW2VgeuFOVmKx mxIQ== X-Forwarded-Encrypted: i=1; AJvYcCUSKUPBOMV+GpLhMh7wtUvLiaZ2unTpKuVSlxjjaAej0FJaa8OrihMEIL/PriEL4nvFFAhgGJmz@lists.cip-project.org X-Gm-Message-State: AOJu0Ywvj/u6FXCwNB5rRZVnvRGsEj6dgInQLOMjkArGXnKAEgczCUcr k55vH5okOx6TFo0/cNKeO8Dx9NWV7AVDU0hQP5kFubGG1XmjA6zSl6uVIay4NpTqHhpljH/daGA S X-Gm-Gg: ASbGncuBjQJCLr21slk0r7uRdMvWOY2vL/dsnM8vhHNpsFm9wmJFwpx5o0MFlOU4WHO V4C0SFa3Pg3suR+r7x+VlMUOT+Zdz77Ih7GLmFGXZAFEJjzB2gEHicazhmiXi5V81JbS0QTOrM9 XmkkkTtTdIEh1Cevx3QsHhbFjpRszczZek7fLuAcAXy1WY2JWvzJot0uyf4e/l53NXTsUODlyep XY8C/OANlRjNGDEFNmhY1gQGWb83VzH65zVtb3TUcTobmNLeJ0rPUr2e6lkq2X342HpznFyygNY kVGd0X/WKmWiuu5cexYy0Q6t+PQRhouBfw== X-Google-Smtp-Source: AGHT+IFVciKsQVUxHhfCYQsT1nx62EZlXCGBTZi3tN3N6hkc+c3RnXms+PuTYMC/C4XcQfWhmYIbLA== X-Received: by 2002:a05:600c:5027:b0:435:294:f1c8 with SMTP id 5b1f17b1804b1-4389143164dmr231913195e9.28.1737709215835; Fri, 24 Jan 2025 01:00:15 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd47f25csm19410935e9.1.2025.01.24.01.00.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:14 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip v2 04/14] clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP Date: Fri, 24 Jan 2025 10:59:55 +0200 Message-ID: <20250124090008.1401077-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:00:21 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17626 From: Claudiu Beznea commit c8bd9bd6446fa034a1877b553bf118606b37c025 upstream. The Renesas RZ/G3S SoC has an IP named Battery Backup Function (VBATTB) that generates the RTC clock. Add clock, reset and power domain support for it. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240614071932.1014067-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [claudiu.beznea: dropped PM domain part as it is not ready yet] Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/r9a08g045-cpg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index c3e6da2de197..55e7d42dc472 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -215,6 +215,7 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9), DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0), DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0), + DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0), }; static const struct rzg2l_reset r9a08g045_resets[] = { @@ -231,6 +232,7 @@ static const struct rzg2l_reset r9a08g045_resets[] = { DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0), DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1), DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2), + DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0), }; static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { @@ -238,6 +240,7 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { MOD_CLK_BASE + R9A08G045_IA55_PCLK, MOD_CLK_BASE + R9A08G045_IA55_CLK, MOD_CLK_BASE + R9A08G045_DMAC_ACLK, + MOD_CLK_BASE + R9A08G045_VBAT_BCLK, }; const struct rzg2l_cpg_info r9a08g045_cpg_info = { From patchwork Fri Jan 24 08:59:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949117 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B11FC3DA4A for ; Fri, 24 Jan 2025 09:00:21 +0000 (UTC) Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) by mx.groups.io with SMTP id smtpd.web10.7428.1737709218516165697 for ; Fri, 24 Jan 2025 01:00:18 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=CAY39Jcn; spf=pass (domain: tuxon.dev, ip: 209.85.128.43, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-43626213fffso18866945e9.1 for ; Fri, 24 Jan 2025 01:00:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709217; x=1738314017; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2TDhDVdmrLyUjwA3Rd9ZKV50+C7dveaBYHkQzItSHlw=; b=CAY39Jcn4PECHGAqpXOZDJYI7NlQT2LqRFxQm16UqWC08yOBVQcMZum39CpWnEUuOK VQltYuQoFcot3ZXfTHKP4Y93hXPbFnFyFeQLHGlMoErSyKipmMa2EcNROaKsZhadHmES M5EdKxv7wpGeg1maAR2d8A1MOR4r8boYMxT2iaYdnNLjnU4st/0PWLER+0dGYt0bGAdP czADYfUvBB+Vnn4B0bsVA7KWNp30AouojcgA6faCsOVHvOMtx4d8SpcOj51NnQwSRc2L SwLIDo3hThf3yHWfkn9SID76thTs+LxCxaEeDaR5u/rlOmtC3Utos36AU8ugo5QQpdOO cQlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709217; x=1738314017; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2TDhDVdmrLyUjwA3Rd9ZKV50+C7dveaBYHkQzItSHlw=; b=EBgyNYhWa/3ZMpPG4l0//Z/n8MxqW0t4r66+AsSLnVJZr8smlJXw0AbEIXpp0mJptx mIa6yH5tcnIUGBQ3BlU6ROYOfUMUiJeAAzUmecTsqlL/P/IvZATGa7pdStIshTUEJNMR wTTj6WmrgyZ3CVaBvgqLBCdzNv5Se/gEiyE8su9iMqTs2I9PomDLiLTjcS+dqDVu6O7R uJ4RrvQOzGfjGt7cS8Af8MjdoCnpfxHqUZgZxbkEWu+mPZQvVpKCNvZWNl+Tnm4pdC+Q TyuLtsMEza2Et4OI2v8qxBRhBrJVr0+laUw8Lqrpr9HOgusGk8eKHOdE0S3zd0vTnObV hY2A== X-Forwarded-Encrypted: i=1; AJvYcCX6nZqrAtYGsFtoK5p8RF7yPPRQCJXSOekPbIzC1MKGrncTEYGyN/k7vMRCe85+VlE1hnE5rT8+@lists.cip-project.org X-Gm-Message-State: AOJu0YxTrk7FEai9QGYtgFyx1miTt8Mjzh24AktC6R5QJ/IJxyG2ftqq dz9DpvPmhfRBbqfW2PPAWWOr5Hv7YV2ZqBMpZP6kIA+28145ipVTkjx2is1wEAQ= X-Gm-Gg: ASbGncvWFen9N2sThfzac82aBLMnL/QigtTQR91FIZbJX6VMgviOJ/rvpqjekJtPt1x YWt/dl7ye9zLrWH3noxnKBwQ53Tj6JLkgSkqJ7RwGGKFx/FabuuhfgF3I1KR+a3ZTBin35UCXTk xYbECsgbqcAu4krYqiOi7e83YxxcXDDoF3bKmR099QrJ+1dTruZ47L61HRcQkHmygcp3N5xl//3 DHmql2oamZJsg4T1SOyXKbakgBo3GI0DpqGlze7pdyInlauyEqGgx6VATgzzNVIXXIQLwf8srFR OykmRxNxOqD9Qzy0rgRqr0yCWyt70CSd2g== X-Google-Smtp-Source: AGHT+IFbC4rrkRzV4tb2RJqY3VvFxwkG+AeY3BcKVTOyktVlVCkteJWbxbibIejysSCa3f22wxQ0rA== X-Received: by 2002:a05:600c:3b87:b0:436:2155:be54 with SMTP id 5b1f17b1804b1-438bd052e25mr20984545e9.1.1737709216962; Fri, 24 Jan 2025 01:00:16 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd47f25csm19410935e9.1.2025.01.24.01.00.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:16 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip v2 05/14] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB Date: Fri, 24 Jan 2025 10:59:56 +0200 Message-ID: <20250124090008.1401077-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:00:21 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17627 From: Claudiu Beznea commit cdfd5daf90af8363fb1f58e08c829a775b2e2fc5 upstream. The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC, the tamper detector and a small general usage memory of 128B. The VBATTB controller controls the clock for the RTC on the Renesas RZ/G3S. The HW block diagram for the clock logic is as follows: +----------+ XC `\ RTXIN --->| |----->| \ +----+ VBATTCLK | 32K clock| | |----->|gate|-----------> | osc | XBYP | | +----+ RTXOUT --->| |----->| / +----------+ ,/ One could connect as input to this HW block either a crystal or an external clock device. This is board specific. After discussions w/ Stephen Boyd the clock tree associated with this hardware block was exported in Linux as: input-xtal xbyp xc mux vbattclk where: - input-xtal is the input clock (connected to RTXIN, RTXOUT pins) - xc, xbyp are mux inputs - mux is the internal mux - vbattclk is the gate clock that feeds in the end the RTC to allow selecting the input of the MUX though assigned-clock DT properties, using the already existing clock drivers and avoid adding other DT properties. This allows select the input of the mux based on the type of the connected input clock: - if the 32768 crystal is connected as input for the VBATTB, the input of the mux should be xc - if an external clock device is connected as input for the VBATTB the input of the mux should be xbyp Add bindings for the VBATTB controller. Reviewed-by: Geert Uytterhoeven Reviewed-by: Krzysztof Kozlowski Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- .../clock/renesas,r9a08g045-vbattb.yaml | 84 +++++++++++++++++++ .../clock/renesas,r9a08g045-vbattb.h | 13 +++ 2 files changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml create mode 100644 include/dt-bindings/clock/renesas,r9a08g045-vbattb.h diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml new file mode 100644 index 000000000000..3707e4118949 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Battery Backup Function (VBATTB) + +description: + Renesas VBATTB is an always on powered module (backed by battery) which + controls the RTC clock (VBATTCLK), tamper detection logic and a small + general usage memory (128B). + +maintainers: + - Claudiu Beznea + +properties: + compatible: + const: renesas,r9a08g045-vbattb + + reg: + maxItems: 1 + + interrupts: + items: + - description: tamper detector interrupt + + clocks: + items: + - description: VBATTB module clock + - description: RTC input clock (crystal or external clock device) + + clock-names: + items: + - const: bclk + - const: rtx + + '#clock-cells': + const: 1 + + power-domains: + maxItems: 1 + + resets: + items: + - description: VBATTB module reset + + quartz-load-femtofarads: + description: load capacitance of the on board crystal + enum: [ 4000, 7000, 9000, 12500 ] + default: 4000 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - '#clock-cells' + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + clock-controller@1005c000 { + compatible = "renesas,r9a08g045-vbattb"; + reg = <0x1005c000 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; + clock-names = "bclk", "rtx"; + assigned-clocks = <&vbattb VBATTB_MUX>; + assigned-clock-parents = <&vbattb VBATTB_XC>; + #clock-cells = <1>; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + quartz-load-femtofarads = <12500>; + }; diff --git a/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h new file mode 100644 index 000000000000..67774eafad06 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ +#define __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ + +#define VBATTB_XC 0 +#define VBATTB_XBYP 1 +#define VBATTB_MUX 2 +#define VBATTB_VBATTCLK 3 + +#endif /* __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ */ From patchwork Fri Jan 24 08:59:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949119 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44D9BC02181 for ; Fri, 24 Jan 2025 09:00:31 +0000 (UTC) Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.groups.io with SMTP id smtpd.web10.7430.1737709221028274582 for ; Fri, 24 Jan 2025 01:00:21 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=q8Q80iF5; spf=pass (domain: tuxon.dev, ip: 209.85.128.49, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-4361f664af5so20554725e9.1 for ; Fri, 24 Jan 2025 01:00:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709219; x=1738314019; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YkOOlbvGcsS/e6T9rMa53xOSvwVJ3hv5PZhseCFv4RQ=; b=q8Q80iF520F6EPcyH1Zay01nP4l1qvUozHoqV6ajJJj/Nb2pjIa3wxBGhI1pMWR6yN YzL7pw94CcLSO78HHGTvjz5hqR6fGtluSmEE32LKzzL347vb0dwVnoFY18SBZ2tJ1meT OLK3JvQy5SMICV+fEwVEAGbcEsri60qJAgnSNw8RqAzaEsfEJhPlK7+x1kNi+hkNldcE uTNLgze3oY921Vjec4IkQakOS+Ndq9aFpQTE+vXwTQexGtwBpb2m13yD+iCqL//Z+jHk 6ZuyvU0dO4qN9dZ8YhzKM58UP4DbuwOVilvNx9XoKr0oiO/aMChbfUgSZnU2S6jp78S4 AwvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709219; x=1738314019; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YkOOlbvGcsS/e6T9rMa53xOSvwVJ3hv5PZhseCFv4RQ=; b=AWIIZXq/0arMnVtN9JF38TzORuk2q7GNhoU7U0hQ3KFB+R/SsVIjnefE0lWhi45+B8 bUveW2ke0EHHZPw8vTOi0J+Te/aUuVPJWH4FqYiq6M3HjYB6G03VxAo5OuOuNbZsH/sh jSf++A0DdjcHmN/guLsoPnN+9ZrYmBKVCfLEN+PvFr67IdA5fSOmoLDw0G0MYt5JkC+I HFGP1Oi6HqidkUeI1Re3yTrqv3QQ3lu09mwvl2QxjjoEuEb5FFdw83AISrnFDS8sxE3H 7H9NyNz+CIR/Cp42jfgKKUZ3MW3VuJMDfYnm+96ojAHK8GqP/x9Kijx70BssWbHYpqAU detg== X-Forwarded-Encrypted: i=1; AJvYcCX+zzYRwEAfsEI28ybcKzOM0SOJE0ciqwnO/0yhbAZFtfsqJAgXneGWiWy1ekB157gVHwLN8Ev0@lists.cip-project.org X-Gm-Message-State: AOJu0YxeUObHwayhdLlTvebOotPgs1irWhiKY2saPr35QYDmF+u5BJHM ZiDQLtcHUMX3G82asuD3SSRtFhyS+MGhVVuZCneO6yg02ZWwKXOTv04/mo84r2Q= X-Gm-Gg: ASbGncsJO8eJlEAI0HWThmFRiAj6IQLDbVssHuemhGKPpREwb6ytLIbofIVTM+RQytr Sz9lWkAD6ijFtYrCk9YngD/gm0/voO4K1bc/okdKrx4FMtVySoW6kjbsPJohCw2QSvuxroK1nD/ fyPMFRNlJYkAI8qw3ujV52pkJwo2Fg/O/gpIsZb4JhxQcTVP8yUxvzAsXEK9VJd8gvXRSdXtt0m fhHvdF6+ICHduK+OuaiHkT8mh1sZ6IbxqSsRAiqidipSvhM165i4Qoz7EfxZ46AzyS6zWsdot84 0DsEJgxDEH3qFshoV7Fpsl3cgULAy6ie9g== X-Google-Smtp-Source: AGHT+IGsE+rzFaUTgaPfb7Th2Hme5wPwrXl3+j4ScNnd1ywJkT4lwZjgnQfGTzpYKIlKysxR/1XOKQ== X-Received: by 2002:a05:6000:18a7:b0:386:4312:53ec with SMTP id ffacd0b85a97d-38bf5663683mr28004633f8f.17.1737709219368; Fri, 24 Jan 2025 01:00:19 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd47f25csm19410935e9.1.2025.01.24.01.00.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:18 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip v2 06/14] clk: renesas: vbattb: Add VBATTB clock driver Date: Fri, 24 Jan 2025 10:59:57 +0200 Message-ID: <20250124090008.1401077-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:00:31 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17628 From: Claudiu Beznea commit be20a73e03e19005cfa5c1c4d6158af1ba02f056 upstream. The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used by the RTC. The input to the VBATTB could be a 32KHz crystal or an external clock device. The HW block diagram for the clock generator is as follows: +----------+ XC `\ RTXIN --->| |----->| \ +----+ VBATTCLK | 32K clock| | |----->|gate|-----------> | osc | XBYP | | +----+ RTXOUT --->| |----->| / +----------+ , After discussions w/ Stephen Boyd the clock tree associated with this hardware block was exported in Linux as: vbattb-xtal xbyp xc mux vbattbclk where: - input-xtal is the input clock (connected to RTXIN, RTXOUT pins) - xc, xbyp are mux inputs - mux is the internal mux - vbattclk is the gate clock that feeds in the end the RTC to allow selecting the input of the MUX though assigned-clock DT properties, using the already existing clock drivers and avoid adding other DT properties. If the crystal is connected on RTXIN, RTXOUT pins the XC will be selected as mux input. If an external clock device is connected on RTXIN, RTXOUT pins the XBYP will be selected as mux input. The load capacitance of the internal crystal can be configured with renesas,vbattb-load-nanofarads DT property. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/Kconfig | 5 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/clk-vbattb.c | 205 +++++++++++++++++++++++++++++++ 3 files changed, 211 insertions(+) create mode 100644 drivers/clk/renesas/clk-vbattb.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 69396e197959..04593172392e 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -223,6 +223,11 @@ config CLK_RZG2L bool "Renesas RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST select RESET_CONTROLLER +config CLK_RENESAS_VBATTB + tristate "Renesas VBATTB clock controller" + depends on ARCH_RZG2L || COMPILE_TEST + select RESET_CONTROLLER + # Generic config CLK_RENESAS_CPG_MSSR bool "CPG/MSSR clock support" if COMPILE_TEST diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 879a07d445f9..46bdcbcbf183 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -50,3 +50,4 @@ obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o obj-$(CONFIG_CLK_RENESAS_CPG_MSTP) += clk-mstp.o obj-$(CONFIG_CLK_RENESAS_DIV6) += clk-div6.o +obj-$(CONFIG_CLK_RENESAS_VBATTB) += clk-vbattb.o diff --git a/drivers/clk/renesas/clk-vbattb.c b/drivers/clk/renesas/clk-vbattb.c new file mode 100644 index 000000000000..ff9d1ead455c --- /dev/null +++ b/drivers/clk/renesas/clk-vbattb.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * VBATTB clock driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define VBATTB_BKSCCR 0x1c +#define VBATTB_BKSCCR_SOSEL 6 +#define VBATTB_SOSCCR2 0x24 +#define VBATTB_SOSCCR2_SOSTP2 0 +#define VBATTB_XOSCCR 0x30 +#define VBATTB_XOSCCR_OUTEN 16 +#define VBATTB_XOSCCR_XSEL GENMASK(1, 0) +#define VBATTB_XOSCCR_XSEL_4_PF 0x0 +#define VBATTB_XOSCCR_XSEL_7_PF 0x1 +#define VBATTB_XOSCCR_XSEL_9_PF 0x2 +#define VBATTB_XOSCCR_XSEL_12_5_PF 0x3 + +/** + * struct vbattb_clk - VBATTB clock data structure + * @base: base address + * @lock: lock + */ +struct vbattb_clk { + void __iomem *base; + spinlock_t lock; +}; + +static int vbattb_clk_validate_load_capacitance(u32 *reg_lc, u32 of_lc) +{ + switch (of_lc) { + case 4000: + *reg_lc = VBATTB_XOSCCR_XSEL_4_PF; + break; + case 7000: + *reg_lc = VBATTB_XOSCCR_XSEL_7_PF; + break; + case 9000: + *reg_lc = VBATTB_XOSCCR_XSEL_9_PF; + break; + case 12500: + *reg_lc = VBATTB_XOSCCR_XSEL_12_5_PF; + break; + default: + return -EINVAL; + } + + return 0; +} + +static void vbattb_clk_action(void *data) +{ + struct device *dev = data; + struct reset_control *rstc = dev_get_drvdata(dev); + int ret; + + ret = reset_control_assert(rstc); + if (ret) + dev_err(dev, "Failed to de-assert reset!"); + + ret = pm_runtime_put_sync(dev); + if (ret < 0) + dev_err(dev, "Failed to runtime suspend!"); + + of_clk_del_provider(dev->of_node); +} + +static int vbattb_clk_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct clk_parent_data parent_data = {}; + struct clk_hw_onecell_data *clk_data; + const struct clk_hw *parent_hws[2]; + struct device *dev = &pdev->dev; + struct reset_control *rstc; + struct vbattb_clk *vbclk; + u32 of_lc, reg_lc; + struct clk_hw *hw; + /* 4 clocks are exported: VBATTB_XC, VBATTB_XBYP, VBATTB_MUX, VBATTB_VBATTCLK. */ + u8 num_clks = 4; + int ret; + + /* Default to 4pF as this is not needed if external clock device is connected. */ + of_lc = 4000; + of_property_read_u32(np, "quartz-load-femtofarads", &of_lc); + + ret = vbattb_clk_validate_load_capacitance(®_lc, of_lc); + if (ret) + return ret; + + vbclk = devm_kzalloc(dev, sizeof(*vbclk), GFP_KERNEL); + if (!vbclk) + return -ENOMEM; + + clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, num_clks), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + clk_data->num = num_clks; + + vbclk->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(vbclk->base)) + return PTR_ERR(vbclk->base); + + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; + + rstc = devm_reset_control_get_shared(dev, NULL); + if (IS_ERR(rstc)) + return PTR_ERR(rstc); + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + ret = reset_control_deassert(rstc); + if (ret) { + pm_runtime_put_sync(dev); + return ret; + } + + dev_set_drvdata(dev, rstc); + ret = devm_add_action_or_reset(dev, vbattb_clk_action, dev); + if (ret) + return ret; + + spin_lock_init(&vbclk->lock); + + parent_data.fw_name = "rtx"; + hw = devm_clk_hw_register_gate_parent_data(dev, "xc", &parent_data, 0, + vbclk->base + VBATTB_SOSCCR2, + VBATTB_SOSCCR2_SOSTP2, + CLK_GATE_SET_TO_DISABLE, &vbclk->lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_XC] = hw; + + hw = devm_clk_hw_register_fixed_factor_fwname(dev, np, "xbyp", "rtx", 0, 1, 1); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_XBYP] = hw; + + parent_hws[0] = clk_data->hws[VBATTB_XC]; + parent_hws[1] = clk_data->hws[VBATTB_XBYP]; + hw = devm_clk_hw_register_mux_parent_hws(dev, "mux", parent_hws, 2, 0, + vbclk->base + VBATTB_BKSCCR, + VBATTB_BKSCCR_SOSEL, + 1, 0, &vbclk->lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_MUX] = hw; + + /* Set load capacitance before registering the VBATTCLK clock. */ + scoped_guard(spinlock, &vbclk->lock) { + u32 val = readl_relaxed(vbclk->base + VBATTB_XOSCCR); + + val &= ~VBATTB_XOSCCR_XSEL; + val |= reg_lc; + writel_relaxed(val, vbclk->base + VBATTB_XOSCCR); + } + + /* This feeds the RTC counter clock and it needs to stay on. */ + hw = devm_clk_hw_register_gate_parent_hw(dev, "vbattclk", hw, CLK_IS_CRITICAL, + vbclk->base + VBATTB_XOSCCR, + VBATTB_XOSCCR_OUTEN, 0, + &vbclk->lock); + + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_VBATTCLK] = hw; + + return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); +} + +static const struct of_device_id vbattb_clk_match[] = { + { .compatible = "renesas,r9a08g045-vbattb" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, vbattb_clk_match); + +static struct platform_driver vbattb_clk_driver = { + .driver = { + .name = "renesas-vbattb-clk", + .of_match_table = vbattb_clk_match, + }, + .probe = vbattb_clk_probe, +}; +module_platform_driver(vbattb_clk_driver); + +MODULE_DESCRIPTION("Renesas VBATTB Clock Driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); From patchwork Fri Jan 24 08:59:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949123 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F21DC0218F for ; Fri, 24 Jan 2025 09:00:31 +0000 (UTC) Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) by mx.groups.io with SMTP id smtpd.web10.7432.1737709223215616634 for ; Fri, 24 Jan 2025 01:00:23 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=jsNrUqB7; spf=pass (domain: tuxon.dev, ip: 209.85.128.51, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-436345cc17bso12957225e9.0 for ; Fri, 24 Jan 2025 01:00:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709221; x=1738314021; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OjtRyfTgZS3PaUggTQ0LoCLu4U5xv/Jge0GwFBL9qQY=; b=jsNrUqB7dggUeIgz06VhdqA5g+XYTm8hsIKMXfjVg5RublDGWdsZBMGjk8L1c9THXo kppnyo1VsdoV/DaM068eFWE06M/scLuksM0qpOXvTz4svHAv61kszlvJdt5kYHcA9p5u m/VJDMxdfmnFv0Hjkr5Xy7ohe3JUpzXVezTnvY/+AsFlsRiX1bmc6tyM+n/9ab52OAA4 i/ltF3phn3Vuu/l40jryx5wcy7/E3HVGCPsnE8dMuLXBEWRubewF4FBbUNANtb1onn31 0hAgzpu890ib7ajydIsSBvBpR6ohtGGBw4u6xN0naHLXdoEop51KutdKmvjFF04cADcu QVaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709221; x=1738314021; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OjtRyfTgZS3PaUggTQ0LoCLu4U5xv/Jge0GwFBL9qQY=; b=nooJELn8myNmDJoV1jvZIGQyElyRgTASL0ji3Nt3O0VYQxHx5ejmS2jOQyFhbe2Nzy He8nFuM/I32HX+olp/jjOdVqlYplzEW2T136ktBuIWWRDqkDWlM6YChhc1ri5qn3vq8I 9/DrVjuOQ0ke7d3iFvjAkdSz0N0gqvS0zDmesqm78WfJF5MeHIaZKOuuz/i2fa5XKVcl xB0a9Wu9dj4D7gIbTHek/DEFNSQPOZjroi38DbMrtT4Qdkgz6WwFLD5hn+zZ1+QPRbch ex+iuU+yKX/3Ad+VSieGJkkMb3HtZEI1JabCTm/NGHxtoKdR43QQsISy9TwHu5Iu4viI vYog== X-Forwarded-Encrypted: i=1; AJvYcCW9jS889JvLwarjmMPm19QT2LkHUN3mzXB9txD7YYzdLtqTl9MfJtMzv2s7DJMSuOdsvrxRVFP9@lists.cip-project.org X-Gm-Message-State: AOJu0Yy7f1m1YUARet+ycwQv0XUy9U/WcsdXaJ709nzgNy5sWcJZdUVf KgGnmV4Cd0U9lF4wJm5jvApD8yDP8yjY3qWJXdnLtDfzlgAkJj6COZ+p0dYBeeKM/BKaF2uDWkr 9 X-Gm-Gg: ASbGncuVsIIzmfUV2dbfjuesDSYR60L1emdokXqK206zx6Mb4FryKvDGTK2FdQali6A DDC2gZUPfvYzKElP0Ar2f6Z7mkBixGBsssz3t23P6NPKfw6PZoXEOgxulQdA1Mj1j9a0ti+vGXQ S2dK00aMNSS51cxH4Aqieyk6RcfEMDBZ7SOhunePTBnAjH1EQ+qqEaIlZOtO0bedAJoPO81bIlA rqd59mjf7QKa8noqXqktBL4575cbGGuGzHhK+RC2iHinRdbEq4FJ75Otd9BRnVrY4jz1Y27ldaZ YhW4/e8R5HXqHnHvHm6X9yzj/z2reAD/oQ== X-Google-Smtp-Source: AGHT+IHXHovEkXcq3uqX3e1HtimIBknbjs5HMoxnnp8KumiSlqVU9zbyFakcZNWYE7aV4ulkNkKdUA== X-Received: by 2002:a05:600c:46ca:b0:434:a367:2bd9 with SMTP id 5b1f17b1804b1-438913dfd7fmr323573575e9.14.1737709221383; Fri, 24 Jan 2025 01:00:21 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd47f25csm19410935e9.1.2025.01.24.01.00.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:19 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip v2 07/14] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RTCA-3 IP Date: Fri, 24 Jan 2025 10:59:58 +0200 Message-ID: <20250124090008.1401077-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:00:31 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17629 From: Claudiu Beznea commit 71c61a45c951eca67dd2cbc4de9cdd687ece4ead upstream. Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC. The RTC IP available on Renesas RZ/V2H is almost identical with the one found on Renesas RZ/G3S (it misses the time capture functionality which is not yet implemented on proposed driver). For this, added also a generic compatible that will be used at the moment as fallback for both RZ/G3S and RZ/V2H. Reviewed-by: Rob Herring (Arm) Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20241030110120.332802-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Alexandre Belloni Signed-off-by: Claudiu Beznea --- .../bindings/rtc/renesas,rz-rtca3.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml diff --git a/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml new file mode 100644 index 000000000000..e70eeb66aa64 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/renesas,rz-rtca3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RTCA-3 Real Time Clock + +maintainers: + - Claudiu Beznea + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + items: + - enum: + - renesas,r9a08g045-rtca3 # RZ/G3S + - const: renesas,rz-rtca3 + + reg: + maxItems: 1 + + interrupts: + items: + - description: Alarm interrupt + - description: Periodic interrupt + - description: Carry interrupt + + interrupt-names: + items: + - const: alarm + - const: period + - const: carry + + clocks: + items: + - description: RTC bus clock + - description: RTC counter clock + + clock-names: + items: + - const: bus + - const: counter + + power-domains: + maxItems: 1 + + resets: + items: + - description: VBATTB module reset + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + rtc@1004ec00 { + compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; + reg = <0x1004ec00 0x400>; + interrupts = , + , + ; + interrupt-names = "alarm", "period", "carry"; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattclk VBATTB_VBATTCLK>; + clock-names = "bus", "counter"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + }; From patchwork Fri Jan 24 08:59:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949124 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6388CC02190 for ; Fri, 24 Jan 2025 09:00:31 +0000 (UTC) Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) by mx.groups.io with SMTP id smtpd.web11.7426.1737709225649763139 for ; Fri, 24 Jan 2025 01:00:26 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=g1Ev6rA0; spf=pass (domain: tuxon.dev, ip: 209.85.128.50, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-43635796b48so12079555e9.0 for ; Fri, 24 Jan 2025 01:00:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709224; x=1738314024; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MT4ugj+vgOIbDsSf9z3BiB9BhfXPYtcur1XNMe2FGYA=; b=g1Ev6rA0fABn4Zd5v2Tlh9G7sFQQXA4LmsK9QzP5Cdema8tBN1cXIxCR0GOmCkbEwB DesyqId2LcyrV8ao5iDpH8ZI8kdYoNizt0/39wDJYAfxq649Mwc9mmhBUz6IWAKxgqXx QJ0QAm2WtMbQPHIkFpE1YNXka8qxXlFodCYJUloTnHFRWkWPvRKyxAlef6127lA9cCMd QLphyrDbO2k7sHoUcfp+D0tsa2pOeJaOi76n/UMqp+j9MJ/w+vjunV9H6JnrOWWbqLgG 9UCwSmCKryuYCn1NH+slAqU+XCyI6EVh1YNx7jiAngvNoxj32dd0dmukYhF/Rd+aknAU GDAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709224; x=1738314024; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MT4ugj+vgOIbDsSf9z3BiB9BhfXPYtcur1XNMe2FGYA=; b=JUz6jrzXAnK6vuISZwo7teavZX//PTPPqbz8dEYk+A7JPSsurk3QypT5qOnkSYgg5x dCKKYAC47CxvrGD1sCz1uEpiu4zrTdQURYS0Vwm4X3/0veFPT0xnnrfiL7uU7/FXkWHq aRFYzlx9kUSqZSQLbvaayCJxaf1usiEHeKt2Ci/eiZfczlaTcH0Q4lne4Vd2UqUJzuns dNlCBGFL5nBlOKNFKjNA98XQxfOlw/g/WEd4ekIs4cildJ72YGkUEqTLWDpE7Wpe9cBc H6h7pgmGXbbDUzbInoT2ZqNh+9upty2gos8pYDQBm5E6HVN7BVL9bRivhDLEkSsmpm/e ncXg== X-Forwarded-Encrypted: i=1; AJvYcCWvUgfRVW9LyuyQSbkOd2gNYRo9u1sv1CpH8wsTQflPO3M8K9GbUSbfq5rCQTWTcxloPRK/idOD@lists.cip-project.org X-Gm-Message-State: AOJu0YxzNrDA8rdZe/MI9NLFRfej8QeUUAoYdGV/d/d8d1ZMfeh7NtLL QlKczb8FBX3ZESMTJtoQ2YAmM5Z0xfZC62svSsFahMbqjXC2AJGlxYxU8RncOlk= X-Gm-Gg: ASbGnctlKz337kw5JRMeLC7UAXQl/lUjhXQysdKwbkWcWba4C+JmOTXT9cSlUt8hUFQ 0KFmnWcr69mbaxtyfChVB4hFyjdt6zokyQ5QGrkIm4S5Ew/o98ALq+HtqHOchsumhS+Fv2Qf/RY V8wZ/NngOb/LESUXO3iKV4Nd9lo/PGYBlFaekMJDhTslADEt8yVl7QxyzgXnghz62YFyHPzOFv0 ooZsDrE9tvKxID2txSzdJSGXWFCCOr/wk2tv5bIpNavqD82P1bXPeIWSl9rdtC5OoaNfusAFnWK S+5CgZjB/toG4tYCKRzpIF37Ktw9IW8Dlg== X-Google-Smtp-Source: AGHT+IHqaPQotJxeR9x2GVyfVE2cWPzFvvOUppL5WphUxNdkNffNezanXlqNRv3Zm0OTPkQFydNV1A== X-Received: by 2002:a05:600c:3b87:b0:436:2155:be54 with SMTP id 5b1f17b1804b1-438bd052e25mr20989145e9.1.1737709223758; Fri, 24 Jan 2025 01:00:23 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd47f25csm19410935e9.1.2025.01.24.01.00.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:21 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip v2 08/14] rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S SoC Date: Fri, 24 Jan 2025 10:59:59 +0200 Message-ID: <20250124090008.1401077-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:00:31 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17630 From: Claudiu Beznea commit d4488377609e36cd9785533c29ccea4b86c292b9 upstream. The RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC has calendar count mode and binary count mode (selectable though RCR2.CNTMD) capabilities, alarm capabilities, clock error correction capabilities. It can generate alarm, period, carry interrupts. Add a driver for RTCA-3 IP. The driver implements calendar count mode (as the conversion b/w RTC and system time is simpler, done with bcd2bin(), bin2bcd()), read and set time, read and set alarm, read and set an offset. Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20241030110120.332802-6-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Alexandre Belloni [claudiu.beznea: - dropped references to RTC_DRV_MA35D1 as it is not present in v6.1 cip - changed return type of rtca3_remove() to int and return 0] Signed-off-by: Claudiu Beznea --- MAINTAINERS | 8 + drivers/rtc/Kconfig | 10 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-renesas-rtca3.c | 901 ++++++++++++++++++++++++++++++++ 4 files changed, 920 insertions(+) create mode 100644 drivers/rtc/rtc-renesas-rtca3.c diff --git a/MAINTAINERS b/MAINTAINERS index 90366b990f11..4f5f924124d2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17629,6 +17629,14 @@ S: Supported F: Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml F: drivers/counter/rz-mtu3-cnt.c +RENESAS RTCA-3 RTC DRIVER +M: Claudiu Beznea +L: linux-rtc@vger.kernel.org +L: linux-renesas-soc@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml +F: drivers/rtc/rtc-renesas-rtca3.c + RENESAS RZ/N1 A5PSW SWITCH DRIVER M: Clément Léger L: linux-renesas-soc@vger.kernel.org diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 87dc050ca004..d0ae7f805c84 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1942,6 +1942,16 @@ config RTC_DRV_TI_K3 This driver can also be built as a module, if so, the module will be called "rtc-ti-k3". +config RTC_DRV_RENESAS_RTCA3 + tristate "Renesas RTCA-3 RTC" + depends on ARCH_RENESAS + help + If you say yes here you get support for the Renesas RTCA-3 RTC + available on the Renesas RZ/G3S SoC. + + This driver can also be built as a module, if so, the module + will be called "rtc-rtca3". + comment "HID Sensor RTC drivers" config RTC_DRV_HID_SENSOR_TIME diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index aab22bc63432..4fc1de1987f7 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -154,6 +154,7 @@ obj-$(CONFIG_RTC_DRV_RX8010) += rtc-rx8010.o obj-$(CONFIG_RTC_DRV_RX8025) += rtc-rx8025.o obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o obj-$(CONFIG_RTC_DRV_RZN1) += rtc-rzn1.o +obj-$(CONFIG_RTC_DRV_RENESAS_RTCA3) += rtc-renesas-rtca3.o obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o obj-$(CONFIG_RTC_DRV_S3C) += rtc-s3c.o obj-$(CONFIG_RTC_DRV_S5M) += rtc-s5m.o diff --git a/drivers/rtc/rtc-renesas-rtca3.c b/drivers/rtc/rtc-renesas-rtca3.c new file mode 100644 index 000000000000..7683df87eafa --- /dev/null +++ b/drivers/rtc/rtc-renesas-rtca3.c @@ -0,0 +1,901 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * On-Chip RTC Support available on RZ/G3S SoC + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Counter registers. */ +#define RTCA3_RSECCNT 0x2 +#define RTCA3_RSECCNT_SEC GENMASK(6, 0) +#define RTCA3_RMINCNT 0x4 +#define RTCA3_RMINCNT_MIN GENMASK(6, 0) +#define RTCA3_RHRCNT 0x6 +#define RTCA3_RHRCNT_HR GENMASK(5, 0) +#define RTCA3_RHRCNT_PM BIT(6) +#define RTCA3_RWKCNT 0x8 +#define RTCA3_RWKCNT_WK GENMASK(2, 0) +#define RTCA3_RDAYCNT 0xa +#define RTCA3_RDAYCNT_DAY GENMASK(5, 0) +#define RTCA3_RMONCNT 0xc +#define RTCA3_RMONCNT_MONTH GENMASK(4, 0) +#define RTCA3_RYRCNT 0xe +#define RTCA3_RYRCNT_YEAR GENMASK(7, 0) + +/* Alarm registers. */ +#define RTCA3_RSECAR 0x10 +#define RTCA3_RSECAR_SEC GENMASK(6, 0) +#define RTCA3_RMINAR 0x12 +#define RTCA3_RMINAR_MIN GENMASK(6, 0) +#define RTCA3_RHRAR 0x14 +#define RTCA3_RHRAR_HR GENMASK(5, 0) +#define RTCA3_RHRAR_PM BIT(6) +#define RTCA3_RWKAR 0x16 +#define RTCA3_RWKAR_DAYW GENMASK(2, 0) +#define RTCA3_RDAYAR 0x18 +#define RTCA3_RDAYAR_DATE GENMASK(5, 0) +#define RTCA3_RMONAR 0x1a +#define RTCA3_RMONAR_MON GENMASK(4, 0) +#define RTCA3_RYRAR 0x1c +#define RTCA3_RYRAR_YR GENMASK(7, 0) +#define RTCA3_RYRAREN 0x1e + +/* Alarm enable bit (for all alarm registers). */ +#define RTCA3_AR_ENB BIT(7) + +/* Control registers. */ +#define RTCA3_RCR1 0x22 +#define RTCA3_RCR1_AIE BIT(0) +#define RTCA3_RCR1_CIE BIT(1) +#define RTCA3_RCR1_PIE BIT(2) +#define RTCA3_RCR1_PES GENMASK(7, 4) +#define RTCA3_RCR1_PES_1_64_SEC 0x8 +#define RTCA3_RCR2 0x24 +#define RTCA3_RCR2_START BIT(0) +#define RTCA3_RCR2_RESET BIT(1) +#define RTCA3_RCR2_AADJE BIT(4) +#define RTCA3_RCR2_ADJP BIT(5) +#define RTCA3_RCR2_HR24 BIT(6) +#define RTCA3_RCR2_CNTMD BIT(7) +#define RTCA3_RSR 0x20 +#define RTCA3_RSR_AF BIT(0) +#define RTCA3_RSR_CF BIT(1) +#define RTCA3_RSR_PF BIT(2) +#define RTCA3_RADJ 0x2e +#define RTCA3_RADJ_ADJ GENMASK(5, 0) +#define RTCA3_RADJ_ADJ_MAX 0x3f +#define RTCA3_RADJ_PMADJ GENMASK(7, 6) +#define RTCA3_RADJ_PMADJ_NONE 0 +#define RTCA3_RADJ_PMADJ_ADD 1 +#define RTCA3_RADJ_PMADJ_SUB 2 + +/* Polling operation timeouts. */ +#define RTCA3_DEFAULT_TIMEOUT_US 150 +#define RTCA3_IRQSET_TIMEOUT_US 5000 +#define RTCA3_START_TIMEOUT_US 150000 +#define RTCA3_RESET_TIMEOUT_US 200000 + +/** + * enum rtca3_alrm_set_step - RTCA3 alarm set steps + * @RTCA3_ALRM_SSTEP_DONE: alarm setup done step + * @RTCA3_ALRM_SSTEP_IRQ: two 1/64 periodic IRQs were generated step + * @RTCA3_ALRM_SSTEP_INIT: alarm setup initialization step + */ +enum rtca3_alrm_set_step { + RTCA3_ALRM_SSTEP_DONE = 0, + RTCA3_ALRM_SSTEP_IRQ = 1, + RTCA3_ALRM_SSTEP_INIT = 3, +}; + +/** + * struct rtca3_ppb_per_cycle - PPB per cycle + * @ten_sec: PPB per cycle in 10 seconds adjutment mode + * @sixty_sec: PPB per cycle in 60 seconds adjustment mode + */ +struct rtca3_ppb_per_cycle { + int ten_sec; + int sixty_sec; +}; + +/** + * struct rtca3_priv - RTCA3 private data structure + * @base: base address + * @rtc_dev: RTC device + * @rstc: reset control + * @set_alarm_completion: alarm setup completion + * @alrm_sstep: alarm setup step (see enum rtca3_alrm_set_step) + * @lock: device lock + * @ppb: ppb per cycle for each the available adjustment modes + * @wakeup_irq: wakeup IRQ + */ +struct rtca3_priv { + void __iomem *base; + struct rtc_device *rtc_dev; + struct reset_control *rstc; + struct completion set_alarm_completion; + atomic_t alrm_sstep; + spinlock_t lock; + struct rtca3_ppb_per_cycle ppb; + int wakeup_irq; +}; + +static void rtca3_byte_update_bits(struct rtca3_priv *priv, u8 off, u8 mask, u8 val) +{ + u8 tmp; + + tmp = readb(priv->base + off); + tmp &= ~mask; + tmp |= (val & mask); + writeb(tmp, priv->base + off); +} + +static u8 rtca3_alarm_handler_helper(struct rtca3_priv *priv) +{ + u8 val, pending; + + val = readb(priv->base + RTCA3_RSR); + pending = val & RTCA3_RSR_AF; + writeb(val & ~pending, priv->base + RTCA3_RSR); + + if (pending) + rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF); + + return pending; +} + +static irqreturn_t rtca3_alarm_handler(int irq, void *dev_id) +{ + struct rtca3_priv *priv = dev_id; + u8 pending; + + guard(spinlock)(&priv->lock); + + pending = rtca3_alarm_handler_helper(priv); + + return IRQ_RETVAL(pending); +} + +static irqreturn_t rtca3_periodic_handler(int irq, void *dev_id) +{ + struct rtca3_priv *priv = dev_id; + u8 val, pending; + + guard(spinlock)(&priv->lock); + + val = readb(priv->base + RTCA3_RSR); + pending = val & RTCA3_RSR_PF; + + if (pending) { + writeb(val & ~pending, priv->base + RTCA3_RSR); + + if (atomic_read(&priv->alrm_sstep) > RTCA3_ALRM_SSTEP_IRQ) { + /* Alarm setup in progress. */ + atomic_dec(&priv->alrm_sstep); + + if (atomic_read(&priv->alrm_sstep) == RTCA3_ALRM_SSTEP_IRQ) { + /* + * We got 2 * 1/64 periodic interrupts. Disable + * interrupt and let alarm setup continue. + */ + rtca3_byte_update_bits(priv, RTCA3_RCR1, + RTCA3_RCR1_PIE, 0); + readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, val, + !(val & RTCA3_RCR1_PIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + complete(&priv->set_alarm_completion); + } + } + } + + return IRQ_RETVAL(pending); +} + +static void rtca3_prepare_cntalrm_regs_for_read(struct rtca3_priv *priv, bool cnt) +{ + /* Offset b/w time and alarm registers. */ + u8 offset = cnt ? 0 : 0xe; + + /* + * According to HW manual (section 22.6.4. Notes on writing to and + * reading from registers) after writing to count registers, alarm + * registers, year alarm enable register, bits RCR2.AADJE, AADJP, + * and HR24 register, we need to do 3 empty reads before being + * able to fetch the registers content. + */ + for (u8 i = 0; i < 3; i++) { + readb(priv->base + RTCA3_RSECCNT + offset); + readb(priv->base + RTCA3_RMINCNT + offset); + readb(priv->base + RTCA3_RHRCNT + offset); + readb(priv->base + RTCA3_RWKCNT + offset); + readb(priv->base + RTCA3_RDAYCNT + offset); + readw(priv->base + RTCA3_RYRCNT + offset); + if (!cnt) + readb(priv->base + RTCA3_RYRAREN); + } +} + +static int rtca3_read_time(struct device *dev, struct rtc_time *tm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + u8 sec, min, hour, wday, mday, month, tmp; + u8 trials = 0; + u32 year100; + u16 year; + + guard(spinlock_irqsave)(&priv->lock); + + tmp = readb(priv->base + RTCA3_RCR2); + if (!(tmp & RTCA3_RCR2_START)) + return -EINVAL; + + do { + /* Clear carry interrupt. */ + rtca3_byte_update_bits(priv, RTCA3_RSR, RTCA3_RSR_CF, 0); + + /* Read counters. */ + sec = readb(priv->base + RTCA3_RSECCNT); + min = readb(priv->base + RTCA3_RMINCNT); + hour = readb(priv->base + RTCA3_RHRCNT); + wday = readb(priv->base + RTCA3_RWKCNT); + mday = readb(priv->base + RTCA3_RDAYCNT); + month = readb(priv->base + RTCA3_RMONCNT); + year = readw(priv->base + RTCA3_RYRCNT); + + tmp = readb(priv->base + RTCA3_RSR); + + /* + * We cannot generate carries due to reading 64Hz counter as + * the driver doesn't implement carry, thus, carries will be + * generated once per seconds. Add a timeout of 5 trials here + * to avoid infinite loop, if any. + */ + } while ((tmp & RTCA3_RSR_CF) && ++trials < 5); + + if (trials >= 5) + return -ETIMEDOUT; + + tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECCNT_SEC, sec)); + tm->tm_min = bcd2bin(FIELD_GET(RTCA3_RMINCNT_MIN, min)); + tm->tm_hour = bcd2bin(FIELD_GET(RTCA3_RHRCNT_HR, hour)); + tm->tm_wday = bcd2bin(FIELD_GET(RTCA3_RWKCNT_WK, wday)); + tm->tm_mday = bcd2bin(FIELD_GET(RTCA3_RDAYCNT_DAY, mday)); + tm->tm_mon = bcd2bin(FIELD_GET(RTCA3_RMONCNT_MONTH, month)) - 1; + year = FIELD_GET(RTCA3_RYRCNT_YEAR, year); + year100 = bcd2bin((year == 0x99) ? 0x19 : 0x20); + tm->tm_year = (year100 * 100 + bcd2bin(year)) - 1900; + + return 0; +} + +static int rtca3_set_time(struct device *dev, struct rtc_time *tm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + u8 rcr2, tmp; + int ret; + + guard(spinlock_irqsave)(&priv->lock); + + /* Stop the RTC. */ + rcr2 = readb(priv->base + RTCA3_RCR2); + writeb(rcr2 & ~RTCA3_RCR2_START, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + !(tmp & RTCA3_RCR2_START), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* Update time. */ + writeb(bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECCNT); + writeb(bin2bcd(tm->tm_min), priv->base + RTCA3_RMINCNT); + writeb(bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRCNT); + writeb(bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKCNT); + writeb(bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYCNT); + writeb(bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONCNT); + writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRCNT); + + /* Make sure we can read back the counters. */ + rtca3_prepare_cntalrm_regs_for_read(priv, true); + + /* Start RTC. */ + writeb(rcr2 | RTCA3_RCR2_START, priv->base + RTCA3_RCR2); + return readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + (tmp & RTCA3_RCR2_START), + 10, RTCA3_DEFAULT_TIMEOUT_US); +} + +static int rtca3_alarm_irq_set_helper(struct rtca3_priv *priv, + u8 interrupts, + unsigned int enabled) +{ + u8 tmp, val; + + if (enabled) { + /* + * AIE, CIE, PIE bit indexes in RSR corresponds with + * those on RCR1. Same interrupts mask can be used. + */ + rtca3_byte_update_bits(priv, RTCA3_RSR, interrupts, 0); + val = interrupts; + } else { + val = 0; + } + + rtca3_byte_update_bits(priv, RTCA3_RCR1, interrupts, val); + return readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + ((tmp & interrupts) == val), + 10, RTCA3_IRQSET_TIMEOUT_US); +} + +static int rtca3_alarm_irq_enable(struct device *dev, unsigned int enabled) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + + guard(spinlock_irqsave)(&priv->lock); + + return rtca3_alarm_irq_set_helper(priv, RTCA3_RCR1_AIE, enabled); +} + +static int rtca3_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + u8 sec, min, hour, wday, mday, month; + struct rtc_time *tm = &wkalrm->time; + u32 year100; + u16 year; + + guard(spinlock_irqsave)(&priv->lock); + + sec = readb(priv->base + RTCA3_RSECAR); + min = readb(priv->base + RTCA3_RMINAR); + hour = readb(priv->base + RTCA3_RHRAR); + wday = readb(priv->base + RTCA3_RWKAR); + mday = readb(priv->base + RTCA3_RDAYAR); + month = readb(priv->base + RTCA3_RMONAR); + year = readw(priv->base + RTCA3_RYRAR); + + tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECAR_SEC, sec)); + tm->tm_min = bcd2bin(FIELD_GET(RTCA3_RMINAR_MIN, min)); + tm->tm_hour = bcd2bin(FIELD_GET(RTCA3_RHRAR_HR, hour)); + tm->tm_wday = bcd2bin(FIELD_GET(RTCA3_RWKAR_DAYW, wday)); + tm->tm_mday = bcd2bin(FIELD_GET(RTCA3_RDAYAR_DATE, mday)); + tm->tm_mon = bcd2bin(FIELD_GET(RTCA3_RMONAR_MON, month)) - 1; + year = FIELD_GET(RTCA3_RYRAR_YR, year); + year100 = bcd2bin((year == 0x99) ? 0x19 : 0x20); + tm->tm_year = (year100 * 100 + bcd2bin(year)) - 1900; + + wkalrm->enabled = !!(readb(priv->base + RTCA3_RCR1) & RTCA3_RCR1_AIE); + + return 0; +} + +static int rtca3_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + struct rtc_time *tm = &wkalrm->time; + u8 rcr1, tmp; + int ret; + + scoped_guard(spinlock_irqsave, &priv->lock) { + tmp = readb(priv->base + RTCA3_RCR2); + if (!(tmp & RTCA3_RCR2_START)) + return -EPERM; + + /* Disable AIE to prevent false interrupts. */ + rcr1 = readb(priv->base + RTCA3_RCR1); + rcr1 &= ~RTCA3_RCR1_AIE; + writeb(rcr1, priv->base + RTCA3_RCR1); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + !(tmp & RTCA3_RCR1_AIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* Set the time and enable the alarm. */ + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_min), priv->base + RTCA3_RMINAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONAR); + + writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRAR); + writeb(RTCA3_AR_ENB, priv->base + RTCA3_RYRAREN); + + /* Make sure we can read back the counters. */ + rtca3_prepare_cntalrm_regs_for_read(priv, false); + + /* Need to wait for 2 * 1/64 periodic interrupts to be generated. */ + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_INIT); + reinit_completion(&priv->set_alarm_completion); + + /* Enable periodic interrupt. */ + rcr1 |= RTCA3_RCR1_PIE; + writeb(rcr1, priv->base + RTCA3_RCR1); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + (tmp & RTCA3_RCR1_PIE), + 10, RTCA3_IRQSET_TIMEOUT_US); + } + + if (ret) + goto setup_failed; + + /* Wait for the 2 * 1/64 periodic interrupts. */ + ret = wait_for_completion_interruptible_timeout(&priv->set_alarm_completion, + msecs_to_jiffies(500)); + if (ret <= 0) { + ret = -ETIMEDOUT; + goto setup_failed; + } + + scoped_guard(spinlock_irqsave, &priv->lock) { + ret = rtca3_alarm_irq_set_helper(priv, RTCA3_RCR1_AIE, wkalrm->enabled); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); + } + + return ret; + +setup_failed: + scoped_guard(spinlock_irqsave, &priv->lock) { + /* + * Disable PIE to avoid interrupt storm in case HW needed more than + * specified timeout for setup. + */ + writeb(rcr1 & ~RTCA3_RCR1_PIE, priv->base + RTCA3_RCR1); + readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, !(tmp & ~RTCA3_RCR1_PIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); + } + + return ret; +} + +static int rtca3_read_offset(struct device *dev, long *offset) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + u8 val, radj, cycles; + u32 ppb_per_cycle; + + scoped_guard(spinlock_irqsave, &priv->lock) { + radj = readb(priv->base + RTCA3_RADJ); + val = readb(priv->base + RTCA3_RCR2); + } + + cycles = FIELD_GET(RTCA3_RADJ_ADJ, radj); + + if (!cycles) { + *offset = 0; + return 0; + } + + if (val & RTCA3_RCR2_ADJP) + ppb_per_cycle = priv->ppb.ten_sec; + else + ppb_per_cycle = priv->ppb.sixty_sec; + + *offset = cycles * ppb_per_cycle; + val = FIELD_GET(RTCA3_RADJ_PMADJ, radj); + if (val == RTCA3_RADJ_PMADJ_SUB) + *offset = -(*offset); + + return 0; +} + +static int rtca3_set_offset(struct device *dev, long offset) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + int cycles, cycles10, cycles60; + u8 radj, adjp, tmp; + int ret; + + /* + * Automatic time error adjustment could be set at intervals of 10 + * or 60 seconds. + */ + cycles10 = DIV_ROUND_CLOSEST(offset, priv->ppb.ten_sec); + cycles60 = DIV_ROUND_CLOSEST(offset, priv->ppb.sixty_sec); + + /* We can set b/w 1 and 63 clock cycles. */ + if (cycles60 >= -RTCA3_RADJ_ADJ_MAX && + cycles60 <= RTCA3_RADJ_ADJ_MAX) { + cycles = cycles60; + adjp = 0; + } else if (cycles10 >= -RTCA3_RADJ_ADJ_MAX && + cycles10 <= RTCA3_RADJ_ADJ_MAX) { + cycles = cycles10; + adjp = RTCA3_RCR2_ADJP; + } else { + return -ERANGE; + } + + radj = FIELD_PREP(RTCA3_RADJ_ADJ, abs(cycles)); + if (!cycles) + radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_NONE); + else if (cycles > 0) + radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_ADD); + else + radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_SUB); + + guard(spinlock_irqsave)(&priv->lock); + + tmp = readb(priv->base + RTCA3_RCR2); + + if ((tmp & RTCA3_RCR2_ADJP) != adjp) { + /* RADJ.PMADJ need to be set to zero before setting RCR2.ADJP. */ + writeb(0, priv->base + RTCA3_RADJ); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, !tmp, + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + rtca3_byte_update_bits(priv, RTCA3_RCR2, RTCA3_RCR2_ADJP, adjp); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + ((tmp & RTCA3_RCR2_ADJP) == adjp), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + } + + writeb(radj, priv->base + RTCA3_RADJ); + return readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, (tmp == radj), + 10, RTCA3_DEFAULT_TIMEOUT_US); +} + +static const struct rtc_class_ops rtca3_ops = { + .read_time = rtca3_read_time, + .set_time = rtca3_set_time, + .read_alarm = rtca3_read_alarm, + .set_alarm = rtca3_set_alarm, + .alarm_irq_enable = rtca3_alarm_irq_enable, + .set_offset = rtca3_set_offset, + .read_offset = rtca3_read_offset, +}; + +static int rtca3_initial_setup(struct clk *clk, struct rtca3_priv *priv) +{ + unsigned long osc32k_rate; + u8 val, tmp, mask; + u32 sleep_us; + int ret; + + osc32k_rate = clk_get_rate(clk); + if (!osc32k_rate) + return -EINVAL; + + sleep_us = DIV_ROUND_UP_ULL(1000000ULL, osc32k_rate) * 6; + + priv->ppb.ten_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 10)); + priv->ppb.sixty_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 60)); + + /* + * According to HW manual (section 22.4.2. Clock and count mode setting procedure) + * we need to wait at least 6 cycles of the 32KHz clock after clock was enabled. + */ + usleep_range(sleep_us, sleep_us + 10); + + /* Disable all interrupts. */ + mask = RTCA3_RCR1_AIE | RTCA3_RCR1_CIE | RTCA3_RCR1_PIE; + ret = rtca3_alarm_irq_set_helper(priv, mask, 0); + if (ret) + return ret; + + mask = RTCA3_RCR2_START | RTCA3_RCR2_HR24; + val = readb(priv->base + RTCA3_RCR2); + /* Nothing to do if already started in 24 hours and calendar count mode. */ + if ((val & mask) == mask) + return 0; + + /* Reconfigure the RTC in 24 hours and calendar count mode. */ + mask = RTCA3_RCR2_START | RTCA3_RCR2_CNTMD; + writeb(0, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* + * Set 24 hours mode. According to HW manual (section 22.3.19. RTC Control + * Register 2) this needs to be done separate from stop operation. + */ + mask = RTCA3_RCR2_HR24; + val = RTCA3_RCR2_HR24; + writeb(val, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, (tmp & mask), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* Execute reset. */ + mask = RTCA3_RCR2_RESET; + writeb(val | RTCA3_RCR2_RESET, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask), + 10, RTCA3_RESET_TIMEOUT_US); + if (ret) + return ret; + + /* + * According to HW manual (section 22.6.3. Notes on writing to and reading + * from registers) after reset we need to wait 6 clock cycles before + * writing to RTC registers. + */ + usleep_range(sleep_us, sleep_us + 10); + + /* Set no adjustment. */ + writeb(0, priv->base + RTCA3_RADJ); + ret = readb_poll_timeout(priv->base + RTCA3_RADJ, tmp, !tmp, 10, + RTCA3_DEFAULT_TIMEOUT_US); + + /* Start the RTC and enable automatic time error adjustment. */ + mask = RTCA3_RCR2_START | RTCA3_RCR2_AADJE; + val |= RTCA3_RCR2_START | RTCA3_RCR2_AADJE; + writeb(val, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, ((tmp & mask) == mask), + 10, RTCA3_START_TIMEOUT_US); + if (ret) + return ret; + + /* + * According to HW manual (section 22.6.4. Notes on writing to and reading + * from registers) we need to wait 1/128 seconds while the clock is operating + * (RCR2.START bit = 1) to be able to read the counters after a return from + * reset. + */ + usleep_range(8000, 9000); + + /* Set period interrupt to 1/64 seconds. It is necessary for alarm setup. */ + val = FIELD_PREP(RTCA3_RCR1_PES, RTCA3_RCR1_PES_1_64_SEC); + rtca3_byte_update_bits(priv, RTCA3_RCR1, RTCA3_RCR1_PES, val); + return readb_poll_timeout(priv->base + RTCA3_RCR1, tmp, ((tmp & RTCA3_RCR1_PES) == val), + 10, RTCA3_DEFAULT_TIMEOUT_US); +} + +static int rtca3_request_irqs(struct platform_device *pdev, struct rtca3_priv *priv) +{ + struct device *dev = &pdev->dev; + int ret, irq; + + irq = platform_get_irq_byname(pdev, "alarm"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get alarm IRQ!\n"); + + ret = devm_request_irq(dev, irq, rtca3_alarm_handler, 0, "rtca3-alarm", priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to request alarm IRQ!\n"); + priv->wakeup_irq = irq; + + irq = platform_get_irq_byname(pdev, "period"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get period IRQ!\n"); + + ret = devm_request_irq(dev, irq, rtca3_periodic_handler, 0, "rtca3-period", priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to request period IRQ!\n"); + + /* + * Driver doesn't implement carry handler. Just get the IRQ here + * for backward compatibility, in case carry support will be added later. + */ + irq = platform_get_irq_byname(pdev, "carry"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get carry IRQ!\n"); + + return 0; +} + +static void rtca3_action(void *data) +{ + struct device *dev = data; + struct rtca3_priv *priv = dev_get_drvdata(dev); + int ret; + + ret = reset_control_assert(priv->rstc); + if (ret) + dev_err(dev, "Failed to de-assert reset!"); + + ret = pm_runtime_put_sync(dev); + if (ret < 0) + dev_err(dev, "Failed to runtime suspend!"); +} + +static int rtca3_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rtca3_priv *priv; + struct clk *clk; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; + + priv->rstc = devm_reset_control_get_shared(dev, NULL); + if (IS_ERR(priv->rstc)) + return PTR_ERR(priv->rstc); + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + ret = reset_control_deassert(priv->rstc); + if (ret) { + pm_runtime_put_sync(dev); + return ret; + } + + dev_set_drvdata(dev, priv); + ret = devm_add_action_or_reset(dev, rtca3_action, dev); + if (ret) + return ret; + + /* + * This must be an always-on clock to keep the RTC running even after + * driver is unbinded. + */ + clk = devm_clk_get_enabled(dev, "counter"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + spin_lock_init(&priv->lock); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); + init_completion(&priv->set_alarm_completion); + + ret = rtca3_initial_setup(clk, priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to setup the RTC!\n"); + + ret = rtca3_request_irqs(pdev, priv); + if (ret) + return ret; + + device_init_wakeup(&pdev->dev, 1); + + priv->rtc_dev = devm_rtc_allocate_device(&pdev->dev); + if (IS_ERR(priv->rtc_dev)) + return PTR_ERR(priv->rtc_dev); + + priv->rtc_dev->ops = &rtca3_ops; + priv->rtc_dev->max_user_freq = 256; + priv->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000; + priv->rtc_dev->range_max = RTC_TIMESTAMP_END_2099; + + return devm_rtc_register_device(priv->rtc_dev); +} + +static int rtca3_remove(struct platform_device *pdev) +{ + struct rtca3_priv *priv = platform_get_drvdata(pdev); + + guard(spinlock_irqsave)(&priv->lock); + + /* + * Disable alarm, periodic interrupts. The RTC device cannot + * power up the system. + */ + rtca3_alarm_irq_set_helper(priv, RTCA3_RCR1_AIE | RTCA3_RCR1_PIE, 0); + + return 0; +} + +static int rtca3_suspend(struct device *dev) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + + if (!device_may_wakeup(dev)) + return 0; + + /* Alarm setup in progress. */ + if (atomic_read(&priv->alrm_sstep) != RTCA3_ALRM_SSTEP_DONE) + return -EBUSY; + + enable_irq_wake(priv->wakeup_irq); + + return 0; +} + +static int rtca3_clean_alarm(struct rtca3_priv *priv) +{ + struct rtc_device *rtc_dev = priv->rtc_dev; + time64_t alarm_time, now; + struct rtc_wkalrm alarm; + struct rtc_time tm; + u8 pending; + int ret; + + ret = rtc_read_alarm(rtc_dev, &alarm); + if (ret) + return ret; + + if (!alarm.enabled) + return 0; + + ret = rtc_read_time(rtc_dev, &tm); + if (ret) + return ret; + + alarm_time = rtc_tm_to_time64(&alarm.time); + now = rtc_tm_to_time64(&tm); + if (alarm_time >= now) + return 0; + + /* + * Heuristically, it has been determined that when returning from deep + * sleep state the RTCA3_RSR.AF is zero even though the alarm expired. + * Call again the rtc_update_irq() if alarm helper detects this. + */ + + guard(spinlock_irqsave)(&priv->lock); + + pending = rtca3_alarm_handler_helper(priv); + if (!pending) + rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF); + + return 0; +} + +static int rtca3_resume(struct device *dev) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + + if (!device_may_wakeup(dev)) + return 0; + + disable_irq_wake(priv->wakeup_irq); + + /* + * According to the HW manual (section 22.6.4 Notes on writing to + * and reading from registers) we need to wait 1/128 seconds while + * RCR2.START = 1 to be able to read the counters after a return from low + * power consumption state. + */ + mdelay(8); + + /* + * The alarm cannot wake the system from deep sleep states. In case + * we return from deep sleep states and the alarm expired we need + * to disable it to avoid failures when setting another alarm. + */ + return rtca3_clean_alarm(priv); +} + +static DEFINE_SIMPLE_DEV_PM_OPS(rtca3_pm_ops, rtca3_suspend, rtca3_resume); + +static const struct of_device_id rtca3_of_match[] = { + { .compatible = "renesas,rz-rtca3", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rtca3_of_match); + +static struct platform_driver rtca3_platform_driver = { + .driver = { + .name = "rtc-rtca3", + .pm = pm_ptr(&rtca3_pm_ops), + .of_match_table = rtca3_of_match, + }, + .probe = rtca3_probe, + .remove = rtca3_remove, +}; +module_platform_driver(rtca3_platform_driver); + +MODULE_DESCRIPTION("Renesas RTCA-3 RTC driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); From patchwork Fri Jan 24 09:00:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949118 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AA07C0218D for ; Fri, 24 Jan 2025 09:00:31 +0000 (UTC) Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) by mx.groups.io with SMTP id smtpd.web10.7433.1737709226560031321 for ; Fri, 24 Jan 2025 01:00:26 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=ilkagwqA; spf=pass (domain: tuxon.dev, ip: 209.85.128.44, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-43618283dedso18771145e9.3 for ; Fri, 24 Jan 2025 01:00:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709225; x=1738314025; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9zy5Ld7NGydwRu6FAuloMv9y+mc+qqkUcwb3dRcSgM4=; b=ilkagwqAVV19suftjCYFmEydoNKAezUfPuSsNNw6X89DUIWDpsdDa8mddUj8zkgGhM eAgX2v8PBZDe1zk4t4yG6UtDQ0qfP8KVt99Nh2WYdTr85po3Zn6kpj0FiQJ34TBNkGBq IwIKytltd6zC1rTYO4clAAVaeED+87UtRPkfNWG8S8lme/15McfARMVS3GY/qIBRY/hd AtJEgcPFuPNZL46MMAMNtveV42grkurTBDETYL2aJxcPYgNf+OFbdDZGEW6qqsO+ogQK yaqOzSRDcm3XmcLvTQHSlfmn9V7wf+g3lYPF1a0+x1KV7d9Qlr/xlBqflQEa9tRq+JxJ VZ+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709225; x=1738314025; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9zy5Ld7NGydwRu6FAuloMv9y+mc+qqkUcwb3dRcSgM4=; b=wo52HgzQt/gdAPcjZ91LQlK76VinVXv6eE8qJ0UECKedgxZRughWp7mvhoQ3tbyX0S WMsoKr215HLX/+VPxqYjjq89NjsDTyFICNO7QANfLtuqxhwna8orHOKJFilipVDP7DUm npoeszDoq2uR3GnuVIIdWlAy/aYoCeEyQQ3tCBCIGlqJOMeYcKW7BljAjUOoI5mAEIU/ x/RZy2ME8lCncDxumBNW17kd4uVuPAmlWm51rtCKVExZBbTaei7CMC+cBMjk1R6UrJxn ySjbgrC3FbNJD6KYaCVekPzqRkM83wBJZIsT6aR0Okpa2TZw8yJdBLZJxg2tsEGwp6uI DA8A== X-Forwarded-Encrypted: i=1; AJvYcCV0laE3HPqopFCqbFHWr53rRUbfTIV1zFlhFySofkEdlsInXiSUHCiva8iS4QSw17EU+eW5Bktr@lists.cip-project.org X-Gm-Message-State: AOJu0YxyITBD65kZ5wjtLC6aNtMh/G1X695IDO9QdqW+t76JIbkbqZdE 17foXYi/C4C98CAyWPBBhk+KFJzpE+pAhcwNdC9H5F/ZTX0+1cSsXc4S401+gmF91l2SNpRCHd7 w X-Gm-Gg: ASbGncvO1ySCfaLgPeS3/qjryCjM2uhmDWEdZgaOdckFs6fpeRT5Y77DWTvTSWDNbVb rhpcDwcbabGTh0Tp37Z1M0DsEKv5XQgtVlYLBa0lI8dI24KZW1oWPU/x9Fyk+Nr/eRt11MvM4bh QfKbnUFd2qi/sO2bRILDb66otwKy8odQuNMQ2c4eoWiqSAOS6AIFxb604lMHvhhTjZgyUwigAbj uaghdzAZopY7OAKsXXjSwZNVICEFjsBxG47cpVnBniF3Pobej0tdivCTnBoG8oWW040fbgxDDFt yCo3zvYcXNtMFzR4JGQSdEkicde+AjduXQ== X-Google-Smtp-Source: AGHT+IFCvEjAIVuoB/XThAjpm6EI1tQtHy3pzXl6cun2QCNbxzgtI7GPd3V4LsdK4gcHPWJlnPNuYw== X-Received: by 2002:a05:600c:511b:b0:435:14d:f61a with SMTP id 5b1f17b1804b1-438914304a8mr212277605e9.25.1737709224988; Fri, 24 Jan 2025 01:00:24 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd47f25csm19410935e9.1.2025.01.24.01.00.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:24 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip v2 09/14] rtc: renesas-rtca3: Fix compilation error on RISC-V Date: Fri, 24 Jan 2025 11:00:00 +0200 Message-ID: <20250124090008.1401077-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:00:31 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17631 From: Claudiu Beznea commit 8f315a5c7376b2bc324d62a8400184da77f25e28 upstream. Fix the following compilation errors when building the RTCA3 for RISCV: ../drivers/rtc/rtc-renesas-rtca3.c:270:23: error: call to undeclared function 'FIELD_GET'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 270 | tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECCNT_SEC, sec)); | ^ ../drivers/rtc/rtc-renesas-rtca3.c:369:23: error: call to undeclared function 'FIELD_GET'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 369 | tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECAR_SEC, sec)); | ^ ../drivers/rtc/rtc-renesas-rtca3.c:476:11: error: call to undeclared function 'FIELD_GET'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 476 | cycles = FIELD_GET(RTCA3_RADJ_ADJ, radj); | ^ ../drivers/rtc/rtc-renesas-rtca3.c:523:9: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 523 | radj = FIELD_PREP(RTCA3_RADJ_ADJ, abs(cycles)); | ^ ../drivers/rtc/rtc-renesas-rtca3.c:658:8: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 658 | val = FIELD_PREP(RTCA3_RCR1_PES, RTCA3_RCR1_PES_1_64_SEC); | ^ Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20241101095720.2247815-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Alexandre Belloni Signed-off-by: Claudiu Beznea --- drivers/rtc/rtc-renesas-rtca3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/rtc/rtc-renesas-rtca3.c b/drivers/rtc/rtc-renesas-rtca3.c index 7683df87eafa..4bc28680f650 100644 --- a/drivers/rtc/rtc-renesas-rtca3.c +++ b/drivers/rtc/rtc-renesas-rtca3.c @@ -5,6 +5,7 @@ * Copyright (C) 2024 Renesas Electronics Corp. */ #include +#include #include #include #include From patchwork Fri Jan 24 09:00:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949122 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51951C0218C for ; Fri, 24 Jan 2025 09:00:31 +0000 (UTC) Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) by mx.groups.io with SMTP id smtpd.web11.7428.1737709227698908432 for ; Fri, 24 Jan 2025 01:00:28 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=hK73FmXc; spf=pass (domain: tuxon.dev, ip: 209.85.128.51, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-4361dc6322fso12145985e9.3 for ; Fri, 24 Jan 2025 01:00:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709226; x=1738314026; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZzGO9ARih/R7OvarGAIo/MMNukwFVP28FODqkLvyhug=; b=hK73FmXcMYOSTpepdHbHnCq88cRXixEPQIQH865FQ3rxz6DGIy3nvZ5C3bkb1g3NRS YYIUXOkH9zS2d8gUHVcn2PnUVovCfzkCRei4EwlotJxZckpim3WPmpXkj8URuLCepn3N i+jS8VPGJ5Z0sFjDritrOkxwvr0F8V3dekkKcCNWFG7zzPR2KIKjfqmgcHzAi7npnKbS a//uMhhsN4+GETMuLQ3qDSY7IYPzsWcAQ/jG+Q6DonSmIlMmdT2PxUf7DbWrMUHH3JaX 4CFK08u4rFvSGfD9BgWXziIUApg+8J/UZZPb2m6sgooYrx7aGc2ARo/M8cvcuyeIZs1w uTYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709226; x=1738314026; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZzGO9ARih/R7OvarGAIo/MMNukwFVP28FODqkLvyhug=; b=WuinJ5cYRApttaxrpQJFLL+HM+j/O+FK7VwZBmpn/KTpXBAuAVQsf5PqBZ7JbcGglE 0f0cgQpPKCXUHYVh2VUb88CoJxt1adRl2G/SKIR36+63FmLv/xPLlQEygLK069f677eW gMrTLFZVmn+zl+Tn5diNHog1P2CfgVheMZ+NDOCn9Tc39j/9K6Nd3hLGVNEzjvNFSjLG F8pkDOUiBC9YgFz3GValhRIFgVODjWrCisCW6y2ASGawbACvV5FL2eW7Bm+abO3EsJdW s20axM1tloxHn59xN0Q51L/1fw5MHTqeoOKiu1grEOSvaPNMz2R778HBgnMU91C1+xnj tx9g== X-Forwarded-Encrypted: i=1; AJvYcCVpPKTfoKdUQ+5Xw3vQZkl4mE4Ne8srP+OFdkhnQfw0jGy8Ua/rsMqHDjiD4wKpW2hHOb0SjwLd@lists.cip-project.org X-Gm-Message-State: AOJu0YwJvKDkxUhB1F1tYVktgIssoKxbVLDWTxPD2eADXzi9RMfs3mQN iEzaxL3jXkWGK/5xp6wXpbna+tjPDaJP/m353tx6/epGdrZx3IdE0QNWVl3V8Pc= X-Gm-Gg: ASbGnct4G+ujcu0n4oQqFyo7nOiy2227x2yJ7KL7NK5DlsWM3SZoFLcIXfVPg+ITTvN lP/I0EJU2xUMn6OhGoe4i+cFLg+srXrHEq+jHNx8h2vYGlzrcDQJrAcnIcwwnpOW8Pi93BAvvCD X63APSYZ4T+XtGbSgZouGkxaEeaamP7n/iv5K4k/lFw65SO53qL4RHlZUkep84KHefiLCTp/LPb lK2NUw8NSEVOYPSTy6Snx2FT+ET0eoGctSog2QeEIGPBpqs35f90cDQjXwjwKe1NRKXQem9/P0k rHVyDMJFpijOeW27LKCJ6jkh+H8xqulZmQ== X-Google-Smtp-Source: AGHT+IGKypmj4TbhX93YxgvXYu10q8J4rVZnQ4bZtF2Ac+C9XP9UEQXc1vrPZigJbRlOxP3niEvJFw== X-Received: by 2002:a5d:5848:0:b0:38b:dbf0:34f2 with SMTP id ffacd0b85a97d-38bf59f03c7mr28311526f8f.52.1737709226180; Fri, 24 Jan 2025 01:00:26 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd47f25csm19410935e9.1.2025.01.24.01.00.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:25 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip v2 10/14] arm64: dts: renesas: r9a08g045: Add VBATTB node Date: Fri, 24 Jan 2025 11:00:01 +0200 Message-ID: <20250124090008.1401077-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:00:31 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17632 From: Claudiu Beznea commit 23c44956bce5aa79c060fc3e5d51843735e6eda6 upstream. Add the DT node for the VBATTB IP along with DT bindings for the clock it provides. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-6-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [claudiu.beznea: the backported patch has references for i2c nodes; the i2c nodes are not available in v6.1 cip, thus fixed conflict by dropping the i2c nodes] Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index f5f3f4f4c8d6..7bc8969a7b5a 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -72,6 +72,18 @@ scif0: serial@1004b800 { status = "disabled"; }; + vbattb: clock-controller@1005c000 { + compatible = "renesas,r9a08g045-vbattb"; + reg = <0 0x1005c000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; + clock-names = "bclk", "rtx"; + #clock-cells = <1>; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + status = "disabled"; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a08g045-cpg"; reg = <0 0x11010000 0 0x10000>; @@ -296,4 +308,11 @@ timer { <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; + + vbattb_xtal: vbattb-xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; }; From patchwork Fri Jan 24 09:00:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949120 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6291EC0218E for ; Fri, 24 Jan 2025 09:00:31 +0000 (UTC) Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) by mx.groups.io with SMTP id smtpd.web10.7437.1737709229559378118 for ; Fri, 24 Jan 2025 01:00:29 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=f0m5DWw3; spf=pass (domain: tuxon.dev, ip: 209.85.221.46, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-385f07cd1a4so1811584f8f.1 for ; Fri, 24 Jan 2025 01:00:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709228; x=1738314028; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=avEm0xWoaPOuBqma5bKPsWNEysSf4Ic0Xdn9jpjXkLw=; b=f0m5DWw3YFATjCJ6oldRZbbjOt4bKBKEOj8JCG+pyLqJJKEHY2834E4Fe3H+W7WXkL KU7OVVlSVXG+y/PCg4lrV7ieZQwYHzg5KxwsBXc8HwIyzizV/mQCevjVUJbDEzmhfFNl dvRLJuVetRqYmtJ8RoRXrvg1RrO2jhmHECAK0yJE437697V7K4CKIg0t7vNVdLAWD9Wh 2ZHF4PHSk/Q+489om99ZYM/y0yPytzruSV63Eu2H0LFTBUI5EGXWk6YvNk6C26cU9Qvh AgwnH8e3O7jS5KtNE7EpLqkQj25uNaU5nJU1Poa/XWBkLLQ2R6rZG6j33eI56kh4xl+f 8J2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709228; x=1738314028; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=avEm0xWoaPOuBqma5bKPsWNEysSf4Ic0Xdn9jpjXkLw=; b=IO5PwZCtpy3h39EZaO9/2d8bubJCcJWRiadmG7Mu7xEE8ik5f0sf/RrIa5d2F4CT8a ixyryrsSxNJYnngTIoDEkoehht9rSZcXku91dfYtXlRMd43ISahPaEwWJIdSuGIvfWFD kHkaApxCIztbNBPgyKwcxbV/oMj27qAk5EI3FGBibrzk1WL0ynrzGXFKdGP7TZ6rTxWx JTLeJGuk6gSdu0jw+y+pWA8HzvHGB8VhxPcRgNIioimLsoJIZ5+KCO/SJi1CT/AnAhUQ jbTi1Ch0n0XNjsPX0OEIuwbB8phx/Vaqj062/XVO4mPpC7v0iuwwciPPPGdgZ1muT6sL MHZg== X-Forwarded-Encrypted: i=1; AJvYcCWzROuwPbVYDyA2M27KcdGu/WeYo5I0Jar4qF6RGOY8O5IA5xKdyutT9q1F5nPQRzrfPJwA0Cax@lists.cip-project.org X-Gm-Message-State: AOJu0Yz643CLFzDcB86NXYAxMGSbOlwl/CgL0pui5k4r7p3ifGy+juPj lTn+rB//g8djxwTM5JJGTyNR5KcjLaJ5XmYLlRgNGsRSSRJp+66mD0WPbgJlRss= X-Gm-Gg: ASbGncvcQ4NmUk3w0NAPtRXbeAUl9mQCYX/L4b9Forl0fzafhpLaK+RgeUk4hdncnX6 Iw9Q0Idy4FV64Did4yef1MOTdo8rL4WYDQNeskI7nznV4DhmPM2Kcb3UozMyh8meLOGxjs0f96Y bvTiWKizbMEO6wRnmPNCxjBKcC1ppSXbJVkG1F63zk1eDNnbP6+0t4LifKNc1TDJNkolg3Qa+VA MlBHDmP8W//NolHQlqCcXtx7gl9ES91z94r12LCPg0lGKrHPBfIcRrDVGXTgnMol0ZYqfYRQ1Jj DBTT/snX57govTp8i8R0+p503hfKAyHZJg== X-Google-Smtp-Source: AGHT+IFuuUumaBRNTEHo5GBwPOe4hfaz3YAEHlfQDb5O6M8GPW+b0glNFIdDCng7PCIicGmGAMwhnw== X-Received: by 2002:a5d:47c9:0:b0:386:416b:9c69 with SMTP id ffacd0b85a97d-38bf5662912mr30219617f8f.16.1737709227819; Fri, 24 Jan 2025 01:00:27 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd47f25csm19410935e9.1.2025.01.24.01.00.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:26 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip v2 11/14] arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB Date: Fri, 24 Jan 2025 11:00:02 +0200 Message-ID: <20250124090008.1401077-12-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:00:31 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17633 From: Claudiu Beznea commit ac948eb8ead1265ff034955bdbbb081744f1e7ed upstream. Enable the VBATTB controller. It provides the clock for RTC. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-8-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index acac4666ae59..67178d8c4108 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2023 Renesas Electronics Corp. */ +#include #include #include @@ -341,6 +342,17 @@ mux { }; }; +&vbattb { + assigned-clocks = <&vbattb VBATTB_MUX>; + assigned-clock-parents = <&vbattb VBATTB_XC>; + quartz-load-femtofarads = <12500>; + status = "okay"; +}; + +&vbattb_xtal { + clock-frequency = <32768>; +}; + &wdt0 { timeout-sec = <60>; status = "okay"; From patchwork Fri Jan 24 09:00:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949121 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44DCEC0218B for ; Fri, 24 Jan 2025 09:00:31 +0000 (UTC) Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.groups.io with SMTP id smtpd.web10.7438.1737709230540899769 for ; Fri, 24 Jan 2025 01:00:30 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=rfEhgX+V; spf=pass (domain: tuxon.dev, ip: 209.85.128.49, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-4361dc6322fso12146365e9.3 for ; Fri, 24 Jan 2025 01:00:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709229; x=1738314029; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QT9gIUiudDAAdT7+/KwLCRVApT8O0rjggfgBvSy6a4o=; b=rfEhgX+VyfpzLDA2x6uZ7/4PpCo51+tQ7qWcYDCBUifRPVCmm5OImHWx+zciAe2t0y L+4YQ2LDNQ9dsVy1A/0JktG8GssLMSJG+MDogSX6BhQz4Uj1tAcf4ga/n9SpGqa2yUYV k/fa88qWFqfcAq5UFcrITAIkwN3mv3IU1lLshGuGxDdhPKT4xL6lu6p3y2dAu+0N0tqX YN8UN9Vo9zEpH98sTGT0nf6Sl3e00nE2UogrSV30YDwDXKbRFFdIJJr3ljJQI/Tl16fM jHAeHzthA7td4w3LZSvO8Y5w91ybHQfG5D/63dAGmfFO3xHqA5aPqsmMTE1vw1nge75U jc4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709229; x=1738314029; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QT9gIUiudDAAdT7+/KwLCRVApT8O0rjggfgBvSy6a4o=; b=v8yUlKzPc7HK0OgR/155ftEAVDdQbl0vW+6VcB5ih1fdT2A9P8x+2NRjMAOSnqRX0R oZ/s4RRmaLJV8+vtBLniP+dImLDh4rGLKC7nNYqjncYiBetDqVGd85UpMCLwtYi0dshM U4dsQiGna4+GjqzY8EL7Yx1d/tMbkyqPb5h3d+IsJxcDPMOwj0vRKuWKhhaV8EKp2lhE orkYZD24qive60Nhp5PE431Pjhyfn2fVsdsOh3vcYp2lspnFFo8wY06jwoj/dbhgYvtn trMQ9yJ9hOds0bkKtdXMlw9XUrgFxHvN56pPHQQdgR6OeS0p2os+0ocPV28XVQR447d2 V9ZA== X-Forwarded-Encrypted: i=1; AJvYcCU4qhJNr2v442YF1kojG3mCp4+33uCW1P3YHc1xBQ2d1pdexvSlBZRJmzyqs0aUHejU4DnSzDWK@lists.cip-project.org X-Gm-Message-State: AOJu0YyLuCC7TYC6VdwScQf1xcTrESfSUJEO+Na/t7YUTUH1GTy8s+yD Hk/R3hHRPeO13woB0W2pa6TIkKsnzRzWqUlMi9xflODChTyM74GzCVUlKl0UtTo= X-Gm-Gg: ASbGncuhG0eabN29Bk5NXEZ3L7Vgt3eDZDGz/GhhkpSWhFHNMTRSkB3Dx2wgOTo+FzF w1GeSHx2hrpUw5Km/EBPgEc+cbmxxaRQ+xa7Iw7LCrixsV8hNgomj+vFOxObVrmkFrRa3neiTE/ UTo4LUe3OJ5OmYnq8PPD+wkVxq45QeiU8gv/UQy7rQYu1jL49UQ9m3RE9Ev87+8CD80SE3gv7NR Jiyz0Zeww4HvN0CkNed7A5w/VcOhhZMij4WO1FOmcWIedDEXA5TefthFDLw9eZLENG/RhN2OOtD 3f/+x9Q7vYmb8ajxuPJ0of16mhRJvhQuCw== X-Google-Smtp-Source: AGHT+IEvIRBMVcLeWm30GPCjET410L/nZBg0LznQIElnf5j+QBEgZHAiUbRjb4pZmap6GyyYtk6puQ== X-Received: by 2002:a05:600c:3149:b0:434:f270:a513 with SMTP id 5b1f17b1804b1-4389144e70fmr279274955e9.29.1737709228969; Fri, 24 Jan 2025 01:00:28 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd47f25csm19410935e9.1.2025.01.24.01.00.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:28 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip v2 12/14] arm64: dts: renesas: r9a08g045: Add RTC node Date: Fri, 24 Jan 2025 11:00:03 +0200 Message-ID: <20250124090008.1401077-13-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:00:31 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17634 From: Claudiu Beznea commit 2d768aee9f5294d2023e824c0906e2e7d1414629 upstream. Add the DT node for the RTC IP available on the Renesas RZ/G3S SoC. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-7-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 7bc8969a7b5a..3401c1200a1c 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -7,6 +7,7 @@ #include #include +#include / { compatible = "renesas,r9a08g045"; @@ -72,6 +73,20 @@ scif0: serial@1004b800 { status = "disabled"; }; + rtc: rtc@1004ec00 { + compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; + reg = <0 0x1004ec00 0 0x400>; + interrupts = , + , + ; + interrupt-names = "alarm", "period", "carry"; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb VBATTB_VBATTCLK>; + clock-names = "bus", "counter"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + status = "disabled"; + }; + vbattb: clock-controller@1005c000 { compatible = "renesas,r9a08g045-vbattb"; reg = <0 0x1005c000 0 0x1000>; From patchwork Fri Jan 24 09:00:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949125 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B698C0218B for ; Fri, 24 Jan 2025 09:00:41 +0000 (UTC) Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) by mx.groups.io with SMTP id smtpd.web10.7440.1737709231799602478 for ; Fri, 24 Jan 2025 01:00:32 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=SwTzmwJK; spf=pass (domain: tuxon.dev, ip: 209.85.128.43, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-4361b6f9faeso11922265e9.1 for ; Fri, 24 Jan 2025 01:00:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709230; x=1738314030; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rZ/lXKoSkUmuSxtM2ry8mqYHW2bCm5mIiSIX1gifECs=; b=SwTzmwJKSEknanGvFEGpBMvKrykkH5f74d9H3xKnk02ducbGWF7KD1LzGkwRjip79Q MopiHc2yKstlGY0kMbnFodVtoK2Qmbi2g59HGNNiazAhnnpS09t/4MrtjmGnRQbFaXh/ AKj4Ghtt9wfJpsmjAcbfXCB5LzJEeV5H1aMEOv7cpQL1g0osA3ClpN7XIDB2rHd0LpBY MNiubaGW/Wd12CMHGHGvOqpcfodkD4Cv6NGNeJNJv54P+pRcPEZ3tyEoJm5JRJUEWx8n uW3COe33lwbfJCAQtysZY5Gyp2NgSv3L5sjbHk+I5iqrMsF6yK2HShAmxsQAvX34kUlK tC0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709230; x=1738314030; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rZ/lXKoSkUmuSxtM2ry8mqYHW2bCm5mIiSIX1gifECs=; b=qOwy59mrcUlg05ZeeRuekdwkNmaT/khRcJSVIUq4u8o3qV8dbBXHpa68QnV32vVxtZ LNf9/84aTJq9vzLluW58B1mP2A/ySjm5Pjtnmkgd+a3A/RH4oE+yJGxpukJexBK7LQi1 wiIwdj9yiTEiCOdjtyVNMzirO1Xad+85eBtrCTsgmvKC4ZuWI1OADxEGYc+WNEcJiWS6 mEOJpSpTZHNKD8ZjpINm2BBuumxonLl6eNNehPqrnN9lgBgJ/YLZfNkPkLRXywkN7e5X tTaQpSWlGXMHAJxow09Sx74P9aAx25D4tgvtDuBnlnLpjs6+RZmJmlkmFpOyH/92HfwF c88g== X-Forwarded-Encrypted: i=1; AJvYcCX6vHNGclAhmt1w1X6hLQCX+P9QD4Po7VfbAixaeGN1cYasqySHGxZ/wsZw6XWhAhR0LtxfoNEI@lists.cip-project.org X-Gm-Message-State: AOJu0YyXu9Xgz/2xaO2ouf5euBejycn3e3GLTx7VTkK8Q/snh3mvNk3/ c5tqHSlaXxxzdHLUnITbzvY2BtKV0C4oogtF1xQyHnATQDqpBcWSEVGq6McGLxY= X-Gm-Gg: ASbGnct4AwYuvT6iLAY6728BzRBWIFVMFHJdxhNnpL7P+d9Ia4ovUnPLokjW6bKI69z IbDlw7ocI/vJOw5a9jCj+t3tPZaWpdxseYKwqNYDfpfva9RBT0FIbmYPHCB9J8+yjb6kPCygVyw /V2JYmxe6GCEhzggCqOnI9lAmmS63VdMXOtIEs9WR4FFMVsSABGfP2LY59r5rMvq9hqHugOVls9 A6uOSW3jqRWV0jPfSpi2C1lL9VFqiRylomyqA/bYmbWWem14Y74IOpNR5uj4Hxf8njKvzMvjAjj 8ZHKIqA/IOJ6Q9QYtAjLZIkGsa5BFtEX8A== X-Google-Smtp-Source: AGHT+IHfHlNUT3ZVLyfQvsR2W6W+AD3US3cGS4DwxW9vR21eX/cQi0c78LjxMm+4OYznvu60mLKguA== X-Received: by 2002:a05:600c:4e0c:b0:434:ff08:202e with SMTP id 5b1f17b1804b1-438b88568e8mr59144255e9.8.1737709230231; Fri, 24 Jan 2025 01:00:30 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd47f25csm19410935e9.1.2025.01.24.01.00.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:29 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip v2 13/14] arm64: dts: renesas: rzg3s-smarc-som: Enable RTC Date: Fri, 24 Jan 2025 11:00:04 +0200 Message-ID: <20250124090008.1401077-14-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:00:41 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17635 From: Claudiu Beznea commit 0cd647cd53db0315361e41056e10739a5ee1e668 upstream. Enable RTC. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-9-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 67178d8c4108..b07d9251d182 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -342,6 +342,10 @@ mux { }; }; +&rtc { + status = "okay"; +}; + &vbattb { assigned-clocks = <&vbattb VBATTB_MUX>; assigned-clock-parents = <&vbattb VBATTB_XC>; From patchwork Fri Jan 24 09:00:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949126 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B669C02181 for ; Fri, 24 Jan 2025 09:00:41 +0000 (UTC) Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) by mx.groups.io with SMTP id smtpd.web10.7441.1737709233018754483 for ; Fri, 24 Jan 2025 01:00:33 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=iMCRrAin; spf=pass (domain: tuxon.dev, ip: 209.85.128.54, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-4363ae65100so19370605e9.0 for ; Fri, 24 Jan 2025 01:00:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709231; x=1738314031; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pdoaaBkruq8UaBR6aG2nxEBiJ4gLHmsErL0xCb1P+ys=; b=iMCRrAin3ZRDk5YR6xsyMHQHYfAX4jhMn21UoTRbtLHPIjHK9znJB2D6bJl7pV5lTx pQuFnxlSLV+I1bZppRoSKRTxER2DOB2rjmBeNf+i0Y41cA7H6x0pIYafCmfoWdcGeTRH xeivq+wUegM6il6yp/oAmcwdDSHJfoVoP+ZHQTFLW0mSB91IkC80NPBRh9j2g9td9x4M M4YFSRK0DdxzWGILxNmSNzL/DUPMq3GhwmgOEBjMBEc+QronmAISXxHbceZw4UCA6jEm dDiHQl0CNws7LFE+GXgmcrWe6N/i05E5vVafGHRtADxj8msN7kRb/rUrtBya80DE93m+ ocvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709231; x=1738314031; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pdoaaBkruq8UaBR6aG2nxEBiJ4gLHmsErL0xCb1P+ys=; b=GsX8dQa8iD47Q07jn1rm2wF8NFRo9NOpDqDl804KrPzBGlV0EA10X+6cWX37Fb4diu oLKwz+mQUhz/rpUym3Y0dyL8Dbx+agMsF/9Lo16L6OWGGnpASgJ6kh1p6lLTF8595APi FBbbScNu7rI3WVGYhTJxW3MFY0em2smAdmZcyMAjHpJ3r3rboXTPnj8hBhus0EVo26ey qUIvzAOicLB53pCnQo+U5vmuydrORcjmJLx0024QnmSpObzGDdj/GphG4Q/H/Zql+bW/ MKir5DLK+Qo+KUcrIkjuo/7Vso103iYPRdQR8rq5/gSqTi9iZMpxWs9y1y2LhO2HCqkZ DdXA== X-Forwarded-Encrypted: i=1; AJvYcCXOeuA/mL7YNPAk/z6ICT+2hoxJLMmyzbrgFgnt9de6ipv9lJp2yAoX+bFa/7g+f8vkCSCpqEgi@lists.cip-project.org X-Gm-Message-State: AOJu0YxbTvOGlYtl0xmr1uCcmWbLmTt813TKHNuIGDN3VLYsdNgfc1JI huzUeNFnB0//sGPByX41TPEoLVnS3ik9QmdXjelnhaufofAeVZ7Nw4yxvkfXDjk= X-Gm-Gg: ASbGncsgxifhZZbtsGDvkUVZEabt/TMdAkw2EmvJ9lProGvhPqj/lmb+P9bBcPnwc/x pRVc7FG2SWsviwSdogvjrY8HvXw7HC7dGPqptBuLjtBdsunkdhzNcZaRmOYmEzynNuhjPXr/VVL sYZChmQPz7/KPmwxfw+bVx5S8WOc6xB0l3lQbBJqYqOVmCBx82EoRRCjIB/Vkj2EQ8tszwuXgNS jWI7+Zwu4H49VCPr/+K/Kenx7C48JXRjqlmlypqFcJg5l6a3HJGeYcsHRj6yAQu6fPFz9gRRzfS wFk32RSPUxhT6oiditBXLFcNCoEsBOTOJw== X-Google-Smtp-Source: AGHT+IGCTMy5ViNwtQ2l6ka4lHJiZSoV06UtoYt9QAzQxUWaRuSh88aDvPlEq3j+uD1a2nnywgetZA== X-Received: by 2002:a05:600c:3d96:b0:434:a26c:8291 with SMTP id 5b1f17b1804b1-4389143b5dbmr255301105e9.24.1737709231327; Fri, 24 Jan 2025 01:00:31 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd47f25csm19410935e9.1.2025.01.24.01.00.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:30 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v6.1.y-cip v2 14/14] arm64: defconfig: Enable VBATTB clock and Renesas RTCA-3 Date: Fri, 24 Jan 2025 11:00:05 +0200 Message-ID: <20250124090008.1401077-15-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090008.1401077-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:00:41 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17636 From: Claudiu Beznea commit c520bbb523304ba98de9ffeeb0ef289921434125 upstream. Enable the Renesas VBATTB clock and RTCA-3 RTC drivers. These are available on the Renesas RZ/G3S SoC. VBATTB is the clock provider for the RTC counter. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-10-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [claudiu.beznea: fixed conflict by dropping CONFIG_RTC_DRV_TI_K3=m and CONFIG_TEGRA186_TIMER=y; although drivers for these are avaiable in the v6.1.y cip they were not enabled in the previous arm64 defconfig] Signed-off-by: Claudiu Beznea --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 6f644364b743..a15bfa82fe59 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1016,6 +1016,7 @@ CONFIG_RTC_DRV_SNVS=m CONFIG_RTC_DRV_IMX_SC=m CONFIG_RTC_DRV_MT6397=m CONFIG_RTC_DRV_XGENE=y +CONFIG_RTC_DRV_RENESAS_RTCA3=m CONFIG_DMADEVICES=y CONFIG_DMA_BCM2835=y CONFIG_DMA_SUN6I=m @@ -1104,6 +1105,7 @@ CONFIG_SM_VIDEOCC_8250=y CONFIG_QCOM_HFPLL=y CONFIG_CLK_GFM_LPASS_SM8250=m CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y +CONFIG_CLK_RENESAS_VBATTB=m CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y CONFIG_RENESAS_OSTM=y