From patchwork Fri Jan 24 09:00:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949129 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C556C0218E for ; Fri, 24 Jan 2025 09:00:51 +0000 (UTC) Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) by mx.groups.io with SMTP id smtpd.web11.7435.1737709246162725261 for ; Fri, 24 Jan 2025 01:00:46 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=Dgy7s021; spf=pass (domain: tuxon.dev, ip: 209.85.218.49, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f49.google.com with SMTP id a640c23a62f3a-aaecf50578eso430902966b.2 for ; Fri, 24 Jan 2025 01:00:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709244; x=1738314044; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IDZzIafRWGe3jNg/iY2dGBgYzIf/GSbAKZ3dLZhE8dM=; b=Dgy7s021zRaLT9Ras0k/kw4iOAmniWuqQbjX1aOMI2+77KjfbEz1LHGOGaLo2fDt7o Mg2hT5aJGO44kLn4eRWcyR/HxCJh1l6QapY95zuncvICW3Zrgr2m0q2pR3lYuQlpcm3Z OUwR1X5R+GyjtYpyrU3NeYFnn1xtaT5togDRwGtBG4sgZAXjv/GieVuFFVr0T24AQ+N2 K7Tg4LOOWI+fovQzBAvbDXC6K5ap6HfmvjsSUD7IFANS/3jF+d5po1ChT+6jys8++r4c EHNDEVguPA+VnnWrsGL8ez8VNVBuiQ5bcmo91qjxI5l2nRLgf/47EPPrU8OU3csR9usH iuHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709244; x=1738314044; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IDZzIafRWGe3jNg/iY2dGBgYzIf/GSbAKZ3dLZhE8dM=; b=Pj155IXb65QaR/JhMwwdCQHPhyID9sTEFNbuojTW3o2ZfC//bml/IXEpifGnTOErM6 NUZfmoT3nbSv6riR16YJh8+lECgJkuwP6MGfzP2GdOhDrcCQ3KQFCTvdZo/7l6OuyRTV nA6hp/7tB6uJIKS5Ozy/JfI88I/Y4YOdLXxIQ3AacRg6L2WprtOWXkDDnhdCzKeILKFb KBztAyFYRgFg2aj8IT9zw6E+tQGh+XFZy6sBrDFuIXvvMVCBtbP6u6c/sP+s5k1en1jm Q7IaRqnmwRoAtfjK38GEt0+FdUkBb5vTjLrA3IsLv9Op3I876XyvDMuwtuJgrF13nV+E NeKQ== X-Forwarded-Encrypted: i=1; AJvYcCWXhg1x41Oy05f3dl1e76utVFIfXsaWUbsBkItObEXrkTAYgWbUIo88LSY2nZKeD4tEU2fXWZq5@lists.cip-project.org X-Gm-Message-State: AOJu0YxqerD+X8uzax9P5Ne9mGJM3WF7zj/PfIXs7cwopzE2RZR/1SlR vLI9RyCV83BfZoH6XJtABySOOPpNYua0k+djfewAshLcw7jRLnZuc2yITkwfWdY= X-Gm-Gg: ASbGncs3KQ/uG/UvBRm1QjwTwLieyoMQyqmAjJVf4aYttZphZWMP/mwtpQIZcwoNt39 M2BpeoJlb4KGSMq0JltsIYU7iAyS3IV0KQ6px/k++5PR2Qudf2YDYoVf3d11/Lr2KisY6u875m8 fL2fb1aoIFfSYFmq+XD06ZZaT8AtiQZxPIkjuTjjlYEYk9M/FwjXWwk5ZC8KymQ3wyUdq0nTPPx hRCPgTs7AJDxzZ37dItBiKLp2oidwvdvfkmf4E6zO3r5kgjX8JT3pj4CS2bDdNr+HBm6RZYSFJK WVED2k/gjndwNR5cc56wXB0eULij5ptjZQ== X-Google-Smtp-Source: AGHT+IEx5g7FQc8nyJqDliHsNxmO10OgtXinEdUdY4FkAe/qtGVTmCG9W2dhkWTDd+PxMmivEJceTw== X-Received: by 2002:a17:907:1c91:b0:aaf:c27e:12e7 with SMTP id a640c23a62f3a-ab38b15ce17mr2818304566b.23.1737709244225; Fri, 24 Jan 2025 01:00:44 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab6760fbce4sm92200766b.127.2025.01.24.01.00.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:43 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip v2 01/16] clk: Add devm_clk_hw_register_gate_parent_data() Date: Fri, 24 Jan 2025 11:00:26 +0200 Message-ID: <20250124090041.1401132-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:00:51 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17638 From: Claudiu Beznea Add devm_clk_hw_register_gate_parent_data() macro to be used in the Renesas VBATTB clock driver. This macro originates from the upstream commit d54c1fd4a51e ("Add clock driver for Sunplus SP7021 SoC"). Signed-off-by: Claudiu Beznea --- include/linux/clk-provider.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 75cdef73e751..411f50478043 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -571,6 +571,25 @@ struct clk *clk_register_gate(struct device *dev, const char *name, __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \ (flags), (reg), (bit_idx), \ (clk_gate_flags), (lock)) +/** + * devm_clk_hw_register_gate_parent_data - register a gate clock with the + * clock framework + * @dev: device that is registering this clock + * @name: name of this clock + * @parent_data: parent clk data + * @flags: framework-specific flags for this clock + * @reg: register address to control gating of this clock + * @bit_idx: which bit in the register controls gating of this clock + * @clk_gate_flags: gate-specific flags for this clock + * @lock: shared register lock for this clock + */ +#define devm_clk_hw_register_gate_parent_data(dev, name, parent_data, flags, \ + reg, bit_idx, clk_gate_flags, \ + lock) \ + __devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL, \ + (parent_data), (flags), (reg), (bit_idx), \ + (clk_gate_flags), (lock)) + void clk_unregister_gate(struct clk *clk); void clk_hw_unregister_gate(struct clk_hw *hw); int clk_gate_is_enabled(struct clk_hw *hw); From patchwork Fri Jan 24 09:00:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949131 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7607DC0218C for ; Fri, 24 Jan 2025 09:00:51 +0000 (UTC) Received: from mail-ed1-f51.google.com (mail-ed1-f51.google.com [209.85.208.51]) by mx.groups.io with SMTP id smtpd.web10.7446.1737709247422418163 for ; Fri, 24 Jan 2025 01:00:47 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=JfaRP5nF; spf=pass (domain: tuxon.dev, ip: 209.85.208.51, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ed1-f51.google.com with SMTP id 4fb4d7f45d1cf-5d3bdccba49so3444179a12.1 for ; Fri, 24 Jan 2025 01:00:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709246; x=1738314046; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/j9L8MoygLCP+eAzrb3Sudr807COGZZUyuDmw1NOUKo=; b=JfaRP5nFp9TukINDigJYYOc8XBhbEvJsBtZ1lFgzUYaSu0qoFcTMH2WFAC8tJXGmYi skjKSyh81l6paM/AEy8IPNxW+D43nKFp7OGDwj+diJWwHfeBw5LaPSA0ueXWVYFx3m8y WuaYzFNnXLZAeXIEqqGjk5vY1ifTcKjSTZWjkTnv9jhgWQ4S7FKoaew/jkh0xOdODauI +DOg220YVJOzawRxl2Yo2/BF5w/7SsctMTINpBEdZD4iXC4eMK2okpvUy5WSSw2UjIBN YptCcRZszIevdmCufNs5ljK1nHkgda3ENE3hxo0vnTP5/nHL/MCEDN5/btF4sAT7bceU 7Nug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709246; x=1738314046; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/j9L8MoygLCP+eAzrb3Sudr807COGZZUyuDmw1NOUKo=; b=t+3XJqCc3Xg5c+Ak26rx8ujgu1IuiorHE1d5SYKzoestDxx85/lLfnCYnYkEwoDZSJ ROvpo/gQWsABAM+QaAaFJVVZ9Dh9ny1Vt/AIxo+EGul5mnFIG7dXP264SucVzxUkq0P+ BUH4Z2CglN2e6Uzw/9RqvxuNWnk8LBk8aAeF3GWfJvaPyFy2YM/fss1h/j/WBo1T7ALc lxbCgmuCYbZ5nyO0aCSxrNASbpQlXzXhniHC9PXWPqrz1GErzF683Cp1Ckb3fDhV2AwJ fH0cCQ4m2x5ACRddJHdeecZmG8ZXQoIsTQJVM+JU0UMRyasqmIuvpmX3pSh6qpg8YxFK Cmzw== X-Forwarded-Encrypted: i=1; AJvYcCVPbn4bz1u+SD0e5MDB9aixqZogZVlSdVXdbBFdEwbB+pCECKu+Y/Ipco+rLJLXLE6CjTiuKW/O@lists.cip-project.org X-Gm-Message-State: AOJu0Yzq7eFwFVS07dxMGDlm03jjL04hU6auIIv8tYbKICtn0cI5V74g PYw7PjA33CiKE0ygT4/CmVE6E84v1AwgMG8wxRsIK8hjv/JpG1TmhjaP9r77Gz4= X-Gm-Gg: ASbGncsn/UI/l/dKdM18MAeCD3iscwL8WYTeA7CWJBOSRPS91shFq1rcOSsrk/TgoWS A4s/8qbc2eZb5V8H7cmYFYlMfyfGU4Dpv1XOpQmgWUX4vWTtXARJePDjlAE/mDVqJAztrcC5ZOz 5eYrNsd48bCZGrZeQijR6qRSYJv9Ckp0LRAr51F3vaefle1egmfDc2EyNzqxcxv8CiN3NweuFdc BMK15Y3ZW+mla786lKzF8pl3HpnnDj7zhdIL9GjqJI/ShNPurao3rOxaSrubO92QOfthKNbZxi1 3nVGbgIHQgwsb42V89DiyNH6quaAy0qZSw== X-Google-Smtp-Source: AGHT+IE+b/UbJbOSV/Qqae3kijcthPmQO96sTQtMcZsPgJ26Hq63iQU3NwozLnupIuHJKdRXhWHRVg== X-Received: by 2002:a17:907:3606:b0:aab:dc3e:1c84 with SMTP id a640c23a62f3a-ab38b274a03mr2403097066b.17.1737709245733; Fri, 24 Jan 2025 01:00:45 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab6760fbce4sm92200766b.127.2025.01.24.01.00.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:44 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip v2 02/16] clk: fixed-factor: add fwname-based constructor functions Date: Fri, 24 Jan 2025 11:00:27 +0200 Message-ID: <20250124090041.1401132-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:00:51 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17639 From: Théo Lebrun commit ae156a3633d377d43990eb539f8a007c0c2bf769 upstream. Add four functions to register clk_hw based on the fw_name field in clk_parent_data, ie the value in the DT property `clock-names`. There are variants for devm or not and passing an accuracy or not passing one: - clk_hw_register_fixed_factor_fwname - clk_hw_register_fixed_factor_with_accuracy_fwname - devm_clk_hw_register_fixed_factor_fwname - devm_clk_hw_register_fixed_factor_with_accuracy_fwname The `struct clk_parent_data` init is extracted from __clk_hw_register_fixed_factor to each calling function. It is required to allow each function to pass whatever field they want, not only index. Signed-off-by: Théo Lebrun Link: https://lore.kernel.org/r/20240221-mbly-clk-v7-2-31d4ce3630c3@bootlin.com Signed-off-by: Stephen Boyd Reviewed-by: Pavel Machek [claudiu.beznea: dropped the accuracy part] Signed-off-by: Claudiu Beznea --- drivers/clk/clk-fixed-factor.c | 59 ++++++++++++++++++++++++++-------- include/linux/clk-provider.h | 6 ++++ 2 files changed, 51 insertions(+), 14 deletions(-) diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index bf55b9b71c6a..97623e100d44 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -72,13 +72,12 @@ static void devm_clk_hw_register_fixed_factor_release(struct device *dev, void * static struct clk_hw * __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, const char *name, const char *parent_name, - const struct clk_hw *parent_hw, int index, + const struct clk_hw *parent_hw, const struct clk_parent_data *pdata, unsigned long flags, unsigned int mult, unsigned int div, bool devm) { struct clk_fixed_factor *fix; struct clk_init_data init = { }; - struct clk_parent_data pdata = { .index = index }; struct clk_hw *hw; int ret; @@ -107,7 +106,7 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, else if (parent_hw) init.parent_hws = &parent_hw; else - init.parent_data = &pdata; + init.parent_data = pdata; init.num_parents = 1; hw = &fix->hw; @@ -144,7 +143,9 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, const char *name, unsigned int index, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL, index, + const struct clk_parent_data pdata = { .index = index }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL, &pdata, flags, mult, div, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_index); @@ -166,8 +167,10 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev, const char *name, const struct clk_hw *parent_hw, unsigned long flags, unsigned int mult, unsigned int div) { + const struct clk_parent_data pdata = { .index = -1 }; + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw, - -1, flags, mult, div, true); + &pdata, flags, mult, div, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_parent_hw); @@ -175,9 +178,10 @@ struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev, const char *name, const struct clk_hw *parent_hw, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, - parent_hw, -1, flags, mult, div, - false); + const struct clk_parent_data pdata = { .index = -1 }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw, + &pdata, flags, mult, div, false); } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_parent_hw); @@ -185,11 +189,24 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1, - flags, mult, div, false); + const struct clk_parent_data pdata = { .index = -1 }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, + &pdata, flags, mult, div, false); } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor); +struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div) +{ + const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name }; + + return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL, + &pdata, flags, mult, div, false); +} +EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_fwname); + struct clk *clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) @@ -232,16 +249,30 @@ struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1, - flags, mult, div, true); + const struct clk_parent_data pdata = { .index = -1 }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, + &pdata, flags, mult, div, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor); +struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div) +{ + const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name }; + + return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL, + &pdata, flags, mult, div, true); +} +EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_fwname); + #ifdef CONFIG_OF static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node) { struct clk_hw *hw; const char *clk_name = node->name; + const struct clk_parent_data pdata = { .index = 0 }; u32 div, mult; int ret; @@ -259,8 +290,8 @@ static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node) of_property_read_string(node, "clock-output-names", &clk_name); - hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, NULL, 0, - 0, mult, div, false); + hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, NULL, + &pdata, 0, mult, div, false); if (IS_ERR(hw)) { /* * Clear OF_POPULATED flag so that clock registration can be diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 411f50478043..b13ab221d653 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -985,10 +985,16 @@ void clk_unregister_fixed_factor(struct clk *clk); struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); +struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div); void clk_hw_unregister_fixed_factor(struct clk_hw *hw); struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); +struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div); struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, const char *name, unsigned int index, unsigned long flags, unsigned int mult, unsigned int div); From patchwork Fri Jan 24 09:00:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949128 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 675D8C02181 for ; Fri, 24 Jan 2025 09:00:51 +0000 (UTC) Received: from mail-ed1-f52.google.com (mail-ed1-f52.google.com [209.85.208.52]) by mx.groups.io with SMTP id smtpd.web11.7439.1737709249506588361 for ; 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([82.78.167.35]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab6760fbce4sm92200766b.127.2025.01.24.01.00.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:46 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip v2 03/16] clk: gate: Add devm_clk_hw_register_gate() Date: Fri, 24 Jan 2025 11:00:28 +0200 Message-ID: <20250124090041.1401132-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:00:51 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17640 From: Horatiu Vultur commit 815f0e738a8d5663a02350e2580706829144a722 upstream. Add devm_clk_hw_register_gate() - devres-managed version of clk_hw_register_gate() Suggested-by: Stephen Boyd Signed-off-by: Horatiu Vultur Acked-by: Nicolas Ferre Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20211103085102.1656081-2-horatiu.vultur@microchip.com Reviewed-by: Pavel Machek [claudiu.beznea: fixed conflict] Signed-off-by: Claudiu Beznea --- drivers/clk/clk-gate.c | 35 +++++++++++++++++++++++++++++++++++ include/linux/clk-provider.h | 23 +++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 070dc47e95a1..64283807600b 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -222,3 +223,37 @@ void clk_hw_unregister_gate(struct clk_hw *hw) kfree(gate); } EXPORT_SYMBOL_GPL(clk_hw_unregister_gate); + +static void devm_clk_hw_release_gate(struct device *dev, void *res) +{ + clk_hw_unregister_gate(*(struct clk_hw **)res); +} + +struct clk_hw *__devm_clk_hw_register_gate(struct device *dev, + struct device_node *np, const char *name, + const char *parent_name, const struct clk_hw *parent_hw, + const struct clk_parent_data *parent_data, + unsigned long flags, + void __iomem *reg, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock) +{ + struct clk_hw **ptr, *hw; + + ptr = devres_alloc(devm_clk_hw_release_gate, sizeof(*ptr), GFP_KERNEL); + if (!ptr) + return ERR_PTR(-ENOMEM); + + hw = __clk_hw_register_gate(dev, np, name, parent_name, parent_hw, + parent_data, flags, reg, bit_idx, + clk_gate_flags, lock); + + if (!IS_ERR(hw)) { + *ptr = hw; + devres_add(dev, ptr); + } else { + devres_free(ptr); + } + + return hw; +} +EXPORT_SYMBOL_GPL(__devm_clk_hw_register_gate); diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index b13ab221d653..0e41b029f898 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -517,6 +517,13 @@ struct clk_hw *__clk_hw_register_gate(struct device *dev, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock); +struct clk_hw *__devm_clk_hw_register_gate(struct device *dev, + struct device_node *np, const char *name, + const char *parent_name, const struct clk_hw *parent_hw, + const struct clk_parent_data *parent_data, + unsigned long flags, + void __iomem *reg, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock); struct clk *clk_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, @@ -589,6 +596,22 @@ struct clk *clk_register_gate(struct device *dev, const char *name, __devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL, \ (parent_data), (flags), (reg), (bit_idx), \ (clk_gate_flags), (lock)) +/* + * devm_clk_hw_register_gate - register a gate clock with the clock framework + * @dev: device that is registering this clock + * @name: name of this clock + * @parent_name: name of this clock's parent + * @flags: framework-specific flags for this clock + * @reg: register address to control gating of this clock + * @bit_idx: which bit in the register controls gating of this clock + * @clk_gate_flags: gate-specific flags for this clock + * @lock: shared register lock for this clock + */ +#define devm_clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,\ + clk_gate_flags, lock) \ + __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ + NULL, (flags), (reg), (bit_idx), \ + (clk_gate_flags), (lock)) void clk_unregister_gate(struct clk *clk); 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([82.78.167.35]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab6760fbce4sm92200766b.127.2025.01.24.01.00.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:47 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip v2 04/16] clk: Add devm_clk_hw_register_gate_parent_hw() Date: Fri, 24 Jan 2025 11:00:29 +0200 Message-ID: <20250124090041.1401132-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:00:51 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17641 From: Claudiu Beznea commit e1ef630c56d36770e180f0d0bf7b61b5289f5c48 upstream. Add devm_clk_hw_register_gate_parent_hw() macro to allow registering devres managed gate clocks providing struct clk_hw object as parent. Reviewed-by: Geert Uytterhoeven Acked-by: Stephen Boyd Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Reviewed-by: Pavel Machek [claudiu.beznea: fixed conflict] Signed-off-by: Claudiu Beznea --- include/linux/clk-provider.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 0e41b029f898..9f34b4268e6a 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -578,6 +578,24 @@ struct clk *clk_register_gate(struct device *dev, const char *name, __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \ (flags), (reg), (bit_idx), \ (clk_gate_flags), (lock)) +/** + * devm_clk_hw_register_gate_parent_hw - register a gate clock with the clock + * framework + * @dev: device that is registering this clock + * @name: name of this clock + * @parent_hw: pointer to parent clk + * @flags: framework-specific flags for this clock + * @reg: register address to control gating of this clock + * @bit_idx: which bit in the register controls gating of this clock + * @clk_gate_flags: gate-specific flags for this clock + * @lock: shared register lock for this clock + */ +#define devm_clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, \ + reg, bit_idx, clk_gate_flags, \ + lock) \ + __devm_clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \ + NULL, (flags), (reg), (bit_idx), \ + (clk_gate_flags), (lock)) /** * devm_clk_hw_register_gate_parent_data - register a gate clock with the * clock framework From patchwork Fri Jan 24 09:00:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949134 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D975C0218B for ; Fri, 24 Jan 2025 09:01:01 +0000 (UTC) Received: from mail-ed1-f51.google.com (mail-ed1-f51.google.com [209.85.208.51]) by mx.groups.io with SMTP id smtpd.web10.7447.1737709251853211047 for ; Fri, 24 Jan 2025 01:00:52 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=hwfkHA5l; spf=pass (domain: tuxon.dev, ip: 209.85.208.51, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ed1-f51.google.com with SMTP id 4fb4d7f45d1cf-5da12292b67so3099030a12.3 for ; Fri, 24 Jan 2025 01:00:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709250; x=1738314050; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1WUbikmmdFs6DqjBocKLpWYwpo+iLOaUCsX5Gpawot4=; b=hwfkHA5lae0z6BR4pcCIMUGR9EdXKVsPbCrE9VYQo8bjNC2uDC+Uk1LzwMYbhS+Hpe hSEYSRqRKBYJovfu4+tqks8zpW4XkmQFC4h9ZyDiVh66Zgpgztd53bdecoQPczHK8M84 puPj2jchgSu4DaLYJVKfJd/sbUqx41LpZpFQ7Gn20yBUs2fEssxOVHgvJED/2y+t5V93 EmnKbLo557mIoiChXWn2XOK9e5FY0LbkrS1t9FDLvQ5ATFGRjIjnbyj+pIXgY47VODWK K1+rKHWoxKnpnu0MNfqV9memqsGCIihcGY6q0OrTx0kE7I8tOi2vAEzy3ZDRAjQTL9aL Zh7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709250; x=1738314050; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1WUbikmmdFs6DqjBocKLpWYwpo+iLOaUCsX5Gpawot4=; b=FiNsdDjXHCnx8cpF73wGzJHGy6uNXsJRbazw8Aq2+ey7hMB3Dso7mDEQNu6IY3wWmF vJvb/t2fFPT15W1rhxXAXpYvrSukvz+cL+HFbeL5LMOzxdJsqApCbjr8b0ci+IvdKzdb tY4mh1OE+Y5qBqll6M7Ews2U/A45oqKKzLXZq0h4g90S/NHddce0TsZB186H3YSdgejo WyZgdyO14T+162bXqAfVd434E20rqBirsgYDaoHUHZrIPRArVh+YepV2HrlU5iwknIdC iJ8SaSTY4/emP4wGeET6C7bTtJM6H/pf70MyCE6o036jwTFliGTIgeFQpO8Aspy0y9JJ nBgg== X-Forwarded-Encrypted: i=1; AJvYcCUaWvutj7Dq8IsQDL729uUA61JLDUH32FVUPlBmTjmDMHSbJUlGkDJoZ5I/VV01ALZhZqPTBpMK@lists.cip-project.org X-Gm-Message-State: AOJu0YwbdLYzeD7qiZHQqDrflg1laNWygXaSI3jTrvgnM+bX1oARwmK8 ifzyZQhLtlUyrl8fmI2J3qOJ63GTMoKfHzaMqVuJT/mSoaY7dir58klTYFooa62nID/KOKI+FTP D X-Gm-Gg: ASbGnctmcP1zzpmiEqkrPZZnAhCQN/RBuKzpmXpQbtOUAxgYQzKQiA7H2BA+AMJonBZ eCaO67JRrC5lhAczLOHS1gVqM8PoO3r429a3iNM+rQgZLVrL/sgIaEReiRLRMU12oUeGdfjz+Rh H4f2kdrnz7csO8xVu+2io1MfVpXEj31BLTRbmuOuUwCmWf6LliCMOU5KQ+UCAx3FW/BVF5wWqY6 Zx16TjnS7Swx2q/L6xqTpFTrIssYwWuOkatNoCyIlioBzaYlk5dcdNyrSA8QMwgPfrqRY1YMVj+ 0SCMz63xtWDDRaRUfZNOfZy5qXEHvHAVUQ== X-Google-Smtp-Source: AGHT+IFivPr5/JAwE1TYS6xdPNkEMCkNmIqZroOjx2ZZD9UeGcHzvaXt1hCaRM1b0pFtWtVigev0Pw== X-Received: by 2002:a05:6402:524b:b0:5d0:9054:b119 with SMTP id 4fb4d7f45d1cf-5db7db07787mr63196152a12.21.1737709250169; Fri, 24 Jan 2025 01:00:50 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab6760fbce4sm92200766b.127.2025.01.24.01.00.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:49 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip v2 05/16] clk: mux: Introduce devm_clk_hw_register_mux_parent_hws() Date: Fri, 24 Jan 2025 11:00:30 +0200 Message-ID: <20250124090041.1401132-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:01:01 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17642 From: Marijn Suijten commit df63af17f3375239e0be124844f304b4a4b60665 upstream. Add the devres variant of clk_hw_register_mux_hws() for registering a mux clock with clk_hw parent pointers instead of parent names. Signed-off-by: Marijn Suijten Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220629225331.357308-3-marijn.suijten@somainline.org Signed-off-by: Stephen Boyd Reviewed-by: Pavel Machek Signed-off-by: Claudiu Beznea --- include/linux/clk-provider.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 9f34b4268e6a..50eaf1946009 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -988,6 +988,13 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name, (parent_names), NULL, NULL, (flags), (reg), \ (shift), BIT((width)) - 1, (clk_mux_flags), \ NULL, (lock)) +#define devm_clk_hw_register_mux_parent_hws(dev, name, parent_hws, \ + num_parents, flags, reg, shift, \ + width, clk_mux_flags, lock) \ + __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ + (parent_hws), NULL, (flags), (reg), \ + (shift), BIT((width)) - 1, \ + (clk_mux_flags), NULL, (lock)) int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, unsigned int val); From patchwork Fri Jan 24 09:00:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949136 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B5F2C02191 for ; Fri, 24 Jan 2025 09:01:01 +0000 (UTC) Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) by mx.groups.io with SMTP id smtpd.web11.7443.1737709253240763094 for ; Fri, 24 Jan 2025 01:00:53 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=Q7zlwg95; spf=pass (domain: tuxon.dev, ip: 209.85.218.41, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f41.google.com with SMTP id a640c23a62f3a-aaeec07b705so365319966b.2 for ; Fri, 24 Jan 2025 01:00:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709252; x=1738314052; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kfz5U+16lj5ldQgxOF+0aFhyP67gyfkoyTfLfOK2g1s=; b=Q7zlwg95OVwNmFR9lozWbxDM2FF1LIkbHg6Hp5w+BEUTQnD/HzSvz4OJyf9C+BcrLg VWg/pLQgkjeVVHNcLj93em+rvukV/HpA1yVo3TZZohuCXRRpBbY8clV4gFrgb55jQUdI Lrrv3NYJmK+sQQVvP/fCDIW6qW0xtId93691CSV49MkRih7aU1kLPWGpkCNMkr28S+pa u9g7aATZijgojOpsJFOEwbIbWvA2ks5mXjGyhcf46YNj11RkFBWr1Z26zS4nwjSn3QmA Wy6ZNGeaq5E3nQwtx7IbRYM/9w3dT8vnUESIOtHYXr+x4xYWPtLOKEceJr6mA2oVegPc sbMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709252; x=1738314052; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kfz5U+16lj5ldQgxOF+0aFhyP67gyfkoyTfLfOK2g1s=; b=P2nYeqrzHnZBJf/R7iVFcIOno2hrjqsiKx++nINZZTNqgYDJFiSxN8InJQmxnMNf7w yfxMrTjzCseZ6iC/p8HHLjxcmKfwKmWbcr2pna6lKPjA5N+R0WwHGWEW3G5KRZNZfjFW hykwSXrkZTguB2plitPXMlUy3BXYqdCxoC79PtAzHFHLYzE4vZs9Ig6HoHWIkxWXLfTo LJxhfPLY5JTY81+5I5JviooYoVckX6fzA4Us2rStXLSX9TvOfHiMsCKr+HvR9LscNj/p S2a5jcriLQ2fSplcqm+8IF2iAcwWzyF1liEB7TDNs0RSe6mYeVs8Yn82J8B810Sn4Eet rnRg== X-Forwarded-Encrypted: i=1; AJvYcCUWqocs3qbGEwhf0+z5CS5b3c3InbpzXQOVtjIzE6CzVlt0G9RTGF3dEV4wYkf1QPcCejPtP4RL@lists.cip-project.org X-Gm-Message-State: AOJu0YwjYc+j1q4ka74KsJwlyjrddg8iX8roAr2ABFXpScYvIbwltqCO IO4EARTKvstNhnQTSQBYW5Sex5AovhSwkC5R8cFHHYig0DVPafle+GL6AEmeDoc= X-Gm-Gg: ASbGnctKhu/Lp+1Ye3G1ibUWvn4q8JEF+jU1hJARdCAYGUgHhpf8LJwRuFSP34srNrk S4JqZ4z7oeZqPjJnUofDb8mS1rpuyNFIVRRpXBxl9HZwE+JqjM62GQKJZlKi/BpB69Tn2Rg+l/Q 6izxT0ePtritaxC+jDp/hdoh5YmXCgJu5CfeJaA6emSZ0f5fRQboNw3GobX1LpGB+SppFzWWFl+ jzgtl5CfJ1xarWvhzQfTKvGlM62EpZF5j2TRQFGozoSrwsvgIXFtPozNrtiqn9ZU8qjWaGiszTt 7z1zMDDqQjlzCF4DZt3hIqMRvktye06I8A== X-Google-Smtp-Source: AGHT+IHRyWX+HllDM1aJl4/l3vTce9TdaM96KogkBiUoDcLHjRytaOCJBZNl4q8JusQPPKhG5z/cpA== X-Received: by 2002:a17:906:4783:b0:aa6:3f93:fb99 with SMTP id a640c23a62f3a-ab38b3841e5mr2973081566b.36.1737709251579; Fri, 24 Jan 2025 01:00:51 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab6760fbce4sm92200766b.127.2025.01.24.01.00.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:50 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip v2 06/16] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB Date: Fri, 24 Jan 2025 11:00:31 +0200 Message-ID: <20250124090041.1401132-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:01:01 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17643 From: Claudiu Beznea commit cdfd5daf90af8363fb1f58e08c829a775b2e2fc5 upstream. The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC, the tamper detector and a small general usage memory of 128B. The VBATTB controller controls the clock for the RTC on the Renesas RZ/G3S. The HW block diagram for the clock logic is as follows: +----------+ XC `\ RTXIN --->| |----->| \ +----+ VBATTCLK | 32K clock| | |----->|gate|-----------> | osc | XBYP | | +----+ RTXOUT --->| |----->| / +----------+ ,/ One could connect as input to this HW block either a crystal or an external clock device. This is board specific. After discussions w/ Stephen Boyd the clock tree associated with this hardware block was exported in Linux as: input-xtal xbyp xc mux vbattclk where: - input-xtal is the input clock (connected to RTXIN, RTXOUT pins) - xc, xbyp are mux inputs - mux is the internal mux - vbattclk is the gate clock that feeds in the end the RTC to allow selecting the input of the MUX though assigned-clock DT properties, using the already existing clock drivers and avoid adding other DT properties. This allows select the input of the mux based on the type of the connected input clock: - if the 32768 crystal is connected as input for the VBATTB, the input of the mux should be xc - if an external clock device is connected as input for the VBATTB the input of the mux should be xbyp Add bindings for the VBATTB controller. Reviewed-by: Geert Uytterhoeven Reviewed-by: Krzysztof Kozlowski Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Reviewed-by: Pavel Machek Signed-off-by: Claudiu Beznea --- .../clock/renesas,r9a08g045-vbattb.yaml | 84 +++++++++++++++++++ .../clock/renesas,r9a08g045-vbattb.h | 13 +++ 2 files changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml create mode 100644 include/dt-bindings/clock/renesas,r9a08g045-vbattb.h diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml new file mode 100644 index 000000000000..3707e4118949 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Battery Backup Function (VBATTB) + +description: + Renesas VBATTB is an always on powered module (backed by battery) which + controls the RTC clock (VBATTCLK), tamper detection logic and a small + general usage memory (128B). + +maintainers: + - Claudiu Beznea + +properties: + compatible: + const: renesas,r9a08g045-vbattb + + reg: + maxItems: 1 + + interrupts: + items: + - description: tamper detector interrupt + + clocks: + items: + - description: VBATTB module clock + - description: RTC input clock (crystal or external clock device) + + clock-names: + items: + - const: bclk + - const: rtx + + '#clock-cells': + const: 1 + + power-domains: + maxItems: 1 + + resets: + items: + - description: VBATTB module reset + + quartz-load-femtofarads: + description: load capacitance of the on board crystal + enum: [ 4000, 7000, 9000, 12500 ] + default: 4000 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - '#clock-cells' + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + clock-controller@1005c000 { + compatible = "renesas,r9a08g045-vbattb"; + reg = <0x1005c000 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; + clock-names = "bclk", "rtx"; + assigned-clocks = <&vbattb VBATTB_MUX>; + assigned-clock-parents = <&vbattb VBATTB_XC>; + #clock-cells = <1>; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + quartz-load-femtofarads = <12500>; + }; diff --git a/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h new file mode 100644 index 000000000000..67774eafad06 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ +#define __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ + +#define VBATTB_XC 0 +#define VBATTB_XBYP 1 +#define VBATTB_MUX 2 +#define VBATTB_VBATTCLK 3 + +#endif /* __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ */ From patchwork Fri Jan 24 09:00:32 2025 Content-Type: text/plain; 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([82.78.167.35]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab6760fbce4sm92200766b.127.2025.01.24.01.00.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:52 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip v2 07/16] clk: renesas: vbattb: Add VBATTB clock driver Date: Fri, 24 Jan 2025 11:00:32 +0200 Message-ID: <20250124090041.1401132-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:01:01 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17644 From: Claudiu Beznea commit be20a73e03e19005cfa5c1c4d6158af1ba02f056 upstream. The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used by the RTC. The input to the VBATTB could be a 32KHz crystal or an external clock device. The HW block diagram for the clock generator is as follows: +----------+ XC `\ RTXIN --->| |----->| \ +----+ VBATTCLK | 32K clock| | |----->|gate|-----------> | osc | XBYP | | +----+ RTXOUT --->| |----->| / +----------+ , After discussions w/ Stephen Boyd the clock tree associated with this hardware block was exported in Linux as: vbattb-xtal xbyp xc mux vbattbclk where: - input-xtal is the input clock (connected to RTXIN, RTXOUT pins) - xc, xbyp are mux inputs - mux is the internal mux - vbattclk is the gate clock that feeds in the end the RTC to allow selecting the input of the MUX though assigned-clock DT properties, using the already existing clock drivers and avoid adding other DT properties. If the crystal is connected on RTXIN, RTXOUT pins the XC will be selected as mux input. If an external clock device is connected on RTXIN, RTXOUT pins the XBYP will be selected as mux input. The load capacitance of the internal crystal can be configured with renesas,vbattb-load-nanofarads DT property. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Reviewed-by: Pavel Machek [claudiu.beznea: dropped cleanup.h helpers, include to fix compilation errors] Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/Kconfig | 5 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/clk-vbattb.c | 204 +++++++++++++++++++++++++++++++ 3 files changed, 210 insertions(+) create mode 100644 drivers/clk/renesas/clk-vbattb.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 8e03eab59115..de7db5fa07de 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -206,6 +206,11 @@ config CLK_RZG2L bool "Renesas RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST select RESET_CONTROLLER +config CLK_RENESAS_VBATTB + tristate "Renesas VBATTB clock controller" + depends on ARCH_RZG2L || COMPILE_TEST + select RESET_CONTROLLER + # Generic config CLK_RENESAS_CPG_MSSR bool "CPG/MSSR clock support" if COMPILE_TEST diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 34815dd77f58..f40b8233eac5 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -46,3 +46,4 @@ obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o obj-$(CONFIG_CLK_RENESAS_CPG_MSTP) += clk-mstp.o obj-$(CONFIG_CLK_RENESAS_DIV6) += clk-div6.o +obj-$(CONFIG_CLK_RENESAS_VBATTB) += clk-vbattb.o diff --git a/drivers/clk/renesas/clk-vbattb.c b/drivers/clk/renesas/clk-vbattb.c new file mode 100644 index 000000000000..a5f9b736ef2c --- /dev/null +++ b/drivers/clk/renesas/clk-vbattb.c @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * VBATTB clock driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define VBATTB_BKSCCR 0x1c +#define VBATTB_BKSCCR_SOSEL 6 +#define VBATTB_SOSCCR2 0x24 +#define VBATTB_SOSCCR2_SOSTP2 0 +#define VBATTB_XOSCCR 0x30 +#define VBATTB_XOSCCR_OUTEN 16 +#define VBATTB_XOSCCR_XSEL GENMASK(1, 0) +#define VBATTB_XOSCCR_XSEL_4_PF 0x0 +#define VBATTB_XOSCCR_XSEL_7_PF 0x1 +#define VBATTB_XOSCCR_XSEL_9_PF 0x2 +#define VBATTB_XOSCCR_XSEL_12_5_PF 0x3 + +/** + * struct vbattb_clk - VBATTB clock data structure + * @base: base address + * @lock: lock + */ +struct vbattb_clk { + void __iomem *base; + spinlock_t lock; +}; + +static int vbattb_clk_validate_load_capacitance(u32 *reg_lc, u32 of_lc) +{ + switch (of_lc) { + case 4000: + *reg_lc = VBATTB_XOSCCR_XSEL_4_PF; + break; + case 7000: + *reg_lc = VBATTB_XOSCCR_XSEL_7_PF; + break; + case 9000: + *reg_lc = VBATTB_XOSCCR_XSEL_9_PF; + break; + case 12500: + *reg_lc = VBATTB_XOSCCR_XSEL_12_5_PF; + break; + default: + return -EINVAL; + } + + return 0; +} + +static void vbattb_clk_action(void *data) +{ + struct device *dev = data; + struct reset_control *rstc = dev_get_drvdata(dev); + int ret; + + ret = reset_control_assert(rstc); + if (ret) + dev_err(dev, "Failed to de-assert reset!"); + + ret = pm_runtime_put_sync(dev); + if (ret < 0) + dev_err(dev, "Failed to runtime suspend!"); + + of_clk_del_provider(dev->of_node); +} + +static int vbattb_clk_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct clk_parent_data parent_data = {}; + struct clk_hw_onecell_data *clk_data; + const struct clk_hw *parent_hws[2]; + struct device *dev = &pdev->dev; + struct reset_control *rstc; + struct vbattb_clk *vbclk; + u32 of_lc, reg_lc, val; + struct clk_hw *hw; + /* 4 clocks are exported: VBATTB_XC, VBATTB_XBYP, VBATTB_MUX, VBATTB_VBATTCLK. */ + u8 num_clks = 4; + int ret; + + /* Default to 4pF as this is not needed if external clock device is connected. */ + of_lc = 4000; + of_property_read_u32(np, "quartz-load-femtofarads", &of_lc); + + ret = vbattb_clk_validate_load_capacitance(®_lc, of_lc); + if (ret) + return ret; + + vbclk = devm_kzalloc(dev, sizeof(*vbclk), GFP_KERNEL); + if (!vbclk) + return -ENOMEM; + + clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, num_clks), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + clk_data->num = num_clks; + + vbclk->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(vbclk->base)) + return PTR_ERR(vbclk->base); + + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; + + rstc = devm_reset_control_get_shared(dev, NULL); + if (IS_ERR(rstc)) + return PTR_ERR(rstc); + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + ret = reset_control_deassert(rstc); + if (ret) { + pm_runtime_put_sync(dev); + return ret; + } + + dev_set_drvdata(dev, rstc); + ret = devm_add_action_or_reset(dev, vbattb_clk_action, dev); + if (ret) + return ret; + + spin_lock_init(&vbclk->lock); + + parent_data.fw_name = "rtx"; + hw = devm_clk_hw_register_gate_parent_data(dev, "xc", &parent_data, 0, + vbclk->base + VBATTB_SOSCCR2, + VBATTB_SOSCCR2_SOSTP2, + CLK_GATE_SET_TO_DISABLE, &vbclk->lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_XC] = hw; + + hw = devm_clk_hw_register_fixed_factor_fwname(dev, np, "xbyp", "rtx", 0, 1, 1); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_XBYP] = hw; + + parent_hws[0] = clk_data->hws[VBATTB_XC]; + parent_hws[1] = clk_data->hws[VBATTB_XBYP]; + hw = devm_clk_hw_register_mux_parent_hws(dev, "mux", parent_hws, 2, 0, + vbclk->base + VBATTB_BKSCCR, + VBATTB_BKSCCR_SOSEL, + 1, 0, &vbclk->lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_MUX] = hw; + + /* Set load capacitance before registering the VBATTCLK clock. */ + spin_lock(&vbclk->lock); + val = readl_relaxed(vbclk->base + VBATTB_XOSCCR); + val &= ~VBATTB_XOSCCR_XSEL; + val |= reg_lc; + writel_relaxed(val, vbclk->base + VBATTB_XOSCCR); + spin_unlock(&vbclk->lock); + + /* This feeds the RTC counter clock and it needs to stay on. */ + hw = devm_clk_hw_register_gate_parent_hw(dev, "vbattclk", hw, CLK_IS_CRITICAL, + vbclk->base + VBATTB_XOSCCR, + VBATTB_XOSCCR_OUTEN, 0, + &vbclk->lock); + + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_VBATTCLK] = hw; + + return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); +} + +static const struct of_device_id vbattb_clk_match[] = { + { .compatible = "renesas,r9a08g045-vbattb" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, vbattb_clk_match); + +static struct platform_driver vbattb_clk_driver = { + .driver = { + .name = "renesas-vbattb-clk", + .of_match_table = vbattb_clk_match, + }, + .probe = vbattb_clk_probe, +}; +module_platform_driver(vbattb_clk_driver); + +MODULE_DESCRIPTION("Renesas VBATTB Clock Driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); From patchwork Fri Jan 24 09:00:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949135 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8040BC0218D for ; Fri, 24 Jan 2025 09:01:01 +0000 (UTC) Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) by mx.groups.io with SMTP id smtpd.web10.7451.1737709256218906779 for ; Fri, 24 Jan 2025 01:00:56 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=He/ULYp8; spf=pass (domain: tuxon.dev, ip: 209.85.128.47, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-436341f575fso19245845e9.1 for ; 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([82.78.167.35]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab6760fbce4sm92200766b.127.2025.01.24.01.00.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:53 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip v2 08/16] clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP Date: Fri, 24 Jan 2025 11:00:33 +0200 Message-ID: <20250124090041.1401132-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:01:01 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17645 From: Claudiu Beznea commit c8bd9bd6446fa034a1877b553bf118606b37c025 upstream. The Renesas RZ/G3S SoC has an IP named Battery Backup Function (VBATTB) that generates the RTC clock. Add clock, reset and power domain support for it. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240614071932.1014067-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Reviewed-by: Pavel Machek [claudiu.beznea: dropped PM domain part as it is not ready yet] Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/r9a08g045-cpg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index c3e6da2de197..55e7d42dc472 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -215,6 +215,7 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9), DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0), DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0), + DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0), }; static const struct rzg2l_reset r9a08g045_resets[] = { @@ -231,6 +232,7 @@ static const struct rzg2l_reset r9a08g045_resets[] = { DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0), DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1), DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2), + DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0), }; static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { @@ -238,6 +240,7 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { MOD_CLK_BASE + R9A08G045_IA55_PCLK, MOD_CLK_BASE + R9A08G045_IA55_CLK, MOD_CLK_BASE + R9A08G045_DMAC_ACLK, + MOD_CLK_BASE + R9A08G045_VBAT_BCLK, }; const struct rzg2l_cpg_info r9a08g045_cpg_info = { From patchwork Fri Jan 24 09:00:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949133 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C958C0218C for ; Fri, 24 Jan 2025 09:01:01 +0000 (UTC) Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) by mx.groups.io with SMTP id smtpd.web10.7453.1737709257970896227 for ; Fri, 24 Jan 2025 01:00:58 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=nbA73IqC; spf=pass (domain: tuxon.dev, ip: 209.85.218.50, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f50.google.com with SMTP id a640c23a62f3a-aaf900cc7fbso302035566b.3 for ; Fri, 24 Jan 2025 01:00:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709256; x=1738314056; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QnLNZZyiCZVevgpKmltWagN5En4nuc4DObaUHjCsGpI=; b=nbA73IqC7g7+BHEKCjV7EUTJgnB1g9MrPNTFLPapiAk54Ut3cuqpMh/CH2xc1tsJDP vNihifB3aEtLcXpCaZrf4+tm7/Uq7LLVYxe8xl14MIjUBe/TiH4JgB8xr9mX6vsISQZF 6OQC3yK02jczxdJB0HPem6qVTOuk73d2taKfPFGu2cGpDYzOSCDnQg2jFG3dpRq8eCdS nRSaBEpOlkZPRO9WOjhm9NABBGetUR+sP25fOPFztBUGl7xX+VisfffDeol/cHPlkhq4 lmgX4YppRSrPOsg0Dg2+v1TV2wxIgSfAW/YenLCbYycyYOujb9G0cC2OHaXBbcH+2rnK nabQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709256; x=1738314056; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QnLNZZyiCZVevgpKmltWagN5En4nuc4DObaUHjCsGpI=; b=WoUUIT9N0j1t8Cztax4fTOQq5nb3n6+SUeiSCDYIHQktIXUOQ3wQnYZ8ugrDmOPqMs N5JY5mg1SZivRFHdjuYvQQRRNSpHh2NSXUrza/SYTxRlD5XHJhIMRP0UC8Ef27GVAP9C kK4W27mcEaKqmey5qqYb9TsSQkfEXLLSI5wPQGuACUGrQiQAbEjEYZr+AQy50BejMeD0 Fjl6azrv/WXi0wyIA4/2zls5ZltiARlyOLYMsSsllcLDVlzZBDpxd8aNiq4cvx4wnGd2 T5GIozww2vwlqB1Ip7CxstJGlr/2hSe8PFe29dbmdDVB60/MG8Ar4Nz8QsetC3rq8jEX PmzQ== X-Forwarded-Encrypted: i=1; AJvYcCVHK26UE/6seoWVsa2+QvrytL3/tVR5NPH/YLRH2NE6PktBj7uafObyOpogLuip+rpXngiRcd8N@lists.cip-project.org X-Gm-Message-State: AOJu0YzJGCJ4cP11Ll2mvMJFBd8PgyEHe3BnngXUEao4BI/YhLsPXbKd FgZP1Opw+A/GRMzywvp+ozrPFrcLofszvLGAMZ3AQ4CfKJ1Qz48P1HZopKLKBzETkp5DJia3OES p X-Gm-Gg: ASbGncu4rIW0qDEd1Vs1ZcZEVtxsPLBOR4wQBpqxTSBs5+HWyJsBodLtA7ge5bYml+a WG/Nme2NC1wDCOt5oeyy9NdhLvqU5wDrUBSnmJlCinjT5xwKG6e394oyBvzA9KixnAJzd8ez7F4 0Hr8BGNIG+RLaUSFGJE3G5L6+HNG5u3E1gUMFFFmjTvezOHvx72lmEWzY5MGNe2weXXIMFph9cR ikHDRcDkkCLZo3lCIuqN+yjGwUKw7XbzKKAMzbiMzF0d5TKxv7jRgi5fWnYzDUGzAw16F/ZjPlV BUC9JEyoAdq/xlIrXqLd+wY3XbHLKndHsw== X-Google-Smtp-Source: AGHT+IHVF5+2WhU0bbzyU34FGGntN43s/FvyoB6sJgqCvK3QNewgdAl5qk/lPg60SCQTEyy6hlnDiw== X-Received: by 2002:a17:906:7956:b0:aac:2128:c89e with SMTP id a640c23a62f3a-ab38b3852abmr2609888066b.43.1737709256335; Fri, 24 Jan 2025 01:00:56 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab6760fbce4sm92200766b.127.2025.01.24.01.00.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:55 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip v2 09/16] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RTCA-3 IP Date: Fri, 24 Jan 2025 11:00:34 +0200 Message-ID: <20250124090041.1401132-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:01:01 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17646 From: Claudiu Beznea commit 71c61a45c951eca67dd2cbc4de9cdd687ece4ead upstream. Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC. The RTC IP available on Renesas RZ/V2H is almost identical with the one found on Renesas RZ/G3S (it misses the time capture functionality which is not yet implemented on proposed driver). For this, added also a generic compatible that will be used at the moment as fallback for both RZ/G3S and RZ/V2H. Reviewed-by: Rob Herring (Arm) Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20241030110120.332802-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Alexandre Belloni Reviewed-by: Pavel Machek Signed-off-by: Claudiu Beznea --- .../bindings/rtc/renesas,rz-rtca3.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml diff --git a/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml new file mode 100644 index 000000000000..e70eeb66aa64 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/renesas,rz-rtca3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RTCA-3 Real Time Clock + +maintainers: + - Claudiu Beznea + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + items: + - enum: + - renesas,r9a08g045-rtca3 # RZ/G3S + - const: renesas,rz-rtca3 + + reg: + maxItems: 1 + + interrupts: + items: + - description: Alarm interrupt + - description: Periodic interrupt + - description: Carry interrupt + + interrupt-names: + items: + - const: alarm + - const: period + - const: carry + + clocks: + items: + - description: RTC bus clock + - description: RTC counter clock + + clock-names: + items: + - const: bus + - const: counter + + power-domains: + maxItems: 1 + + resets: + items: + - description: VBATTB module reset + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + rtc@1004ec00 { + compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; + reg = <0x1004ec00 0x400>; + interrupts = , + , + ; + interrupt-names = "alarm", "period", "carry"; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattclk VBATTB_VBATTCLK>; + clock-names = "bus", "counter"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + }; From patchwork Fri Jan 24 09:00:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949138 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91E8BC0218E for ; Fri, 24 Jan 2025 09:01:01 +0000 (UTC) Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) by mx.groups.io with SMTP id smtpd.web10.7454.1737709259596345555 for ; Fri, 24 Jan 2025 01:01:00 -0800 Authentication-Results: mx.groups.io; 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([82.78.167.35]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab6760fbce4sm92200766b.127.2025.01.24.01.00.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:56 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip v2 10/16] rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S SoC Date: Fri, 24 Jan 2025 11:00:35 +0200 Message-ID: <20250124090041.1401132-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:01:01 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17647 From: Claudiu Beznea commit d4488377609e36cd9785533c29ccea4b86c292b9 upstream. The RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC has calendar count mode and binary count mode (selectable though RCR2.CNTMD) capabilities, alarm capabilities, clock error correction capabilities. It can generate alarm, period, carry interrupts. Add a driver for RTCA-3 IP. The driver implements calendar count mode (as the conversion b/w RTC and system time is simpler, done with bcd2bin(), bin2bcd()), read and set time, read and set alarm, read and set an offset. Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20241030110120.332802-6-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Alexandre Belloni Reviewed-by: Pavel Machek [claudiu.beznea: - fixed conflicts - dropped cleanup.h helpers - fix "loop initial declarations are only allowed in C99 or C11 mode" compilation error - use rtc_register_device() instead of devres helper for registration and dropped the driver's remove with it - use SIMPLE_DEV_PM_OPS() - include ] Signed-off-by: Claudiu Beznea --- MAINTAINERS | 8 + drivers/rtc/Kconfig | 10 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-renesas-rtca3.c | 922 ++++++++++++++++++++++++++++++++ 4 files changed, 941 insertions(+) create mode 100644 drivers/rtc/rtc-renesas-rtca3.c diff --git a/MAINTAINERS b/MAINTAINERS index 4e2d9ed016ab..bb6f787ea461 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14945,6 +14945,14 @@ S: Supported F: Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml F: drivers/iio/adc/rzg2l_adc.c +RENESAS RTCA-3 RTC DRIVER +M: Claudiu Beznea +L: linux-rtc@vger.kernel.org +L: linux-renesas-soc@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml +F: drivers/rtc/rtc-renesas-rtca3.c + RESET CONTROLLER FRAMEWORK M: Philipp Zabel S: Maintained diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 8ddd334e049e..6b876bad9143 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1921,6 +1921,16 @@ config RTC_DRV_ASPEED This driver can also be built as a module, if so, the module will be called "rtc-aspeed". +config RTC_DRV_RENESAS_RTCA3 + tristate "Renesas RTCA-3 RTC" + depends on ARCH_RENESAS + help + If you say yes here you get support for the Renesas RTCA-3 RTC + available on the Renesas RZ/G3S SoC. + + This driver can also be built as a module, if so, the module + will be called "rtc-rtca3". + comment "HID Sensor RTC drivers" config RTC_DRV_HID_SENSOR_TIME diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index bfb57464118d..e17d71c129ad 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -148,6 +148,7 @@ obj-$(CONFIG_RTC_DRV_RX6110) += rtc-rx6110.o obj-$(CONFIG_RTC_DRV_RX8010) += rtc-rx8010.o obj-$(CONFIG_RTC_DRV_RX8025) += rtc-rx8025.o obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o +obj-$(CONFIG_RTC_DRV_RENESAS_RTCA3) += rtc-renesas-rtca3.o obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o obj-$(CONFIG_RTC_DRV_S3C) += rtc-s3c.o obj-$(CONFIG_RTC_DRV_S5M) += rtc-s5m.o diff --git a/drivers/rtc/rtc-renesas-rtca3.c b/drivers/rtc/rtc-renesas-rtca3.c new file mode 100644 index 000000000000..5a8dd2ad6b60 --- /dev/null +++ b/drivers/rtc/rtc-renesas-rtca3.c @@ -0,0 +1,922 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * On-Chip RTC Support available on RZ/G3S SoC + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Counter registers. */ +#define RTCA3_RSECCNT 0x2 +#define RTCA3_RSECCNT_SEC GENMASK(6, 0) +#define RTCA3_RMINCNT 0x4 +#define RTCA3_RMINCNT_MIN GENMASK(6, 0) +#define RTCA3_RHRCNT 0x6 +#define RTCA3_RHRCNT_HR GENMASK(5, 0) +#define RTCA3_RHRCNT_PM BIT(6) +#define RTCA3_RWKCNT 0x8 +#define RTCA3_RWKCNT_WK GENMASK(2, 0) +#define RTCA3_RDAYCNT 0xa +#define RTCA3_RDAYCNT_DAY GENMASK(5, 0) +#define RTCA3_RMONCNT 0xc +#define RTCA3_RMONCNT_MONTH GENMASK(4, 0) +#define RTCA3_RYRCNT 0xe +#define RTCA3_RYRCNT_YEAR GENMASK(7, 0) + +/* Alarm registers. */ +#define RTCA3_RSECAR 0x10 +#define RTCA3_RSECAR_SEC GENMASK(6, 0) +#define RTCA3_RMINAR 0x12 +#define RTCA3_RMINAR_MIN GENMASK(6, 0) +#define RTCA3_RHRAR 0x14 +#define RTCA3_RHRAR_HR GENMASK(5, 0) +#define RTCA3_RHRAR_PM BIT(6) +#define RTCA3_RWKAR 0x16 +#define RTCA3_RWKAR_DAYW GENMASK(2, 0) +#define RTCA3_RDAYAR 0x18 +#define RTCA3_RDAYAR_DATE GENMASK(5, 0) +#define RTCA3_RMONAR 0x1a +#define RTCA3_RMONAR_MON GENMASK(4, 0) +#define RTCA3_RYRAR 0x1c +#define RTCA3_RYRAR_YR GENMASK(7, 0) +#define RTCA3_RYRAREN 0x1e + +/* Alarm enable bit (for all alarm registers). */ +#define RTCA3_AR_ENB BIT(7) + +/* Control registers. */ +#define RTCA3_RCR1 0x22 +#define RTCA3_RCR1_AIE BIT(0) +#define RTCA3_RCR1_CIE BIT(1) +#define RTCA3_RCR1_PIE BIT(2) +#define RTCA3_RCR1_PES GENMASK(7, 4) +#define RTCA3_RCR1_PES_1_64_SEC 0x8 +#define RTCA3_RCR2 0x24 +#define RTCA3_RCR2_START BIT(0) +#define RTCA3_RCR2_RESET BIT(1) +#define RTCA3_RCR2_AADJE BIT(4) +#define RTCA3_RCR2_ADJP BIT(5) +#define RTCA3_RCR2_HR24 BIT(6) +#define RTCA3_RCR2_CNTMD BIT(7) +#define RTCA3_RSR 0x20 +#define RTCA3_RSR_AF BIT(0) +#define RTCA3_RSR_CF BIT(1) +#define RTCA3_RSR_PF BIT(2) +#define RTCA3_RADJ 0x2e +#define RTCA3_RADJ_ADJ GENMASK(5, 0) +#define RTCA3_RADJ_ADJ_MAX 0x3f +#define RTCA3_RADJ_PMADJ GENMASK(7, 6) +#define RTCA3_RADJ_PMADJ_NONE 0 +#define RTCA3_RADJ_PMADJ_ADD 1 +#define RTCA3_RADJ_PMADJ_SUB 2 + +/* Polling operation timeouts. */ +#define RTCA3_DEFAULT_TIMEOUT_US 150 +#define RTCA3_IRQSET_TIMEOUT_US 5000 +#define RTCA3_START_TIMEOUT_US 150000 +#define RTCA3_RESET_TIMEOUT_US 200000 + +/** + * enum rtca3_alrm_set_step - RTCA3 alarm set steps + * @RTCA3_ALRM_SSTEP_DONE: alarm setup done step + * @RTCA3_ALRM_SSTEP_IRQ: two 1/64 periodic IRQs were generated step + * @RTCA3_ALRM_SSTEP_INIT: alarm setup initialization step + */ +enum rtca3_alrm_set_step { + RTCA3_ALRM_SSTEP_DONE = 0, + RTCA3_ALRM_SSTEP_IRQ = 1, + RTCA3_ALRM_SSTEP_INIT = 3, +}; + +/** + * struct rtca3_ppb_per_cycle - PPB per cycle + * @ten_sec: PPB per cycle in 10 seconds adjutment mode + * @sixty_sec: PPB per cycle in 60 seconds adjustment mode + */ +struct rtca3_ppb_per_cycle { + int ten_sec; + int sixty_sec; +}; + +/** + * struct rtca3_priv - RTCA3 private data structure + * @base: base address + * @rtc_dev: RTC device + * @rstc: reset control + * @set_alarm_completion: alarm setup completion + * @alrm_sstep: alarm setup step (see enum rtca3_alrm_set_step) + * @lock: device lock + * @ppb: ppb per cycle for each the available adjustment modes + * @wakeup_irq: wakeup IRQ + */ +struct rtca3_priv { + void __iomem *base; + struct rtc_device *rtc_dev; + struct reset_control *rstc; + struct completion set_alarm_completion; + atomic_t alrm_sstep; + spinlock_t lock; + struct rtca3_ppb_per_cycle ppb; + int wakeup_irq; +}; + +static void rtca3_byte_update_bits(struct rtca3_priv *priv, u8 off, u8 mask, u8 val) +{ + u8 tmp; + + tmp = readb(priv->base + off); + tmp &= ~mask; + tmp |= (val & mask); + writeb(tmp, priv->base + off); +} + +static u8 rtca3_alarm_handler_helper(struct rtca3_priv *priv) +{ + u8 val, pending; + + val = readb(priv->base + RTCA3_RSR); + pending = val & RTCA3_RSR_AF; + writeb(val & ~pending, priv->base + RTCA3_RSR); + + if (pending) + rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF); + + return pending; +} + +static irqreturn_t rtca3_alarm_handler(int irq, void *dev_id) +{ + struct rtca3_priv *priv = dev_id; + u8 pending; + + spin_lock(&priv->lock); + pending = rtca3_alarm_handler_helper(priv); + spin_unlock(&priv->lock); + + return IRQ_RETVAL(pending); +} + +static irqreturn_t rtca3_periodic_handler(int irq, void *dev_id) +{ + struct rtca3_priv *priv = dev_id; + u8 val, pending; + + spin_lock(&priv->lock); + + val = readb(priv->base + RTCA3_RSR); + pending = val & RTCA3_RSR_PF; + + if (pending) { + writeb(val & ~pending, priv->base + RTCA3_RSR); + + if (atomic_read(&priv->alrm_sstep) > RTCA3_ALRM_SSTEP_IRQ) { + /* Alarm setup in progress. */ + atomic_dec(&priv->alrm_sstep); + + if (atomic_read(&priv->alrm_sstep) == RTCA3_ALRM_SSTEP_IRQ) { + /* + * We got 2 * 1/64 periodic interrupts. Disable + * interrupt and let alarm setup continue. + */ + rtca3_byte_update_bits(priv, RTCA3_RCR1, + RTCA3_RCR1_PIE, 0); + readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, val, + !(val & RTCA3_RCR1_PIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + complete(&priv->set_alarm_completion); + } + } + } + + spin_unlock(&priv->lock); + + return IRQ_RETVAL(pending); +} + +static void rtca3_prepare_cntalrm_regs_for_read(struct rtca3_priv *priv, bool cnt) +{ + /* Offset b/w time and alarm registers. */ + u8 offset = cnt ? 0 : 0xe; + u8 i; + + /* + * According to HW manual (section 22.6.4. Notes on writing to and + * reading from registers) after writing to count registers, alarm + * registers, year alarm enable register, bits RCR2.AADJE, AADJP, + * and HR24 register, we need to do 3 empty reads before being + * able to fetch the registers content. + */ + for (i = 0; i < 3; i++) { + readb(priv->base + RTCA3_RSECCNT + offset); + readb(priv->base + RTCA3_RMINCNT + offset); + readb(priv->base + RTCA3_RHRCNT + offset); + readb(priv->base + RTCA3_RWKCNT + offset); + readb(priv->base + RTCA3_RDAYCNT + offset); + readw(priv->base + RTCA3_RYRCNT + offset); + if (!cnt) + readb(priv->base + RTCA3_RYRAREN); + } +} + +static int rtca3_read_time(struct device *dev, struct rtc_time *tm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + u8 sec, min, hour, wday, mday, month, tmp; + unsigned long flags; + u8 trials = 0; + u32 year100; + int ret = 0; + u16 year; + + spin_lock_irqsave(&priv->lock, flags); + + tmp = readb(priv->base + RTCA3_RCR2); + if (!(tmp & RTCA3_RCR2_START)) { + ret = -EINVAL; + goto unlock; + } + + do { + /* Clear carry interrupt. */ + rtca3_byte_update_bits(priv, RTCA3_RSR, RTCA3_RSR_CF, 0); + + /* Read counters. */ + sec = readb(priv->base + RTCA3_RSECCNT); + min = readb(priv->base + RTCA3_RMINCNT); + hour = readb(priv->base + RTCA3_RHRCNT); + wday = readb(priv->base + RTCA3_RWKCNT); + mday = readb(priv->base + RTCA3_RDAYCNT); + month = readb(priv->base + RTCA3_RMONCNT); + year = readw(priv->base + RTCA3_RYRCNT); + + tmp = readb(priv->base + RTCA3_RSR); + + /* + * We cannot generate carries due to reading 64Hz counter as + * the driver doesn't implement carry, thus, carries will be + * generated once per seconds. Add a timeout of 5 trials here + * to avoid infinite loop, if any. + */ + } while ((tmp & RTCA3_RSR_CF) && ++trials < 5); + + if (trials >= 5) { + ret = -ETIMEDOUT; + goto unlock; + } + + tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECCNT_SEC, sec)); + tm->tm_min = bcd2bin(FIELD_GET(RTCA3_RMINCNT_MIN, min)); + tm->tm_hour = bcd2bin(FIELD_GET(RTCA3_RHRCNT_HR, hour)); + tm->tm_wday = bcd2bin(FIELD_GET(RTCA3_RWKCNT_WK, wday)); + tm->tm_mday = bcd2bin(FIELD_GET(RTCA3_RDAYCNT_DAY, mday)); + tm->tm_mon = bcd2bin(FIELD_GET(RTCA3_RMONCNT_MONTH, month)) - 1; + year = FIELD_GET(RTCA3_RYRCNT_YEAR, year); + year100 = bcd2bin((year == 0x99) ? 0x19 : 0x20); + tm->tm_year = (year100 * 100 + bcd2bin(year)) - 1900; + +unlock: + spin_unlock_irqrestore(&priv->lock, flags); + return ret; +} + +static int rtca3_set_time(struct device *dev, struct rtc_time *tm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + unsigned long flags; + u8 rcr2, tmp; + int ret; + + spin_lock_irqsave(&priv->lock, flags); + + /* Stop the RTC. */ + rcr2 = readb(priv->base + RTCA3_RCR2); + writeb(rcr2 & ~RTCA3_RCR2_START, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + !(tmp & RTCA3_RCR2_START), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + goto unlock; + + /* Update time. */ + writeb(bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECCNT); + writeb(bin2bcd(tm->tm_min), priv->base + RTCA3_RMINCNT); + writeb(bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRCNT); + writeb(bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKCNT); + writeb(bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYCNT); + writeb(bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONCNT); + writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRCNT); + + /* Make sure we can read back the counters. */ + rtca3_prepare_cntalrm_regs_for_read(priv, true); + + /* Start RTC. */ + writeb(rcr2 | RTCA3_RCR2_START, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + (tmp & RTCA3_RCR2_START), + 10, RTCA3_DEFAULT_TIMEOUT_US); +unlock: + spin_unlock_irqrestore(&priv->lock, flags); + return ret; +} + +static int rtca3_alarm_irq_set_helper(struct rtca3_priv *priv, + u8 interrupts, + unsigned int enabled) +{ + u8 tmp, val; + + if (enabled) { + /* + * AIE, CIE, PIE bit indexes in RSR corresponds with + * those on RCR1. Same interrupts mask can be used. + */ + rtca3_byte_update_bits(priv, RTCA3_RSR, interrupts, 0); + val = interrupts; + } else { + val = 0; + } + + rtca3_byte_update_bits(priv, RTCA3_RCR1, interrupts, val); + return readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + ((tmp & interrupts) == val), + 10, RTCA3_IRQSET_TIMEOUT_US); +} + +static int rtca3_alarm_irq_enable(struct device *dev, unsigned int enabled) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + unsigned long flags; + int ret; + + spin_lock_irqsave(&priv->lock, flags); + ret = rtca3_alarm_irq_set_helper(priv, RTCA3_RCR1_AIE, enabled); + spin_unlock_irqrestore(&priv->lock, flags); + + return ret; +} + +static int rtca3_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + u8 sec, min, hour, wday, mday, month; + struct rtc_time *tm = &wkalrm->time; + unsigned long flags; + u32 year100; + u16 year; + + spin_lock_irqsave(&priv->lock, flags); + + sec = readb(priv->base + RTCA3_RSECAR); + min = readb(priv->base + RTCA3_RMINAR); + hour = readb(priv->base + RTCA3_RHRAR); + wday = readb(priv->base + RTCA3_RWKAR); + mday = readb(priv->base + RTCA3_RDAYAR); + month = readb(priv->base + RTCA3_RMONAR); + year = readw(priv->base + RTCA3_RYRAR); + + tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECAR_SEC, sec)); + tm->tm_min = bcd2bin(FIELD_GET(RTCA3_RMINAR_MIN, min)); + tm->tm_hour = bcd2bin(FIELD_GET(RTCA3_RHRAR_HR, hour)); + tm->tm_wday = bcd2bin(FIELD_GET(RTCA3_RWKAR_DAYW, wday)); + tm->tm_mday = bcd2bin(FIELD_GET(RTCA3_RDAYAR_DATE, mday)); + tm->tm_mon = bcd2bin(FIELD_GET(RTCA3_RMONAR_MON, month)) - 1; + year = FIELD_GET(RTCA3_RYRAR_YR, year); + year100 = bcd2bin((year == 0x99) ? 0x19 : 0x20); + tm->tm_year = (year100 * 100 + bcd2bin(year)) - 1900; + + wkalrm->enabled = !!(readb(priv->base + RTCA3_RCR1) & RTCA3_RCR1_AIE); + + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int rtca3_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + struct rtc_time *tm = &wkalrm->time; + unsigned long flags; + u8 rcr1, tmp; + int ret; + + spin_lock_irqsave(&priv->lock, flags); + + tmp = readb(priv->base + RTCA3_RCR2); + if (!(tmp & RTCA3_RCR2_START)) { + ret = -EPERM; + goto unlock; + } + + /* Disable AIE to prevent false interrupts. */ + rcr1 = readb(priv->base + RTCA3_RCR1); + rcr1 &= ~RTCA3_RCR1_AIE; + writeb(rcr1, priv->base + RTCA3_RCR1); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + !(tmp & RTCA3_RCR1_AIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + goto unlock; + + /* Set the time and enable the alarm. */ + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_min), priv->base + RTCA3_RMINAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYAR); + writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONAR); + + writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRAR); + writeb(RTCA3_AR_ENB, priv->base + RTCA3_RYRAREN); + + /* Make sure we can read back the counters. */ + rtca3_prepare_cntalrm_regs_for_read(priv, false); + + /* Need to wait for 2 * 1/64 periodic interrupts to be generated. */ + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_INIT); + reinit_completion(&priv->set_alarm_completion); + + /* Enable periodic interrupt. */ + rcr1 |= RTCA3_RCR1_PIE; + writeb(rcr1, priv->base + RTCA3_RCR1); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, + (tmp & RTCA3_RCR1_PIE), + 10, RTCA3_IRQSET_TIMEOUT_US); + + spin_unlock_irqrestore(&priv->lock, flags); + + if (ret) + goto setup_failed; + + /* Wait for the 2 * 1/64 periodic interrupts. */ + ret = wait_for_completion_interruptible_timeout(&priv->set_alarm_completion, + msecs_to_jiffies(500)); + if (ret <= 0) { + ret = -ETIMEDOUT; + goto setup_failed; + } + + spin_lock_irqsave(&priv->lock, flags); + ret = rtca3_alarm_irq_set_helper(priv, RTCA3_RCR1_AIE, wkalrm->enabled); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); + spin_unlock_irqrestore(&priv->lock, flags); + + return ret; + +setup_failed: + spin_lock_irqsave(&priv->lock, flags); + /* + * Disable PIE to avoid interrupt storm in case HW needed more than + * specified timeout for setup. + */ + writeb(rcr1 & ~RTCA3_RCR1_PIE, priv->base + RTCA3_RCR1); + readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, !(tmp & ~RTCA3_RCR1_PIE), + 10, RTCA3_DEFAULT_TIMEOUT_US); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); +unlock: + spin_unlock_irqrestore(&priv->lock, flags); + + return ret; +} + +static int rtca3_read_offset(struct device *dev, long *offset) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + u8 val, radj, cycles; + unsigned long flags; + u32 ppb_per_cycle; + + spin_lock_irqsave(&priv->lock, flags); + radj = readb(priv->base + RTCA3_RADJ); + val = readb(priv->base + RTCA3_RCR2); + spin_unlock_irqrestore(&priv->lock, flags); + + cycles = FIELD_GET(RTCA3_RADJ_ADJ, radj); + + if (!cycles) { + *offset = 0; + return 0; + } + + if (val & RTCA3_RCR2_ADJP) + ppb_per_cycle = priv->ppb.ten_sec; + else + ppb_per_cycle = priv->ppb.sixty_sec; + + *offset = cycles * ppb_per_cycle; + val = FIELD_GET(RTCA3_RADJ_PMADJ, radj); + if (val == RTCA3_RADJ_PMADJ_SUB) + *offset = -(*offset); + + return 0; +} + +static int rtca3_set_offset(struct device *dev, long offset) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + int cycles, cycles10, cycles60; + unsigned long flags; + u8 radj, adjp, tmp; + int ret; + + /* + * Automatic time error adjustment could be set at intervals of 10 + * or 60 seconds. + */ + cycles10 = DIV_ROUND_CLOSEST(offset, priv->ppb.ten_sec); + cycles60 = DIV_ROUND_CLOSEST(offset, priv->ppb.sixty_sec); + + /* We can set b/w 1 and 63 clock cycles. */ + if (cycles60 >= -RTCA3_RADJ_ADJ_MAX && + cycles60 <= RTCA3_RADJ_ADJ_MAX) { + cycles = cycles60; + adjp = 0; + } else if (cycles10 >= -RTCA3_RADJ_ADJ_MAX && + cycles10 <= RTCA3_RADJ_ADJ_MAX) { + cycles = cycles10; + adjp = RTCA3_RCR2_ADJP; + } else { + return -ERANGE; + } + + radj = FIELD_PREP(RTCA3_RADJ_ADJ, abs(cycles)); + if (!cycles) + radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_NONE); + else if (cycles > 0) + radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_ADD); + else + radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_SUB); + + spin_lock_irqsave(&priv->lock, flags); + + tmp = readb(priv->base + RTCA3_RCR2); + + if ((tmp & RTCA3_RCR2_ADJP) != adjp) { + /* RADJ.PMADJ need to be set to zero before setting RCR2.ADJP. */ + writeb(0, priv->base + RTCA3_RADJ); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, !tmp, + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + goto unlock; + + rtca3_byte_update_bits(priv, RTCA3_RCR2, RTCA3_RCR2_ADJP, adjp); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, + ((tmp & RTCA3_RCR2_ADJP) == adjp), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + goto unlock; + } + + writeb(radj, priv->base + RTCA3_RADJ); + ret = readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, (tmp == radj), + 10, RTCA3_DEFAULT_TIMEOUT_US); + +unlock: + spin_unlock_irqrestore(&priv->lock, flags); + return ret; +} + +static const struct rtc_class_ops rtca3_ops = { + .read_time = rtca3_read_time, + .set_time = rtca3_set_time, + .read_alarm = rtca3_read_alarm, + .set_alarm = rtca3_set_alarm, + .alarm_irq_enable = rtca3_alarm_irq_enable, + .set_offset = rtca3_set_offset, + .read_offset = rtca3_read_offset, +}; + +static int rtca3_initial_setup(struct clk *clk, struct rtca3_priv *priv) +{ + unsigned long osc32k_rate; + u8 val, tmp, mask; + u32 sleep_us; + int ret; + + osc32k_rate = clk_get_rate(clk); + if (!osc32k_rate) + return -EINVAL; + + sleep_us = DIV_ROUND_UP_ULL(1000000ULL, osc32k_rate) * 6; + + priv->ppb.ten_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 10)); + priv->ppb.sixty_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 60)); + + /* + * According to HW manual (section 22.4.2. Clock and count mode setting procedure) + * we need to wait at least 6 cycles of the 32KHz clock after clock was enabled. + */ + usleep_range(sleep_us, sleep_us + 10); + + /* Disable all interrupts. */ + mask = RTCA3_RCR1_AIE | RTCA3_RCR1_CIE | RTCA3_RCR1_PIE; + ret = rtca3_alarm_irq_set_helper(priv, mask, 0); + if (ret) + return ret; + + mask = RTCA3_RCR2_START | RTCA3_RCR2_HR24; + val = readb(priv->base + RTCA3_RCR2); + /* Nothing to do if already started in 24 hours and calendar count mode. */ + if ((val & mask) == mask) + return 0; + + /* Reconfigure the RTC in 24 hours and calendar count mode. */ + mask = RTCA3_RCR2_START | RTCA3_RCR2_CNTMD; + writeb(0, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* + * Set 24 hours mode. According to HW manual (section 22.3.19. RTC Control + * Register 2) this needs to be done separate from stop operation. + */ + mask = RTCA3_RCR2_HR24; + val = RTCA3_RCR2_HR24; + writeb(val, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, (tmp & mask), + 10, RTCA3_DEFAULT_TIMEOUT_US); + if (ret) + return ret; + + /* Execute reset. */ + mask = RTCA3_RCR2_RESET; + writeb(val | RTCA3_RCR2_RESET, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask), + 10, RTCA3_RESET_TIMEOUT_US); + if (ret) + return ret; + + /* + * According to HW manual (section 22.6.3. Notes on writing to and reading + * from registers) after reset we need to wait 6 clock cycles before + * writing to RTC registers. + */ + usleep_range(sleep_us, sleep_us + 10); + + /* Set no adjustment. */ + writeb(0, priv->base + RTCA3_RADJ); + ret = readb_poll_timeout(priv->base + RTCA3_RADJ, tmp, !tmp, 10, + RTCA3_DEFAULT_TIMEOUT_US); + + /* Start the RTC and enable automatic time error adjustment. */ + mask = RTCA3_RCR2_START | RTCA3_RCR2_AADJE; + val |= RTCA3_RCR2_START | RTCA3_RCR2_AADJE; + writeb(val, priv->base + RTCA3_RCR2); + ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, ((tmp & mask) == mask), + 10, RTCA3_START_TIMEOUT_US); + if (ret) + return ret; + + /* + * According to HW manual (section 22.6.4. Notes on writing to and reading + * from registers) we need to wait 1/128 seconds while the clock is operating + * (RCR2.START bit = 1) to be able to read the counters after a return from + * reset. + */ + usleep_range(8000, 9000); + + /* Set period interrupt to 1/64 seconds. It is necessary for alarm setup. */ + val = FIELD_PREP(RTCA3_RCR1_PES, RTCA3_RCR1_PES_1_64_SEC); + rtca3_byte_update_bits(priv, RTCA3_RCR1, RTCA3_RCR1_PES, val); + return readb_poll_timeout(priv->base + RTCA3_RCR1, tmp, ((tmp & RTCA3_RCR1_PES) == val), + 10, RTCA3_DEFAULT_TIMEOUT_US); +} + +static int rtca3_request_irqs(struct platform_device *pdev, struct rtca3_priv *priv) +{ + struct device *dev = &pdev->dev; + int ret, irq; + + irq = platform_get_irq_byname(pdev, "alarm"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get alarm IRQ!\n"); + + ret = devm_request_irq(dev, irq, rtca3_alarm_handler, 0, "rtca3-alarm", priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to request alarm IRQ!\n"); + priv->wakeup_irq = irq; + + irq = platform_get_irq_byname(pdev, "period"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get period IRQ!\n"); + + ret = devm_request_irq(dev, irq, rtca3_periodic_handler, 0, "rtca3-period", priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to request period IRQ!\n"); + + /* + * Driver doesn't implement carry handler. Just get the IRQ here + * for backward compatibility, in case carry support will be added later. + */ + irq = platform_get_irq_byname(pdev, "carry"); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get carry IRQ!\n"); + + return 0; +} + +static void rtca3_action(void *data) +{ + struct device *dev = data; + struct rtca3_priv *priv = dev_get_drvdata(dev); + int ret; + + ret = reset_control_assert(priv->rstc); + if (ret) + dev_err(dev, "Failed to de-assert reset!"); + + ret = pm_runtime_put_sync(dev); + if (ret < 0) + dev_err(dev, "Failed to runtime suspend!"); +} + +static int rtca3_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rtca3_priv *priv; + struct clk *clk; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; + + priv->rstc = devm_reset_control_get_shared(dev, NULL); + if (IS_ERR(priv->rstc)) + return PTR_ERR(priv->rstc); + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + ret = reset_control_deassert(priv->rstc); + if (ret) { + pm_runtime_put_sync(dev); + return ret; + } + + dev_set_drvdata(dev, priv); + ret = devm_add_action_or_reset(dev, rtca3_action, dev); + if (ret) + return ret; + + /* + * This must be an always-on clock to keep the RTC running even after + * driver is unbinded. + */ + clk = devm_clk_get_enabled(dev, "counter"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + spin_lock_init(&priv->lock); + atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); + init_completion(&priv->set_alarm_completion); + + ret = rtca3_initial_setup(clk, priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to setup the RTC!\n"); + + ret = rtca3_request_irqs(pdev, priv); + if (ret) + return ret; + + device_init_wakeup(&pdev->dev, 1); + + priv->rtc_dev = devm_rtc_allocate_device(&pdev->dev); + if (IS_ERR(priv->rtc_dev)) + return PTR_ERR(priv->rtc_dev); + + priv->rtc_dev->ops = &rtca3_ops; + priv->rtc_dev->max_user_freq = 256; + priv->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000; + priv->rtc_dev->range_max = RTC_TIMESTAMP_END_2099; + + return rtc_register_device(priv->rtc_dev); +} + +static int rtca3_suspend(struct device *dev) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + + if (!device_may_wakeup(dev)) + return 0; + + /* Alarm setup in progress. */ + if (atomic_read(&priv->alrm_sstep) != RTCA3_ALRM_SSTEP_DONE) + return -EBUSY; + + enable_irq_wake(priv->wakeup_irq); + + return 0; +} + +static int rtca3_clean_alarm(struct rtca3_priv *priv) +{ + struct rtc_device *rtc_dev = priv->rtc_dev; + time64_t alarm_time, now; + struct rtc_wkalrm alarm; + unsigned long flags; + struct rtc_time tm; + u8 pending; + int ret; + + ret = rtc_read_alarm(rtc_dev, &alarm); + if (ret) + return ret; + + if (!alarm.enabled) + return 0; + + ret = rtc_read_time(rtc_dev, &tm); + if (ret) + return ret; + + alarm_time = rtc_tm_to_time64(&alarm.time); + now = rtc_tm_to_time64(&tm); + if (alarm_time >= now) + return 0; + + /* + * Heuristically, it has been determined that when returning from deep + * sleep state the RTCA3_RSR.AF is zero even though the alarm expired. + * Call again the rtc_update_irq() if alarm helper detects this. + */ + + spin_lock_irqsave(&priv->lock, flags); + + pending = rtca3_alarm_handler_helper(priv); + if (!pending) + rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF); + + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int rtca3_resume(struct device *dev) +{ + struct rtca3_priv *priv = dev_get_drvdata(dev); + + if (!device_may_wakeup(dev)) + return 0; + + disable_irq_wake(priv->wakeup_irq); + + /* + * According to the HW manual (section 22.6.4 Notes on writing to + * and reading from registers) we need to wait 1/128 seconds while + * RCR2.START = 1 to be able to read the counters after a return from low + * power consumption state. + */ + mdelay(8); + + /* + * The alarm cannot wake the system from deep sleep states. In case + * we return from deep sleep states and the alarm expired we need + * to disable it to avoid failures when setting another alarm. + */ + return rtca3_clean_alarm(priv); +} + +static SIMPLE_DEV_PM_OPS(rtca3_pm_ops, rtca3_suspend, rtca3_resume); + +static const struct of_device_id rtca3_of_match[] = { + { .compatible = "renesas,rz-rtca3", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rtca3_of_match); + +static struct platform_driver rtca3_platform_driver = { + .driver = { + .name = "rtc-rtca3", + .pm = pm_ptr(&rtca3_pm_ops), + .of_match_table = rtca3_of_match, + }, + .probe = rtca3_probe, +}; +module_platform_driver(rtca3_platform_driver); + +MODULE_DESCRIPTION("Renesas RTCA-3 RTC driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); From patchwork Fri Jan 24 09:00:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949132 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D912C02181 for ; Fri, 24 Jan 2025 09:01:01 +0000 (UTC) Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) by mx.groups.io with SMTP id smtpd.web10.7455.1737709260723645886 for ; Fri, 24 Jan 2025 01:01:01 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=AlC75qSd; spf=pass (domain: tuxon.dev, ip: 209.85.218.47, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f47.google.com with SMTP id a640c23a62f3a-aaecf50578eso430956966b.2 for ; Fri, 24 Jan 2025 01:01:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709259; x=1738314059; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lbqTs9unRn7Hi+pzk+KIjC3twFnxhii645av4K0DEo4=; b=AlC75qSdOh8UifSM5CSb0UpHlYYYNyya4oyOYg6QUr4Sb2sWnVwxymL82irJoXFUIh UpitgjpvA08fyOuZeDOsG5J8sbu/NY4Q7dHDCee7aOVaxr4prcZSvYDMFMDLN6rePA26 DiJNSytR5DmmA/oZa4z/O6fuEUYDEinLIKgDIQxBh+9BJT6OsXqzUhWPARqRLYiPrpGt +3lZ5rB7IPTLMCH+/XoYblYflILSfGElT2PZ0sGizDp6pKycTjuFrLAKl29598HkbH4E WhP0b+00gCp5u+GbZsjusMniWNJn0EDQkwRJup/Gv3GateVN1df1nWThLq9V6p4kkOmT OxlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709259; x=1738314059; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lbqTs9unRn7Hi+pzk+KIjC3twFnxhii645av4K0DEo4=; b=LI89BlohIpL3s1nO7gP9EFISoquq2G+GVx086ld8XmRlXxDjg8Kq5c7AGN1O81diwG /ua10dLZHAsSftzIzA2Ja/INbXN8qXxwOKKzyQbDYzQTS/rA2Re4ovgahY9Han73O1sR HQfST5vpzhzJlNm0MrPf2ncIgq5/wPTOvz+vtWHE0ymayp2a7t7NAgWbHxOdDcqZkI3k 9ya1IMtRr+hvhoRBxTVfVqJHm9/NTHdxzvsfHBAPNqxwrH7mb4SDXfSr2CnYfufbU/8a TELoSMpm6hROpk1Cf4gyYsq1tJzRkmMcOyp28y8kajF9tx03eNkuxT1mQQRZu2sWT/CE e8VA== X-Forwarded-Encrypted: i=1; AJvYcCUt1dBN8WTI4N9VIXCOfxF/DVW15d+OL6BAHBoJNx5TJbw8NEqRHFjpRdi6DKq5NXgItVDnnGJp@lists.cip-project.org X-Gm-Message-State: AOJu0Yy+l2495FCmpkTSu+zF2xjcYz4ZgMffxAilww+y7pQ2P4a2iBtt iVWiHSExgFoPPWjqCIpjknsUAXqktilt2iYQ/yqpFl2JqpJSuE2+WIp++UwsdMc= X-Gm-Gg: ASbGnctCKP8jqmCA2p25I60ctyi3Uk1IrxHwcWkjliVmrWpyYYJVo15GxD4e0+S90SQ AyffDuBRO6c/ua9m8rv/sWfQKsAB1ji0dMVzYn59+P+/VfwzHUOmgdB2j4iy9fOVSqMJ0X4St8W EBx3J33pkEFDnWJv8asqiE/xAVj4dKmPRpXJ4f4z3nMDuVkYRzaYdWTSifibcW7QqHETAsc1IQO YxJEzsfway1I8H/zX+Gh71nnN//+Kkjf5sKR1TDN9Zvu/C8BTarFHnAFdcQREb2nuQHuICXu0uj POegWgi/X22ylVSJ6fYfDuHU9eC1DoI6bQ== X-Google-Smtp-Source: AGHT+IGyLiUWG22pObAPr7VdBzxNahSr1JeaPqzIP9OocsnmCjibmLxpqQ7YECdsDeswyaxCht4syg== X-Received: by 2002:a17:907:3606:b0:ab3:60eb:f858 with SMTP id a640c23a62f3a-ab38b381338mr2644968266b.38.1737709259045; Fri, 24 Jan 2025 01:00:59 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab6760fbce4sm92200766b.127.2025.01.24.01.00.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:58 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip v2 11/16] rtc: renesas-rtca3: Fix compilation error on RISC-V Date: Fri, 24 Jan 2025 11:00:36 +0200 Message-ID: <20250124090041.1401132-12-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:01:01 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17648 From: Claudiu Beznea commit 8f315a5c7376b2bc324d62a8400184da77f25e28 upstream. Fix the following compilation errors when building the RTCA3 for RISCV: ../drivers/rtc/rtc-renesas-rtca3.c:270:23: error: call to undeclared function 'FIELD_GET'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 270 | tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECCNT_SEC, sec)); | ^ ../drivers/rtc/rtc-renesas-rtca3.c:369:23: error: call to undeclared function 'FIELD_GET'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 369 | tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECAR_SEC, sec)); | ^ ../drivers/rtc/rtc-renesas-rtca3.c:476:11: error: call to undeclared function 'FIELD_GET'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 476 | cycles = FIELD_GET(RTCA3_RADJ_ADJ, radj); | ^ ../drivers/rtc/rtc-renesas-rtca3.c:523:9: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 523 | radj = FIELD_PREP(RTCA3_RADJ_ADJ, abs(cycles)); | ^ ../drivers/rtc/rtc-renesas-rtca3.c:658:8: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 658 | val = FIELD_PREP(RTCA3_RCR1_PES, RTCA3_RCR1_PES_1_64_SEC); | ^ Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20241101095720.2247815-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Alexandre Belloni Reviewed-by: Pavel Machek [claudiu.beznea: fixed conflict] Signed-off-by: Claudiu Beznea --- drivers/rtc/rtc-renesas-rtca3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/rtc/rtc-renesas-rtca3.c b/drivers/rtc/rtc-renesas-rtca3.c index 5a8dd2ad6b60..e3a9bb16b1ec 100644 --- a/drivers/rtc/rtc-renesas-rtca3.c +++ b/drivers/rtc/rtc-renesas-rtca3.c @@ -5,6 +5,7 @@ * Copyright (C) 2024 Renesas Electronics Corp. */ #include +#include #include #include #include From patchwork Fri Jan 24 09:00:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949140 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FC27C0218B for ; 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([82.78.167.35]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab6760fbce4sm92200766b.127.2025.01.24.01.00.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:00:59 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip v2 12/16] arm64: dts: renesas: r9a08g045: Add VBATTB node Date: Fri, 24 Jan 2025 11:00:37 +0200 Message-ID: <20250124090041.1401132-13-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:01:11 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17649 From: Claudiu Beznea commit 23c44956bce5aa79c060fc3e5d51843735e6eda6 upstream. Add the DT node for the VBATTB IP along with DT bindings for the clock it provides. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-6-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Reviewed-by: Pavel Machek [claudiu.beznea: the backported patch has references for i2c nodes; the i2c nodes are not available in v5.10 cip, thus fixed conflict by dropping the i2c nodes] Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index f5f3f4f4c8d6..7bc8969a7b5a 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -72,6 +72,18 @@ scif0: serial@1004b800 { status = "disabled"; }; + vbattb: clock-controller@1005c000 { + compatible = "renesas,r9a08g045-vbattb"; + reg = <0 0x1005c000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; + clock-names = "bclk", "rtx"; + #clock-cells = <1>; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + status = "disabled"; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a08g045-cpg"; reg = <0 0x11010000 0 0x10000>; @@ -296,4 +308,11 @@ timer { <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; + + vbattb_xtal: vbattb-xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; }; From patchwork Fri Jan 24 09:00:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949143 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA7FBC0218D for ; Fri, 24 Jan 2025 09:01:11 +0000 (UTC) Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) by mx.groups.io with SMTP id smtpd.web11.7453.1737709263747351265 for ; Fri, 24 Jan 2025 01:01:04 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=i/wcXiMW; spf=pass (domain: tuxon.dev, ip: 209.85.218.53, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-aaec61d0f65so410622166b.1 for ; Fri, 24 Jan 2025 01:01:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709262; x=1738314062; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HXCpiqVyMDixgTZL5X7LC+i/BPq4PaBUIA0VzYmUtdY=; b=i/wcXiMWVgp2wf9V/4XU6QwfLD2A3YOfVR3plWcMM8haQghk7UbFXK7oz90gHayrPI GWSDF1oGrcgLQ1PQFsfTE/w7yqamMJ9QyH1pQrB+frAMSz7hBzz5y0TBovGsWoKRy6yW 471IdGfoXDUU3hUWf/Du/qjbqZEfhl0jZ/TYbvNc2V7rzI+8KkODY0Lj8IGA+kD6xLXw SjJsGmTxwMa9uw6nPfBTgieeNPxmbpCa0lILZiHeceodWUPlYKigDMaoPPylp5iokkvC LUdp8RuCjw96COGe0ouuvwgUVPBfW7qQS3wJ/dorismdO0aRAASS1HPcBLSOJ0Jz+NgB s06A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709262; x=1738314062; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HXCpiqVyMDixgTZL5X7LC+i/BPq4PaBUIA0VzYmUtdY=; b=ggv27ogFlrDmu3PuKG5N3QgJ4F8I+C+ktIqD6LnKkbCjWhANZbLCHJtMfHWqPK8uhi CDi0TWzuxwUTo2MSaIaq3vPdTOX0ZB4CUfSBcdTc/eteKw9TW6Ii3COWaPmcJRrP6NVo WITkVp4PsuKYJFYyZRN/7JxLd+R+YXhwczcE4FaHmYEuP0BW8aoB/2+o8v+DFQKBMmT8 u1aCBZjtKCJpzxpeEsTnkFptUCar3GhiZnYX2XWU1yygkxAB7h7yM6IawJRQLHhigs2u jOqYNQrCZB3AG+Z36xeQ4o4WHIm45o81hKeWUlESNt/8ZiB0qVraMnXREx5Oh7O26v0L lx7g== X-Forwarded-Encrypted: i=1; AJvYcCVywKrttxzn2Ze6djJ4z7U1nTjgoO/ASeMw6iyqpPfGazIn2Jr5JMoReNWe62dIpBs/+hOtiRgc@lists.cip-project.org X-Gm-Message-State: AOJu0Yy+xureW3Cr4DdhFyV9Fh3BAEMcAGReSei0Z5EMpKGMIa6Aj4st Sgnm3ZvMwkSHeFJ6nGTfZ0djgeBy0lNhBI+wI7m3UDMXDg9+4fWxBm3BK3FV7Ew= X-Gm-Gg: ASbGncsbRIOv/aR0fchiLO6yySy2ZlFDMwpbkQpp/vDTBXe1iyVOkGbzCF2qGwzcNDi 4+LaoBjKsEAGGd1LoVktHOj3noUoW7fRPsDUFtSBSq11v+2gP29JdSb1vhokJH3yUncew7wbZof xVfe3zf0hDNo/dFgHRfFkx8JtrUYbN4M8GA4L4X8CLC5nWbBwqLMci9mcjXqQmgAYL+U+ViU/kF EJM0spe9rr30GThHa53d69ZrFcmSkgI84d7LRUFKpTq3tes4QRuYuaxW/V/ahZ6qA5x/OsfLOC5 bpmuPtnDidL+VWVIHJBbUy9J6gmAchJPBg== X-Google-Smtp-Source: AGHT+IHfiha0Oi8YYgdb9EiJkbGcOyLvoU8dwkg5CpuDn0AFYp18QcDZaJ0AwT6jiZ8ZetOX9tFaCQ== X-Received: by 2002:a17:907:2cc5:b0:ab2:c78f:e4ae with SMTP id a640c23a62f3a-ab38b12a246mr2835627366b.20.1737709262056; Fri, 24 Jan 2025 01:01:02 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab6760fbce4sm92200766b.127.2025.01.24.01.01.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:01:01 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip v2 13/16] arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB Date: Fri, 24 Jan 2025 11:00:38 +0200 Message-ID: <20250124090041.1401132-14-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:01:11 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17650 From: Claudiu Beznea commit ac948eb8ead1265ff034955bdbbb081744f1e7ed upstream. Enable the VBATTB controller. It provides the clock for RTC. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-8-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Reviewed-by: Pavel Machek Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index acac4666ae59..67178d8c4108 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2023 Renesas Electronics Corp. */ +#include #include #include @@ -341,6 +342,17 @@ mux { }; }; +&vbattb { + assigned-clocks = <&vbattb VBATTB_MUX>; + assigned-clock-parents = <&vbattb VBATTB_XC>; + quartz-load-femtofarads = <12500>; + status = "okay"; +}; + +&vbattb_xtal { + clock-frequency = <32768>; +}; + &wdt0 { timeout-sec = <60>; status = "okay"; From patchwork Fri Jan 24 09:00:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949139 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1E51C0218E for ; Fri, 24 Jan 2025 09:01:11 +0000 (UTC) Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) by mx.groups.io with SMTP id smtpd.web11.7454.1737709265048820694 for ; Fri, 24 Jan 2025 01:01:05 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=JylTvlsk; spf=pass (domain: tuxon.dev, ip: 209.85.218.42, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f42.google.com with SMTP id a640c23a62f3a-aaeec07b705so365364766b.2 for ; Fri, 24 Jan 2025 01:01:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709263; x=1738314063; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DpGb7kiQv4TjwfE0PIXkbdbDly9aR6lFb2N3C6Ml7lo=; b=JylTvlskRNPKVi7+jZUDJgMWDOPPDKQHCRRmLuAMffkBZj/nh9KeXP4zz8Q3ZtMqiR MPkP11YRHqoGfcA49kFTDQf7wKEa2RuYtLwFYsRfBT6Ouc3S/1tl+lYcjM7n+VrZP1LF F11QMw66AL2PZvhviM9zpIwPqMWHIYi0nFeSmdJmyyu8XsXDhM1fpRNZO8a7W20vjGr9 vLenLf5O2U+cQe04TsBiQVQ0a4FiaK/3Cji4qt/d2Eh7QGY/AL2p1fnJAD6lnSa4pcN3 tq3cEYBLuTdmEWvBXvFzEJHc4+q8UhNR0P+HjHz+LMG2vuvzmvSMreMBzjPzXY9/G29z /yeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709263; x=1738314063; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DpGb7kiQv4TjwfE0PIXkbdbDly9aR6lFb2N3C6Ml7lo=; b=nRbv+Zs4ap/88VHwD3Iky4HsaETTrs5rsp/SiSZsTWU/+U+v5NPO8t8bMcSyBM9WFg D/xt92ZYB8oxYDMNANetZs7Noc7fxHmbGSjo46pP4TsEFpfDmMylSmLo0ViC4GWd034H 1SXVjUsW2Ks4G10ouJIFMZ0MbbHiRvnFNNGAZEV0MZive845KKxcESbXU90cM7IQAQIE mf+UjFiFrCahPYsiufKLJlHIOO62hEqSQcgTchtHxe6DugskyZMhWZnXuaonEYC26gRc RRmtJD/LiGuR1QLy4HhVWagRXnaFJNVGD4aLClpXpV5PJ9MhAHE1XELEPeIT4X7sitIR Cdsg== X-Forwarded-Encrypted: i=1; AJvYcCVi9g4XV4utSGzPERIDdGyZF2BscAkehJ6+KK3xJSM3LYUi0Pavjmyh+wMF9E8CJmvYOaJDgTn5@lists.cip-project.org X-Gm-Message-State: AOJu0Yw/UQOvtrbL6f0aurfG2Gic/O5wwe0wTGr8qVOhX096LPAWlRG+ XXXgYSi66x0ALcUNL3tv2FUFG+yuBW0tkREdHqjqmkEAfWpXOXZx+LZ4qGYjkXc= X-Gm-Gg: ASbGncspKc6T2vm4nUfxCYcIRSHgMl3bX9u15SFnbfHW1B5CjnucWbdHS+rS21Fa2LZ fnuMmAu3vV2VGC30LPK2uwbwTOXBw3dG4dEfGhxwJd8BEbYzLhX+4UU5N6+eOHWrhJzVan/6QcA vNUbd0BLnZDC9QAOtm4LxIF1VIrwQxvNSyNiAS3VvpVaw/X/vMQmcrPUgZUZ+ZDD6ZDCGlLqE21 W7ZTOBfS6yjuIXIgl/CixjnZPwubMGe4rz+DrrzEohWTFHzLhj/EAsu5gl6CGIQxbzTE+VLkgjy W4zxQp0+VbWDav2Vn/2T5SdVReLnAyeWAQ== X-Google-Smtp-Source: AGHT+IGAvW+vjymxnSM9TwyLuqNr+iIO8acr2Zo7ljuUPAntSYDlwcNl1BtviaENWwqeULPiOju+sQ== X-Received: by 2002:a17:907:c1c:b0:ab6:726b:580 with SMTP id a640c23a62f3a-ab6726b05f6mr297691366b.8.1737709263455; Fri, 24 Jan 2025 01:01:03 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab6760fbce4sm92200766b.127.2025.01.24.01.01.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:01:02 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip v2 14/16] arm64: dts: renesas: r9a08g045: Add RTC node Date: Fri, 24 Jan 2025 11:00:39 +0200 Message-ID: <20250124090041.1401132-15-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:01:11 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17651 From: Claudiu Beznea commit 2d768aee9f5294d2023e824c0906e2e7d1414629 upstream. Add the DT node for the RTC IP available on the Renesas RZ/G3S SoC. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-7-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Reviewed-by: Pavel Machek Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 7bc8969a7b5a..3401c1200a1c 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -7,6 +7,7 @@ #include #include +#include / { compatible = "renesas,r9a08g045"; @@ -72,6 +73,20 @@ scif0: serial@1004b800 { status = "disabled"; }; + rtc: rtc@1004ec00 { + compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; + reg = <0 0x1004ec00 0 0x400>; + interrupts = , + , + ; + interrupt-names = "alarm", "period", "carry"; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb VBATTB_VBATTCLK>; + clock-names = "bus", "counter"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + status = "disabled"; + }; + vbattb: clock-controller@1005c000 { compatible = "renesas,r9a08g045-vbattb"; reg = <0 0x1005c000 0 0x1000>; From patchwork Fri Jan 24 09:00:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949141 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FBF6C02181 for ; Fri, 24 Jan 2025 09:01:11 +0000 (UTC) Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) by mx.groups.io with SMTP id smtpd.web10.7458.1737709266520475636 for ; Fri, 24 Jan 2025 01:01:06 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=IlRvjxEV; spf=pass (domain: tuxon.dev, ip: 209.85.218.41, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f41.google.com with SMTP id a640c23a62f3a-ab633d9582aso332243266b.1 for ; Fri, 24 Jan 2025 01:01:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709265; x=1738314065; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=s/YNikkkxhG5IDAJLIfsvzBE/9wz3dlXvplx+eyQvZg=; b=IlRvjxEVZotnU7rYe3BUXO55w4CRFoFbKHY70mYIY7IClb3XgcY7/YEFagaMiYxpbW xUDF02ubnAvVlUA+9WvNTXpBq22vQcPBh1oEVSYkNVOXOcsm8HnqrRJo7339Y4wkIH1S YEZ8EVlmlLiCG6jcEAHfQ1FNYm2ATvqqz7dKZTcWVN9eVVJDWc+tG0z7yO601VcdsdQ0 AYQQ0pEDlXw2CMUe0476AItY2WqUf1sFzAJLDdL41003BaRgEHibofxwDi7FVYJgifHg u0mqKnnHhyuTW0a7NqDcYTmanwaLhCQMJ5z4sDf3vA9SNhDJcgUkXWGBtAoGO6tw9Fp6 iNKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709265; x=1738314065; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=s/YNikkkxhG5IDAJLIfsvzBE/9wz3dlXvplx+eyQvZg=; b=u3ISTphFhegsPKUgq4j9L+0krWNuQ/iyppd4PGQUIiNzNJ48C7vC7DwY2HPUVvoF07 3zM5wOWkx37U49V890SPWlgKw9E+M5cgyApljOtXDOnHTG9RGU+o3waEJVPkUD/xQ7kZ hGChEkOiH1yD1GNm2Q8kFcp1dJrYDZ357BQk5o1dgvNCIsDXy1duqXfgk1bhtLoWAAV/ o+qkgrVp+3cu55STK752bT290VlsXjr75f3Uq48y49mamEZpt+KCf1qMdb04vEfrK1C3 V/Usk/3GfR2BFzddAlWfztwiDlom4VaAknsxuRiO/0B6Is56+HSQqhsaEcIwq3vj4DN6 Odlw== X-Forwarded-Encrypted: i=1; AJvYcCUMND3DkipPUvZtRw2icS+LKrU0HfVkMh9Zwl1YRq4KopWmiUmd7b/CdLQbaOaFJ+LrPRbKFvq9@lists.cip-project.org X-Gm-Message-State: AOJu0YxZHd+ZcewhhHZ0K5sBI5SrNuSaBEpi8p1PM469TSBXVNI6tH0e I3cU4J6tJssVQ+KFCmuiE75CbJkdhjK22L7s/h35kBHPCgcBqc9JdRm3LhNzgOw= X-Gm-Gg: ASbGncsCLemQ7dgQ1gsfxs4F3862UFIFk6OYthqaeaidVuUe3PHZ6+mJ8x/3YW++GA4 MsgSOp1Dnlyij4ZToE+7mQQdCX/0xmgBPXwklZeDV0N9gzhuZE3r6vJNVUMRHXQdEayqqRvgclK vOEwMnwo+N6C1ncVTNW+a8JCNTw0SORd5C5FfFMBsAazZ+/ptZ9viLxjYGsaTAMBRhayVzc0Qmj QzQIrLaZlHaWf/uVIiUga7dFe5mfVD4fAkuKEbnlX/TbmTwaxu+jmQyBizrpksYfyrExcYsCj7p UlaScmPh29uafLbouKlow3iZmOyMXqPb9w== X-Google-Smtp-Source: AGHT+IHn25fbCHRiCesnjDjzGD8EYp7MEaNjSu6RkbnzXbFaVJ8gD8N5WdWrz4jsDn1RwLj095mYIQ== X-Received: by 2002:a17:906:1e4a:b0:ab6:4faa:bc82 with SMTP id a640c23a62f3a-ab64faabd04mr803071566b.25.1737709264560; Fri, 24 Jan 2025 01:01:04 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab6760fbce4sm92200766b.127.2025.01.24.01.01.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:01:04 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip v2 15/16] arm64: dts: renesas: rzg3s-smarc-som: Enable RTC Date: Fri, 24 Jan 2025 11:00:40 +0200 Message-ID: <20250124090041.1401132-16-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:01:11 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17652 From: Claudiu Beznea commit 0cd647cd53db0315361e41056e10739a5ee1e668 upstream. Enable RTC. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-9-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Reviewed-by: Pavel Machek Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 67178d8c4108..b07d9251d182 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -342,6 +342,10 @@ mux { }; }; +&rtc { + status = "okay"; +}; + &vbattb { assigned-clocks = <&vbattb VBATTB_MUX>; assigned-clock-parents = <&vbattb VBATTB_XC>; From patchwork Fri Jan 24 09:00:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13949142 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB0ACC0218C for ; Fri, 24 Jan 2025 09:01:11 +0000 (UTC) Received: from mail-ed1-f42.google.com (mail-ed1-f42.google.com [209.85.208.42]) by mx.groups.io with SMTP id smtpd.web10.7459.1737709267305770103 for ; Fri, 24 Jan 2025 01:01:07 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=I+HnWjdG; spf=pass (domain: tuxon.dev, ip: 209.85.208.42, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ed1-f42.google.com with SMTP id 4fb4d7f45d1cf-5dc149e14fcso1983805a12.2 for ; Fri, 24 Jan 2025 01:01:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1737709266; x=1738314066; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z+z8rDJB5ksnUk72JegiGb9Xcvdr9FNKs59p2tUBp7s=; b=I+HnWjdGiVM6yJ9Lt3ryX2JQCxRGhoXyvPE0jL7nQ0kLRZmkS918fv5vLCfKPNbt2J w3XHhX1hZPl6Mejbpaf7WuKhIuYP4Xp77hDMcoGnALzWGNa3rrjczfAk1WMdLz9lheHJ jZSHKCpu3En+IB7/Zlt5GC0/7e4NfNxIJnewGU7vihBROFeXc1sod0y4/I34EIocarQT JDAQbHlDrqYzhvtj71eY0hGDUfMlgFdALa8dmbwg3bnrHPCaXBEdEPPU8ZUs4WQHVpob Uedv7ZqLvwKotOyfkG44+PPD2Lar5rPFfNoTHeAQbl3ChkP19i3JcpyQdwO/yHXstq91 pZlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737709266; x=1738314066; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z+z8rDJB5ksnUk72JegiGb9Xcvdr9FNKs59p2tUBp7s=; b=PMOI+lkEvF6YcC0gOd3m4B8wdtzjP6D/CPr+umXMLnlDNipL0QtvX8s7KSbeVz39mY PuIidb1OH4OvlX6asiGrNT1WYGnIkjx10v2RHrWTcJT/MZ+oYbuv7QC19+VIljmZODdG oD/UbazgaVbbUErm97Hvu8wShsJLZJiyJ1xIewiSCZv3YPvi5ii12JWKf9o6AMORm4Im HSjcM041RuERxAiCrhHhlyoeWXVVRvbKifaQS0BsunSepOnPWymB6AU8db9LRcibD/2r O0QhuJlQ0/n5q1iBFKnu9Y5nl8u3H/glecHCLpdhbAGBjApymtGFpVAaH1K7Jwn+1hs4 0u2g== X-Forwarded-Encrypted: i=1; AJvYcCUJl3/saRGs75Y7JuwoqYYxIqPm7ruwjo+Hj5VucaG4QEnaibCBvdsFuFmFuNw12AqhBOUSJF4W@lists.cip-project.org X-Gm-Message-State: AOJu0YxnaL9hyPncRO4fFclMbznKkkPvhWcOsyIvxzLuJvaBYb5J+Jfz 1JYEOrzOvGStohmgdZ6gTpXPQpTwIDEtFGP+bj5+hogVxcwtyEBlj2A2EEaNVBE= X-Gm-Gg: ASbGncuKUyT2/wHbwzQqrHozyI7SQBaS86oyV04n9f+bf0sERHAOKFYcW2dJjx0yavk fbzInreYRMYLmqcr/TYUP/sA+nTT3YX741XO+bUSL8I65IG3rApJ4QD6Pt5dAuGm731tL/tgt3C BIeOofb3pCU2tdtRlM9B0xQQWjoVMHnpOkBzY6Ymn5xtrPVK+3XB+mRnxA0x/UGYPbFhV3zsm8g QOjKfpkoU1Kb1YR+vb7wh0854rxNTTQLKnXHjEI2kZu+KtJ/+Fp2EyzVX5Zdommy2qPJRIwRgFB UXnOgpPfT3eyOKKcuC+06eeQgcbjyI1EHw== X-Google-Smtp-Source: AGHT+IGb2Vf/9jNINvHWhFmWVXOPn3cSfMVlDJwH4rL6Yl+LNAFolXauZhaWiw15KeB7DSFSTeXRog== X-Received: by 2002:a17:907:3f23:b0:ab3:f88:b54e with SMTP id a640c23a62f3a-ab38b2e71e0mr2632279766b.31.1737709265703; Fri, 24 Jan 2025 01:01:05 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.35]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab6760fbce4sm92200766b.127.2025.01.24.01.01.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 01:01:05 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: claudiu.beznea@tuxon.dev, cip-dev@lists.cip-project.org Subject: [PATCH v5.10.y-cip v2 16/16] arm64: defconfig: Enable VBATTB clock and Renesas RTCA-3 Date: Fri, 24 Jan 2025 11:00:41 +0200 Message-ID: <20250124090041.1401132-17-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> References: <20250124090041.1401132-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 09:01:11 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/17653 From: Claudiu Beznea commit c520bbb523304ba98de9ffeeb0ef289921434125 upstream. Enable the Renesas VBATTB clock and RTCA-3 RTC drivers. These are available on the Renesas RZ/G3S SoC. VBATTB is the clock provider for the RTC counter. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241101095720.2247815-10-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Reviewed-by: Pavel Machek [claudiu.beznea: fixed conflict by keeping only RTC and VBATTB flags] Signed-off-by: Claudiu Beznea --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 297d671306ce..14a6a6978714 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -854,6 +854,7 @@ CONFIG_RTC_DRV_TEGRA=y CONFIG_RTC_DRV_SNVS=m CONFIG_RTC_DRV_IMX_SC=m CONFIG_RTC_DRV_XGENE=y +CONFIG_RTC_DRV_RENESAS_RTCA3=m CONFIG_DMADEVICES=y CONFIG_DMA_BCM2835=y CONFIG_DMA_SUN6I=m @@ -926,6 +927,7 @@ CONFIG_SM_GCC_8250=y CONFIG_SM_GPUCC_8150=y CONFIG_SM_GPUCC_8250=y CONFIG_QCOM_HFPLL=y +CONFIG_CLK_RENESAS_VBATTB=m CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y CONFIG_RENESAS_OSTM=y