From patchwork Fri Jan 24 11:22:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13949299 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E82A021B18C for ; Fri, 24 Jan 2025 11:23:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737717791; cv=none; b=UuDqYvAdL1SdNu5ShhyBwpwg0JHzJg91lzGN8HssdkLzotWF+RElNaxcx1YgSYdMkZnU8O08Fiy6v4zaToVd2J0mBL7s/k9LxkjBhAzi4Ddtir4Mzcud1Gn5OkuOG1vUxf8pxePC2aPMU6mD42rXV4bvpBKv6joB4955aDhvKf8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737717791; c=relaxed/simple; bh=1cCWyVa5AK2/6g1dA5pRl5YsQKIo2vs/YZuAmrzjF+g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CT98fVwKuqWYyfMeLsoKGLxYgaj0Cv6jDQi13TH6bAAwNmBTaV7wDlKemQ/QT3Vcw7tB2JLEC2K4wlrhHba1V2x1uPQPE5Fb8jkp00NrYVKrmvRYYgSjrPZ41fQKccb1brJbPhTG6eap3fMu2VnK/YfyvDNswXhJvfFhDWPPp8k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=On3/Jag2; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="On3/Jag2" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 50OAoe5x025634 for ; Fri, 24 Jan 2025 11:23:09 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= r3fyHfyMlBiD4pkCqczBKmlgoz+Ny2UI/7GNprFqSSU=; b=On3/Jag2cLhSaqMy tCFOKub8I2bQ1uB37dtEsbiCox22aIxINxnSwwnmEJW7Zs64uvW1b9yfP7vCDeoR dhefG0720a/IuXkFjqHbflzDuLhx5Y/KBdbPzE+iIcmjPTffWFWmrHNpFV7++L0d uSaO5JOTdfbahldA/9yccU4SeE576331ZiiUKMh785Bthm02WXH4qA9sSKfdJ3WR Y/W/vRzk6s4CxSin4rjQ+/m6W6jfbF1hHWd30E+5goptIUL03nFOuBMHvZ+EM0dq yw+i/crA4jN5/4C/vbtKQUGLISmRc8RRYH/A7DqBr5/IgchFrkYZb0qHE4/GJmtd O55jTg== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44c9fd03m8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Fri, 24 Jan 2025 11:23:08 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-2166f9f52fbso59967105ad.2 for ; Fri, 24 Jan 2025 03:23:08 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737717787; x=1738322587; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r3fyHfyMlBiD4pkCqczBKmlgoz+Ny2UI/7GNprFqSSU=; b=I7p/cnMMWSGDITN/bQreiW8Lrh1fPuxG+K2se5b0+v5viQ2BQ7z/nY5mZ/0N2axc0U pQHkeAZoKtaGJGET0fUqCm/1e8JEN7B79Q32RmPzqA+P0/qCNDA8IQdavdcWOBG6X5ox EH2MpvW3ApuacKsXpxmlI59B77lII8LjFMVumqufvWn6jUQ5/6H3piN2p7rsB0CjiCab rU3nE5u9rHVR78Z0c/5DF66O3ki8rBpDu6obmJFQYhhfroofAkfX5oit9VJ91vyxG4Im mlZWRSCzxIk5LUn9m5FEwZDCsKN6WPNfB7Z/zO24+gP3hgbtSAIfw6gxYKr/sZVsDRz2 5AAg== X-Gm-Message-State: AOJu0YylWndJYTzQjbzAclFki7Zp4RcFptWy+JWQsLDnuB9yFF6nw68g Ui7ZWf+CgM8zNEEMeIf0klBsHgQUJ4BFnc0m+2RSDgLyoyZqHWxLS6SZfQlY8imtkZB8MkfLzx3 6ihJW33Jz917DJWR3uKAam+xq9p+tZ8mE9MHBN1d4NpziFyYLZB6+IRrM05aC6p2I X-Gm-Gg: ASbGncv0805NNf2zBeYpHsVQHfQslmM1JivE+fd/jn4frJgxKLsk1D1/ZwxXN7K95j8 J17rLYAFP7MDI7AP7u3bFjrzshcfOJaOAU3A7fhGa08YFaHVEs1sOcz4zk0/1a56V3lxExZWIqu ORKAP9AmFeNgXita13DS6bopTyVD++umdP1rMiZzDmqWygH9L9FGFDkHw6FBYCq42eN8+gXCUI5 fIqF69VLATQ4lAaBroYoHzXsPT7oEuUsLRm9FQtAKpOYJcBVc0REGbe7GHKNM+XRFdZaSWHDMh1 bNreJNLYIgwDeuILtf47Zq/vLY8IXw== X-Received: by 2002:a17:902:e544:b0:21a:87d1:168a with SMTP id d9443c01a7336-21c3563c6e6mr493277035ad.41.1737717787513; Fri, 24 Jan 2025 03:23:07 -0800 (PST) X-Google-Smtp-Source: AGHT+IFy2tDIcgxd5++o9SOPR2tYwiD2dziflaSrZA/gwxFQXN3UBI1mtwMZRzdExbNkM+eWLzrPqw== X-Received: by 2002:a17:902:e544:b0:21a:87d1:168a with SMTP id d9443c01a7336-21c3563c6e6mr493276635ad.41.1737717787163; Fri, 24 Jan 2025 03:23:07 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21da414cc20sm14025385ad.165.2025.01.24.03.23.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 03:23:06 -0800 (PST) From: Krishna Chaitanya Chundru Date: Fri, 24 Jan 2025 16:52:47 +0530 Subject: [PATCH v4 1/4] arm64: dts: qcom: x1e80100: Add PCIe lane equalization preset properties Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250124-preset_v2-v4-1-0b512cad08e1@oss.qualcomm.com> References: <20250124-preset_v2-v4-0-0b512cad08e1@oss.qualcomm.com> In-Reply-To: <20250124-preset_v2-v4-0-0b512cad08e1@oss.qualcomm.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, konrad.dybcio@oss.qualcomm.com, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com, Bjorn Andersson , Konrad Dybcio , Krishna Chaitanya Chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1737717776; l=1380; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=1cCWyVa5AK2/6g1dA5pRl5YsQKIo2vs/YZuAmrzjF+g=; b=O3T80ZKL0sUlxwGUvDzRVdMKESDBubPScoivfbYlONH8VRavEh0VwCnLXbPceheS0NYL3m5N4 iwVCUDvQjQfA5Jkf9dzx6putbgPDoxEbIiDQADqY0XC42Cc5Dh7zv04 X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-ORIG-GUID: PuLTdOHjocRjZr5mJs5pIge5dmIJKAnn X-Proofpoint-GUID: PuLTdOHjocRjZr5mJs5pIge5dmIJKAnn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-24_04,2025-01-23_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=930 suspectscore=0 adultscore=0 phishscore=0 priorityscore=1501 spamscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 impostorscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501240083 Add PCIe lane equalization preset properties for 8 GT/s and 16 GT/s data rates used in lane equalization procedure. Signed-off-by: Krishna Chaitanya Chundru --- This patch depends on the this dt binding pull request which got recently merged: https://github.com/devicetree-org/dt-schema/pull/146 --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index a36076e3c56b..6a2074297030 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2993,6 +2993,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&pcie6a_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + + eq-presets-16gts = /bits/ 8 <0x55 0x55>; + status = "disabled"; }; @@ -3115,6 +3119,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&pcie5_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + status = "disabled"; }; @@ -3235,6 +3241,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&pcie4_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + status = "disabled"; pcie4_port0: pcie@0 { From patchwork Fri Jan 24 11:22:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13949300 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A28221B8FE for ; Fri, 24 Jan 2025 11:23:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737717796; cv=none; b=Lgos6JkIG0lKweLxaWNuApxJAQS74y+p8XAOKE15ad9enu5O798+tfzoNVO1+VgX1g5Eii/mhT9iQceNyt/BnLiphBn04iE31AO5Zc4E3UyfsGM2uc2ej5Q9dQgl+SOoKWOS5Y8J8S4UelPVPFCPnldrRfmjtidN3lC9meKq5Ds= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737717796; c=relaxed/simple; bh=f7z3CtNmxsHSKM03nohqE7aPIUwkTTXaD4CtcTYvgDI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JH3c3s+Xf9XncJmU9P2Vlm9BHBBmha9xHNhAsBRyktk+oBhk4ePFzQfDz93aFi7w2uKGIa4fkgoVRCKTPJttBqXl0S0Rx3PeAD75kfwJ/X40aHQPK2LEDEik+ZomzboCRXfmTd2a9yfIxYqQFl6/sgyGGpzX14HOn6VwWhzrh/4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=kkZbhuBd; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="kkZbhuBd" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 50O8bpKM031428 for ; Fri, 24 Jan 2025 11:23:13 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= oPZTHj57MEyCMgMIvbxGmIatD2m1gGCN5WI13Bi7xRU=; b=kkZbhuBdHl1uAuGJ HBFUN73RL2SeQ2BP7OmraJE1AqijhtepG7nv+ExmAFRGZat08YNjwrP14rl7YmtU Ihq0L45meBLwIjzKFyg8PLtsHKfpMN1wzjtbJb9U9RiixlSzGKfnzhMaYxXFF9wv SuREmW9tKRklReA9raAGhXmUtJzipF0L9zQLoxUVQ9mde5ozXy5q0+Lh58oz6O7P 0zlr1zjIHcXnjfTOhTsQ29UCvl5cjMwFcfBfPFCk2ClcqKVbb5Ut5ZNYhMeliVhS FttmKtjxUxzYHwKtjbsKQxqohm/xkZ8iHLCzxNDpzDhgHo80rG5Z6c2xoYhYR2i3 TMBDew== Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44c7h50gnj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Fri, 24 Jan 2025 11:23:13 +0000 (GMT) Received: by mail-pl1-f198.google.com with SMTP id d9443c01a7336-21661949f23so57752755ad.3 for ; Fri, 24 Jan 2025 03:23:13 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737717793; x=1738322593; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oPZTHj57MEyCMgMIvbxGmIatD2m1gGCN5WI13Bi7xRU=; b=BnJ7ifCt899Ez/rUGZZL2T9hpfGuizkZqtOuHJfwcm52UAFrwbg6SkeL5Rs06CHc72 7DaZB1sLMhiZIRl1bnqYpetFhTjoLEifnLaWf+9I9SR2G9YIXAZSDUKkm+6pmUaTlnkW 2nBlWZVgbxLzIc4EQ5DtTDWt7mN6tomDMkWn21Z1Sx7q+aWMUvT1zs2dgGCBvvKJSQNb mBcjRqwMuci6IHOCQTLvkfWdaj9cfG5eRc+knfgk4arA2h5dMsfg4oXz+zxK+mA7KQBa CRsAtUhsJWlFKBAy3hidQp6gXUss7slsYJz31rorr8slxTtCs8h2XBpVK7uqvSjKdpe7 er6w== X-Gm-Message-State: AOJu0YyijNYyIqN7Aoq0F76KkRTbpqwhJyIOvWEG936iPlnWJ+ACCi/w PqZaB7lsJxmYe7bufGdwioYLPEAzNz4SAAncvID2uyFJk/LnOyH8iHhd1/RLORcwMDUnACFN81X 2DuaSKmmdYbpNf7AUDCvo/Kvoa/MEZJC7uWPmo4+0rBzk/8LNTDObUVsQrAA9Fpcr X-Gm-Gg: ASbGncueTYpAAOyNPZ0SOWlu9QmmLFrKW5ye5CbGQ/KsfW7aoodvoTCiPWLqxJfW8Xg w+FnSWSNwK6iEP3W6Q3ysMborvqAwZ/He6n5Ceu8Q1sGPas2t3q2gbPE8PO98GBc6dgjFcW3c3o qP1wpIHCVZye4Sak5K3sPbxBMaz7vLjT7kqq5l8dYTHDA1XMmTPnqvOFs5I+2NIUQqOv4uCxMAe YO2gUg6KYZioF68FQ45Q97SBrg+R6SP2FYVkjQGpjbt8xIeiioffgtpV2PslTov4kKsA5wf6gzK tL6RRALjqIGdd67g9+HH3S4URyA61Q== X-Received: by 2002:a17:902:f681:b0:216:1cfa:2bda with SMTP id d9443c01a7336-21c3564858emr475850405ad.43.1737717792789; Fri, 24 Jan 2025 03:23:12 -0800 (PST) X-Google-Smtp-Source: AGHT+IEr5DYYXHE2G/vBfLJJCN6ckREbrK5+wnUplikzoVZhqw80AYnBOws3G++Q2Ix4csuj5Tuxeg== X-Received: by 2002:a17:902:f681:b0:216:1cfa:2bda with SMTP id d9443c01a7336-21c3564858emr475849925ad.43.1737717792330; Fri, 24 Jan 2025 03:23:12 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21da414cc20sm14025385ad.165.2025.01.24.03.23.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 03:23:11 -0800 (PST) From: Krishna Chaitanya Chundru Date: Fri, 24 Jan 2025 16:52:48 +0530 Subject: [PATCH v4 2/4] PCI: of: Add API to retrieve equalization presets from device tree Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250124-preset_v2-v4-2-0b512cad08e1@oss.qualcomm.com> References: <20250124-preset_v2-v4-0-0b512cad08e1@oss.qualcomm.com> In-Reply-To: <20250124-preset_v2-v4-0-0b512cad08e1@oss.qualcomm.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, konrad.dybcio@oss.qualcomm.com, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com, Bjorn Andersson , Konrad Dybcio , Krishna Chaitanya Chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1737717776; l=4612; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=f7z3CtNmxsHSKM03nohqE7aPIUwkTTXaD4CtcTYvgDI=; b=ONmPOabKI/5+CXlcVHrVmoVXeeLa+NbJKA7XyAUP+yvdzFIStSgyQzc7zxbrQEzYeC/fnPWAJ KCBUFQE8411CxldWCVXPOcrFJlTYhQcHAoFUXYQDP7askNWfbP5Nxd1 X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-ORIG-GUID: VArcNWKz8eM98WawirIlPG33b9Ox7Bh9 X-Proofpoint-GUID: VArcNWKz8eM98WawirIlPG33b9Ox7Bh9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-24_04,2025-01-23_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 malwarescore=0 impostorscore=0 clxscore=1015 adultscore=0 suspectscore=0 lowpriorityscore=0 mlxscore=0 mlxlogscore=999 phishscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501240083 PCIe equalization presets are predefined settings used to optimize signal integrity by compensating for signal loss and distortion in high-speed data transmission. As per PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4 for data rates of 8.0 GT/s, 16.0 GT/s, 32.0 GT/s, and 64.0 GT/s, there is a way to configure lane equalization presets for each lane to enhance the PCIe link reliability. Each preset value represents a different combination of pre-shoot and de-emphasis values. For each data rate, different registers are defined: for 8.0 GT/s, registers are defined in section 7.7.3.4; for 16.0 GT/s, in section 7.7.5.9, etc. The 8.0 GT/s rate has an extra receiver preset hint, requiring 16 bits per lane, while the remaining data rates use 8 bits per lane. Based on the number of lanes and the supported data rate, this function reads the device tree property and stores in the presets structure. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/of.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci.h | 24 +++++++++++++++++++++++- 2 files changed, 70 insertions(+), 1 deletion(-) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index dacea3fc5128..7aa17c0042c5 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -826,3 +826,50 @@ u32 of_pci_get_slot_power_limit(struct device_node *node, return slot_power_limit_mw; } EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit); + +/** + * of_pci_get_equalization_presets - Parses the "eq-presets-ngts" property. + * + * @dev: Device containing the properties. + * @presets: Pointer to store the parsed data. + * @num_lanes: Maximum number of lanes supported. + * + * If the property is present read and store the data in the preset structure + * assign default value 0xff to indicate property is not present. + * + * If the property is not found or is invalid, returns 0. + */ +int of_pci_get_equalization_presets(struct device *dev, + struct pci_eq_presets *presets, + int num_lanes) +{ + char name[20]; + int ret; + + presets->eq_presets_8gts[0] = 0xff; + if (of_property_present(dev->of_node, "eq-presets-8gts")) { + ret = of_property_read_u16_array(dev->of_node, "eq-presets-8gts", + presets->eq_presets_8gts, num_lanes); + if (ret) { + dev_err(dev, "Error reading eq-presets-8gts %d\n", ret); + return ret; + } + } + + for (int i = 0; i < EQ_PRESET_TYPE_MAX; i++) { + presets->eq_presets_Ngts[i][0] = 0xff; + snprintf(name, sizeof(name), "eq-presets-%dgts", 8 << (i + 1)); + if (of_property_present(dev->of_node, name)) { + ret = of_property_read_u8_array(dev->of_node, name, + presets->eq_presets_Ngts[i], + num_lanes); + if (ret) { + dev_err(dev, "Error %s %d\n", name, ret); + return ret; + } + } + } + + return 0; +} +EXPORT_SYMBOL_GPL(of_pci_get_equalization_presets); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 14d00ce45bfa..3a8c04e3b30d 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -7,6 +7,8 @@ /* Number of possible devfns: 0.0 to 1f.7 inclusive */ #define MAX_NR_DEVFNS 256 +#define MAX_NR_LANES 16 + #define PCI_FIND_CAP_TTL 48 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ @@ -732,6 +734,18 @@ static inline u64 pci_rebar_size_to_bytes(int size) struct device_node; +enum equalization_preset_type { + EQ_PRESET_TYPE_16GTS, + EQ_PRESET_TYPE_32GTS, + EQ_PRESET_TYPE_64GTS, + EQ_PRESET_TYPE_MAX +}; + +struct pci_eq_presets { + u16 eq_presets_8gts[MAX_NR_LANES]; + u8 eq_presets_Ngts[EQ_PRESET_TYPE_MAX][MAX_NR_LANES]; +}; + #ifdef CONFIG_OF int of_pci_parse_bus_range(struct device_node *node, struct resource *res); int of_get_pci_domain_nr(struct device_node *node); @@ -746,7 +760,9 @@ void pci_set_bus_of_node(struct pci_bus *bus); void pci_release_bus_of_node(struct pci_bus *bus); int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); - +int of_pci_get_equalization_presets(struct device *dev, + struct pci_eq_presets *presets, + int num_lanes); #else static inline int of_pci_parse_bus_range(struct device_node *node, struct resource *res) @@ -793,6 +809,12 @@ static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_br return 0; } +static inline int of_pci_get_equalization_presets(struct device *dev, + struct pci_eq_presets *presets, + int num_lanes) +{ + return 0; +} #endif /* CONFIG_OF */ struct of_changeset; From patchwork Fri Jan 24 11:22:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13949301 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82D9621C17B for ; Fri, 24 Jan 2025 11:23:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737717801; cv=none; b=XPGpEXoxuABk3zLbsLH/DqK3g8buQjQwTm3orfDKqSKtPqxXZ8knShnBF1CVTWNTYAr3R9/4BdqpdxGCZj9/ArB/Wc2ifbWKxIO45Vt17/nZvvvsWYoupxSSGnIVIb8sndCJBMz79W83qS1bUHP6mJLg7ITnhwj63DXW7jrJfbU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737717801; c=relaxed/simple; bh=5rxRkPnumzzfAdemdZBFDf4pCGC4z3dLReWUJOLysOk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eEEQhTE1Z4TmwyRAaTCj9G4GPkF/CEZm/aQn5eYkiski8R5W3U1v8hxmikCTFYDZEVuXfni3QRVl56rjFjwQA//9e9l8G/XAFvFGQmx97Gm4zSPK/nek3LQpYIyCcsCQIiY7sD7+/5sjUq2LUrHKyIwIYMjZ9p08+3esirGYHlE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=D5NYFeEC; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="D5NYFeEC" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 50O8HRGv002999 for ; Fri, 24 Jan 2025 11:23:19 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= yQsJM/reDtTZynjk4EeE4bMecMMhIsTfkx5E7VPjZRU=; b=D5NYFeECrB+NIu2h 0RjuRpUEOxguxk9hUACSGBKDDxE71BQn0PWFc6KO3j7zTlHLAt0o2ky4Ao+8XKtl 2zQ3rWfdUNtddM9z9k+5HCD01oknrLI6JnEe+Do7/vrQTCRlrRR8uGCUlVUrx0nR 7kveaNHmapp4HOqsWjmk/IpidsBSKmIh27p66QgDh5bd2FGJnGh8FUD0c16LYPhm gMrp5OZot+3wCkSQ11hZsreTMgFhg82YxNs0b66bWkRdXo4whZ16DvHRjTdR5eJB JuYwNnLNoaGk9V4bR7D9qVtt0aEpokDyNgPDskvkKymWdj2bQZ7k4Vw9+S/90VYJ 0R6Umw== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44c77n8j9r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Fri, 24 Jan 2025 11:23:18 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-216430a88b0so40556695ad.0 for ; Fri, 24 Jan 2025 03:23:18 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737717798; x=1738322598; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yQsJM/reDtTZynjk4EeE4bMecMMhIsTfkx5E7VPjZRU=; b=cc2GlB2IkLKaZgQj6MDTJs0lZjP0OkLXvSUhTcvcaU95Z1/ApxHV4r4CQaj88j5+71 FEWa5GTnWgm88Q2gRsM8cHGpcvW2db5vp+UKj4GpgKO+4YuclB/VKSwMV19/o/JvgEv5 3ClI4u7G8Dh0itgwaE9QV++c2Z9FrC7JvGw349Jp8Fv2z+9BoVQcGOtmmUpLAUG3eQsq G84XRNgvQb639+3PjlKXpkV6Lu/LvRfBlfAeGaIDTLEPoyV4v3sE39ogPUeCxqZVUh/m BlNnN/KppXh7a9I0FVdNUBdLLST0YKn6ah0Ex/3zwRplrlcuIC8yxTEKno+v4mSYC0ST nStg== X-Gm-Message-State: AOJu0YyIRcEQWIifvrruPZEY03+hNFqnKayhne4SScqlsS9H6tMpcrk9 qGcGyMXGQ7oElj1jTe2j1G06ETgNldDyEz65WK88e3sZ1G/uC+PDaxKLCt36OtgHLK2lP4IeyeX fdLcPyZHJpFYeQLUvsTAF0pOhDQibVQUVoazRxBM5ANJhUvrxTtXdP8XTx+nVRp1e X-Gm-Gg: ASbGncvcYVHB8aID+zP9k9o4NdFZhSZYaKeKZXeBA3XJLWFc85aC8GVo6wxPo/cOWzX v96j5tkPUr3WPawaYrJMB7bf8OQM2gF7olzi1DEdefykpkXdlBqz0T2dNDC9QtyRoX6mjDwHygO GUkwc1/s2mbGIj8IqerlTBf5ixf/QSUVHyllCoKDUHcZKRG5kJdTVTfSn3NuHDAEUUQ18khZJfQ hhzQUmqwQxQIP4MnxQKfdaQnjjcu1C9VaTJYfyZmAfUjsuCMX1sxUra1WoNoY6l7HUJ4P+sT5wT bbigIF9LPndm2RImqEOOVcORzW6cGw== X-Received: by 2002:a17:902:ea11:b0:216:3889:6f6f with SMTP id d9443c01a7336-21c353ef827mr388132695ad.17.1737717797951; Fri, 24 Jan 2025 03:23:17 -0800 (PST) X-Google-Smtp-Source: AGHT+IF3Jqk6JwmPr0oV22Ct9YC/haBNCR5+wlGUm1dWyD9lp1UJigU4ZqRujgW8yn5pehGWZ6HDsQ== X-Received: by 2002:a17:902:ea11:b0:216:3889:6f6f with SMTP id d9443c01a7336-21c353ef827mr388132335ad.17.1737717797512; Fri, 24 Jan 2025 03:23:17 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21da414cc20sm14025385ad.165.2025.01.24.03.23.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 03:23:17 -0800 (PST) From: Krishna Chaitanya Chundru Date: Fri, 24 Jan 2025 16:52:49 +0530 Subject: [PATCH v4 3/4] PCI: dwc: Improve handling of PCIe lane configuration Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250124-preset_v2-v4-3-0b512cad08e1@oss.qualcomm.com> References: <20250124-preset_v2-v4-0-0b512cad08e1@oss.qualcomm.com> In-Reply-To: <20250124-preset_v2-v4-0-0b512cad08e1@oss.qualcomm.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, konrad.dybcio@oss.qualcomm.com, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com, Bjorn Andersson , Konrad Dybcio , Krishna Chaitanya Chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1737717776; l=3448; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=5rxRkPnumzzfAdemdZBFDf4pCGC4z3dLReWUJOLysOk=; b=DonzVQzdHIl/WfHGG9u0Cqbhe1IO8nnLwtceD1UvRCtOb+1eL/WEb1u3AvWnzxwtvnu2w+jjh /JUC2z5bR+ZBzFWy77WB08SVCXfQqFBvYWAlzX4NH0b3nqUKL7QSwTF X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: 0Il5zI7WdQsYejWNhHLxkM5IacXWHiaa X-Proofpoint-ORIG-GUID: 0Il5zI7WdQsYejWNhHLxkM5IacXWHiaa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-24_04,2025-01-23_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 mlxlogscore=999 clxscore=1015 adultscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501240082 Currently even if the number of lanes hardware supports is equal to the number lanes provided in the devicetree, the driver is trying to configure again the maximum number of lanes which is not needed. Update number of lanes only when it is not equal to hardware capability. And also if the num-lanes property is not present in the devicetree update the num_lanes with the maximum hardware supports. Introduce dw_pcie_link_get_max_link_width() to get the maximum lane width the hardware supports. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++ drivers/pci/controller/dwc/pcie-designware.c | 14 +++++++++++++- drivers/pci/controller/dwc/pcie-designware.h | 1 + 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 3e41865c7290..2cd0acbf9e18 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -504,6 +504,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) dw_pcie_iatu_detect(pci); + if (pci->num_lanes < 1) + pci->num_lanes = dw_pcie_link_get_max_link_width(pci); + /* * Allocate the resource for MSG TLP before programming the iATU * outbound window in dw_pcie_setup_rc(). Since the allocation depends diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 6d6cbc8b5b2c..acb2a963ae1a 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -736,6 +736,16 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) } +int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) +{ + u32 lnkcap; + u8 cap; + + cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); + return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap); +} + static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) { u32 lnkcap, lwsc, plc; @@ -1069,6 +1079,7 @@ void dw_pcie_edma_remove(struct dw_pcie *pci) void dw_pcie_setup(struct dw_pcie *pci) { + int num_lanes = dw_pcie_link_get_max_link_width(pci); u32 val; dw_pcie_link_set_max_speed(pci); @@ -1102,5 +1113,6 @@ void dw_pcie_setup(struct dw_pcie *pci) val |= PORT_LINK_DLL_LINK_EN; dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); - dw_pcie_link_set_max_link_width(pci, pci->num_lanes); + if (num_lanes != pci->num_lanes) + dw_pcie_link_set_max_link_width(pci, pci->num_lanes); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 347ab74ac35a..500e793c9361 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -486,6 +486,7 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val); int dw_pcie_link_up(struct dw_pcie *pci); void dw_pcie_upconfig_setup(struct dw_pcie *pci); int dw_pcie_wait_for_link(struct dw_pcie *pci); +int dw_pcie_link_get_max_link_width(struct dw_pcie *pci); int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, const struct dw_pcie_ob_atu_cfg *atu); int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, From patchwork Fri Jan 24 11:22:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13949302 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1477721A952 for ; Fri, 24 Jan 2025 11:23:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737717806; cv=none; b=HB7FsJE5CJ3g75XisA+3jcdNcIgTkulQ0P3K0hofW1c4qBl76olT2FWpjPdaZmMNdK8+nSa2+6S7v53C2nPetbYuK+cJGBOLMyhigj9unhc6ohp0cbN5aJozlyKzh60Mth5Icjl5Qm3jTjtK75vqy32Ai+KJ9nsDravo5ItxR5A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737717806; c=relaxed/simple; bh=aAQ+D093YPpgryfubEJA4YQRIxQgMZqUwYCwdO3dLmA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=J9pMZmONd3U5ej+31sJXgf/GMOASkOs+s/zUpdgYMDkht7sN6aI4CWLd0cimdDcI/riB92vCJga6dbQRLCRD3Dcml67oGLn8uLy9lJzb3uUopxJAoRcs/hi42nkcaLzPP3g3s52yoDlHOdWGNY6XuJyCsYGo+E3AL7V+1Ml/gh4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=jY85dQoY; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="jY85dQoY" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 50OAoUXS025507 for ; Fri, 24 Jan 2025 11:23:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= iDG9cPvoCK8z7X2aaaeCh0RKjsgrck+iVE1+Sq1KuNQ=; b=jY85dQoY1iihLG9Z VN0RjJswK9xU36xn5wzhEL1JDkC12+wKM/pO5kmNnZk+TK0wqjoEog+C1iIz63ux OZjPYcsVBH0IJZ5w7f0Dsherwz2Mgsr9jikMhkxblCviGJ86QVSX3EFCoQFsiFJE yd4I+RHRse3byQGJVWIqXd7mlOLVi8HhiEcw+VF06Vnk8i67AARI6URwDLNaFczv CXmCRhZeX0e/RqKlOhKOpXexsU3wfgQvnXa09qTXnadEjpZRSbsJmx/fu8XeYK9B nvt3tnHQW9imFId4Eqf98EDOcckQocwKDFm289KH2sRVb9Ygs60CLqVceodDFmHb e2yMnQ== Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44c9fd03n3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Fri, 24 Jan 2025 11:23:24 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-216728b170cso39937405ad.2 for ; Fri, 24 Jan 2025 03:23:24 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737717803; x=1738322603; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iDG9cPvoCK8z7X2aaaeCh0RKjsgrck+iVE1+Sq1KuNQ=; b=vQT1hQHRvYqURv4CTWKnNDZ7+mT8h/toflsS83s6XyUlqEa2W6GCW67iE87ZpM19tY hhC6IIH37IXhOgCfuWQfJWSnXrJmYJZZlrK9fRuRHgEqHaYlY8ZX7NHNs1DX6p2l9Zqi 7gOLavDl+5FBylRp+5CZUIuE2FAGF3OITCRRSL6xobqdrfoAJhOI/9p9wEo6GUq8VXky teYwjk87DDHK4Obe23WcaHxfaGieliSkd2zA6KOvnCblFxJEvcSVNZoP80xdLRESkuy9 tHACFB6W1yXL/B7NHZv1k2WHM7lPVUOgkv56f4k6mLZi9ItvTqcMgkHcjjtjRJWVHo0K /Iog== X-Gm-Message-State: AOJu0YxQVlT27GFKT+7UGqfJcZf5LitRU6gYpGrtp1tYQHIMplAV0lIe 0ti0FEWT6POAyH9z8Z1b/Vgzg0xjCHCm+SN7+bzS5VNob2xeyBZSTUsL4Mtwu1V94riUh4bwZ3G ODfZ6fy/+kXFswINcceogfEZ/qGH3s3dvORJLyWNzRrr7PU8km5Dleg+9ESAzNjm6 X-Gm-Gg: ASbGncsDzfco+7YM4rGQ8JacEzCoaLW/BrHCnunovhWYHTAbRmu4Ncj+YhuFNUd9F5N EVrzlH8E6aQEkolrZmemRIL4Ek6LU/sIAsooUY7JJsGbL1wQvsGgWNAQRx4c0qdZzkvYUw6OcfR 87b9Sfcd76YOu3fFGhdR53DPs9HQ3Yh2CmcbtETl8FZ6DfoVWBSbiOAINXXx0e+6GK4cCzSdVH5 x9mJCL8mrQ6x1Ma5pWy5mlEOXw0yZ0VvO2+kM9b7tAQgXZbVRq1GHovLb28AOdyUVPdC01TwTFX UOcv1zTbBxSlwjK984em9iOQD6b+Pw== X-Received: by 2002:a17:902:eccd:b0:216:410d:4c67 with SMTP id d9443c01a7336-21c355c8efbmr494063155ad.41.1737717803263; Fri, 24 Jan 2025 03:23:23 -0800 (PST) X-Google-Smtp-Source: AGHT+IFNcJImFw4UsAKq5Do4gBFlgHd9ffTPhv64PVSXU5XRkZR6vPBecdycKhiJ4wLS04GjTnsMOA== X-Received: by 2002:a17:902:eccd:b0:216:410d:4c67 with SMTP id d9443c01a7336-21c355c8efbmr494062655ad.41.1737717802771; Fri, 24 Jan 2025 03:23:22 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21da414cc20sm14025385ad.165.2025.01.24.03.23.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 03:23:22 -0800 (PST) From: Krishna Chaitanya Chundru Date: Fri, 24 Jan 2025 16:52:50 +0530 Subject: [PATCH v4 4/4] PCI: dwc: Add support for configuring lane equalization presets Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250124-preset_v2-v4-4-0b512cad08e1@oss.qualcomm.com> References: <20250124-preset_v2-v4-0-0b512cad08e1@oss.qualcomm.com> In-Reply-To: <20250124-preset_v2-v4-0-0b512cad08e1@oss.qualcomm.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, konrad.dybcio@oss.qualcomm.com, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com, Bjorn Andersson , Konrad Dybcio , Krishna Chaitanya Chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1737717776; l=4571; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=aAQ+D093YPpgryfubEJA4YQRIxQgMZqUwYCwdO3dLmA=; b=zCquekUDbmf6cUZgPiq91xAlARj7f0SrBOVKD9h7yHqvGVwQ4bbjaXOJlFfJEa9ac27BiOr/E j+BC9Oj5Gv5BW5Si3aH7b6v13mKdWRMRXkIAHpJtElNMyPS4taqzWpp X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-ORIG-GUID: oMMHlsnoCdMhYro42xhnHaVShAaRbftv X-Proofpoint-GUID: oMMHlsnoCdMhYro42xhnHaVShAaRbftv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-24_04,2025-01-23_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 suspectscore=0 adultscore=0 phishscore=0 priorityscore=1501 spamscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 impostorscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501240083 PCIe equalization presets are predefined settings used to optimize signal integrity by compensating for signal loss and distortion in high-speed data transmission. Based upon the number of lanes and the data rate supported, write the preset data read from the device tree in to the lane equalization control registers. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 41 +++++++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 3 ++ include/uapi/linux/pci_regs.h | 3 ++ 3 files changed, 47 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 2cd0acbf9e18..eced862fb8dd 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -507,6 +507,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (pci->num_lanes < 1) pci->num_lanes = dw_pcie_link_get_max_link_width(pci); + ret = of_pci_get_equalization_presets(dev, &pp->presets, pci->num_lanes); + if (ret) + goto err_free_msi; + /* * Allocate the resource for MSG TLP before programming the iATU * outbound window in dw_pcie_setup_rc(). Since the allocation depends @@ -802,6 +806,42 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) return 0; } +static void dw_pcie_program_presets(struct dw_pcie *pci, u8 cap_id, u8 lane_eq_offset, + u8 lane_reg_size, u8 *presets, u8 num_lanes) +{ + u32 cap; + int i; + + cap = dw_pcie_find_ext_capability(pci, cap_id); + if (!cap) + return; + + /* + * Write preset values to the registers byte-by-byte for the given + * number of lanes and register size. + */ + for (i = 0; i < num_lanes * lane_reg_size; i++) + dw_pcie_writeb_dbi(pci, cap + lane_eq_offset + i, presets[i]); +} + +static void dw_pcie_config_presets(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + enum pci_bus_speed speed = pcie_link_speed[pci->max_link_speed]; + + /* For data rate of 8 GT/S each lane equalization control is 16bits wide */ + if (speed >= PCIE_SPEED_8_0GT && pp->presets.eq_presets_8gts[0] != 0xff) + dw_pcie_program_presets(pci, PCI_EXT_CAP_ID_SECPCI, PCI_SECPCI_LE_CTRL, + 0x2, (u8 *)pp->presets.eq_presets_8gts, pci->num_lanes); + + /* For data rate of 16 GT/S each lane equalization control is 8bits wide */ + if (speed >= PCIE_SPEED_16_0GT && + pp->presets.eq_presets_Ngts[EQ_PRESET_TYPE_16GTS][0] != 0xff) + dw_pcie_program_presets(pci, PCI_EXT_CAP_ID_PL_16GT, PCI_PL_16GT_LE_CTRL, + 0x1, pp->presets.eq_presets_Ngts[EQ_PRESET_TYPE_16GTS], + pci->num_lanes); +} + int dw_pcie_setup_rc(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -855,6 +895,7 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) PCI_COMMAND_MASTER | PCI_COMMAND_SERR; dw_pcie_writel_dbi(pci, PCI_COMMAND, val); + dw_pcie_config_presets(pp); /* * If the platform provides its own child bus config accesses, it means * the platform uses its own address translation component rather than diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 500e793c9361..b12b33944df4 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -25,6 +25,8 @@ #include #include +#include "../../pci.h" + /* DWC PCIe IP-core versions (native support since v4.70a) */ #define DW_PCIE_VER_365A 0x3336352a #define DW_PCIE_VER_460A 0x3436302a @@ -379,6 +381,7 @@ struct dw_pcie_rp { bool use_atu_msg; int msg_atu_index; struct resource *msg_res; + struct pci_eq_presets presets; }; struct dw_pcie_ep_ops { diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 12323b3334a9..68fc8873bc60 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1118,6 +1118,9 @@ #define PCI_DLF_CAP 0x04 /* Capabilities Register */ #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */ +/* Secondary PCIe Capability 8.0 GT/s */ +#define PCI_SECPCI_LE_CTRL 0x0c /* Lane Equalization Control Register */ + /* Physical Layer 16.0 GT/s */ #define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ #define PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK 0x0000000F