From patchwork Tue Jan 28 16:14:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13952748 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B3DC2C02192 for ; Tue, 28 Jan 2025 16:16:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcoEx-0005J1-QJ; Tue, 28 Jan 2025 11:15:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcoEu-0005Hp-JU for qemu-devel@nongnu.org; Tue, 28 Jan 2025 11:15:00 -0500 Received: from nyc.source.kernel.org ([147.75.193.91]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcoEs-0002c1-Up for qemu-devel@nongnu.org; Tue, 28 Jan 2025 11:15:00 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 5B0D2A40FAC; Tue, 28 Jan 2025 16:13:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B3F36C4CEDF; Tue, 28 Jan 2025 16:14:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738080894; bh=S9HK0xeqqBFQ5Dh/ahazUko2s71TwD5ZiEw7SlIeLeU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bzpGrhO1zHjZnScmLs14a/jGKsJiYEFGEUb8ZZLTU2DeYCmgD86+X084+EhCL3Jhb vvtaSy/z0jJK1TzJwlVwaq998ZWisYvh+Afh1RC0qeFx/n2Q3SUU+DQXNkHZB5xSUA cMeyxdUxwm1z/hcUSTw16Rm6QYAbQqiqpzCu47IP/KXrNvJk1X6sj22M7pkblhJi6o bIgBybQna2sV4CSRjcduYWUVIWYvt+GYFHDFhAGIdH7UiOqTDPreWNcE0ncAONIsnY momZnTw360z4ON75hhOanS5aMOrBl76KqimGbk3AfiGjm/W4B5o76Jbro6tPB3ybOj 4WF/osW0nMpPA== From: deller@kernel.org To: qemu-devel@nongnu.org, Richard Henderson Cc: Helge Deller , Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PATCH 1/5] hppa: Sync contents of hppa_hardware.h header file with SeaBIOS-hppa Date: Tue, 28 Jan 2025 17:14:46 +0100 Message-ID: <20250128161450.12975-2-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250128161450.12975-1-deller@kernel.org> References: <20250128161450.12975-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=147.75.193.91; envelope-from=deller@kernel.org; helo=nyc.source.kernel.org X-Spam_score_int: -56 X-Spam_score: -5.7 X-Spam_bar: ----- X-Spam_report: (-5.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller The hppa_hardware.h header file holds many constants for addresses and offsets which are needed while building the firmware (SeaBIOS-hppa) and while setting up the virtual machine in QEMU. This patch brings it in sync between both source code repositories. Signed-off-by: Helge Deller Acked-by: Richard Henderson --- hw/hppa/hppa_hardware.h | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/hw/hppa/hppa_hardware.h b/hw/hppa/hppa_hardware.h index a276240967..21c777cba6 100644 --- a/hw/hppa/hppa_hardware.h +++ b/hw/hppa/hppa_hardware.h @@ -6,6 +6,11 @@ #define FIRMWARE_START 0xf0000000 #define FIRMWARE_END 0xf0800000 +#define FIRMWARE_HIGH 0xfffffff0 /* upper 32-bits of 64-bit firmware address */ + +#define RAM_MAP_HIGH 0x0100000000 /* memory above 3.75 GB is mapped here */ + +#define MEM_PDC_ENTRY 0x4800 /* PDC entry address */ #define DEVICE_HPA_LEN 0x00100000 @@ -18,6 +23,7 @@ #define LASI_UART_HPA 0xffd05000 #define LASI_SCSI_HPA 0xffd06000 #define LASI_LAN_HPA 0xffd07000 +#define LASI_RTC_HPA 0xffd09000 #define LASI_LPT_HPA 0xffd02000 #define LASI_AUDIO_HPA 0xffd04000 #define LASI_PS2KBD_HPA 0xffd08000 @@ -27,16 +33,23 @@ #define CPU_HPA 0xfffb0000 #define MEMORY_HPA 0xfffff000 -#define PCI_HPA DINO_HPA /* PCI bus */ #define IDE_HPA 0xf9000000 /* Boot disc controller */ +#define ASTRO_HPA 0xfed00000 +#define ELROY0_HPA 0xfed30000 +#define ELROY2_HPA 0xfed32000 +#define ELROY8_HPA 0xfed38000 +#define ELROYc_HPA 0xfed3c000 +#define ASTRO_MEMORY_HPA 0xfed10200 + +#define SCSI_HPA 0xf1040000 /* emulated SCSI, needs to be in f region */ /* offsets to DINO HPA: */ #define DINO_PCI_ADDR 0x064 #define DINO_CONFIG_DATA 0x068 #define DINO_IO_DATA 0x06c -#define PORT_PCI_CMD (PCI_HPA + DINO_PCI_ADDR) -#define PORT_PCI_DATA (PCI_HPA + DINO_CONFIG_DATA) +#define PORT_PCI_CMD hppa_port_pci_cmd +#define PORT_PCI_DATA hppa_port_pci_data #define FW_CFG_IO_BASE 0xfffa0000 @@ -46,9 +59,24 @@ #define HPPA_MAX_CPUS 16 /* max. number of SMP CPUs */ #define CPU_CLOCK_MHZ 250 /* emulate a 250 MHz CPU */ +#define CR_PSW_DEFAULT 6 /* used by SeaBIOS & QEMU for default PSW */ #define CPU_HPA_CR_REG 7 /* store CPU HPA in cr7 (SeaBIOS internal) */ #define PIM_STORAGE_SIZE 600 /* storage size of pdc_pim_toc_struct (64bit) */ -#define RAM_MAP_HIGH 0x0100000000 /* memory above 3.75 GB is mapped here */ +#define ASTRO_BUS_MODULE 0x0a /* C3700: 0x0a, others maybe 0 ? */ + +/* ASTRO Memory and I/O regions */ +#define ASTRO_BASE_HPA 0xfffed00000 +#define ELROY0_BASE_HPA 0xfffed30000 /* ELROY0_HPA */ + +#define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */ + +#define LMMIO_DIRECT0_BASE 0x300 +#define LMMIO_DIRECT0_MASK 0x308 +#define LMMIO_DIRECT0_ROUTE 0x310 + +/* space register hashing */ +#define HPPA64_DIAG_SPHASH_ENABLE 0x200 /* DIAG_SPHASH_ENAB (bit 54) */ +#define HPPA64_PDC_CACHE_RET_SPID_VAL 0xfe0 /* PDC return value on 64-bit CPU */ #endif From patchwork Tue Jan 28 16:14:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13952744 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DAEB1C02194 for ; Tue, 28 Jan 2025 16:16:03 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcoF0-0005LZ-4i; Tue, 28 Jan 2025 11:15:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcoEx-0005J3-Qw for qemu-devel@nongnu.org; Tue, 28 Jan 2025 11:15:04 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcoEv-0002ca-Sn for qemu-devel@nongnu.org; Tue, 28 Jan 2025 11:15:03 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id C3EAB5C5B0B; Tue, 28 Jan 2025 16:14:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 61CC0C4CED3; Tue, 28 Jan 2025 16:14:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738080896; bh=WbGGD4NOS2h1QHYyZLIzVRv+R3c/kYBil40V5zV5alc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uLAYYnymqtjbXdLzzVK8euyo9Bz2mlKKn3MtUKTV4slgmonvGL0FTtfAlrph2U+oE ZaUCezAP7gyOjHgF5Y20AfqC/KJLyQwDzi3mbZ2uTjiwblZtTpv2Dkgm1FGMxgHSoO 1l7WWgBx8xivjaW3qS3CsfvRLXVDeY1xRYmEfk8K4K9cHGmRf22uu2XKF/ybFtVTBY +9CsbuJEGcf7eDDKlxlwmYMQ+NSyIhWYpSX4oscEdLJchd7EMTTYmXvRzk6J5TQeDv 6/c3yqKw+0hS/qTqojkY5y1rI7UN+0AKxUCOpGZIPFhg7M+ZIXufLvdUKLOZTNEj1J hXeJuynkFciRg== From: deller@kernel.org To: qemu-devel@nongnu.org, Richard Henderson Cc: Helge Deller , Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PATCH 2/5] disas/hppa: implement mfdiag/mtdiag disassembly Date: Tue, 28 Jan 2025 17:14:47 +0100 Message-ID: <20250128161450.12975-3-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250128161450.12975-1-deller@kernel.org> References: <20250128161450.12975-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=139.178.84.217; envelope-from=deller@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -83 X-Spam_score: -8.4 X-Spam_bar: -------- X-Spam_report: (-8.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller The various PA-RISC CPUs implement different CPU-specific diag instructions (mfdiag, mtdiag, mfcpu, mtcpu, ...) to access CPU-internal diagnose/configuration registers, e.g. for cache control, managing space register hashing, control front panel LEDs and read status of the hardware reset button. Those instructions are mostly undocumented, but are used by ODE, HP-UX and Linux. This patch adds some neccessary instructions for PCXL and PCXU CPUs. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson --- disas/hppa.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/disas/hppa.c b/disas/hppa.c index 49e2231ae6..2b58434966 100644 --- a/disas/hppa.c +++ b/disas/hppa.c @@ -606,7 +606,7 @@ struct pa_opcode In the args field, the following characters are unused: - ' " - / 34 6789:; ' + ' " - / 34 678 :; ' '@ C M [\] ' '` e g } ' @@ -650,6 +650,7 @@ Also these: | 6 bit field length at 19,27:31 (fixed extract/deposit) A 13 bit immediate at 18 (to support the BREAK instruction) ^ like b, but describes a control register + 9 like b, but describes a diagnose register ! sar (cr11) register D 26 bit immediate at 31 (to support the DIAG instruction) $ 9 bit immediate at 28 (to support POPBTS) @@ -1322,13 +1323,19 @@ static const struct pa_opcode pa_opcodes[] = { "fdce", 0x040012c0, 0xfc00ffdf, "cZx(b)", pa10, 0}, { "fdce", 0x040012c0, 0xfc003fdf, "cZx(s,b)", pa10, 0}, { "fice", 0x040002c0, 0xfc001fdf, "cZx(S,b)", pa10, 0}, -{ "diag", 0x14000000, 0xfc000000, "D", pa10, 0}, { "idtlbt", 0x04001800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, { "iitlbt", 0x04000800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, +/* completely undocumented, but used by ODE, HP-UX and Linux: */ +{ "mfcpu_pcxu", 0x140008a0, 0xfc9fffe0, "9,t", pa20, 0}, /* PCXU: mfdiag */ +{ "mtcpu_pcxu", 0x14001840, 0xfc00ffff, "x,9", pa20, 0}, + /* These may be specific to certain versions of the PA. Joel claimed they were 72000 (7200?) specific. However, I'm almost certain the mtcpu/mfcpu were undocumented, but available in the older 700 machines. */ +{ "mfcpu_c", 0x14000600, 0xfc00ffff, "9,x", pa10, 0}, /* PCXL: for dr0 and dr8 only */ +{ "mfcpu_t", 0x14001400, 0xfc9fffe0, "9,t", pa10, 0}, /* PCXL: all dr except dr0 and dr8 */ +{ "mtcpu_pcxl", 0x14000240, 0xfc00ffff, "x,9", pa11, 0}, /* PCXL: mtcpu for dr0 and dr8 */ { "mtcpu", 0x14001600, 0xfc00ffff, "x,^", pa10, 0}, { "mfcpu", 0x14001A00, 0xfc00ffff, "^,x", pa10, 0}, { "tocen", 0x14403600, 0xffffffff, "", pa10, 0}, @@ -1336,6 +1343,9 @@ static const struct pa_opcode pa_opcodes[] = { "shdwgr", 0x14402600, 0xffffffff, "", pa10, 0}, { "grshdw", 0x14400620, 0xffffffff, "", pa10, 0}, +/* instead of showing D only, show all other registers too */ +{ "diag", 0x14000000, 0xfc000000, "D x,9,t", pa10, 0}, + /* gfw and gfr are not in the HP PA 1.1 manual, but they are in either the Timex FPU or the Mustang ERS (not sure which) manual. */ { "gfw", 0x04001680, 0xfc00ffdf, "cZx(b)", pa11, 0}, @@ -1801,6 +1811,12 @@ fput_creg (unsigned reg, disassemble_info *info) (*info->fprintf_func) (info->stream, "%s", control_reg[reg]); } +static void +fput_dreg (unsigned reg, disassemble_info *info) +{ + (*info->fprintf_func) (info->stream, "dr%d", reg); +} + /* Print constants with sign. */ static void @@ -2007,6 +2023,9 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info) case '^': fput_creg (GET_FIELD (insn, 6, 10), info); break; + case '9': + fput_dreg (GET_FIELD (insn, 6, 10), info); + break; case 't': fput_reg (GET_FIELD (insn, 27, 31), info); break; From patchwork Tue Jan 28 16:14:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13952745 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 574CEC0218A for ; Tue, 28 Jan 2025 16:16:03 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcoF1-0005NM-Iy; Tue, 28 Jan 2025 11:15:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcoEy-0005Jy-Kd for qemu-devel@nongnu.org; Tue, 28 Jan 2025 11:15:05 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcoEu-0002cb-Rv for qemu-devel@nongnu.org; Tue, 28 Jan 2025 11:15:04 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 6D6935C606A; Tue, 28 Jan 2025 16:14:18 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0C8D6C4CED3; Tue, 28 Jan 2025 16:14:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738080898; bh=CBzHx4+oEw39j3XiP2C3P2o+NN58sL6gTPu1OQ12FQY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Icv17MhgZQUuRiaFmtcSnasO4IrQSir/hGcCm11iduufTpzKHU63Sw4UiCIIaW2+O U7PntP3ZoazexPOOrvHpcXbTBeie0tdsMTvDykRSKIwl4xXWBVC830AKo2yGAYBaYw ZKWtJbp6vXQzJDV/7sOef5VvO2SZ4BpTWUzH7la4OyoZrxIR4PP0Ir2e2PJC1hSMmM EuucRk6GjmY9eFdNhPHuNR7Za5UzTrZkSn8ct3NUvi40xZWRJkKywqx0Ky5sKPjbKA dtgNXzOpr/wvNRuZwYgWF2RdzOTyyavCqjyZ1cr4reEA3yj8EcUrm1N0WqeYjCriLp tcB6Zngt18QmQ== From: deller@kernel.org To: qemu-devel@nongnu.org, Richard Henderson Cc: Helge Deller , Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PATCH 3/5] target/hppa: Implement CPU diagnose registers for 64-bit HP-UX Date: Tue, 28 Jan 2025 17:14:48 +0100 Message-ID: <20250128161450.12975-4-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250128161450.12975-1-deller@kernel.org> References: <20250128161450.12975-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=139.178.84.217; envelope-from=deller@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -83 X-Spam_score: -8.4 X-Spam_bar: -------- X-Spam_report: (-8.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller PA-RISC CPUs have diagnose registers (%dr). Those are mostly undocumented and control cache behaviour, memory behaviour, reset button management and many other related internal CPU things. The Linux kernel turns space-register hashing off unconditionally at bootup. That code was provided by HP at the beginning of the PA-RISC Linux porting effort, and I don't know why it was decided then why Linux should not use space register hashing. 32-bit HP-UX versions seem to not use space register hashing either. But for 64-bit HP-UX versions, Sven Schnelle noticed that space register hashing needs to be enabled and is required, otherwise the HP-UX kernel will crash badly. On 64-bit CPUs space register hashing is controlled by a bit in diagnose register %dr2. Since we want to support Linux and 32- and 64-bit HP-UX, we need to fully emulate the diagnose registers and handle specifically the content of %dr2. Furthermore it turned out that commit 3bdf20819e68 seems wrong and conflicts with the general space register diagnose register, so it is partly reverted here. Signed-off-by: Helge Deller Suggested-by: Sven Schnelle Fixes: 3bdf20819e68 ("target/hppa: Add diag instructions to set/restore shadow registers") --- hw/hppa/machine.c | 5 +++++ target/hppa/cpu.c | 3 ++- target/hppa/cpu.h | 24 ++++++++++++++++-------- target/hppa/helper.c | 4 ++-- target/hppa/insns.decode | 6 ++++-- target/hppa/int_helper.c | 6 +++--- target/hppa/machine.c | 5 +++-- target/hppa/sys_helper.c | 2 +- target/hppa/translate.c | 24 +++++++++++++++++------- 9 files changed, 53 insertions(+), 26 deletions(-) diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 0dd1908214..d5de793b62 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -662,6 +662,11 @@ static void hppa_machine_reset(MachineState *ms, ResetType type) cpu_set_pc(cs, firmware_entry); cpu[i]->env.psw = PSW_Q; cpu[i]->env.gr[5] = CPU_HPA + i * 0x1000; + + /* 64-bit machines start with space-register hashing enabled in %dr2 */ + if (hppa_is_pa20(&cpu[0]->env)) { + cpu[i]->env.dr[2] = HPPA64_DIAG_SPHASH_ENABLE; /* (bit 54) */ + } } cpu[0]->env.gr[26] = ms->ram_size; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index b0bc9d35e4..9a83910cae 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -44,7 +44,8 @@ static vaddr hppa_cpu_get_pc(CPUState *cs) { CPUHPPAState *env = cpu_env(cs); - return hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), + return hppa_form_gva_psw(env, env->psw, + (env->psw & PSW_C ? env->iasq_f : 0), env->iaoq_f & -4); } diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index beea42d105..64e60a3980 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -25,6 +25,7 @@ #include "qemu/cpu-float.h" #include "qemu/interval-tree.h" #include "hw/registerfields.h" +#include "hw/hppa/hppa_hardware.h" #define MMU_ABS_W_IDX 6 #define MMU_ABS_IDX 7 @@ -232,6 +233,7 @@ typedef struct CPUArchState { target_ulong cr[32]; /* control registers */ target_ulong cr_back[2]; /* back of cr17/cr18 */ target_ulong shadow[7]; /* shadow registers */ + target_ulong dr[32]; /* diagnose registers */ /* * During unwind of a memory insn, the base register of the address. @@ -319,27 +321,33 @@ void hppa_translate_code(CPUState *cs, TranslationBlock *tb, #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU -static inline uint64_t gva_offset_mask(target_ulong psw) +static inline uint64_t gva_offset_mask(CPUHPPAState *env, target_ulong psw) { - return (psw & PSW_W - ? MAKE_64BIT_MASK(0, 62) - : MAKE_64BIT_MASK(0, 32)); + if (psw & PSW_W) { + return (env->dr[2] & HPPA64_DIAG_SPHASH_ENABLE) + ? MAKE_64BIT_MASK(0, 62) & + ~((uint64_t)HPPA64_PDC_CACHE_RET_SPID_VAL << 48) + : MAKE_64BIT_MASK(0, 62); + } else { + return MAKE_64BIT_MASK(0, 32); + } } -static inline target_ulong hppa_form_gva_psw(target_ulong psw, uint64_t spc, - target_ulong off) +static inline target_ulong hppa_form_gva_psw(CPUHPPAState *env, + target_ulong psw, + uint64_t spc, target_ulong off) { #ifdef CONFIG_USER_ONLY return off & gva_offset_mask(psw); #else - return spc | (off & gva_offset_mask(psw)); + return spc | (off & gva_offset_mask(env, psw)); #endif } static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, target_ulong off) { - return hppa_form_gva_psw(env->psw, spc, off); + return hppa_form_gva_psw(env, env->psw, spc, off); } hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr); diff --git a/target/hppa/helper.c b/target/hppa/helper.c index d4b1a3cd5a..cd7eeb5dfa 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -133,9 +133,9 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IA_F %08" PRIx64 ":%0*" PRIx64 " (" TARGET_FMT_lx ")\n" "IA_B %08" PRIx64 ":%0*" PRIx64 " (" TARGET_FMT_lx ")\n", env->iasq_f >> 32, w, m & env->iaoq_f, - hppa_form_gva_psw(psw, env->iasq_f, env->iaoq_f), + hppa_form_gva_psw(env, psw, env->iasq_f, env->iaoq_f), env->iasq_b >> 32, w, m & env->iaoq_b, - hppa_form_gva_psw(psw, env->iasq_b, env->iaoq_b)); + hppa_form_gva_psw(env, psw, env->iasq_b, env->iaoq_b)); psw_c[0] = (psw & PSW_W ? 'W' : '-'); psw_c[1] = (psw & PSW_E ? 'E' : '-'); diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 71074a64c1..4eaac750ea 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -644,10 +644,12 @@ xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64 # For 32-bit PA-7300LC (PCX-L2) diag_getshadowregs_pa1 000101 00 0000 0000 0001 1010 0000 0000 diag_putshadowregs_pa1 000101 00 0000 0000 0001 1010 0100 0000 + diag_mfdiag 000101 dr:5 rt:5 0000 0110 0000 0000 + diag_mtdiag 000101 dr:5 r1:5 0001 0110 0000 0000 # For 64-bit PA8700 (PCX-W2) - diag_getshadowregs_pa2 000101 00 0111 1000 0001 1000 0100 0000 - diag_putshadowregs_pa2 000101 00 0111 0000 0001 1000 0100 0000 + diag_mfdiag 000101 dr:5 0 0000 0000 1000 101 rt:5 + diag_mtdiag 000101 dr:5 r1:5 0001 1000 0100 0000 ] diag_unimp 000101 i:26 } diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 58695def82..5aefb3ade4 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -112,9 +112,9 @@ void hppa_cpu_do_interrupt(CPUState *cs) */ if (old_psw & PSW_C) { env->cr[CR_IIASQ] = - hppa_form_gva_psw(old_psw, env->iasq_f, env->iaoq_f) >> 32; + hppa_form_gva_psw(env, old_psw, env->iasq_f, env->iaoq_f) >> 32; env->cr_back[0] = - hppa_form_gva_psw(old_psw, env->iasq_b, env->iaoq_b) >> 32; + hppa_form_gva_psw(env, old_psw, env->iasq_b, env->iaoq_b) >> 32; } else { env->cr[CR_IIASQ] = 0; env->cr_back[0] = 0; @@ -165,7 +165,7 @@ void hppa_cpu_do_interrupt(CPUState *cs) if (old_psw & PSW_C) { int prot, t; - vaddr = hppa_form_gva_psw(old_psw, env->iasq_f, vaddr); + vaddr = hppa_form_gva_psw(env, old_psw, env->iasq_f, vaddr); t = hppa_get_physical_address(env, vaddr, MMU_KERNEL_IDX, 0, 0, &paddr, &prot); if (t >= 0) { diff --git a/target/hppa/machine.c b/target/hppa/machine.c index 211bfcf640..bb47a2e689 100644 --- a/target/hppa/machine.c +++ b/target/hppa/machine.c @@ -198,6 +198,7 @@ static const VMStateField vmstate_env_fields[] = { VMSTATE_UINT64(iasq_b, CPUHPPAState), VMSTATE_UINT32(fr0_shadow, CPUHPPAState), + VMSTATE_UINT64_ARRAY(dr, CPUHPPAState, 32), VMSTATE_END_OF_LIST() }; @@ -208,8 +209,8 @@ static const VMStateDescription * const vmstate_env_subsections[] = { static const VMStateDescription vmstate_env = { .name = "env", - .version_id = 3, - .minimum_version_id = 3, + .version_id = 4, + .minimum_version_id = 4, .fields = vmstate_env_fields, .subsections = vmstate_env_subsections, }; diff --git a/target/hppa/sys_helper.c b/target/hppa/sys_helper.c index da5b569de8..72bb9ea7b5 100644 --- a/target/hppa/sys_helper.c +++ b/target/hppa/sys_helper.c @@ -88,7 +88,7 @@ void HELPER(rfi)(CPUHPPAState *env) * To recreate the space identifier, remove the offset bits. * For pa1.x, the mask reduces to no change to space. */ - mask = gva_offset_mask(env->psw); + mask = gva_offset_mask(env, env->psw); env->iaoq_f = env->cr[CR_IIAOQ]; env->iaoq_b = env->cr_back[1]; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index dc04f9f3c0..45a40d2c5e 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1577,7 +1577,7 @@ static void form_gva(DisasContext *ctx, TCGv_i64 *pgva, TCGv_i64 *pofs, *pofs = ofs; *pgva = addr = tcg_temp_new_i64(); tcg_gen_andi_i64(addr, modify <= 0 ? ofs : base, - gva_offset_mask(ctx->tb_flags)); + gva_offset_mask(cpu_env(ctx->cs), ctx->tb_flags)); #ifndef CONFIG_USER_ONLY if (!is_phys) { tcg_gen_or_i64(addr, addr, space_select(ctx, sp, base)); @@ -4593,19 +4593,29 @@ static bool trans_diag_getshadowregs_pa1(DisasContext *ctx, arg_empty *a) return !ctx->is_pa20 && do_getshadowregs(ctx); } -static bool trans_diag_getshadowregs_pa2(DisasContext *ctx, arg_empty *a) +static bool trans_diag_putshadowregs_pa1(DisasContext *ctx, arg_empty *a) { - return ctx->is_pa20 && do_getshadowregs(ctx); + return !ctx->is_pa20 && do_putshadowregs(ctx); } -static bool trans_diag_putshadowregs_pa1(DisasContext *ctx, arg_empty *a) +static bool trans_diag_mfdiag(DisasContext *ctx, arg_diag_mfdiag *a) { - return !ctx->is_pa20 && do_putshadowregs(ctx); + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + TCGv_i64 dest = dest_gpr(ctx, a->rt); + tcg_gen_ld_i64(dest, tcg_env, + offsetof(CPUHPPAState, dr[a->dr])); + save_gpr(ctx, a->rt, dest); + return nullify_end(ctx); } -static bool trans_diag_putshadowregs_pa2(DisasContext *ctx, arg_empty *a) +static bool trans_diag_mtdiag(DisasContext *ctx, arg_diag_mtdiag *a) { - return ctx->is_pa20 && do_putshadowregs(ctx); + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + tcg_gen_st_i64(load_gpr(ctx, a->r1), tcg_env, + offsetof(CPUHPPAState, dr[a->dr])); + return nullify_end(ctx); } static bool trans_diag_unimp(DisasContext *ctx, arg_diag_unimp *a) From patchwork Tue Jan 28 16:14:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13952746 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 21BCDC0218A for ; Tue, 28 Jan 2025 16:16:28 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcoF2-0005OE-R4; Tue, 28 Jan 2025 11:15:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcoF1-0005NT-Om for qemu-devel@nongnu.org; Tue, 28 Jan 2025 11:15:07 -0500 Received: from nyc.source.kernel.org ([2604:1380:45d1:ec00::3]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcoEw-0002cw-5Z for qemu-devel@nongnu.org; Tue, 28 Jan 2025 11:15:07 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 53B34A40FB5; Tue, 28 Jan 2025 16:13:13 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AB2E5C4CEDF; Tue, 28 Jan 2025 16:14:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738080899; bh=rieKAeNe8lXPSuY7b1WGlRorofRyHpLWNTrPBSIP+fM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IaAGW7VdUmrRZLPiUqUl7RIRjJd0pX1UvYhwPNdNkyBZnra8HgGnkKZ3MRaJCCufD 5Qj/70AUikELFNCmj5Ezxzk6YFfaf9W54GTQaeOfT6ME17lw83fE1+X8nA96o9e6/Z Sx2GFAhLIFaY2lTuxAqrvQM1MbXFTVFiphyKHfpoAV0crtKdf+n2G5BvWBTlgOcEJj ULZQ1frZ6k7k2kX6YEBZ9nvqTAzuchQXraTBwKuqIHA2gH03Twc0gZ+i/s29OuSosq tIDTLn2g3cRuQSDnPaLCdrHqU5vIG/tZLjVerflLO+psYKtCqHhLsnuSnov2PEgxmN esgRuSj4eMdOw== From: deller@kernel.org To: qemu-devel@nongnu.org, Richard Henderson Cc: Helge Deller , Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PATCH 4/5] hw/char: Add emulation of Diva GSP PCI management boards Date: Tue, 28 Jan 2025 17:14:49 +0100 Message-ID: <20250128161450.12975-5-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250128161450.12975-1-deller@kernel.org> References: <20250128161450.12975-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2604:1380:45d1:ec00::3; envelope-from=deller@kernel.org; helo=nyc.source.kernel.org X-Spam_score_int: -56 X-Spam_score: -5.7 X-Spam_bar: ----- X-Spam_report: (-5.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller The Diva GSP ("Guardian Service Processor") PCI boards are Remote Management cards for PA-RISC machines. They come with built-in 16550A UARTs for serial consoles and modem functionalities, as well as a mailbox-like memory area for hardware auto-reboot functionality. Latest generation HP PA-RISC server machines use those Diva cards for console output. Signed-off-by: Helge Deller --- MAINTAINERS | 1 + hw/char/Kconfig | 5 + hw/char/diva-gsp.c | 291 ++++++++++++++++++++++++++++++++++++++++++++ hw/char/meson.build | 1 + 4 files changed, 298 insertions(+) create mode 100644 hw/char/diva-gsp.c diff --git a/MAINTAINERS b/MAINTAINERS index 7be3d8f431..c5e2d6b636 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1191,6 +1191,7 @@ M: Richard Henderson R: Helge Deller S: Odd Fixes F: configs/devices/hppa-softmmu/default.mak +F: hw/char/diva-gsp.c F: hw/display/artist.c F: hw/hppa/ F: hw/input/lasips2.c diff --git a/hw/char/Kconfig b/hw/char/Kconfig index 4b73a803bf..46bc03d321 100644 --- a/hw/char/Kconfig +++ b/hw/char/Kconfig @@ -78,3 +78,8 @@ config GOLDFISH_TTY config SHAKTI_UART bool + +config DIVA_GSP + bool + depends on PCI + select SERIAL diff --git a/hw/char/diva-gsp.c b/hw/char/diva-gsp.c new file mode 100644 index 0000000000..0c40d3964c --- /dev/null +++ b/hw/char/diva-gsp.c @@ -0,0 +1,291 @@ +/* + * HP Diva GSP controller + * + * The Diva PCI boards are Remote Management cards for PA-RISC machines. + * They come with built-in 16550A multi UARTs for serial consoles + * and a mailbox-like memory area for hardware auto-reboot functionality. + * GSP stands for "Guardian Service Processor". Later products were marketed + * "Management Processor" (MP). + * + * Diva cards are multifunctional cards. The first part, the Aux port, + * is on physical machines not useable but we still try to mimic it here. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Helge Deller + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/char/serial.h" +#include "hw/irq.h" +#include "hw/pci/pci_device.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-properties-system.h" +#include "migration/vmstate.h" + +#define PCI_DEVICE_ID_HP_DIVA 0x1048 +/* various DIVA GSP cards: */ +#define PCI_DEVICE_ID_HP_DIVA_TOSCA1 0x1049 +#define PCI_DEVICE_ID_HP_DIVA_TOSCA2 0x104A +#define PCI_DEVICE_ID_HP_DIVA_MAESTRO 0x104B +#define PCI_DEVICE_ID_HP_REO_IOC 0x10f1 +#define PCI_DEVICE_ID_HP_DIVA_HALFDOME 0x1223 +#define PCI_DEVICE_ID_HP_DIVA_KEYSTONE 0x1226 +#define PCI_DEVICE_ID_HP_DIVA_POWERBAR 0x1227 +#define PCI_DEVICE_ID_HP_DIVA_EVEREST 0x1282 +#define PCI_DEVICE_ID_HP_DIVA_AUX 0x1290 +#define PCI_DEVICE_ID_HP_DIVA_RMP3 0x1301 +#define PCI_DEVICE_ID_HP_DIVA_HURRICANE 0x132a + + +#define PCI_SERIAL_MAX_PORTS 4 + +typedef struct PCIDivaSerialState { + PCIDevice dev; + MemoryRegion membar; /* for serial ports */ + MemoryRegion mailboxbar; /* for hardware mailbox */ + uint32_t subvendor; + uint32_t ports; + char *name[PCI_SERIAL_MAX_PORTS]; + SerialState state[PCI_SERIAL_MAX_PORTS]; + uint32_t level[PCI_SERIAL_MAX_PORTS]; + qemu_irq *irqs; + uint8_t prog_if; +} PCIDivaSerialState; + +static void diva_pci_exit(PCIDevice *dev) +{ + PCIDivaSerialState *pci = DO_UPCAST(PCIDivaSerialState, dev, dev); + SerialState *s; + int i; + + for (i = 0; i < pci->ports; i++) { + s = pci->state + i; + qdev_unrealize(DEVICE(s)); + memory_region_del_subregion(&pci->membar, &s->io); + g_free(pci->name[i]); + } + qemu_free_irqs(pci->irqs, pci->ports); +} + +static void multi_serial_irq_mux(void *opaque, int n, int level) +{ + PCIDivaSerialState *pci = opaque; + int i, pending = 0; + + pci->level[n] = level; + for (i = 0; i < pci->ports; i++) { + if (pci->level[i]) { + pending = 1; + } + } + pci_set_irq(&pci->dev, pending); +} + +struct diva_info { + unsigned int nports:4; /* number of serial ports */ + unsigned int omask:12; /* offset mask: BIT(1) -> offset 8 */ +}; + +static struct diva_info diva_get_diva_info(PCIDeviceClass *pc) +{ + switch (pc->subsystem_id) { + case PCI_DEVICE_ID_HP_DIVA_POWERBAR: + case PCI_DEVICE_ID_HP_DIVA_HURRICANE: + return (struct diva_info) { .nports = 1, + .omask = BIT(0) }; + case PCI_DEVICE_ID_HP_DIVA_TOSCA2: + return (struct diva_info) { .nports = 2, + .omask = BIT(0) | BIT(1) }; + case PCI_DEVICE_ID_HP_DIVA_TOSCA1: + case PCI_DEVICE_ID_HP_DIVA_HALFDOME: + case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: + return (struct diva_info) { .nports = 3, + .omask = BIT(0) | BIT(1) | BIT(2) }; + case PCI_DEVICE_ID_HP_DIVA_EVEREST: /* e.g. in rp3410 */ + return (struct diva_info) { .nports = 3, + .omask = BIT(0) | BIT(2) | BIT(7) }; + case PCI_DEVICE_ID_HP_DIVA_MAESTRO: + return (struct diva_info) { .nports = 4, + .omask = BIT(0) | BIT(1) | BIT(2) | BIT(7) }; + } + g_assert_not_reached(); +} + + +static void diva_pci_realize(PCIDevice *dev, Error **errp) +{ + PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); + PCIDivaSerialState *pci = DO_UPCAST(PCIDivaSerialState, dev, dev); + SerialState *s; + struct diva_info di = diva_get_diva_info(pc); + size_t i, offset = 0; + size_t portmask = di.omask; + + pci->dev.config[PCI_CLASS_PROG] = pci->prog_if; + pci->dev.config[PCI_INTERRUPT_PIN] = 0x01; + memory_region_init(&pci->membar, OBJECT(pci), "serial_ports", 4096); + pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &pci->membar); + pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci, di.nports); + + for (i = 0; i < di.nports; i++) { + s = pci->state + i; + if (!qdev_realize(DEVICE(s), NULL, errp)) { + diva_pci_exit(dev); + return; + } + s->irq = pci->irqs[i]; + pci->name[i] = g_strdup_printf("uart #%zu", i + 1); + memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s, + pci->name[i], 8); + + /* calculate offset of given port based on bitmask */ + while ((portmask & BIT(0)) == 0) { + offset += 8; + portmask >>= 1; + } + memory_region_add_subregion(&pci->membar, offset, &s->io); + offset += 8; + portmask >>= 1; + pci->ports++; + } + + /* mailbox bar */ + memory_region_init(&pci->mailboxbar, OBJECT(pci), "mailbox", 128 * KiB); + pci_register_bar(&pci->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_PREFETCH, &pci->mailboxbar); +} + +static const VMStateDescription vmstate_pci_diva = { + .name = "pci-diva-serial", + .version_id = 1, + .minimum_version_id = 1, + .fields = (const VMStateField[]) { + VMSTATE_PCI_DEVICE(dev, PCIDivaSerialState), + VMSTATE_STRUCT_ARRAY(state, PCIDivaSerialState, PCI_SERIAL_MAX_PORTS, + 0, vmstate_serial, SerialState), + VMSTATE_UINT32_ARRAY(level, PCIDivaSerialState, PCI_SERIAL_MAX_PORTS), + VMSTATE_END_OF_LIST() + } +}; + +static const Property diva_serial_properties[] = { + DEFINE_PROP_CHR("chardev1", PCIDivaSerialState, state[0].chr), + DEFINE_PROP_CHR("chardev2", PCIDivaSerialState, state[1].chr), + DEFINE_PROP_CHR("chardev3", PCIDivaSerialState, state[2].chr), + DEFINE_PROP_CHR("chardev4", PCIDivaSerialState, state[3].chr), + DEFINE_PROP_UINT8("prog_if", PCIDivaSerialState, prog_if, 0x02), + DEFINE_PROP_UINT32("subvendor", PCIDivaSerialState, subvendor, + PCI_DEVICE_ID_HP_DIVA_TOSCA1), +}; + +static void diva_serial_class_initfn(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass); + pc->realize = diva_pci_realize; + pc->exit = diva_pci_exit; + pc->vendor_id = PCI_VENDOR_ID_HP; + pc->device_id = PCI_DEVICE_ID_HP_DIVA; + pc->subsystem_vendor_id = PCI_VENDOR_ID_HP; + pc->subsystem_id = PCI_DEVICE_ID_HP_DIVA_TOSCA1; + pc->revision = 3; + pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL; + dc->vmsd = &vmstate_pci_diva; + device_class_set_props(dc, diva_serial_properties); + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); +} + +static void diva_serial_init(Object *o) +{ + PCIDevice *dev = PCI_DEVICE(o); + PCIDivaSerialState *pms = DO_UPCAST(PCIDivaSerialState, dev, dev); + struct diva_info di = diva_get_diva_info(PCI_DEVICE_GET_CLASS(dev)); + size_t i; + + for (i = 0; i < di.nports; i++) { + object_initialize_child(o, "serial[*]", &pms->state[i], TYPE_SERIAL); + } +} + + +/* Diva-aux is the driver for portion 0 of the multifunction PCI device */ + +struct DivaAuxState { + PCIDevice dev; + MemoryRegion mem; + qemu_irq irq; +}; + +#define TYPE_DIVA_AUX "diva-aux" +OBJECT_DECLARE_SIMPLE_TYPE(DivaAuxState, DIVA_AUX) + +static void diva_aux_realize(PCIDevice *dev, Error **errp) +{ + DivaAuxState *pci = DO_UPCAST(DivaAuxState, dev, dev); + + pci->dev.config[PCI_CLASS_PROG] = 0x02; + pci->dev.config[PCI_INTERRUPT_PIN] = 0x01; + pci->irq = pci_allocate_irq(&pci->dev); + + memory_region_init(&pci->mem, OBJECT(pci), "mem", 16); + pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &pci->mem); +} + +static void diva_aux_exit(PCIDevice *dev) +{ + DivaAuxState *pci = DO_UPCAST(DivaAuxState, dev, dev); + qemu_free_irq(pci->irq); +} + +static void diva_aux_class_initfn(ObjectClass *klass, void *data) +{ + PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass); + pc->realize = diva_aux_realize; + pc->exit = diva_aux_exit; + pc->vendor_id = PCI_VENDOR_ID_HP; + pc->device_id = PCI_DEVICE_ID_HP_DIVA_AUX; + pc->subsystem_vendor_id = PCI_VENDOR_ID_HP; + pc->subsystem_id = 0x1291; + pc->revision = 1; + pc->class_id = PCI_CLASS_COMMUNICATION_MULTISERIAL; +} + +static void diva_aux_init(Object *o) +{ +} + +static const TypeInfo diva_aux_info = { + .name = TYPE_DIVA_AUX, + .parent = TYPE_PCI_DEVICE, + .instance_size = sizeof(DivaAuxState), + .instance_init = diva_aux_init, + .class_init = diva_aux_class_initfn, + .interfaces = (InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { }, + }, +}; + + + +static const TypeInfo diva_serial_pci_info = { + .name = "diva-serial", + .parent = TYPE_PCI_DEVICE, + .instance_size = sizeof(PCIDivaSerialState), + .instance_init = diva_serial_init, + .class_init = diva_serial_class_initfn, + .interfaces = (InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { }, + }, +}; + +static void diva_pci_register_type(void) +{ + type_register_static(&diva_serial_pci_info); + type_register_static(&diva_aux_info); +} + +type_init(diva_pci_register_type) diff --git a/hw/char/meson.build b/hw/char/meson.build index 1750834385..98fd86a48f 100644 --- a/hw/char/meson.build +++ b/hw/char/meson.build @@ -20,6 +20,7 @@ system_ss.add(when: 'CONFIG_SHAKTI_UART', if_true: files('shakti_uart.c')) system_ss.add(when: 'CONFIG_VIRTIO_SERIAL', if_true: files('virtio-console.c')) system_ss.add(when: 'CONFIG_XEN_BUS', if_true: files('xen_console.c')) system_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_uartlite.c')) +system_ss.add(when: 'CONFIG_DIVA_GSP', if_true: files('diva-gsp.c')) system_ss.add(when: 'CONFIG_AVR_USART', if_true: files('avr_usart.c')) system_ss.add(when: 'CONFIG_COLDFIRE', if_true: files('mcf_uart.c')) From patchwork Tue Jan 28 16:14:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13952747 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 895FBC02190 for ; Tue, 28 Jan 2025 16:16:31 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcoF4-0005Op-BS; Tue, 28 Jan 2025 11:15:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcoF0-0005M3-EQ for qemu-devel@nongnu.org; Tue, 28 Jan 2025 11:15:06 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcoEw-0002dQ-QH for qemu-devel@nongnu.org; Tue, 28 Jan 2025 11:15:06 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id BC6F95C6079; Tue, 28 Jan 2025 16:14:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 54DC9C4CEE3; Tue, 28 Jan 2025 16:15:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738080901; bh=hxMo1FNFoD+U6gmbbuqjqjojNvNGpUQwcalZq5WZRdw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Byzi0xFoteeeECHNhMe4G7zygIdV93yBXAO6YM+sX0DoM2hB6pfbh7dQ4pqDKh6mh TaN7wvdJYJ0FY/BcnurvkIUcf0MQaPNPEGxw/C3Gb6WWjvCDc/yTjrDL1456rZ6tke /kzmDez+qaKT3R8E/gNRE74/bcD0Ky5p8rfj8INzSSSgSBU9LGSBZOnSavHJTOMs7J B1mimF+l5xyxV+bN1UhlX2uipv2q6L713VMJeGXfCP7GnQRtdnalsqB4Lig9W1eIha Wc+KBtaKJMhQK4+rPtx5MXOwxqksd7jR/VhCykIEriyZBMubgvdKWR1+wCm9o7Fkcz T4qdtsh8maA9Q== From: deller@kernel.org To: qemu-devel@nongnu.org, Richard Henderson Cc: Helge Deller , Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PATCH 5/5] hw/hppa: Wire up Diva GSP card Date: Tue, 28 Jan 2025 17:14:50 +0100 Message-ID: <20250128161450.12975-6-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250128161450.12975-1-deller@kernel.org> References: <20250128161450.12975-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=139.178.84.217; envelope-from=deller@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -83 X-Spam_score: -8.4 X-Spam_bar: -------- X-Spam_report: (-8.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller Until now we used a standard serial-pci device to emulate a HP serial console. This worked nicely with 32-bit Linux and 32-bit HP-UX, but 64-bit HP-UX crashes with it and expects either a Diva GSP card, or a real 64-bit capable PCI graphic card (which we don't have yet). In order to continue with 64-bit HP-UX, switch over to the recently added Diva GSP card emulation. Signed-off-by: Helge Deller --- hw/hppa/Kconfig | 1 + hw/hppa/machine.c | 24 ++++++------------------ 2 files changed, 7 insertions(+), 18 deletions(-) diff --git a/hw/hppa/Kconfig b/hw/hppa/Kconfig index 9312c4294a..cab21045de 100644 --- a/hw/hppa/Kconfig +++ b/hw/hppa/Kconfig @@ -11,6 +11,7 @@ config HPPA_B160L select LASI select SERIAL_MM select SERIAL_PCI + select DIVA_GSP select ISA_BUS select I8259 select IDE_CMD646 diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index d5de793b62..1155d9aba9 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -383,28 +383,16 @@ static void machine_HP_common_init_tail(MachineState *machine, PCIBus *pci_bus, pci_init_nic_devices(pci_bus, mc->default_nic); - /* BMC board: HP Powerbar SP2 Diva (with console only) */ - pci_dev = pci_new(-1, "pci-serial"); + /* BMC board: HP Diva GSP */ + pci_dev = pci_new_multifunction(PCI_DEVFN(2, 0), "diva-serial"); if (!lasi_dev) { /* bind default keyboard/serial to Diva card */ - qdev_prop_set_chr(DEVICE(pci_dev), "chardev", serial_hd(0)); + qdev_prop_set_chr(DEVICE(pci_dev), "chardev1", serial_hd(0)); + qdev_prop_set_chr(DEVICE(pci_dev), "chardev2", serial_hd(1)); + qdev_prop_set_chr(DEVICE(pci_dev), "chardev3", serial_hd(2)); + qdev_prop_set_chr(DEVICE(pci_dev), "chardev4", serial_hd(3)); } - qdev_prop_set_uint8(DEVICE(pci_dev), "prog_if", 0); pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); - pci_config_set_vendor_id(pci_dev->config, PCI_VENDOR_ID_HP); - pci_config_set_device_id(pci_dev->config, 0x1048); - pci_set_word(&pci_dev->config[PCI_SUBSYSTEM_VENDOR_ID], PCI_VENDOR_ID_HP); - pci_set_word(&pci_dev->config[PCI_SUBSYSTEM_ID], 0x1227); /* Powerbar */ - - /* create a second serial PCI card when running Astro */ - if (serial_hd(1) && !lasi_dev) { - pci_dev = pci_new(-1, "pci-serial-4x"); - qdev_prop_set_chr(DEVICE(pci_dev), "chardev1", serial_hd(1)); - qdev_prop_set_chr(DEVICE(pci_dev), "chardev2", serial_hd(2)); - qdev_prop_set_chr(DEVICE(pci_dev), "chardev3", serial_hd(3)); - qdev_prop_set_chr(DEVICE(pci_dev), "chardev4", serial_hd(4)); - pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); - } /* create USB OHCI controller for USB keyboard & mouse on Astro machines */ if (!lasi_dev && machine->enable_graphics && defaults_enabled()) {