From patchwork Tue Jan 28 22:45:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13953329 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7EEBFC0218D for ; Tue, 28 Jan 2025 22:49:07 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcuNt-0002bK-T9; Tue, 28 Jan 2025 17:48:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcuNm-0002ZW-0w for qemu-devel@nongnu.org; Tue, 28 Jan 2025 17:48:36 -0500 Received: from nyc.source.kernel.org ([2604:1380:45d1:ec00::3]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcuNk-000249-GI for qemu-devel@nongnu.org; Tue, 28 Jan 2025 17:48:33 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 16E0CA41454; Tue, 28 Jan 2025 22:46:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id BD28EC4CED3; Tue, 28 Jan 2025 22:48:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738104509; bh=FNz0iSSnQ7yEUot6PeU17QUVLyWFRWyb6UYbabOD1Fw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OvcM1vmCbQR5yavVPO6eJHR7is0IHoghg75FnRfv3+x0Qw1hvf4fOMz08b0fl6PGP yzuDUeFCMaGLgrqQXHvixlarkgbdHe7dkrp2E3FrhKWOYTonOkO8JZRCrosTjWdQq0 EgMLKXwZCU53hTQ0iktqdRUoAPi6x/utT9fPi3ck8gWDQaamlMYArhAyuGVe/o1L4G lKhFQmdAGjD6wgOOSjKf91x4bJ3QZ2xt0HA2BhIxf4COL8m8CBFRrP7GazHfEw55cu 6A9oNZj4DNqyfWUffZEbcfSycXThVmfgCyZbyztH95ie5IMrksSuXuH9ipHdWJ3sKm MapLXvZKhlWvg== From: deller@kernel.org To: richard.henderson@linaro.org, qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 1/4] target/hppa: Add CPU diagnose registers Date: Tue, 28 Jan 2025 23:45:41 +0100 Message-ID: <20250128224817.24715-2-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250128224817.24715-1-deller@kernel.org> References: <20250128224817.24715-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2604:1380:45d1:ec00::3; envelope-from=deller@kernel.org; helo=nyc.source.kernel.org X-Spam_score_int: -56 X-Spam_score: -5.7 X-Spam_bar: ----- X-Spam_report: (-5.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller Add the diagnose registers (%dr) to the CPUArchState. Those are mostly undocumented and control cache behaviour, memory behaviour, reset button management and many other related internal CPU things. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/machine.c | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index beea42d105..b858986c41 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -232,6 +232,7 @@ typedef struct CPUArchState { target_ulong cr[32]; /* control registers */ target_ulong cr_back[2]; /* back of cr17/cr18 */ target_ulong shadow[7]; /* shadow registers */ + target_ulong dr[32]; /* diagnose registers */ /* * During unwind of a memory insn, the base register of the address. diff --git a/target/hppa/machine.c b/target/hppa/machine.c index 211bfcf640..bb47a2e689 100644 --- a/target/hppa/machine.c +++ b/target/hppa/machine.c @@ -198,6 +198,7 @@ static const VMStateField vmstate_env_fields[] = { VMSTATE_UINT64(iasq_b, CPUHPPAState), VMSTATE_UINT32(fr0_shadow, CPUHPPAState), + VMSTATE_UINT64_ARRAY(dr, CPUHPPAState, 32), VMSTATE_END_OF_LIST() }; @@ -208,8 +209,8 @@ static const VMStateDescription * const vmstate_env_subsections[] = { static const VMStateDescription vmstate_env = { .name = "env", - .version_id = 3, - .minimum_version_id = 3, + .version_id = 4, + .minimum_version_id = 4, .fields = vmstate_env_fields, .subsections = vmstate_env_subsections, }; From patchwork Tue Jan 28 22:45:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13953330 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7898C02193 for ; Tue, 28 Jan 2025 22:49:08 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcuNs-0002aO-GR; Tue, 28 Jan 2025 17:48:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcuNm-0002ZX-1G for qemu-devel@nongnu.org; Tue, 28 Jan 2025 17:48:36 -0500 Received: from nyc.source.kernel.org ([2604:1380:45d1:ec00::3]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcuNk-00024A-G0 for qemu-devel@nongnu.org; Tue, 28 Jan 2025 17:48:33 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 6B529A41470; Tue, 28 Jan 2025 22:46:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 14248C4CEDF; Tue, 28 Jan 2025 22:48:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738104511; bh=aaNhqD+qxBnqaQFsiiicFI2/J+SvMD2ciIeBWu/M9qU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sksK2UGT+/GsvfLSdr5mccP2rVH5P8d+HTlGhESvxofCN3cl9GdLWSnJu65jfOj2n 7OwlhrWpPMa+2Ia+7yYpjR4vsAbbGdKJD8iEi/YSEpQn22Lamd3geajl7DVifvSv7i qT5ir7EIdBKVSJdYXt1H93LqgcYqhjF4pW/qkDwFimPGtnWHFvl1Uij+XX3Fe2HmcW 20c6rLkRtRJb7TJrXs11mvj0llK9cxobgekkZn+4MfvMjiooPIVAHMy3NwfRMTDeRR HaHjHDJwzNM7OFFkhe7xisB9Lqwm4vEFZwBH//kUZOxE+p9wDROzDR53Wki1gQzHEb zc/qMRkE6zmdw== From: deller@kernel.org To: richard.henderson@linaro.org, qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 2/4] target/hppa: Add instruction decoding for mfdiag and mtdiag Date: Tue, 28 Jan 2025 23:45:42 +0100 Message-ID: <20250128224817.24715-3-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250128224817.24715-1-deller@kernel.org> References: <20250128224817.24715-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2604:1380:45d1:ec00::3; envelope-from=deller@kernel.org; helo=nyc.source.kernel.org X-Spam_score_int: -56 X-Spam_score: -5.7 X-Spam_bar: ----- X-Spam_report: (-5.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller Add 32- and 64-bit instruction decoding of the mfdiag and mtdiag instructions which modify the diagnose registers. diag_getshadowregs_pa2() and diag_putshadowregs_pa2() were added in commit 3bdf20819e68 based on some analysis of ODE code, but now they conflict with the generic mfdiag/mtdiag instructions. I believe the former analysis was wrong, so remove them again. Note that all diag instructions are badly documented, so most things are based on reverse engineering and thus may be wrong. Signed-off-by: Helge Deller Fixes: 3bdf20819e68 ("target/hppa: Add diag instructions to set/restore shadow registers") Reviewed-by: Richard Henderson --- target/hppa/insns.decode | 6 ++++-- target/hppa/translate.c | 22 ++++++++++++++++------ 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 71074a64c1..4eaac750ea 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -644,10 +644,12 @@ xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64 # For 32-bit PA-7300LC (PCX-L2) diag_getshadowregs_pa1 000101 00 0000 0000 0001 1010 0000 0000 diag_putshadowregs_pa1 000101 00 0000 0000 0001 1010 0100 0000 + diag_mfdiag 000101 dr:5 rt:5 0000 0110 0000 0000 + diag_mtdiag 000101 dr:5 r1:5 0001 0110 0000 0000 # For 64-bit PA8700 (PCX-W2) - diag_getshadowregs_pa2 000101 00 0111 1000 0001 1000 0100 0000 - diag_putshadowregs_pa2 000101 00 0111 0000 0001 1000 0100 0000 + diag_mfdiag 000101 dr:5 0 0000 0000 1000 101 rt:5 + diag_mtdiag 000101 dr:5 r1:5 0001 1000 0100 0000 ] diag_unimp 000101 i:26 } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index dc04f9f3c0..7b9d3deb39 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4593,19 +4593,29 @@ static bool trans_diag_getshadowregs_pa1(DisasContext *ctx, arg_empty *a) return !ctx->is_pa20 && do_getshadowregs(ctx); } -static bool trans_diag_getshadowregs_pa2(DisasContext *ctx, arg_empty *a) +static bool trans_diag_putshadowregs_pa1(DisasContext *ctx, arg_empty *a) { - return ctx->is_pa20 && do_getshadowregs(ctx); + return !ctx->is_pa20 && do_putshadowregs(ctx); } -static bool trans_diag_putshadowregs_pa1(DisasContext *ctx, arg_empty *a) +static bool trans_diag_mfdiag(DisasContext *ctx, arg_diag_mfdiag *a) { - return !ctx->is_pa20 && do_putshadowregs(ctx); + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + TCGv_i64 dest = dest_gpr(ctx, a->rt); + tcg_gen_ld_i64(dest, tcg_env, + offsetof(CPUHPPAState, dr[a->dr])); + save_gpr(ctx, a->rt, dest); + return nullify_end(ctx); } -static bool trans_diag_putshadowregs_pa2(DisasContext *ctx, arg_empty *a) +static bool trans_diag_mtdiag(DisasContext *ctx, arg_diag_mtdiag *a) { - return ctx->is_pa20 && do_putshadowregs(ctx); + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + tcg_gen_st_i64(load_gpr(ctx, a->r1), tcg_env, + offsetof(CPUHPPAState, dr[a->dr])); + return nullify_end(ctx); } static bool trans_diag_unimp(DisasContext *ctx, arg_diag_unimp *a) From patchwork Tue Jan 28 22:45:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13953332 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C4D74C0218A for ; Tue, 28 Jan 2025 22:49:31 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcuNv-0002bt-0p; Tue, 28 Jan 2025 17:48:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcuNm-0002ZY-Nc for qemu-devel@nongnu.org; Tue, 28 Jan 2025 17:48:36 -0500 Received: from nyc.source.kernel.org ([2604:1380:45d1:ec00::3]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcuNl-00024S-5a for qemu-devel@nongnu.org; Tue, 28 Jan 2025 17:48:34 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id B519DA4148E; Tue, 28 Jan 2025 22:46:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6671DC4CED3; Tue, 28 Jan 2025 22:48:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738104512; bh=1XT/07xMdO+36fCCsQzMRTN3C9LUWm0QozbepHCvoD4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ld3EoNuPJs3S0Mnd+jrccZq6yVqUnuhlr9orI/ixj1KCdJe3Hs6z8qs38AOKZ2gLK ZooaFPwiu9V2xRT2054BwdirRirlGGAD42qsH+9cDfmXEbEJotjYES1aXnNSZHbyuB raohV4C+5PoEngiml+miKDjbtHUfacjME+aBw/JXl3tGLBBzmRXdFdujw6OX/ntO5W UOZF6MBB5FfRDOz3qB77MSd26fYBpI9izhLIqxEXTNxe6clAhvltmQZxJXYALmNRg7 JBjxTgiQjNJDzQFRCB3fVehqoIg4pfOuRbijExBIrfr+tw9+KOW/Z6RDhRQ8OZGEfs cZmRi5UzO+3zQ== From: deller@kernel.org To: richard.henderson@linaro.org, qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 3/4] target/hppa: 64-bit CPUs start with space register hashing enabled Date: Tue, 28 Jan 2025 23:45:43 +0100 Message-ID: <20250128224817.24715-4-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250128224817.24715-1-deller@kernel.org> References: <20250128224817.24715-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2604:1380:45d1:ec00::3; envelope-from=deller@kernel.org; helo=nyc.source.kernel.org X-Spam_score_int: -56 X-Spam_score: -5.7 X-Spam_bar: ----- X-Spam_report: (-5.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller Turn on space register hashing for 64-bit CPUs when reset. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson --- target/hppa/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index b0bc9d35e4..c86f9190d2 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -28,6 +28,7 @@ #include "exec/translation-block.h" #include "fpu/softfloat.h" #include "tcg/tcg.h" +#include "hw/hppa/hppa_hardware.h" static void hppa_cpu_set_pc(CPUState *cs, vaddr value) { @@ -217,6 +218,10 @@ static void hppa_cpu_reset_hold(Object *obj, ResetType type) memset(env, 0, offsetof(CPUHPPAState, end_reset_fields)); cpu_hppa_loaded_fr0(env); + + /* 64-bit machines start with space-register hashing enabled in %dr2 */ + env->dr[2] = hppa_is_pa20(env) ? HPPA64_DIAG_SPHASH_ENABLE : 0; + cpu_hppa_put_psw(env, PSW_M); } From patchwork Tue Jan 28 22:45:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13953331 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0FDAC02193 for ; Tue, 28 Jan 2025 22:49:22 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcuNv-0002bv-Lb; Tue, 28 Jan 2025 17:48:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcuNo-0002a6-OU for qemu-devel@nongnu.org; Tue, 28 Jan 2025 17:48:37 -0500 Received: from nyc.source.kernel.org ([147.75.193.91]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcuNm-00024u-Or for qemu-devel@nongnu.org; Tue, 28 Jan 2025 17:48:36 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 0D7D4A41454; Tue, 28 Jan 2025 22:46:47 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B2AA4C4CEE3; Tue, 28 Jan 2025 22:48:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738104513; bh=SaHFgTayjW52a5pwl0Wts/xT1KlH8VgV1/mGFXocnzQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KMHYgjAHEtnclDDUatiCt0cWXlEwDshpDA0IhnMahTHkWVqqkhK2bLsrrp8AMWywN O/p5YhfWXH31V0fAP3X75w/rx1obJjgao0hL5YPonvX3zHvL53kvUDGyfPO0OZnnRF dlQJDfaeLmygfr2UoqgtWuaKjf4Nox1LDsvI4oggJ6VS8OcDbqDmfIE1qb+LQNNYsy kLymddagv8c3yb0UFyOSWmthjDRRm5TCfEMg54bqzSDtZROJTMGH4RfgSTYKc2yQ0I 8dn31+CwZPsbMaY5pdOM4VGR/kJgc++rVNjyVv7l4ROAVKktLnN/jyC5BcRcphfteq EsM8YMdR5HMqw== From: deller@kernel.org To: richard.henderson@linaro.org, qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 4/4] target/hppa: Implement space register hashing for 64-bit HP-UX Date: Tue, 28 Jan 2025 23:45:44 +0100 Message-ID: <20250128224817.24715-5-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250128224817.24715-1-deller@kernel.org> References: <20250128224817.24715-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=147.75.193.91; envelope-from=deller@kernel.org; helo=nyc.source.kernel.org X-Spam_score_int: -56 X-Spam_score: -5.7 X-Spam_bar: ----- X-Spam_report: (-5.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller The Linux kernel turns space-register hashing off unconditionally at bootup. That code was provided by HP at the beginning of the PA-RISC Linux porting effort, and I don't know why it was decided then why Linux should not use space register hashing. 32-bit HP-UX versions seem to not use space register hashing either. But for 64-bit HP-UX versions, Sven Schnelle noticed that space register hashing needs to be enabled and is required, otherwise the HP-UX kernel will crash badly. On 64-bit CPUs space register hashing is controlled by a bit in diagnose register %dr2. Since we want to support Linux and 32- and 64-bit HP-UX, we need to fully emulate the diagnose registers and handle specifically the bit in %dr2. This patch adds the code to calculate the gva memory mask based on the space-register hashing bit in %dr2 and the PSW_W (64-bit) flag. The value is cached in the gva_offset_mask variable in CPUArchState and recalculated at every modification of the CPU PSW or %dr2. Signed-off-by: Helge Deller Suggested-by: Richard Henderson Suggested-by: Sven Schnelle Signed-off-by: Helge Deller Reviewed-by: Richard Henderson --- target/hppa/cpu.c | 5 +++-- target/hppa/cpu.h | 19 +++++++------------ target/hppa/helper.c | 25 +++++++++++++++++++++++-- target/hppa/int_helper.c | 10 ++++++---- target/hppa/sys_helper.c | 4 ++-- target/hppa/translate.c | 8 +++++++- 6 files changed, 48 insertions(+), 23 deletions(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index c86f9190d2..c64495332f 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -45,8 +45,9 @@ static vaddr hppa_cpu_get_pc(CPUState *cs) { CPUHPPAState *env = cpu_env(cs); - return hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), - env->iaoq_f & -4); + return hppa_form_gva_mask(env->gva_offset_mask, + (env->psw & PSW_C ? env->iasq_f : 0), + env->iaoq_f & -4); } void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index b858986c41..52dc6ec700 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -223,6 +223,7 @@ typedef struct CPUArchState { target_ulong psw_cb; /* in least significant bit of next nibble */ target_ulong psw_cb_msb; /* boolean */ + uint64_t gva_offset_mask; /* cached address mask based on PSW and %dr2 */ uint64_t iasq_f; uint64_t iasq_b; @@ -320,27 +321,20 @@ void hppa_translate_code(CPUState *cs, TranslationBlock *tb, #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU -static inline uint64_t gva_offset_mask(target_ulong psw) -{ - return (psw & PSW_W - ? MAKE_64BIT_MASK(0, 62) - : MAKE_64BIT_MASK(0, 32)); -} - -static inline target_ulong hppa_form_gva_psw(target_ulong psw, uint64_t spc, - target_ulong off) +static inline target_ulong hppa_form_gva_mask(uint64_t gva_offset_mask, + uint64_t spc, target_ulong off) { #ifdef CONFIG_USER_ONLY - return off & gva_offset_mask(psw); + return off & gva_offset_mask; #else - return spc | (off & gva_offset_mask(psw)); + return spc | (off & gva_offset_mask); #endif } static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, target_ulong off) { - return hppa_form_gva_psw(env->psw, spc, off); + return hppa_form_gva_mask(env->gva_offset_mask, spc, off); } hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr); @@ -362,6 +356,7 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, target_ulong cpu_hppa_get_psw(CPUHPPAState *env); void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong); +void update_gva_offset_mask(CPUHPPAState *env); void cpu_hppa_loaded_fr0(CPUHPPAState *env); #ifdef CONFIG_USER_ONLY diff --git a/target/hppa/helper.c b/target/hppa/helper.c index d4b1a3cd5a..ac7f58f0af 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "qemu/qemu-print.h" +#include "hw/hppa/hppa_hardware.h" target_ulong cpu_hppa_get_psw(CPUHPPAState *env) { @@ -59,6 +60,22 @@ target_ulong cpu_hppa_get_psw(CPUHPPAState *env) return psw; } +void update_gva_offset_mask(CPUHPPAState *env) +{ + uint64_t gom; + + if (env->psw & PSW_W) { + gom = (env->dr[2] & HPPA64_DIAG_SPHASH_ENABLE) + ? MAKE_64BIT_MASK(0, 62) & + ~((uint64_t)HPPA64_PDC_CACHE_RET_SPID_VAL << 48) + : MAKE_64BIT_MASK(0, 62); + } else { + gom = MAKE_64BIT_MASK(0, 32); + } + + env->gva_offset_mask = gom; +} + void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) { uint64_t reserved; @@ -98,6 +115,8 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) cb |= ((psw >> 9) & 1) << 8; cb |= ((psw >> 8) & 1) << 4; env->psw_cb = cb; + + update_gva_offset_mask(env); } void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags) @@ -133,9 +152,11 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IA_F %08" PRIx64 ":%0*" PRIx64 " (" TARGET_FMT_lx ")\n" "IA_B %08" PRIx64 ":%0*" PRIx64 " (" TARGET_FMT_lx ")\n", env->iasq_f >> 32, w, m & env->iaoq_f, - hppa_form_gva_psw(psw, env->iasq_f, env->iaoq_f), + hppa_form_gva_mask(env->gva_offset_mask, env->iasq_f, + env->iaoq_f), env->iasq_b >> 32, w, m & env->iaoq_b, - hppa_form_gva_psw(psw, env->iasq_b, env->iaoq_b)); + hppa_form_gva_mask(env->gva_offset_mask, env->iasq_b, + env->iaoq_b)); psw_c[0] = (psw & PSW_W ? 'W' : '-'); psw_c[1] = (psw & PSW_E ? 'E' : '-'); diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 58695def82..7d48643bb6 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -94,11 +94,12 @@ void hppa_cpu_do_interrupt(CPUState *cs) HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; int i = cs->exception_index; - uint64_t old_psw; + uint64_t old_psw, old_gva_offset_mask; /* As documented in pa2.0 -- interruption handling. */ /* step 1 */ env->cr[CR_IPSW] = old_psw = cpu_hppa_get_psw(env); + old_gva_offset_mask = env->gva_offset_mask; /* step 2 -- Note PSW_W is masked out again for pa1.x */ cpu_hppa_put_psw(env, @@ -112,9 +113,9 @@ void hppa_cpu_do_interrupt(CPUState *cs) */ if (old_psw & PSW_C) { env->cr[CR_IIASQ] = - hppa_form_gva_psw(old_psw, env->iasq_f, env->iaoq_f) >> 32; + hppa_form_gva_mask(old_gva_offset_mask, env->iasq_f, env->iaoq_f) >> 32; env->cr_back[0] = - hppa_form_gva_psw(old_psw, env->iasq_b, env->iaoq_b) >> 32; + hppa_form_gva_mask(old_gva_offset_mask, env->iasq_b, env->iaoq_b) >> 32; } else { env->cr[CR_IIASQ] = 0; env->cr_back[0] = 0; @@ -165,7 +166,8 @@ void hppa_cpu_do_interrupt(CPUState *cs) if (old_psw & PSW_C) { int prot, t; - vaddr = hppa_form_gva_psw(old_psw, env->iasq_f, vaddr); + vaddr = hppa_form_gva_mask(old_gva_offset_mask, + env->iasq_f, vaddr); t = hppa_get_physical_address(env, vaddr, MMU_KERNEL_IDX, 0, 0, &paddr, &prot); if (t >= 0) { diff --git a/target/hppa/sys_helper.c b/target/hppa/sys_helper.c index da5b569de8..052a6a88a2 100644 --- a/target/hppa/sys_helper.c +++ b/target/hppa/sys_helper.c @@ -73,7 +73,7 @@ target_ulong HELPER(swap_system_mask)(CPUHPPAState *env, target_ulong nsm) * machines set the Q bit from 0 to 1 without an exception, * so let this go without comment. */ - env->psw = (psw & ~PSW_SM) | (nsm & PSW_SM); + cpu_hppa_put_psw(env, (psw & ~PSW_SM) | (nsm & PSW_SM)); return psw & PSW_SM; } @@ -88,7 +88,7 @@ void HELPER(rfi)(CPUHPPAState *env) * To recreate the space identifier, remove the offset bits. * For pa1.x, the mask reduces to no change to space. */ - mask = gva_offset_mask(env->psw); + mask = env->gva_offset_mask; env->iaoq_f = env->cr[CR_IIAOQ]; env->iaoq_b = env->cr_back[1]; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 7b9d3deb39..6c68f98651 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -73,6 +73,7 @@ typedef struct DisasContext { /* IAOQ_Front at entry to TB. */ uint64_t iaoq_first; + uint64_t gva_offset_mask; DisasCond null_cond; TCGLabel *null_lab; @@ -1577,7 +1578,7 @@ static void form_gva(DisasContext *ctx, TCGv_i64 *pgva, TCGv_i64 *pofs, *pofs = ofs; *pgva = addr = tcg_temp_new_i64(); tcg_gen_andi_i64(addr, modify <= 0 ? ofs : base, - gva_offset_mask(ctx->tb_flags)); + ctx->gva_offset_mask); #ifndef CONFIG_USER_ONLY if (!is_phys) { tcg_gen_or_i64(addr, addr, space_select(ctx, sp, base)); @@ -4615,6 +4616,10 @@ static bool trans_diag_mtdiag(DisasContext *ctx, arg_diag_mtdiag *a) nullify_over(ctx); tcg_gen_st_i64(load_gpr(ctx, a->r1), tcg_env, offsetof(CPUHPPAState, dr[a->dr])); + if (ctx->is_pa20 && (a->dr == 2)) { + /* Exit TB to recalculate gva_offset_mask on %dr2 */ + ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; + } return nullify_end(ctx); } @@ -4635,6 +4640,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->tb_flags = ctx->base.tb->flags; ctx->is_pa20 = hppa_is_pa20(cpu_env(cs)); ctx->psw_xb = ctx->tb_flags & (PSW_X | PSW_B); + ctx->gva_offset_mask = cpu_env(cs)->gva_offset_mask; #ifdef CONFIG_USER_ONLY ctx->privilege = PRIV_USER;