From patchwork Wed Jan 29 20:02:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13954082 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 10EFBC0218D for ; Wed, 29 Jan 2025 20:01:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B046A10E887; Wed, 29 Jan 2025 20:01:30 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="W+5GxTBO"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id D00F110E1B3; Wed, 29 Jan 2025 20:01:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738180887; x=1769716887; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=sn5jEwb3mAaEatI4sQTNnZEieru8TEnwxobWHISmh1s=; b=W+5GxTBOhMaZqK4u7kqvPJQy+QyiXN5OILmskB8St2j/SDEBjuvxWCd3 lcreAq70WkssmOiJhg881s4ShPapcVyRLo9W9ntLbfCPtkUhkFtvhv3Zq 89MWDFEEJ75fR7qN/824rbWY5rnnkFlcuBnaoRsHiHZ8d0pI3JKvgbRA6 G0vgDgbgwmsjccd/j7wvn4rW7L1MI1+yBpSmKLaihT9P9EpKaWJGYqdP9 rg3ExpA49lvMQoXMjad1G/Vo0XcZVkdHyizQhkYJN2hWFKKaB4uYCHj1P wKijUANAerBXMPk19NJDczcEfGN/OLZYvidnEFZ1WiAoxIYG4QRAMSDPc A==; X-CSE-ConnectionGUID: 1QiKxB8cTUe9DO6lbksgBQ== X-CSE-MsgGUID: BiYBllKCS9O2NxOjGzMIng== X-IronPort-AV: E=McAfee;i="6700,10204,11330"; a="38977671" X-IronPort-AV: E=Sophos;i="6.13,244,1732608000"; d="scan'208";a="38977671" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:27 -0800 X-CSE-ConnectionGUID: pbW4TqehSkmMHGPO3c0obg== X-CSE-MsgGUID: LbJT6x5vTk2L39YXibEEPw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="113750888" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:26 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH 01/17] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro Date: Wed, 29 Jan 2025 22:02:05 +0200 Message-ID: <20250129200221.2508101-2-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250129200221.2508101-1-imre.deak@intel.com> References: <20250129200221.2508101-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The format of the port width field in the DDI_BUF_CTL and the TRANS_DDI_FUNC_CTL registers are different starting with MTL, where the x3 lane mode for HDMI FRL has a different encoding in the two registers. To account for this use the TRANS_DDI_FUNC_CTL's own port width macro. Signed-off-by: Imre Deak Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index ee1c3fb500a73..11bfb357508b7 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -809,8 +809,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, /* select data lane width */ tmp = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, dsi_trans)); - tmp &= ~DDI_PORT_WIDTH_MASK; - tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); + tmp &= ~TRANS_DDI_PORT_WIDTH_MASK; + tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count); /* select input pipe */ tmp &= ~TRANS_DDI_EDP_INPUT_MASK; From patchwork Wed Jan 29 20:02:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13954084 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B0D53C02194 for ; Wed, 29 Jan 2025 20:01:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E6D1C10E894; Wed, 29 Jan 2025 20:01:30 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="gmu5FnCt"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 466D310E887; Wed, 29 Jan 2025 20:01:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738180888; x=1769716888; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=S0LM0XpRO0Jl+UJQEV69qtO9wz0EnZ8xvtyFA1jUFWA=; b=gmu5FnCtC5z16W7zyDqUARD81a+KJZ5bf86T+3/XyrYJY5JHpOlyia6g AMWw8YSEA7paygOzUFRtldRtopHVuP+Ttft1olp26Da0Qt5UcDNUua/SW Dst9/8856ljjOnzFizxoDbCrpbBpKVcQMQUMrXgkH/29pG3LkVynlqDAl ur0YtwHit2JYdu1sZpkP3cTmV8lnHibxQpAl/XgKG5WpXdJeYATaNdAkw 0w21+Xuy+nBms627Zgb0TxqeIVxQuCg6j+/h52GRedDAfRQ7R2hWoS4Mc mNiF3lHFtb9zvCXJejv/dbTZONFKchGgIfzC08wTYBLxUFleCOeSURgmT g==; X-CSE-ConnectionGUID: lLxd2JCQSq24GzmFTJx2/g== X-CSE-MsgGUID: Oi3PORNVT+i3l01reOFh4g== X-IronPort-AV: E=McAfee;i="6700,10204,11330"; a="38977673" X-IronPort-AV: E=Sophos;i="6.13,244,1732608000"; d="scan'208";a="38977673" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:28 -0800 X-CSE-ConnectionGUID: QwC+hvQaRiyDu/xvEcJOdQ== X-CSE-MsgGUID: 4Baij0fBQ4CC24EhO9qHng== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="113750890" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:27 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Imre Deak Subject: [PATCH 02/17] drm/i915/ddi: Fix HDMI port width programming in DDI_BUF_CTL Date: Wed, 29 Jan 2025 22:02:06 +0200 Message-ID: <20250129200221.2508101-3-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250129200221.2508101-1-imre.deak@intel.com> References: <20250129200221.2508101-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Imre Deak Fix the port width programming in the DDI_BUF_CTL register on MTLP+, where this had an off-by-one error. Signed-off-by: Imre Deak Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index dc319f37b1be9..36e7dde422d37 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3501,7 +3501,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port), XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); - buf_ctl |= DDI_PORT_WIDTH(lane_count); + buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); if (DISPLAY_VER(dev_priv) >= 20) buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 03da51b03fb90..04e47d0a8ab92 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3635,7 +3635,7 @@ enum skl_power_gate { #define DDI_BUF_IS_IDLE (1 << 7) #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) #define DDI_A_4_LANES (1 << 4) -#define DDI_PORT_WIDTH(width) (((width) - 1) << 1) +#define DDI_PORT_WIDTH(width) (((width) == 3 ? 4 : ((width) - 1)) << 1) #define DDI_PORT_WIDTH_MASK (7 << 1) #define DDI_PORT_WIDTH_SHIFT 1 #define DDI_INIT_DISPLAY_DETECTED (1 << 0) From patchwork Wed Jan 29 20:02:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13954083 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 95B51C0218F for ; Wed, 29 Jan 2025 20:01:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EB37D10E899; Wed, 29 Jan 2025 20:01:31 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="nfLdv+8e"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6AC3B10E887; Wed, 29 Jan 2025 20:01:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738180890; x=1769716890; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=IKzLHJ+KGlc5nK5c0Ra80IB30r0bPnrEVc1dvnuW8Wk=; b=nfLdv+8e0+eUZW++1DoQz7PDANT36MmMU4VK32XsoiKvfBtLjAtiWDEe JnUopqoExdtuOJOarveU7zI4SpYk82mpVahZNPc9PDwxawswb7DlWhY1M qZFLVaU4skq8NBcko2TfQq0uxUDu7CmRNINj4mM85ysUOn+rOWBelXkGr tGmYzdzIz/uOhrHtH7NHgFLV/23hY1kxEP9CSB9YPKeqZQgn4RRJ12ler XieDTB80YUruwmAcfpFEmJcr9IZ39jw+LIjJGulIBsFKvoI32V6XEplqF BinSOyPV6PRg18Vhomj//I8dwt6Cvxxs3tZ3aQUCbl3Y4e43dTul7xlyn A==; X-CSE-ConnectionGUID: doPSLGSLT8GjG78qymP9Gg== X-CSE-MsgGUID: Wvxyl0kqRb20myoKfcyPpg== X-IronPort-AV: E=McAfee;i="6700,10204,11330"; a="38977678" X-IronPort-AV: E=Sophos;i="6.13,244,1732608000"; d="scan'208";a="38977678" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:29 -0800 X-CSE-ConnectionGUID: JPnkMPikQ9Wog3DV+q5cYg== X-CSE-MsgGUID: d0g4N7WLQF2Xn92hBdx5Pw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="113750892" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:28 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH 03/17] drm/i915/ddi: Make all the PORT_WIDTH macros work the same way Date: Wed, 29 Jan 2025 22:02:07 +0200 Message-ID: <20250129200221.2508101-4-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250129200221.2508101-1-imre.deak@intel.com> References: <20250129200221.2508101-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Make the PORT_WIDTH macro of the XELPDP_PORT_CTL1 register work the same way as those used for the DDI_BUF_CTL and the TRANS_DDI_FUNC_CTL registers: accept a width parameter and convert it to the given register's encoding. Signed-off-by: Imre Deak Reviewed-by: Jani Nikula --- .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 3 ++- drivers/gpu/drm/i915/display/intel_ddi.c | 22 ++----------------- 2 files changed, 4 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h index 4a3cf08007e31..a24531656aa89 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h @@ -110,7 +110,8 @@ #define XELPDP_TCSS_POWER_REQUEST REG_BIT(5) #define XELPDP_TCSS_POWER_STATE REG_BIT(4) #define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1) -#define XELPDP_PORT_WIDTH(val) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val) +#define XELPDP_PORT_WIDTH(width) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, \ + (width) == 3 ? 4 : (width) - 1) #define _XELPDP_PORT_BUF_CTL2(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ _XELPDP_PORT_BUF_CTL1_LN0_A, \ diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 36e7dde422d37..76e8296cb134b 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2525,23 +2525,6 @@ static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) OVERLAP_PIXELS_MASK, dss1); } -static u8 mtl_get_port_width(u8 lane_count) -{ - switch (lane_count) { - case 1: - return 0; - case 2: - return 1; - case 3: - return 4; - case 4: - return 3; - default: - MISSING_CASE(lane_count); - return 4; - } -} - static void mtl_ddi_enable_d2d(struct intel_encoder *encoder) { @@ -2575,7 +2558,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, enum port port = encoder->port; u32 val = 0; - val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count)); + val |= XELPDP_PORT_WIDTH(crtc_state->lane_count); if (intel_dp_is_uhbr(crtc_state)) val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; @@ -3490,10 +3473,9 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, buf_ctl |= DDI_A_4_LANES; if (DISPLAY_VER(dev_priv) >= 14) { - u8 lane_count = mtl_get_port_width(crtc_state->lane_count); u32 port_buf = 0; - port_buf |= XELPDP_PORT_WIDTH(lane_count); + port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count); if (dig_port->lane_reversal) port_buf |= XELPDP_PORT_REVERSAL; From patchwork Wed Jan 29 20:02:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13954085 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 729DFC0218D for ; Wed, 29 Jan 2025 20:01:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 82BDE10E890; Wed, 29 Jan 2025 20:01:32 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="dcRqgKr4"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id CEA0910E890; Wed, 29 Jan 2025 20:01:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738180891; x=1769716891; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ep9c9SvN1zYennt8PzN+Ybem+V84SwyP9yHgwqQNjMQ=; b=dcRqgKr4w4EpeUz1WCULswut+bcsOg/PswYQMsElC2hh6y+DrKcAtjBw QROu/9ExKNEhICVgggPLx2WrlOWF9jhibZV+QYsJnNmLkpwfl0O5Tdvy4 j2oDQKGwTNjdngYGBfKGm5xaKZBfq/GrMOAxi7qJl4VjrE7CkdqYpNKLr XEspdoXpQVyTHH0H19kWHQtNCsrmVqAxCOCJ4JtC+tdpKH/tzckmipSy9 2pewLsS1+Wph+50wSdj2/zgrwr0TraBj+d4SFCjOrg1c1Am0mKSAe2mtL tD5hYlMkBLrRVFLGMVRLNL6OvwCkEU56bAy5rFvFGIg5iYuXAcw+GXx/e w==; X-CSE-ConnectionGUID: mv0fwx54TkqUu7z6OVIQAA== X-CSE-MsgGUID: jZhvMplPSgybyir+BphRxA== X-IronPort-AV: E=McAfee;i="6700,10204,11330"; a="38977684" X-IronPort-AV: E=Sophos;i="6.13,244,1732608000"; d="scan'208";a="38977684" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:31 -0800 X-CSE-ConnectionGUID: hlNtDbzbTACeNNPjmTV87A== X-CSE-MsgGUID: ojqeDRJOSPeimiObyEwruQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="113750895" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:29 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Imre Deak Subject: [PATCH 04/17] drm/i915/ddi: Set missing TC DP PHY lane stagger delay in DDI_BUF_CTL Date: Wed, 29 Jan 2025 22:02:08 +0200 Message-ID: <20250129200221.2508101-5-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250129200221.2508101-1-imre.deak@intel.com> References: <20250129200221.2508101-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Imre Deak Add the missing PHY lane stagger delay programming for ICL-ADL platforms on TypeC DP outputs. Bspec: 7534, 49533 Signed-off-by: Imre Deak Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 76e8296cb134b..6192c0d3c87a5 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -328,9 +328,21 @@ static u32 ddi_buf_phy_link_rate(int port_clock) } } +static int dp_phy_lane_stagger_delay(int port_clock) +{ + /* + * Return the number of link symbols per 100 ns: + * port_clock (10 kHz) -> bits / 100 us + * / symbol_size -> symbols / 100 us + * / 1000 -> symbols / 100 ns + */ + return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000); +} + static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); @@ -356,6 +368,12 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, if (!intel_tc_port_in_tbt_alt_mode(dig_port)) intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; } + + if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) { + int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock); + + intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay); + } } static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 04e47d0a8ab92..7fe4e71fc08ec 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3632,6 +3632,9 @@ enum skl_power_gate { #define DDI_BUF_PORT_DATA_20BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1) #define DDI_BUF_PORT_DATA_40BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2) #define DDI_BUF_PORT_REVERSAL (1 << 16) +#define DDI_BUF_LANE_STAGGER_DELAY_MASK REG_GENMASK(15, 8) +#define DDI_BUF_LANE_STAGGER_DELAY(symbols) REG_FIELD_PREP(DDI_BUF_LANE_STAGGER_DELAY_MASK, \ + symbols) #define DDI_BUF_IS_IDLE (1 << 7) #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) #define DDI_A_4_LANES (1 << 4) From patchwork Wed Jan 29 20:02:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13954087 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5CE4DC02193 for ; Wed, 29 Jan 2025 20:01:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E41BB10E8AC; Wed, 29 Jan 2025 20:01:38 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="d/2yG5YG"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id C9E0110E890; Wed, 29 Jan 2025 20:01:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738180892; x=1769716892; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=8METGeXp+hm/UiVDLku97jKLNGcJvcW5Fks0GLwshDc=; b=d/2yG5YGyRfMTbjt72QXJHLkEGEzQ6aAMZAbBgP9czyF2cBsa+jx5VLL heSTCiIjDeFoDr9p2vQ7u6bwJGWj5X/feBLXPcxMLQZRHWOtcWi9eMmET 129hRvd7gBWSpOkagTw/wa+QOLX/06+kPDsIlGUZTDs/fY/MkxZvo79Hr tBJ7BFjVdgjhMZuY5QMXkuSiz8pePiUPLOXDrBFHmGlBRDIPD1Yu+jmTz 0TOGaYNlFyivgC8HKMf8UQPccy9CqwX/Lhz5VS+5qhkIpGsqCICnZt6n0 NLatQeahnknJRFSec11mXZul+R3bv3Qxo71duejqE8ZKlMVliij2WbWlG w==; X-CSE-ConnectionGUID: fcyqt/hHQHuJh5MTHLayQA== X-CSE-MsgGUID: 7f/T0o68Qe2Fahw1qNo8vg== X-IronPort-AV: E=McAfee;i="6700,10204,11330"; a="38977687" X-IronPort-AV: E=Sophos;i="6.13,244,1732608000"; d="scan'208";a="38977687" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:32 -0800 X-CSE-ConnectionGUID: p4ptXklnS/afuqZNaisxEA== X-CSE-MsgGUID: wIsFIFC5RiSTFohubCm51g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="113750898" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:31 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH 05/17] drm/i915/ddi: Simplify the port enabling via DDI_BUF_CTL Date: Wed, 29 Jan 2025 22:02:09 +0200 Message-ID: <20250129200221.2508101-6-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250129200221.2508101-1-imre.deak@intel.com> References: <20250129200221.2508101-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In the past intel_digital_port::dp.prepare_link_retrain() could be called directly (vs. from a modeset) to retrain an enabled link. In that case the port had to be first disabled and then re-enabled. That changed with commit 2885d283cce5 ("drm/i915/dp: Retrain SST links via a modeset commit"), after which the only way prepare_link_retrain() can be called is from a modeset during link training when the port is still disabled. Simplify things accordingly, assuming the disabled port state. Signed-off-by: Imre Deak Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_ddi.c | 23 ++++------------------- 1 file changed, 4 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 6192c0d3c87a5..3138dc4034797 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3743,8 +3743,8 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, * necessary disable and enable port */ dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); - if (dp_tp_ctl & DP_TP_CTL_ENABLE) - mtl_disable_ddi_buf(encoder, crtc_state); + + drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; @@ -3787,26 +3787,11 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, struct intel_encoder *encoder = &dig_port->base; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; - u32 dp_tp_ctl, ddi_buf_ctl; - bool wait = false; + u32 dp_tp_ctl; dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); - if (dp_tp_ctl & DP_TP_CTL_ENABLE) { - ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); - if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { - intel_de_write(dev_priv, DDI_BUF_CTL(port), - ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); - wait = true; - } - - dp_tp_ctl &= ~DP_TP_CTL_ENABLE; - intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); - intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); - - if (wait) - intel_wait_ddi_buf_idle(dev_priv, port); - } + drm_WARN_ON(&dev_priv->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || From patchwork Wed Jan 29 20:02:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13954088 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8AD79C02194 for ; Wed, 29 Jan 2025 20:01:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1152810E8AD; Wed, 29 Jan 2025 20:01:39 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Ab5V89ld"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id F035210E89C; Wed, 29 Jan 2025 20:01:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738180893; x=1769716893; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=0m22DV12DoJ0fXFK3N+FHD9MyimfB1HyYtkB2ul77hg=; b=Ab5V89ldLvn+KPuWU3aKyk60C/3sU3y7zmVhpTKYbPFAr6wRN9WOCtFz NyvaJYmA3canf6i2vasRhhrm7zIOPPp6WFIOAwtrT29N3/yxUhtYGVZyG yrstqUBgRLOsLak4db11CLvIDuzJOaFkrJpKHfKLKVjgpOXDsVRxvP7Zk VbSxo+TlqD/m8V7qPndOEH5neld7VNKOb8l1fjC7jLwAi00+mqOTm799A 7QYL6aU/zplvO0YxcHbVmqUzrcEZlKXUI5Jt6Huy6SXOSfb7VJataqX7Z fj2jXheFES6bs2m3krEyV/sD8gNNRlz0Um+lcAIeCW+w8CcZvNTzzMFA4 A==; X-CSE-ConnectionGUID: foqmIw5sSVep7MnN4pXgnQ== X-CSE-MsgGUID: mguc1n6qTlKqaXk5auX1Xw== X-IronPort-AV: E=McAfee;i="6700,10204,11330"; a="38977693" X-IronPort-AV: E=Sophos;i="6.13,244,1732608000"; d="scan'208";a="38977693" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:33 -0800 X-CSE-ConnectionGUID: n5Xm9RG1T26Wr9axWtYwBQ== X-CSE-MsgGUID: 1L6OGLkvT2Cqzu5zsVPQwg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="113750900" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:32 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH 06/17] drm/i915/ddi: Simplify the port disabling via DDI_BUF_CTL Date: Wed, 29 Jan 2025 22:02:10 +0200 Message-ID: <20250129200221.2508101-7-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250129200221.2508101-1-imre.deak@intel.com> References: <20250129200221.2508101-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" A port can be disabled only via a modeset (or during HW state sanitization) when the port is enabled. Thus it's not required to check the port's enabled state before disabling it. In any case if the port happened to be disabled, the following disabling would be just a nop and waiting for the buffer's idle state should succeed. Simplify the disabling sequence accordingly. Signed-off-by: Imre Deak Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_ddi.c | 23 +++++------------------ 1 file changed, 5 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 3138dc4034797..24c56d2aa5f31 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3062,17 +3062,12 @@ static void mtl_disable_ddi_buf(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; - u32 val; /* 3.b Clear DDI_CTL_DE Enable to 0. */ - val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); - if (val & DDI_BUF_CTL_ENABLE) { - val &= ~DDI_BUF_CTL_ENABLE; - intel_de_write(dev_priv, DDI_BUF_CTL(port), val); + intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); - /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ - mtl_wait_ddi_buf_idle(dev_priv, port); - } + /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ + mtl_wait_ddi_buf_idle(dev_priv, port); /* 3.d Disable D2D Link */ mtl_ddi_disable_d2d_link(encoder); @@ -3089,15 +3084,8 @@ static void disable_ddi_buf(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; - bool wait = false; - u32 val; - val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); - if (val & DDI_BUF_CTL_ENABLE) { - val &= ~DDI_BUF_CTL_ENABLE; - intel_de_write(dev_priv, DDI_BUF_CTL(port), val); - wait = true; - } + intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); if (intel_crtc_has_dp_encoder(crtc_state)) intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), @@ -3105,8 +3093,7 @@ static void disable_ddi_buf(struct intel_encoder *encoder, intel_ddi_disable_fec(encoder, crtc_state); - if (wait) - intel_wait_ddi_buf_idle(dev_priv, port); + intel_wait_ddi_buf_idle(dev_priv, port); } static void intel_disable_ddi_buf(struct intel_encoder *encoder, From patchwork Wed Jan 29 20:02:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13954089 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0EBA7C02195 for ; Wed, 29 Jan 2025 20:01:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 17D5110E8AE; Wed, 29 Jan 2025 20:01:39 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="PAjANBZL"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 29ED810E8A1; Wed, 29 Jan 2025 20:01:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738180894; x=1769716894; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=+mKPTN5yadMwqOkTPFu3lSf1uoRoLPQt8a9QWjtE02o=; b=PAjANBZLnZeO22LG218cGPyG+ZDg0NP7W4AUiBnAE5p5ic4YuuRJ0192 23B+gI7iMUOPkJlYPIOmhMUFUqOCqqMZdJlCxMXLA3+Dgom7tw6+FIt5u sTwM8WdKJZco15lD98AcDt0panzP5v4W5NwPtjcMej2nWAooH55s52mIC TjM4qcMFI6hXSTt3TeAoELociIJSMNfglhK77zCqF90hv/8zjcdHdaMHs K0KhlAwr5bwRznMONgJJh0SAag4ibp79G7a9vWs0V1QuydvFJ/LpU5UCY WUdXCswiaTIVnlGfi7gS1jE/B0rgioXUxJ1GiR5caCasUl2cg3liBBelG w==; X-CSE-ConnectionGUID: A8z4wQtoRQmAjfUP+oXRdQ== X-CSE-MsgGUID: OVCRYk9xT8OXGTgC4mmzxw== X-IronPort-AV: E=McAfee;i="6700,10204,11330"; a="38977696" X-IronPort-AV: E=Sophos;i="6.13,244,1732608000"; d="scan'208";a="38977696" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:34 -0800 X-CSE-ConnectionGUID: 5O7R26cvTqmKPE6R9YZP1A== X-CSE-MsgGUID: nr872NHATL+FDHB6AIhadQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="113750902" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:33 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH 07/17] drm/i915/ddi: Simplify waiting for a port to idle via DDI_BUF_CTL Date: Wed, 29 Jan 2025 22:02:11 +0200 Message-ID: <20250129200221.2508101-8-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250129200221.2508101-1-imre.deak@intel.com> References: <20250129200221.2508101-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" When waiting for a port to idle, there is no point in distinguishing the platform specific timeouts, instead of just using the maximum timeout. Simplify things accordingly, describing the Bspec platform specific timeouts in code comments. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 78 +++++++++++------------- 1 file changed, 36 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 24c56d2aa5f31..d040558b5d029 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -177,69 +177,63 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, trans->entries[level].hsw.trans2); } -static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port) +static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port) { - int ret; + struct drm_i915_private *i915 = to_i915(display->drm); - /* FIXME: find out why Bspec's 100us timeout is too short */ - ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)) & - XELPDP_PORT_BUF_PHY_IDLE), 10000); - if (ret) - drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n", - port_name(port)); + if (DISPLAY_VER(display) >= 14) + return XELPDP_PORT_BUF_CTL1(i915, port); + else + return DDI_BUF_CTL(port); } void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, enum port port) { - if (IS_BROXTON(dev_priv)) { + struct intel_display *display = &dev_priv->display; + + /* + * Bspec's platform specific timeouts: + * MTL+ : 100 us + * BXT : fixed 16 us + * HSW-ADL: 8 us + * + * FIXME: MTL requires 10 ms based on tests, find out why 100 us is too short + */ + if (display->platform.broxton) { udelay(16); return; } - if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & - DDI_BUF_IS_IDLE), 8)) - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", + static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); + if (intel_de_wait_for_set(display, intel_ddi_buf_status_reg(display, port), + DDI_BUF_IS_IDLE, 10)) + drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n", port_name(port)); } static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; - int timeout_us; - int ret; - /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ - if (DISPLAY_VER(dev_priv) < 10) { + /* + * Bspec's platform specific timeouts: + * MTL+ : 10000 us + * DG2 : 1200 us + * TGL-ADL combo PHY: 1000 us + * TGL-ADL TypeC PHY: 3000 us + * HSW-ICL : fixed 518 us + */ + if (DISPLAY_VER(display) < 10) { usleep_range(518, 1000); return; } - if (DISPLAY_VER(dev_priv) >= 14) { - timeout_us = 10000; - } else if (IS_DG2(dev_priv)) { - timeout_us = 1200; - } else if (DISPLAY_VER(dev_priv) >= 12) { - if (intel_encoder_is_tc(encoder)) - timeout_us = 3000; - else - timeout_us = 1000; - } else { - timeout_us = 500; - } - - if (DISPLAY_VER(dev_priv) >= 14) - ret = _wait_for(!(intel_de_read(dev_priv, - XELPDP_PORT_BUF_CTL1(dev_priv, port)) & - XELPDP_PORT_BUF_PHY_IDLE), - timeout_us, 10, 10); - else - ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), - timeout_us, 10, 10); - - if (ret) - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", + static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); + if (intel_de_wait_for_clear(display, intel_ddi_buf_status_reg(display, port), + DDI_BUF_IS_IDLE, 10)) + drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n", port_name(port)); } @@ -3067,7 +3061,7 @@ static void mtl_disable_ddi_buf(struct intel_encoder *encoder, intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ - mtl_wait_ddi_buf_idle(dev_priv, port); + intel_wait_ddi_buf_idle(dev_priv, port); /* 3.d Disable D2D Link */ mtl_ddi_disable_d2d_link(encoder); From patchwork Wed Jan 29 20:02:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13954086 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F394DC0218D for ; Wed, 29 Jan 2025 20:01:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9826510E88D; Wed, 29 Jan 2025 20:01:38 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="PHDM3yAt"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4C9F310E8AB; Wed, 29 Jan 2025 20:01:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738180895; x=1769716895; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=n/jg7Tj7Lcm1bv6dY2Ga5gc67VzgU7PFl5/ml6vRdx4=; b=PHDM3yAtRpVSFY01RA9LZ4P+CMZnXP9UhPm6pGHd899UVoVoE1pTF5H9 8s3mJtXgV2CYKtnU77eNNslYUGTXJ53vElMxZqNfakPOCtzscIINhvwuE 44Z+zXx++/J01T6EkN6DHM5Bd7XjBHLmuPuIoXktHz0/B4RSvpA4164w0 3OxMEyosJEjyiP+b44tykOLBteNNrOanVB8+qjesUa0MDi9c6nFrwWOy2 UxTh/mJGvvCnVGIli+QX7q0nRoeRfHj30KEiTeQX7r+YZBB5RY2V2/uG3 0e+20J9DFESIuZNshRmgJE9JI/Qu9AU8wepZ847foy4hqFcwrOCxKVNw7 A==; X-CSE-ConnectionGUID: un7et0tURjmuOTfNxw12GA== X-CSE-MsgGUID: m9q4wTNMTNqy1syIzKa4WQ== X-IronPort-AV: E=McAfee;i="6700,10204,11330"; a="38977700" X-IronPort-AV: E=Sophos;i="6.13,244,1732608000"; d="scan'208";a="38977700" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:35 -0800 X-CSE-ConnectionGUID: trIAeGuzSnq+fft7SVW8ZQ== X-CSE-MsgGUID: SZKrV0K6SjiaNY0nyjlqqA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="113750904" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:34 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH 08/17] drm/i915/ddi: Move platform checks within mtl_ddi_enable/disable_d2d_link() Date: Wed, 29 Jan 2025 22:02:12 +0200 Message-ID: <20250129200221.2508101-9-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250129200221.2508101-1-imre.deak@intel.com> References: <20250129200221.2508101-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The prefix of the mtl_ddi_enable_d2d() / mtl_ddi_disable_d2d_link() names show already what are the relevant platforms, so the corresponding platform check is a detail that can be hidden in the functions, do so. Signed-off-by: Imre Deak Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_ddi.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index d040558b5d029..07188606a0177 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2545,6 +2545,9 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder) i915_reg_t reg; u32 set_bits, wait_bits; + if (DISPLAY_VER(dev_priv) < 14) + return; + if (DISPLAY_VER(dev_priv) >= 20) { reg = DDI_BUF_CTL(port); set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; @@ -3035,6 +3038,9 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder) i915_reg_t reg; u32 clr_bits, wait_bits; + if (DISPLAY_VER(dev_priv) < 14) + return; + if (DISPLAY_VER(dev_priv) >= 20) { reg = DDI_BUF_CTL(port); clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; @@ -3411,8 +3417,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); /* e. Enable D2D Link for C10/C20 Phy */ - if (DISPLAY_VER(dev_priv) >= 14) - mtl_ddi_enable_d2d(encoder); + mtl_ddi_enable_d2d(encoder); encoder->set_signal_levels(encoder, crtc_state); From patchwork Wed Jan 29 20:02:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13954093 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6C353C0218F for ; Wed, 29 Jan 2025 20:01:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0BD8D10E8B2; Wed, 29 Jan 2025 20:01:59 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="fM53nDY9"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5CC2010E88F; Wed, 29 Jan 2025 20:01:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738180912; x=1769716912; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=YjQLmTXvQeaUL0hdwYhe0n9S0vzRY+ZwiSi3xvJ8x+I=; b=fM53nDY9925Um+/QdkAXlpqiXurfc1+3bhFRaEow9pVXpQAOEe6qs7h4 N+H1vD4If+YYEq5tIppBgpOcVxvLrtpy/0BRq94e8//n2v7YZOqzlhpCl xVZlGK5c8bCDjhnOZod/MVAX7Jd2pWoQxuA+i4ZYSha0oj9rQY3rwi9ub KbVz3jhPsyfNGxNsFFY8Fiw7Sq+Q3G1nbsYdb1/8t05lhbMKFpicBAXwr gg2eNrpeh5Lz7r23A2BAbLPXMDuZQgVYkrWKgIzqb3N0zWeeS7P2SSBg+ JUT9/tk0mjxJAYEmS8Rb/DPnckFYexbThVSoBZNfHBC8uvgAo/40OkOJw w==; X-CSE-ConnectionGUID: yeoB6x1OTPWISKnX5HPoDQ== X-CSE-MsgGUID: VnGeznaFRoeBACLBB+LRJw== X-IronPort-AV: E=McAfee;i="6700,10204,11330"; a="38977704" X-IronPort-AV: E=Sophos;i="6.13,244,1732608000"; d="scan'208";a="38977704" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:36 -0800 X-CSE-ConnectionGUID: E06Z/SMASSu4IpYpWwCftw== X-CSE-MsgGUID: q19YnQyXQE+ryPhgThwhtg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="113750905" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:35 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH 09/17] drm/i915/ddi: Unify the platform specific functions disabling a port Date: Wed, 29 Jan 2025 22:02:13 +0200 Message-ID: <20250129200221.2508101-10-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250129200221.2508101-1-imre.deak@intel.com> References: <20250129200221.2508101-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The functions disabling a port for MTL+ and earlier platforms only differ by an extra step on MTL+ (to disable the D2D link) and the point at which the port's idle state is waited for. Combine the two functions accounting for the above differences, removing the duplication. Signed-off-by: Imre Deak Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_ddi.c | 43 ++++-------------------- 1 file changed, 7 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 07188606a0177..73702ccbb3773 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3057,58 +3057,29 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder) port_name(port)); } -static void mtl_disable_ddi_buf(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +static void intel_disable_ddi_buf(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; - /* 3.b Clear DDI_CTL_DE Enable to 0. */ intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); - /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ - intel_wait_ddi_buf_idle(dev_priv, port); + if (DISPLAY_VER(display) >= 14) + intel_wait_ddi_buf_idle(dev_priv, port); - /* 3.d Disable D2D Link */ mtl_ddi_disable_d2d_link(encoder); - /* 3.e Disable DP_TP_CTL */ if (intel_crtc_has_dp_encoder(crtc_state)) { intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), DP_TP_CTL_ENABLE, 0); } -} - -static void disable_ddi_buf(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum port port = encoder->port; - - intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); - - if (intel_crtc_has_dp_encoder(crtc_state)) - intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), - DP_TP_CTL_ENABLE, 0); intel_ddi_disable_fec(encoder, crtc_state); - intel_wait_ddi_buf_idle(dev_priv, port); -} - -static void intel_disable_ddi_buf(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - - if (DISPLAY_VER(dev_priv) >= 14) { - mtl_disable_ddi_buf(encoder, crtc_state); - - /* 3.f Disable DP_TP_CTL FEC Enable if it is needed */ - intel_ddi_disable_fec(encoder, crtc_state); - } else { - disable_ddi_buf(encoder, crtc_state); - } + if (DISPLAY_VER(display) < 14) + intel_wait_ddi_buf_idle(dev_priv, port); intel_ddi_wait_for_fec_status(encoder, crtc_state, false); } From patchwork Wed Jan 29 20:02:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13954094 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8A5F5C02194 for ; Wed, 29 Jan 2025 20:01:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2806E10E8B0; Wed, 29 Jan 2025 20:01:59 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="XtQvziQh"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9401510E89A; Wed, 29 Jan 2025 20:01:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738180913; x=1769716913; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=3x3/9ZidmbfgPxhdDKLCgL4PzXhXMvSG42IwgElzJLA=; b=XtQvziQh3AK8nJs/wr2Mph/rGjDQ+APNBZspsCZA3DzBmLYqQKgQexXU EGzKImXQtMs+xc3ctfspqRrO0283i53iB1rn061s6m+RKzpkr01eKhPTY 2YZH3ZAigk+a+B9GAGLlk6aDq2C9mgTN0SWbcCprYiG5N/GhF9lSm+ljU jJkZ/nzpqn1YxYBKebIDSH2vL/VHK93fgarec1oDplmkpi2ef+l5P+bGd IqW73kvOYEBTUGfu61kZBbUBc3yGgi32LNkLxSGgDg1K4LIXzeZDSbjc6 lirQze2WO9maZg2KGqk/oiLWK3e+ttzid125zt7k/D2kE6WcbLRZY7LMo g==; X-CSE-ConnectionGUID: Fz+KyuuzRcOPAHQD9WcYmA== X-CSE-MsgGUID: lMm/R9KZT9uEUfSoREDWIQ== X-IronPort-AV: E=McAfee;i="6700,10204,11330"; a="38977710" X-IronPort-AV: E=Sophos;i="6.13,244,1732608000"; d="scan'208";a="38977710" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:38 -0800 X-CSE-ConnectionGUID: EsL5ojutT5ilL0buDEtt/w== X-CSE-MsgGUID: bMUSaT6mSHCba3LUR0hOZQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="113750906" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:36 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH 10/17] drm/i915/ddi: Add a helper to enable a port Date: Wed, 29 Jan 2025 22:02:14 +0200 Message-ID: <20250129200221.2508101-11-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250129200221.2508101-1-imre.deak@intel.com> References: <20250129200221.2508101-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a helper to enable a port instead of open-coding it. Signed-off-by: Imre Deak Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++++++++++------------- 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 73702ccbb3773..ddb182550ad0f 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3057,6 +3057,17 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder) port_name(port)); } +static void intel_enable_ddi_buf(struct intel_encoder *encoder, u32 buf_ctl) +{ + struct intel_display *display = to_intel_display(encoder); + enum port port = encoder->port; + + intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE); + intel_de_posting_read(display, DDI_BUF_CTL(port)); + + intel_wait_ddi_buf_active(encoder); +} + static void intel_disable_ddi_buf(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -3375,7 +3386,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_connector *connector = conn_state->connector; enum port port = encoder->port; - u32 buf_ctl; + u32 buf_ctl = 0; if (!intel_hdmi_handle_sink_scrambling(encoder, connector, crtc_state->hdmi_high_tmds_clock_ratio, @@ -3440,8 +3451,6 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, * is filled with lane count, already set in the crtc_state. * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. */ - buf_ctl = DDI_BUF_CTL_ENABLE; - if (dig_port->lane_reversal) buf_ctl |= DDI_BUF_PORT_REVERSAL; if (dig_port->ddi_a_4_lanes) @@ -3467,9 +3476,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; } - intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); - - intel_wait_ddi_buf_active(encoder); + intel_enable_ddi_buf(encoder, buf_ctl); } static void intel_ddi_enable(struct intel_atomic_state *state, @@ -3692,7 +3699,6 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, struct intel_display *display = to_intel_display(crtc_state); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct intel_encoder *encoder = &dig_port->base; - enum port port = encoder->port; u32 dp_tp_ctl; /* @@ -3726,15 +3732,11 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, mtl_port_buf_ctl_program(encoder, crtc_state); /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ - intel_dp->DP |= DDI_BUF_CTL_ENABLE; if (DISPLAY_VER(display) >= 20) intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; - intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); - intel_de_posting_read(display, DDI_BUF_CTL(port)); - - /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */ - intel_wait_ddi_buf_active(encoder); + intel_enable_ddi_buf(encoder, intel_dp->DP); + intel_dp->DP |= DDI_BUF_CTL_ENABLE; } static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, @@ -3743,7 +3745,6 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct intel_encoder *encoder = &dig_port->base; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum port port = encoder->port; u32 dp_tp_ctl; dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); @@ -3766,11 +3767,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) adlp_tbt_to_dp_alt_switch_wa(encoder); + intel_enable_ddi_buf(encoder, intel_dp->DP); intel_dp->DP |= DDI_BUF_CTL_ENABLE; - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); - intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); - - intel_wait_ddi_buf_active(encoder); } static void intel_ddi_set_link_train(struct intel_dp *intel_dp, From patchwork Wed Jan 29 20:02:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13954095 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F0CCBC02196 for ; Wed, 29 Jan 2025 20:01:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 69AC610E8B5; Wed, 29 Jan 2025 20:01:59 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="jM18nmL0"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 625B010E88F; Wed, 29 Jan 2025 20:01:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738180913; x=1769716913; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ObVtlcP77zvVBys9uz+fP1lD2I0L1wlTwiNmrducPeo=; b=jM18nmL0QhIA5oZX25mbJGT9mmHcjX5Ok33cN/pYz5xnMmw9QvszPdi8 xAHSs73eZorLKb18ix20D6NnVnXuJK3U8plTy8m8fjzFeLnPAsnMx+JZ9 3YWyc2qC5CNvlpESGrL1y/ZGAS4GYLfTvZXQ1RXw+5cRrtffO61mmz9hQ v+FoIo3ZKn4pC6oCEh60efUgfSBIvdB3XCuC5wVQvZRPiA54yIJVf3OSz ODeCaNUJ1uJpssgyabrl67cM37MNHCq8DGAWhhgGed30vU6D2DYxLqOUQ agAzdKweRMSqSMzIQCH+cNU4r40b5qcT6klUwBhlKqlAOTTxyyJnNajMi g==; X-CSE-ConnectionGUID: KpqoZpccQ3aHz7EKv4eLxQ== X-CSE-MsgGUID: ThfncO7PSmqWfPY5S1WbEQ== X-IronPort-AV: E=McAfee;i="6700,10204,11330"; a="38977717" X-IronPort-AV: E=Sophos;i="6.13,244,1732608000"; d="scan'208";a="38977717" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:39 -0800 X-CSE-ConnectionGUID: FQ7UrJdPRkCyq2eSHLB7zA== X-CSE-MsgGUID: 2tQLq5LkRKalXzwyL+SbyA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="113750909" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:37 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Imre Deak Subject: [PATCH 11/17] drm/i915/ddi: Sanitize DDI_BUF_CTL register definitions Date: Wed, 29 Jan 2025 22:02:15 +0200 Message-ID: <20250129200221.2508101-12-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250129200221.2508101-1-imre.deak@intel.com> References: <20250129200221.2508101-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Imre Deak Align the DDI_BUF_CTL register flag definitions with how this is done elsewhere. Signed-off-by: Imre Deak Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7fe4e71fc08ec..5cee6a96270af 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3621,27 +3621,29 @@ enum skl_power_gate { #define _DDI_BUF_CTL_B 0x64100 /* Known as DDI_CTL_DE in MTL+ */ #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) -#define DDI_BUF_CTL_ENABLE (1 << 31) +#define DDI_BUF_CTL_ENABLE REG_BIT(31) #define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29) #define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28) -#define DDI_BUF_TRANS_SELECT(n) ((n) << 24) -#define DDI_BUF_EMP_MASK (0xf << 24) -#define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20) +#define DDI_BUF_EMP_MASK REG_GENMASK(27, 24) +#define DDI_BUF_TRANS_SELECT(n) REG_FIELD_PREP(DDI_BUF_EMP_MASK, n) +#define DDI_BUF_PHY_LINK_RATE_MASK REG_GENMASK(23, 20) +#define DDI_BUF_PHY_LINK_RATE(r) REG_FIELD_PREP(DDI_BUF_PHY_LINK_RATE_MASK, r) #define DDI_BUF_PORT_DATA_MASK REG_GENMASK(19, 18) #define DDI_BUF_PORT_DATA_10BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0) #define DDI_BUF_PORT_DATA_20BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1) #define DDI_BUF_PORT_DATA_40BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2) -#define DDI_BUF_PORT_REVERSAL (1 << 16) +#define DDI_BUF_PORT_REVERSAL REG_BIT(16) #define DDI_BUF_LANE_STAGGER_DELAY_MASK REG_GENMASK(15, 8) #define DDI_BUF_LANE_STAGGER_DELAY(symbols) REG_FIELD_PREP(DDI_BUF_LANE_STAGGER_DELAY_MASK, \ symbols) -#define DDI_BUF_IS_IDLE (1 << 7) +#define DDI_BUF_IS_IDLE REG_BIT(7) #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) -#define DDI_A_4_LANES (1 << 4) -#define DDI_PORT_WIDTH(width) (((width) == 3 ? 4 : ((width) - 1)) << 1) -#define DDI_PORT_WIDTH_MASK (7 << 1) +#define DDI_A_4_LANES REG_BIT(4) +#define DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1) +#define DDI_PORT_WIDTH(width) REG_FIELD_PREP(DDI_PORT_WIDTH_MASK, \ + (width) == 3 ? 4 : (width) - 1) #define DDI_PORT_WIDTH_SHIFT 1 -#define DDI_INIT_DISPLAY_DETECTED (1 << 0) +#define DDI_INIT_DISPLAY_DETECTED REG_BIT(0) /* DDI Buffer Translations */ #define _DDI_BUF_TRANS_A 0x64E00 From patchwork Wed Jan 29 20:02:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13954090 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AFD36C0218D for ; Wed, 29 Jan 2025 20:01:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5FD9710E8AA; Wed, 29 Jan 2025 20:01:57 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="aNSc6ANv"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0D72A10E8A0; Wed, 29 Jan 2025 20:01:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738180915; x=1769716915; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Zq/Hvqy9mbbOFlZmCBp5Gw0viyiw0NBU53mQ3siYh88=; b=aNSc6ANvGVinoK4WPtfgEk276B3dBRovZG8BpGjpu9It1Vi+tQY8qZsD aLwI4eghW1W3lLRm3NwdDb31YkobNmn5/sOo1fPF/sD+YfrjEjlvTIlom nAcnBrx3qjv5iXgmWrLJA2WiGb3Zs9z0k/MqIVr6eUYRe1tUMgrw8lFui cPHTwCtv+8EkFBUDwKc3zNauVJgFR7lrV1ydny4jkUMqmFsRX0trsIMGc 2OmMmYxrCntS259tYKxmDiJrrfFop0koS2gK8DNZED6ScPCtIcmkRAYB+ DJFAi3iQd5igamm2JGYtbyqOegWWeyDA6SVd5EDbbcIbiRUsRjakPGNTv Q==; X-CSE-ConnectionGUID: 6RWJX1BuQ1+KbISliDfHCQ== X-CSE-MsgGUID: PMH0lc+BSj6edhfy5vEGjg== X-IronPort-AV: E=McAfee;i="6700,10204,11330"; a="38977729" X-IronPort-AV: E=Sophos;i="6.13,244,1732608000"; d="scan'208";a="38977729" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:40 -0800 X-CSE-ConnectionGUID: xP4UFoCaTIGX9hbMfUqbIg== X-CSE-MsgGUID: eQjnG+A4SWmTeoVVMea2pQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="113750911" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:39 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Imre Deak Subject: [PATCH 12/17] drm/i915/ddi: Configure/enable a port in DDI_BUF_CTL via read-modify-write Date: Wed, 29 Jan 2025 22:02:16 +0200 Message-ID: <20250129200221.2508101-13-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250129200221.2508101-1-imre.deak@intel.com> References: <20250129200221.2508101-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Imre Deak The various flags in DDI_BUF_CTL must be programmed at different places during a modeset. The expected value of the register at any moment is cached in the intel_dp::DP variable and the whole register is written using this variable. A simpler way would be not maintaining the cached value of the register at all and update only specific fields in the register via read-modify-write. Some places - like D2D link enabling or the port disabling - use RMW already. Based on the above update the register via RMW during the port configuration / enabling as well. After all the places updating DDI_BUF_CTL are changed - probably the voltage-swing/pre-emphasis level setting is the only one remaining - tracking the register value in intel_dp:DP could be removed. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ddb182550ad0f..64c42505f2ad6 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -359,6 +359,10 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, if (IS_ALDERLAKE_P(i915) && intel_encoder_is_tc(encoder)) { intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); + /* + * TODO: remove the following once DDI_BUF_CTL is updated via + * an RMW everywhere. + */ if (!intel_tc_port_in_tbt_alt_mode(dig_port)) intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; } @@ -370,6 +374,22 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, } } +static u32 intel_ddi_buf_ctl_config_mask(struct intel_encoder *encoder) +{ + struct intel_display *display = to_intel_display(encoder); + u32 mask = DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES | + DDI_PORT_WIDTH_MASK; + + if (DISPLAY_VER(display) >= 14) + mask |= DDI_BUF_PORT_DATA_MASK; + if (display->platform.alderlake_p) + mask |= DDI_BUF_PHY_LINK_RATE_MASK; + if (IS_DISPLAY_VER(display, 11, 13)) + mask |= DDI_BUF_LANE_STAGGER_DELAY_MASK; + + return mask; +} + static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, enum port port) { @@ -3062,7 +3082,8 @@ static void intel_enable_ddi_buf(struct intel_encoder *encoder, u32 buf_ctl) struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; - intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE); + intel_de_rmw(display, DDI_BUF_CTL(port), + intel_ddi_buf_ctl_config_mask(encoder), buf_ctl | DDI_BUF_CTL_ENABLE); intel_de_posting_read(display, DDI_BUF_CTL(port)); intel_wait_ddi_buf_active(encoder); From patchwork Wed Jan 29 20:02:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13954091 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3BEF3C02195 for ; Wed, 29 Jan 2025 20:01:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CE01310E8B1; Wed, 29 Jan 2025 20:01:57 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="mUbp9/Cp"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id AADA610E8AB; Wed, 29 Jan 2025 20:01:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738180917; x=1769716917; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=7wTE5eq/gsTZ+bmnqapWApK95QJXUGwCUf8KXQnrk+k=; b=mUbp9/Cpj5lOJLVQ50CtguDYWZdtMV/nSFYCoDu38RIFo9uNQyj6vQ1O wqtTf/k53sWkNTvRck3WDABeGhk+Ryetk214P1R3CVasj6vnWXYEY77cK Hr1cV9RnPbx8Z2b6Zb+RdYzEYacrKBuwGuRgL2pIDBvznHIHDykVp38oD iSA5VyC5dvQvcqGPP9Dm4k7IQZXwjtmEs0stN0Vat/6PhiBOaH8NUc2BT O5i15VqE0FLzfymRyKWDHP9QjxSgYHrLhHgj3FPQfiqjOD6WudXV5+Caj NXsZNBajULiMEhE6ROq33wqiMXcF3dqrjUQab6lqX1L4mCya7FGWPKyF5 g==; X-CSE-ConnectionGUID: zmQ+Hr/9RPyMOoHvFzxEyw== X-CSE-MsgGUID: b8mQzPw7RaOQzNlsp2e20g== X-IronPort-AV: E=McAfee;i="6700,10204,11330"; a="38977737" X-IronPort-AV: E=Sophos;i="6.13,244,1732608000"; d="scan'208";a="38977737" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:41 -0800 X-CSE-ConnectionGUID: vU7fflPqTxiM0j2+j7VYiA== X-CSE-MsgGUID: BZ/DJMtISyC8rTeOPULWuw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="113750912" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:40 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH 13/17] drm/i915/ddi: Factor out a helper to get DDI_BUF_CTL's config value Date: Wed, 29 Jan 2025 22:02:17 +0200 Message-ID: <20250129200221.2508101-14-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250129200221.2508101-1-imre.deak@intel.com> References: <20250129200221.2508101-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Factor out a function to get the configuration fields in the DDI_BUF_CTL register. This can be used for configuring an HDMI output as well. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 32 ++++++++++++++++-------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 64c42505f2ad6..dd8ae5cf96c70 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -333,45 +333,55 @@ static int dp_phy_lane_stagger_delay(int port_clock) return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000); } -static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +static u32 intel_ddi_buf_ctl_config_val(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *i915 = to_i915(encoder->base.dev); - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + u32 val = 0; /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ - intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) | + val |= DDI_PORT_WIDTH(crtc_state->lane_count) | DDI_BUF_TRANS_SELECT(0); if (dig_port->lane_reversal) - intel_dp->DP |= DDI_BUF_PORT_REVERSAL; + val |= DDI_BUF_PORT_REVERSAL; if (dig_port->ddi_a_4_lanes) - intel_dp->DP |= DDI_A_4_LANES; + val |= DDI_A_4_LANES; if (DISPLAY_VER(i915) >= 14) { if (intel_dp_is_uhbr(crtc_state)) - intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; + val |= DDI_BUF_PORT_DATA_40BIT; else - intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; + val |= DDI_BUF_PORT_DATA_10BIT; } if (IS_ALDERLAKE_P(i915) && intel_encoder_is_tc(encoder)) { - intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); + val |= ddi_buf_phy_link_rate(crtc_state->port_clock); /* * TODO: remove the following once DDI_BUF_CTL is updated via * an RMW everywhere. */ if (!intel_tc_port_in_tbt_alt_mode(dig_port)) - intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; + val |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; } if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) { int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock); - intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay); + val |= DDI_BUF_LANE_STAGGER_DELAY(delay); } + + return val; +} + +static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + intel_dp->DP = intel_ddi_buf_ctl_config_val(encoder, crtc_state); } static u32 intel_ddi_buf_ctl_config_mask(struct intel_encoder *encoder) From patchwork Wed Jan 29 20:02:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13954092 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E5A07C02193 for ; Wed, 29 Jan 2025 20:01:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8D92610E8AB; Wed, 29 Jan 2025 20:01:58 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="cstEYPpa"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6E99E10E8AA; Wed, 29 Jan 2025 20:01:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738180916; x=1769716916; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=XDBwVev7FV7xldNU1PsGCXPQj94g5oT9hVpGR7jnwiY=; b=cstEYPpasAIVipSPpvD6w+Eo63OlSwBlM7YZJVgen/A3KidqPPC3FNmR nNJxl4jZ4HoMWhP3xfi6nwe8fsyCEX3g3gcxkjaYYy5t3NGG6iIKqhY0g LoefA6xFXwuPIpwiOTB97HpGXtBWxgC9i3wiPgQmbRJBIj4asJ/f+i7kd 4jyv3YQB04sKLo/pzPs+PkLKv/ZcXR2xRNliZQJvFr1LqSl10ABmoXIRV xSrd4tGflRnC8sKmCURsFQVpeOx0O1459GEkqv5EyBxE3mzZHZ2LLOyOF eMaq8h8JLCTsOChxOXPk+3QOUArTMQJruHa0MBYsgN1FNGFMlZ/SdHpdf Q==; X-CSE-ConnectionGUID: S25yYA3sSl6Nf4oUg0UwaQ== X-CSE-MsgGUID: 1yiZHuj2TbmpRES707qiwg== X-IronPort-AV: E=McAfee;i="6700,10204,11330"; a="38977746" X-IronPort-AV: E=Sophos;i="6.13,244,1732608000"; d="scan'208";a="38977746" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:43 -0800 X-CSE-ConnectionGUID: donRXytVTNSEi/A1CnpKKQ== X-CSE-MsgGUID: G8WYs3PsRta76gyMNs+AEg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="113750914" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:41 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH 14/17] drm/i915/ddi: Reuse helper to compute the HDMI DDI_BUF_CTL config Date: Wed, 29 Jan 2025 22:02:18 +0200 Message-ID: <20250129200221.2508101-15-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250129200221.2508101-1-imre.deak@intel.com> References: <20250129200221.2508101-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Reuse the existing helper to compute the configuration value of the DDI_BUF_CTL register for HDMI outputs instead of open-coding this. Note that dropping the XE2LPD_DDI_BUF_D2D_LINK_ENABLE flag is ok, since an earlier mtl_ddi_enable_d2d() has set it already and intel_enable_ddi_buf()'s RMW will not update this flag. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 30 ++++++++---------------- 1 file changed, 10 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index dd8ae5cf96c70..e03ec9a235d33 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -339,11 +339,14 @@ static u32 intel_ddi_buf_ctl_config_val(struct intel_encoder *encoder, struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + bool is_dp = intel_crtc_has_dp_encoder(crtc_state); u32 val = 0; /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ - val |= DDI_PORT_WIDTH(crtc_state->lane_count) | - DDI_BUF_TRANS_SELECT(0); + if (is_dp || DISPLAY_VER(display) >= 14) + val |= DDI_PORT_WIDTH(crtc_state->lane_count); + + val |= DDI_BUF_TRANS_SELECT(0); if (dig_port->lane_reversal) val |= DDI_BUF_PORT_REVERSAL; @@ -351,14 +354,15 @@ static u32 intel_ddi_buf_ctl_config_val(struct intel_encoder *encoder, val |= DDI_A_4_LANES; if (DISPLAY_VER(i915) >= 14) { - if (intel_dp_is_uhbr(crtc_state)) + if (is_dp && intel_dp_is_uhbr(crtc_state)) val |= DDI_BUF_PORT_DATA_40BIT; else val |= DDI_BUF_PORT_DATA_10BIT; } if (IS_ALDERLAKE_P(i915) && intel_encoder_is_tc(encoder)) { - val |= ddi_buf_phy_link_rate(crtc_state->port_clock); + if (is_dp) + val |= ddi_buf_phy_link_rate(crtc_state->port_clock); /* * TODO: remove the following once DDI_BUF_CTL is updated via * an RMW everywhere. @@ -367,7 +371,7 @@ static u32 intel_ddi_buf_ctl_config_val(struct intel_encoder *encoder, val |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; } - if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) { + if (is_dp && IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) { int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock); val |= DDI_BUF_LANE_STAGGER_DELAY(delay); @@ -3417,7 +3421,6 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_connector *connector = conn_state->connector; enum port port = encoder->port; - u32 buf_ctl = 0; if (!intel_hdmi_handle_sink_scrambling(encoder, connector, crtc_state->hdmi_high_tmds_clock_ratio, @@ -3482,11 +3485,6 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, * is filled with lane count, already set in the crtc_state. * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. */ - if (dig_port->lane_reversal) - buf_ctl |= DDI_BUF_PORT_REVERSAL; - if (dig_port->ddi_a_4_lanes) - buf_ctl |= DDI_A_4_LANES; - if (DISPLAY_VER(dev_priv) >= 14) { u32 port_buf = 0; @@ -3497,17 +3495,9 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port), XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); - - buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); - - if (DISPLAY_VER(dev_priv) >= 20) - buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; - } else if (IS_ALDERLAKE_P(dev_priv) && intel_encoder_is_tc(encoder)) { - drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); - buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; } - intel_enable_ddi_buf(encoder, buf_ctl); + intel_enable_ddi_buf(encoder, intel_ddi_buf_ctl_config_val(encoder, crtc_state)); } static void intel_ddi_enable(struct intel_atomic_state *state, From patchwork Wed Jan 29 20:02:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13954098 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 591DFC0218D for ; Wed, 29 Jan 2025 20:02:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F202110E8B7; Wed, 29 Jan 2025 20:02:17 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="LRxlDvIU"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id ED20D10E8AA; Wed, 29 Jan 2025 20:01:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738180917; x=1769716917; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=HvrQBvZz0GNu8J/IJF4DZbBIMzbzmagjWxxifeK2g0g=; b=LRxlDvIUpldfgdWcUqlBv7OZk7h9gWG6kAr0ymqyEY1LqaR82kwk32pw R04OvuhY2xmXYBmjQUVhxRdRpdgIL2TTCbzfqMHJl7ycO0kFHRBGMsOWF EfiweuFJnNzRtrB9NYLV04GbECzbX0+yyr2FjIdFvfNGTB20sQ7vQu8zQ inEzaCflp9L+J/3I1GW3pkJNzPgeASOkenB77WWLvMsCOPFpWoF/mcuf8 WYaime+zb17U8Ak8alkKsOu446p8KoX/L0UL8a8UV1hT25sF4+AoSlXQN 5Yc5IgQ7AyV0D71RkcpWHwqdcLdNxfG6hDqLsAi6hXZdoO9XfepVOgNZL g==; X-CSE-ConnectionGUID: QLjwLYDsQyGoit4gCNsJqA== X-CSE-MsgGUID: kcUkqoE6Skav88kXON/7zQ== X-IronPort-AV: E=McAfee;i="6700,10204,11330"; a="38977751" X-IronPort-AV: E=Sophos;i="6.13,244,1732608000"; d="scan'208";a="38977751" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:44 -0800 X-CSE-ConnectionGUID: Cr3OmCl1T3SPLRzOl8TtVQ== X-CSE-MsgGUID: PDV4jHbhTViUnHN9PzK71w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="113750917" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:42 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH 15/17] drm/i915/ddi: Reuse helper to compute the HDMI PORT_BUF_CTL1 config Date: Wed, 29 Jan 2025 22:02:19 +0200 Message-ID: <20250129200221.2508101-16-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250129200221.2508101-1-imre.deak@intel.com> References: <20250129200221.2508101-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Reuse the existing helper to compute the configuration value of the XELPDP_PORT_BUF_CTL1 register for HDMI outputs instead of open-coding this. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index e03ec9a235d33..431db1e6b6f07 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2607,9 +2607,12 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, enum port port = encoder->port; u32 val = 0; + if (DISPLAY_VER(display) < 14) + return; + val |= XELPDP_PORT_WIDTH(crtc_state->lane_count); - if (intel_dp_is_uhbr(crtc_state)) + if (intel_crtc_has_dp_encoder(crtc_state) && intel_dp_is_uhbr(crtc_state)) val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; else val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; @@ -2618,7 +2621,8 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, val |= XELPDP_PORT_REVERSAL; intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), - XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, + XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL | + XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, val); } @@ -3418,7 +3422,6 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, { struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_connector *connector = conn_state->connector; enum port port = encoder->port; @@ -3485,17 +3488,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, * is filled with lane count, already set in the crtc_state. * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. */ - if (DISPLAY_VER(dev_priv) >= 14) { - u32 port_buf = 0; - - port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count); - - if (dig_port->lane_reversal) - port_buf |= XELPDP_PORT_REVERSAL; - - intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port), - XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); - } + mtl_port_buf_ctl_program(encoder, crtc_state); intel_enable_ddi_buf(encoder, intel_ddi_buf_ctl_config_val(encoder, crtc_state)); } From patchwork Wed Jan 29 20:02:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13954096 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5E0B3C02197 for ; Wed, 29 Jan 2025 20:02:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6A36F10E8B6; Wed, 29 Jan 2025 20:01:59 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="AblBYmKE"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id CD11110E8B0; Wed, 29 Jan 2025 20:01:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738180918; x=1769716918; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/4IkloCPDRaUl8pM1jxtTxWUIphdBunBdXuUrf8vfLE=; b=AblBYmKEV7ofrsdeoRzwP06YuFsvheUoX5aXvHXWDxzrjHvYQvWt1yrC 1czVqUAp6GPggFHKXkBM05s1NgmHJXau2SuxEzxPxsVQJazpi1Zv3kWCw XXL9xVKDlvLvHGipWvWzejDWbW7Xvq+QZ4tlzT8UAc9SMXMNe4GiwH1Zi mr7DPP9Vm5aMGj9Rf/vYEI7JKom0PfeaPQlkIqN0/qRmthuici007uNz7 dPSD29guzFzq4A/UnGqcPoluNysNBN7OlEuVL0gawcCdPTsYWMCMy4itx oEdGzNYzrayS3PjweQpppXsN5/tdmA+f4evWG+zIAs+om2Gv16Lk7P5AC w==; X-CSE-ConnectionGUID: MxLwZftCQaCk3ViDwGxqZw== X-CSE-MsgGUID: CVwxAQkoTia82Y2vj77yQw== X-IronPort-AV: E=McAfee;i="6700,10204,11330"; a="38977760" X-IronPort-AV: E=Sophos;i="6.13,244,1732608000"; d="scan'208";a="38977760" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:45 -0800 X-CSE-ConnectionGUID: CeivIZLDTZyffgs58qAxVA== X-CSE-MsgGUID: h1sKaDyBQNid28DWXLgbaA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="113750920" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:44 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Imre Deak Subject: [PATCH 16/17] drm/i915/ddi: Move platform/encoder checks within adlp_tbt_to_dp_alt_switch_wa() Date: Wed, 29 Jan 2025 22:02:20 +0200 Message-ID: <20250129200221.2508101-17-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250129200221.2508101-1-imre.deak@intel.com> References: <20250129200221.2508101-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Imre Deak The prefix of adlp_tbt_to_dp_alt_switch_wa() function name shows already what is the relevant platform and encoder type/mode, so the corresponding checks are a detail that can be hidden in the function, do so. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 431db1e6b6f07..a2d82a4c4aa77 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3699,10 +3699,16 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state, static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); enum tc_port tc_port = intel_encoder_to_tc(encoder); int ln; + if (!display->platform.alderlake_p || + (!intel_tc_port_in_dp_alt_mode(dig_port) && !intel_tc_port_in_legacy_mode(dig_port))) + return; + for (ln = 0; ln < 2; ln++) intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); } @@ -3777,9 +3783,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); - if (IS_ALDERLAKE_P(dev_priv) && - (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) - adlp_tbt_to_dp_alt_switch_wa(encoder); + adlp_tbt_to_dp_alt_switch_wa(encoder); intel_enable_ddi_buf(encoder, intel_dp->DP); intel_dp->DP |= DDI_BUF_CTL_ENABLE; From patchwork Wed Jan 29 20:02:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13954097 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0FA25C02195 for ; Wed, 29 Jan 2025 20:02:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9537A10E8B8; Wed, 29 Jan 2025 20:02:00 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="jIQhS5o0"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id DD09310E8B0; Wed, 29 Jan 2025 20:01:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738180919; x=1769716919; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=M9NJgq1Y1hVQuw72B1H9u6s5rF7eFSlV6YJN6iSDS9U=; b=jIQhS5o0WA0z4G0c83ZnDEYfBPBOm4ASLDUM8fOUh+XHVwOQ9H6zr43C 5GA5WTauAg1aCvvWZRdmqVrox6TRkt96UmBXsFQLFSVZj/Id8TmFYZ2kR ZUL8utryhRpVvrxO6rocPeotN/jx6QAVG2OMr8+AJo/DT2Rk+FDY9rQBm RMVnQi62O3lsKEY7tDcpQZUZdiN6+EgrppZMn4CHlqJWr3a0ZxBPuF87p W+he4LHDSPzz0A9kASoPgX5mBrc4noxOFsdfF58Kw4q3t1PtevxN+p8LW V34SNwzgzLoSaUIFqSoSmIA0OqOepoWwD9n1j/KVmWAM+r9Jq4duMUNOh g==; X-CSE-ConnectionGUID: JKYtW5SwSSCLhw6EdmAYcw== X-CSE-MsgGUID: kpmqC/Y5SlClBhU5L+B4ZQ== X-IronPort-AV: E=McAfee;i="6700,10204,11330"; a="38977773" X-IronPort-AV: E=Sophos;i="6.13,244,1732608000"; d="scan'208";a="38977773" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:46 -0800 X-CSE-ConnectionGUID: ZOdHJTgAQ862biLClJP7WQ== X-CSE-MsgGUID: ykqZK7/kQDq2a9VQK26PuQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="113750921" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 12:01:45 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH 17/17] drm/i915/ddi: Unify the platform specific functions enabling a port Date: Wed, 29 Jan 2025 22:02:21 +0200 Message-ID: <20250129200221.2508101-18-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20250129200221.2508101-1-imre.deak@intel.com> References: <20250129200221.2508101-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The functions enabling a port (as part of link training) for MTL+ and earlier platforms only differ by extra steps on MTL+: - enable the D2D link - set the link parameters - configure the PORT_BUF_CTL1 register and an extra step on earlier platforms: - apply an ADLP TypeC workaround All the extra steps are already/can be skipped on unrelated platforms. Combine the two functions accounting for the above differences, removing the duplication. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 52 ++++-------------------- 1 file changed, 8 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index a2d82a4c4aa77..e8bea49a27dbc 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2721,7 +2721,7 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, * stream or multi-stream master transcoder" can just be performed * unconditionally here. * - * mtl_ddi_prepare_link_retrain() that is called by + * intel_ddi_prepare_link_retrain() that is called by * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, * 6.i and 6.j * @@ -3713,8 +3713,8 @@ static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); } -static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state) +static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); @@ -3729,7 +3729,6 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); - /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || intel_dp_is_uhbr(crtc_state)) { @@ -3742,16 +3741,15 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); - /* 6.f Enable D2D Link */ + adlp_tbt_to_dp_alt_switch_wa(encoder); + mtl_ddi_enable_d2d(encoder); - /* 6.g Configure voltage swing and related IO settings */ - encoder->set_signal_levels(encoder, crtc_state); + if (DISPLAY_VER(display) >= 14) + encoder->set_signal_levels(encoder, crtc_state); - /* 6.h Configure PORT_BUF_CTL1 */ mtl_port_buf_ctl_program(encoder, crtc_state); - /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ if (DISPLAY_VER(display) >= 20) intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; @@ -3759,36 +3757,6 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, intel_dp->DP |= DDI_BUF_CTL_ENABLE; } -static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state) -{ - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); - struct intel_encoder *encoder = &dig_port->base; - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - u32 dp_tp_ctl; - - dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); - - drm_WARN_ON(&dev_priv->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); - - dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || - intel_dp_is_uhbr(crtc_state)) { - dp_tp_ctl |= DP_TP_CTL_MODE_MST; - } else { - dp_tp_ctl |= DP_TP_CTL_MODE_SST; - if (crtc_state->enhanced_framing) - dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; - } - intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); - intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); - - adlp_tbt_to_dp_alt_switch_wa(encoder); - - intel_enable_ddi_buf(encoder, intel_dp->DP); - intel_dp->DP |= DDI_BUF_CTL_ENABLE; -} - static void intel_ddi_set_link_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, u8 dp_train_pat) @@ -4612,7 +4580,6 @@ static const struct drm_encoder_funcs intel_ddi_funcs = { static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) { - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); struct intel_connector *connector; enum port port = dig_port->base.port; @@ -4621,10 +4588,7 @@ static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) return -ENOMEM; dig_port->dp.output_reg = DDI_BUF_CTL(port); - if (DISPLAY_VER(i915) >= 14) - dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; - else - dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; + dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; dig_port->dp.set_link_train = intel_ddi_set_link_train; dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;