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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c13a0efsm2733042f8f.60.2025.01.30.10.25.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 30 Jan 2025 10:25:29 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Rob Herring , qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Igor Mitsyanko , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 1/8] hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition Date: Thu, 30 Jan 2025 19:24:34 +0100 Message-ID: <20250130182441.40480-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250130182441.40480-1-philmd@linaro.org> References: <20250130182441.40480-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The 32 IRQ lines skipped are the GIC internal ones. Use the GIC_INTERNAL definition for clarity. No logical change. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/exynos4210.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index dd0edc81d5c..99b05a175d6 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -393,8 +393,9 @@ static void exynos4210_init_board_irqs(Exynos4210State *s) } } if (irq_id) { + irq_id -= GIC_INTERNAL; qdev_connect_gpio_out(splitter, splitin, - qdev_get_gpio_in(extgicdev, irq_id - 32)); + qdev_get_gpio_in(extgicdev, irq_id)); } } for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { @@ -413,6 +414,7 @@ static void exynos4210_init_board_irqs(Exynos4210State *s) } if (irq_id) { + irq_id -= GIC_INTERNAL; assert(splitcount < EXYNOS4210_NUM_SPLITTERS); splitter = DEVICE(&s->splitter[splitcount]); qdev_prop_set_uint16(splitter, "num-lines", 2); @@ -421,7 +423,7 @@ static void exynos4210_init_board_irqs(Exynos4210State *s) s->irq_table[n] = qdev_get_gpio_in(splitter, 0); qdev_connect_gpio_out(splitter, 0, qdev_get_gpio_in(intcdev, n)); qdev_connect_gpio_out(splitter, 1, - qdev_get_gpio_in(extgicdev, irq_id - 32)); + qdev_get_gpio_in(extgicdev, irq_id)); } else { s->irq_table[n] = qdev_get_gpio_in(intcdev, n); } From patchwork Thu Jan 30 18:24:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13954832 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0A8E1C02193 for ; Thu, 30 Jan 2025 18:27:55 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdZFI-0001za-B8; Thu, 30 Jan 2025 13:26:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdZEW-0001J1-MB for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:25:46 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tdZEU-00017X-Rc for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:25:44 -0500 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-38633b5dbcfso1197750f8f.2 for ; Thu, 30 Jan 2025 10:25:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738261541; x=1738866341; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vZk0oTGxDURxLqCpPV0Zd69bGvF/XaBnOTd5i1RlcsU=; b=D2ttSnEmww329jc93cCX7Loc3QveFlpRjHa49/XByX5SKh5Aa8ydJXM9anAxKPNEdT hKOz+JVXlkddkGpV2OwUx7a/iiUnt6KT4jgOfsIGxQeitAbqVCtSYgng4m8EH7GaqdkF odTzSA8Sy5bfebp7VjlL3WIm2kT4cpsk7YtGpKRoFu1UPRK4pHkmPRrnBAhgeOfL+blg uynTuvjQLx+wxHFmskadigoEfcgxKAoF9VOebAD+fUpHk2cLK7TKv9FKJD3dYxplCJvt tsqEBL0OjQIsP0PlsKOR/4A9uRUTR8Ul5T1vLawhxSjBoJTXj+dhOzTQyEclpfHwA+xE PP4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738261541; x=1738866341; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vZk0oTGxDURxLqCpPV0Zd69bGvF/XaBnOTd5i1RlcsU=; b=qSEzUDtyRihVdJXaXZCpuL/dEK3fzEzRKU4aOUXchBpUAWm0I3usoPcN+ewrCr6aTZ jJEV49ZLqeAFAcc5tzfCdyT4C3PX3fXdsHoCcTpiEeJYktHNT+Cbb3b1vn329oTjOGKJ Rhj53U5QI5vkKliBLqRKp9ZMZ4pdB0wvNtRLjS5rIFyDosjgIUu/erE6ggYL59gJdNXQ 0C1crQQbHqbiHuVKTZ9z4GTXYPrEiJf8PZ1DMolEuPtbEMTvMWMH9EsGnS8kyYKA1/at h+/8XRYzoe/vDUDRXzPs5jDLQxQFsTTDvk+EATBTVJU/Kd3A9TFQzPhpsUPeUf7xMUdW XZjw== X-Gm-Message-State: AOJu0Yyg+NqNt6gfJ3rTEYuminST0AWwcfRXz1Se3yJRZbvFKaURQVwX 7h+phY139a6hZ9je760oZmrXVZJuHIpNxO+2FuauWwp1pbfAUPtIt9YDGMr/0gum3o6M+NeLYTo iO20= X-Gm-Gg: ASbGnctbavI1SWSNm6ZK2Z+EoJ467la5G8y9pijFWf6v9XJxCa1NF6Ozp8xSbEX/Qph pPi8HbqifZjfd4Jnt+JHM4DEmSljnvqdUt0Dx8+CA9LWI42/Pw2J6i4cbQQdkVbj6mpFeGbUqJo hZC8cseRMDvUrlVvD3zx3wKy5ESiwsEuwovbHc3TW7f6djLloo/go8mFA+eebArAOrDLAyj8Qob SS6fq9v+ZlBMbCFi3Gi6BMoSMOwfhz9KQm5lmlSI/yZfOcdaR4AKMQrKtLOY05qnZD89XhDMWQ2 Jxorbbv6ueGYQF7I+ik0ew8cHVjQ0Zh12Wp/pRsJIacqCuJXng9L1PqyNJ2iSsrdwQ== X-Google-Smtp-Source: AGHT+IGfE188vZLMhP5pd6SCSIhGlCHXFdgRfnECKuHFzu88TvKH4QJ5gl/qySXuELw6dDYw7rXiHQ== X-Received: by 2002:a5d:4f90:0:b0:385:ee3f:5cbf with SMTP id ffacd0b85a97d-38c519526edmr6505846f8f.20.1738261540837; Thu, 30 Jan 2025 10:25:40 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c1b5780sm2721855f8f.67.2025.01.30.10.25.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 30 Jan 2025 10:25:40 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Rob Herring , qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Igor Mitsyanko , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 2/8] hw/arm/exynos4210: Explicit number of GIC external IRQs Date: Thu, 30 Jan 2025 19:24:35 +0100 Message-ID: <20250130182441.40480-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250130182441.40480-1-philmd@linaro.org> References: <20250130182441.40480-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When not specified, Cortex-A9MP configures its GIC with 64 external IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts configurable"). Add the GIC_EXT_IRQS definition (with a comment) to make that explicit. Except explicitly setting a property value to its same implicit value, there is no logical change intended. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/exynos4210.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 99b05a175d6..75d6e4d1ab9 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -103,6 +103,14 @@ #define EXYNOS4210_PL330_BASE1_ADDR 0x12690000 #define EXYNOS4210_PL330_BASE2_ADDR 0x12850000 +/* + * The Cortex-A9MP may have anything from 0 to 224 external interrupt + * IRQ lines (with another 32 internal). We default to 64+32, which + * is the number provided by the Cortex-A9MP test chip in the + * Realview PBX-A9 and Versatile Express A9 development boards. + */ +#define GIC_EXT_IRQS 64 + enum ExtGicId { EXT_GIC_ID_MDMA_LCD0 = 66, EXT_GIC_ID_PDMA0, @@ -588,6 +596,8 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) /* Private memory region and Internal GIC */ qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS); + qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-irq", + GIC_EXT_IRQS + GIC_INTERNAL); busdev = SYS_BUS_DEVICE(&s->a9mpcore); sysbus_realize(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); From patchwork Thu Jan 30 18:24:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13954825 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 36244C02193 for ; Thu, 30 Jan 2025 18:26:50 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdZFS-0002Hl-C4; Thu, 30 Jan 2025 13:26:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdZEk-0001Rw-Rv for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:26:00 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tdZEj-0001B6-4a for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:25:58 -0500 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-4362bae4d7dso8583705e9.1 for ; Thu, 30 Jan 2025 10:25:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738261555; x=1738866355; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9Z3aEZJL4Zoy5jUwLn3/iNglhcvTDiQUnyONCdVRxkU=; b=asK31Kya/tBaoaeQLuAFOYHg/L+Pas2BLip/vANU0jpXeNvky+txTkWeUVWWY+APz4 3s3f4cCRQTLlUW7h6us66FMzZyGytl6YZD+ql4LmP6tesPQfmfclq76G2e7Ry/ZIYvfZ RabVQxXJS7jWgW7Z2JLyHqnjXKKFkoAEeOidtIoC0hXQO4FhT8maikeA7GG/AQVhQsRq wHb99Qp77ree4muP9ySTzcJ8NyXxgn9rC5iuIniCsuI3e0sAUaPnl3qj8Tgpr4IbZTAs v+U1T892rx1p7+NTErBfo48a0U68ZpHsRqaifdDivFGy76Kc2WdIjsB/wbKCxA1R6qY3 WCjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738261555; x=1738866355; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9Z3aEZJL4Zoy5jUwLn3/iNglhcvTDiQUnyONCdVRxkU=; b=uWYTWqrvv5tNGrF6bR718ftceIPZUTCs63/vi7RCr58f/xiQeG1bc+w8Yz5LdTtgNn V/X98nkdyzDSoqqBsXMLO+iXl2qitanZEBr8XFvEk9XxFfpspyqv4XbjbSqp7Qs6mIKJ 2ozmTgQkD+07w3kdJ5tSvbEjNG0BKK94iWxMrp7YqafpjWxjaqNaf8UV9VUvkgMRCWxV spS5m4g1hIkImHTxbn0kmTLvN17Srkb9wDHX90E1lwowTA9By6A6sGqz03w7fu5Mu3W4 II5IC17JYyMmwjrKojH1LOhez5RZQZXJNyFDqekCViXAC+8q/Mu1/bzImWkAvPNcAmE7 kyBA== X-Gm-Message-State: AOJu0YxV0T+E/QJ3fHyXeryoircjOVbLWSfhyn3vP7FquxFNEzpHlg14 SfUZ7ngYdxJuhEz/DXtyfX1shbsFFwOgK2nMIiTxAaIFhn1qTwkbwSffDthRd70ASJxCXiFdA5S 9s74= X-Gm-Gg: ASbGnctL/EhmgZAzcvXxmKYwpoxmxcmN+AMYKFu0bwChE2EwbTQK2Z9kdpXAzDjU3Eg trswZQp50AOco89znQxd06BHBu7kvx7QGlIpfytz1kZkgQXWateL2q6HqifH/UCovDng4iHrKwE u/pZi3dKcnvZmSey6J13xBn0y7NYUAx9IkIH6Ui+NQIpuwJiqe+NJZ1bc6O4l9e34DJr/NcSwVk Lu9SCKf+jU1cjO+JDIriJgNA0mng1FEBYhlqQiSAn9HilnIhst8C1VaJ3vNfrUIM1jJiJkCRtvL iIj/vpo2fNI8dOfBTPqG9rGzDwORMXSb3gOXhdoA0qQNb7DxNsRZ8kt+3DO/M1Y8MQ== X-Google-Smtp-Source: AGHT+IHXblYVe6ZEv1ROTx59Wdz7A0x2phtSxM6lRbQYq9FYJZgBlhnJDmPUeWe8B4MCY6ArUJTPxQ== X-Received: by 2002:a05:600c:5486:b0:433:c76d:d57e with SMTP id 5b1f17b1804b1-438dc3a40d3mr86795265e9.5.1738261554878; Thu, 30 Jan 2025 10:25:54 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438dcc2f17dsm66550335e9.23.2025.01.30.10.25.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 30 Jan 2025 10:25:54 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Rob Herring , qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Igor Mitsyanko , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 3/8] hw/arm/realview: Explicit number of GIC external IRQs Date: Thu, 30 Jan 2025 19:24:36 +0100 Message-ID: <20250130182441.40480-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250130182441.40480-1-philmd@linaro.org> References: <20250130182441.40480-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When not specified, Cortex-A9MP configures its GIC with 64 external IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts configurable"). Add the GIC_EXT_IRQS definition (with a comment) to make that explicit. Except explicitly setting a property value to its same implicit value, there is no logical change intended. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/realview.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 9900a98f3b8..4a62c83506b 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -35,6 +35,14 @@ #define SMP_BOOT_ADDR 0xe0000000 #define SMP_BOOTREG_ADDR 0x10000030 +/* + * The Cortex-A9MP may have anything from 0 to 224 external interrupt + * IRQ lines (with another 32 internal). We default to 64+32, which + * is the number provided by the Cortex-A9MP test chip in the + * Realview PBX-A9 and Versatile Express A9 development boards. + */ +#define GIC_EXT_IRQS 64 + /* Board init. */ static struct arm_boot_info realview_binfo = { @@ -185,7 +193,12 @@ static void realview_init(MachineState *machine, sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); if (is_mpcore) { - dev = qdev_new(is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore"); + if (is_pb) { + dev = qdev_new(TYPE_A9MPCORE_PRIV); + qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); + } else { + dev = qdev_new("realview_mpcore"); + } qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); @@ -201,7 +214,7 @@ static void realview_init(MachineState *machine, /* For now just create the nIRQ GIC, and ignore the others. */ dev = sysbus_create_simple(TYPE_REALVIEW_GIC, gic_addr, cpu_irq[0]); } - for (n = 0; n < 64; n++) { + for (n = 0; n < GIC_EXT_IRQS; n++) { pic[n] = qdev_get_gpio_in(dev, n); } From patchwork Thu Jan 30 18:24:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13954834 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A1E9C0218A for ; Thu, 30 Jan 2025 18:28:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdZFX-0002eB-9D; Thu, 30 Jan 2025 13:26:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdZEu-0001UF-0Y for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:26:09 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tdZEr-0001Cg-Vo for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:26:07 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-43624b2d453so13210015e9.2 for ; Thu, 30 Jan 2025 10:26:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738261563; x=1738866363; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ffy+7tyS7lEIAtYpG0ijLba+piKy+IqvYcNHx83E6nQ=; b=FgWrhkx7zCaMt3ym1sk1qH8atNJ/fE/1O2jr359mCjU70+Vp9vI27BBbBqZ+7FzJIS DV247SNN0Wa5hLNFqbEfFgwu/nCRLhMj06ohdaTvjhuorzuGeHvtc9JTUX2HlmxHlOVT bkYZrTEtjh4vdUMotGgZNF84FV4/f5MG9BZ69laxCrFQ6cIrFY7cc/Zws53Uf4oXaP/H s/jBU7cRnBMVx4NGgb6gNoc8H//0oqLiYq9E5r8ByO43Z2BFAhE3jZD5Dfnz0w04A8J6 DbxbytXqL18tsHbkpp/GXjxeDmDH3aDbGjjY9oIWSFrXnnhT5Yyk1zyS6t2CfyrJlzht IEWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738261563; x=1738866363; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ffy+7tyS7lEIAtYpG0ijLba+piKy+IqvYcNHx83E6nQ=; b=TGpUYjuhCGBN25H+DkV1aK9fN2iPaAfBp7sbyqiSlkPtbAphUV2WRo7aF9tRtQTXpE Nj8+ITU6x5ccNvJwppGqALkGkN77lIEQeFNMOPuHN9XZWggwqMklDnpfEN7AAAEjSukw b9uHqZDIVMMTibK3LOj2ylEUQihqnb3gLySAkJOkPnOpxR1rzhOzwp36HStiEwbLqikS n2oGeF9mDSTr8y5l0+N9KAv5aTrMv7zy3l6aV+7nmrGU1Jg27yBV8LVMj2qtUUq1NlP4 bigV1tdjDAg8RrFH6MutlZjPCMVHKXzHRDoRLPyQOZ+tHJeX7Bwg0NugIf7RYanlAqf0 KvMg== X-Gm-Message-State: AOJu0YwdU7WEppp7Tq2l/ogO1cPzUD8RGUrQywu3sLH4WRaTt6rxFx1v 1u/ioVBxJFSSsWoVTt/bpJ4tlb6lG3hjnx3BXhcIrXmiYcVZUS3yWDpQIDIb9mOFWzq0IEtOEAI 2iac= X-Gm-Gg: ASbGnctTtwmKhb/Drdm/cH0qzlwaAD4CPJScHNUaSNslnPuzKYtwB8VVZealOWE9aaY ukJ1g4+lM0RKIQKZv156+KJnjAqYFnDcPyFAxR11+8lg3Sycu1qg8HDHYvqgIMDlN77npGUsDVL OHktS7QHtNZOjicaS6BcA6EjASsx2XLYcdyzF4s07+1DEf/8J8Ns75AZk1MbCxoGE/kqJgTE9hy iZGjrhiaN5e2vRe5juPhKPYRBOSuTrFBoPxIcX5yswm6VuOS1/WXCeVGfryA3quvygVqRHlT46g VP+217GWprNBVnqf8oWwlx1YbCnE8FbqmZHIOg7KzgZY2AdSfCzPHe2Bwzg+DW5w+A== X-Google-Smtp-Source: AGHT+IH7f5XGgaRZ9mieNBeNd9xko/crn78bm2p2v4xerpPBfC+EuocJwyZ5UUbkTUysmpbzMxe9MQ== X-Received: by 2002:a05:600c:444c:b0:434:a734:d279 with SMTP id 5b1f17b1804b1-438dc3caef4mr93958155e9.16.1738261562727; Thu, 30 Jan 2025 10:26:02 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438e23e6bf8sm31108925e9.23.2025.01.30.10.26.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 30 Jan 2025 10:26:02 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Rob Herring , qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Igor Mitsyanko , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 4/8] hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL Date: Thu, 30 Jan 2025 19:24:37 +0100 Message-ID: <20250130182441.40480-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250130182441.40480-1-philmd@linaro.org> References: <20250130182441.40480-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We already have a definition to distinct GIC internal IRQs versus external ones, use it. No logical changes. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/xilinx_zynq.c | 34 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 8477b828745..18051458945 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -54,8 +54,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) #define FLASH_SIZE (64 * 1024 * 1024) #define FLASH_SECTOR_SIZE (128 * 1024) -#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */ - #define MPCORE_PERIPHBASE 0xF8F00000 #define ZYNQ_BOARD_MIDR 0x413FC090 @@ -281,12 +279,12 @@ static void zynq_init(MachineState *machine) pic[n] = qdev_get_gpio_in(dev, n); } - n = zynq_init_spi_flashes(0xE0006000, pic[58 - IRQ_OFFSET], false, 0); - n = zynq_init_spi_flashes(0xE0007000, pic[81 - IRQ_OFFSET], false, n); - n = zynq_init_spi_flashes(0xE000D000, pic[51 - IRQ_OFFSET], true, n); + n = zynq_init_spi_flashes(0xE0006000, pic[58 - GIC_INTERNAL], false, 0); + n = zynq_init_spi_flashes(0xE0007000, pic[81 - GIC_INTERNAL], false, n); + n = zynq_init_spi_flashes(0xE000D000, pic[51 - GIC_INTERNAL], true, n); - sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]); - sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]); + sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - GIC_INTERNAL]); + sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - GIC_INTERNAL]); dev = qdev_new(TYPE_CADENCE_UART); busdev = SYS_BUS_DEVICE(dev); @@ -295,7 +293,7 @@ static void zynq_init(MachineState *machine) qdev_get_clock_out(slcr, "uart0_ref_clk")); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, 0xE0000000); - sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]); + sysbus_connect_irq(busdev, 0, pic[59 - GIC_INTERNAL]); dev = qdev_new(TYPE_CADENCE_UART); busdev = SYS_BUS_DEVICE(dev); qdev_prop_set_chr(dev, "chardev", serial_hd(1)); @@ -303,15 +301,15 @@ static void zynq_init(MachineState *machine) qdev_get_clock_out(slcr, "uart1_ref_clk")); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, 0xE0001000); - sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]); + sysbus_connect_irq(busdev, 0, pic[82 - GIC_INTERNAL]); sysbus_create_varargs("cadence_ttc", 0xF8001000, - pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL); + pic[42-GIC_INTERNAL], pic[43-GIC_INTERNAL], pic[44-GIC_INTERNAL], NULL); sysbus_create_varargs("cadence_ttc", 0xF8002000, - pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL); + pic[69-GIC_INTERNAL], pic[70-GIC_INTERNAL], pic[71-GIC_INTERNAL], NULL); - gem_init(0xE000B000, pic[54 - IRQ_OFFSET]); - gem_init(0xE000C000, pic[77 - IRQ_OFFSET]); + gem_init(0xE000B000, pic[54 - GIC_INTERNAL]); + gem_init(0xE000C000, pic[77 - GIC_INTERNAL]); for (n = 0; n < 2; n++) { int hci_irq = n ? 79 : 56; @@ -330,7 +328,7 @@ static void zynq_init(MachineState *machine) qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - GIC_INTERNAL]); di = drive_get(IF_SD, 0, n); blk = di ? blk_by_legacy_dinfo(di) : NULL; @@ -343,7 +341,7 @@ static void zynq_init(MachineState *machine) dev = qdev_new(TYPE_ZYNQ_XADC); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-GIC_INTERNAL]); dev = qdev_new("pl330"); object_property_set_link(OBJECT(dev), "memory", @@ -363,15 +361,15 @@ static void zynq_init(MachineState *machine) busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, 0xF8003000); - sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */ + sysbus_connect_irq(busdev, 0, pic[45-GIC_INTERNAL]); /* abort irq line */ for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */ - sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]); + sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - GIC_INTERNAL]); } dev = qdev_new("xlnx.ps7-dev-cfg"); busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); - sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]); + sysbus_connect_irq(busdev, 0, pic[40 - GIC_INTERNAL]); sysbus_mmio_map(busdev, 0, 0xF8007000); /* From patchwork Thu Jan 30 18:24:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13954829 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AE54CC0218A for ; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438dcc2ede0sm67053955e9.21.2025.01.30.10.26.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 30 Jan 2025 10:26:18 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Rob Herring , qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Igor Mitsyanko , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 5/8] hw/arm/xilinx_zynq: Explicit number of GIC external IRQs Date: Thu, 30 Jan 2025 19:24:38 +0100 Message-ID: <20250130182441.40480-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250130182441.40480-1-philmd@linaro.org> References: <20250130182441.40480-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When not specified, Cortex-A9MP configures its GIC with 64 external IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts configurable"). Add the GIC_EXT_IRQS definition (with a comment) to make that explicit. Except explicitly setting a property value to its same implicit value, there is no logical change intended. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/xilinx_zynq.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 18051458945..dbb003e906a 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -57,6 +57,14 @@ OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) #define MPCORE_PERIPHBASE 0xF8F00000 #define ZYNQ_BOARD_MIDR 0x413FC090 +/* + * The Cortex-A9MP may have anything from 0 to 224 external interrupt + * IRQ lines (with another 32 internal). We default to 64+32, which + * is the number provided by the Cortex-A9MP test chip in the + * Realview PBX-A9 and Versatile Express A9 development boards. + */ +#define GIC_EXT_IRQS 64 + static const int dma_irqs[8] = { 46, 47, 48, 49, 72, 73, 74, 75 }; @@ -205,7 +213,7 @@ static void zynq_init(MachineState *machine) MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); DeviceState *dev, *slcr; SysBusDevice *busdev; - qemu_irq pic[64]; + qemu_irq pic[GIC_EXT_IRQS]; int n; unsigned int smp_cpus = machine->smp.cpus; @@ -261,6 +269,7 @@ static void zynq_init(MachineState *machine) dev = qdev_new(TYPE_A9MPCORE_PRIV); qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); + qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); @@ -275,7 +284,7 @@ static void zynq_init(MachineState *machine) qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); } - for (n = 0; n < 64; n++) { + for (n = 0; n < GIC_EXT_IRQS; n++) { pic[n] = qdev_get_gpio_in(dev, n); } From patchwork Thu Jan 30 18:24:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13954831 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 17B9DC0218A for ; Thu, 30 Jan 2025 18:27:53 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdZFa-0002yi-Lv; Thu, 30 Jan 2025 13:26:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdZFW-0002iR-VJ for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:26:47 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tdZFU-0001LD-Tc for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:26:46 -0500 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-38be3bfb045so1625630f8f.0 for ; Thu, 30 Jan 2025 10:26:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738261603; x=1738866403; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=riA4zmJH/fUcpHKgfppzYaaXrF+oAl0RGRsil+s6hSg=; b=R0WXohcBKGEHuRnfVw1FuPbzgBfcMlkkKvP/qOe54Lj99Xl7JoygCzU9kuKMMC3LPL p01E2/S7alwfEfkQyfq2huxSRFUoe8sP5UZRlaO4TnzF/8zptEu7vgLIhXVyLtEOYqlf J3zgcuFs6tlXr9oSpCvDiPFMV0BNNepVWg71hux4vlXDR08SR4vw0X/TwrziJxyNy2Pn xSc32Ig94j7aLUgnKY/y9VJDp4PCwa5A6/FfQwRVyjIODKKry/mKMwRWL+/RJLSpvysn MCG1cgvOTg+SQOU4Evg0sI8hQoj6/NBVAZ5FLf3+8ks9jdmswvK1kscP9Em5U1HZIDTV 95cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738261603; x=1738866403; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=riA4zmJH/fUcpHKgfppzYaaXrF+oAl0RGRsil+s6hSg=; b=CyrY2x7abO8bELtJfNbmQSSkKnUObiNWF4aYb1KBvVk0Be0J6Ju5pbalShmJC5ZGbk OHp2A9EWy/5CcQfkxzXmAUsyGojANk/Qw54dEBpv4990jNqs8lb3LuqCPiDI+z50xlqn zo0nc08XfVzTarBp2MdxhtBwHprBCw+j5xxa47j+2JJClrJt4wqEydtRvRY9qHpaIn5p xOALDq4xsQHOmPEEQBI65vWhBCSAsKBs/5NLK0svZWcldSa/8fuqELzLVpE35N4uhPtp +UDX+WkueXIBgmKXfbIVPVR+fmBo1JWyGEBIeFydWC+cg61neYklnDO/EhmleSjzbRlc k2dQ== X-Gm-Message-State: AOJu0YxHD2zu9a0WoAg1mW8Cxd78EEJzSltNLJrCC98bkyca/iscmQI5 +xvU+0nn2CjFIZ9/aVJFgAfQteptOiUykQqnpiDUvpQiqJmZL8qhlkQifOFhfQ6nEsgTTjTL5h7 joF4= X-Gm-Gg: ASbGncupv7LoA/X0BQW4cmLQ5HTh4IMITqlwyZFRhhnq21FW7OvTEAXnOoxh68WWbIp ijJ4fsBkYsaapqK1bkASJZ/jEgTrWVsTtveX7QvO9BwYJ7QNdigTQjy5o7Ze8ejV1lyLHEvy6b/ 6DKnpQm4AbkyKDPpuVgfSZ7mZbzBZ95pqQaQj44R3RA07GzzBZ0bYtpRvIHqaLUjzq6ssBc1xJR 1UiYXoZC5YvBnEfX5I/Te2b+/EkUGnCcpvysbcA2hEecPnqGRCBNrvAmbE6Rwq+FNbSfHNuTdru /vtInBTOVsGwp8quWAOPJbmDA8oKCXfLoQ40Rd9WsKAH1cag8WfQMXyrk9TZKPtdsA== X-Google-Smtp-Source: AGHT+IH34UEDzx62k22/qBAWxPwbcHRlx6C+AiBc0kQFEvARbxxUmWQ2neRDb/DsDoxFvg2HA2Eowg== X-Received: by 2002:a05:6000:1a8f:b0:386:3afc:14a7 with SMTP id ffacd0b85a97d-38c60f1654emr420718f8f.7.1738261602664; Thu, 30 Jan 2025 10:26:42 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438dcc26d05sm66624965e9.12.2025.01.30.10.26.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 30 Jan 2025 10:26:41 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Rob Herring , qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Igor Mitsyanko , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 6/8] hw/arm/vexpress: Explicit number of GIC external IRQs Date: Thu, 30 Jan 2025 19:24:39 +0100 Message-ID: <20250130182441.40480-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250130182441.40480-1-philmd@linaro.org> References: <20250130182441.40480-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When not specified, Cortex-A9MP configures its GIC with 64 external IRQs, (see commit a32134aad89 "arm:make the number of GIC interrupts configurable"), and Cortex-15MP to 128 (see commit 528622421eb "hw/cpu/a15mpcore: Correct default value for num-irq"). The Versatile Express board however expects a fixed set of 64 interrupts (see the fixed IRQ length when this board was added in commit 2055283bcc8 ("hw/vexpress: Add model of ARM Versatile Express board"). Add the GIC_EXT_IRQS definition (with a comment) to make that explicit. Except explicitly setting a property value to its same implicit value, there is no logical change intended. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/vexpress.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 42c67034061..8e801aa79cb 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -51,6 +51,14 @@ #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) +/* + * The Cortex-A9MP/A15MP may have anything from 0 to 224 external interrupt + * IRQ lines (with another 32 internal). We default to 64+32, which + * is the number provided by the Cortex-A9MP test chip in the + * Realview PBX-A9 and Versatile Express A9 development boards. + */ +#define GIC_EXT_IRQS 64 + /* Number of virtio transports to create (0..8; limited by * number of available IRQ lines). */ @@ -241,6 +249,7 @@ static void init_cpus(MachineState *ms, const char *cpu_type, */ dev = qdev_new(privdev); qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); + qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, periphbase); @@ -251,7 +260,7 @@ static void init_cpus(MachineState *ms, const char *cpu_type, * external interrupts starting from 32 (because there * are internal interrupts 0..31). */ - for (n = 0; n < 64; n++) { + for (n = 0; n < GIC_EXT_IRQS; n++) { pic[n] = qdev_get_gpio_in(dev, n); } @@ -543,7 +552,7 @@ static void vexpress_common_init(MachineState *machine) VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine); VEDBoardInfo *daughterboard = vmc->daughterboard; DeviceState *dev, *sysctl, *pl041; - qemu_irq pic[64]; + qemu_irq pic[GIC_EXT_IRQS]; uint32_t sys_id; DriveInfo *dinfo; PFlashCFI01 *pflash0; From patchwork Thu Jan 30 18:24:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13954830 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 82A1AC02193 for ; Thu, 30 Jan 2025 18:27:26 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdZFq-0004k5-VP; Thu, 30 Jan 2025 13:27:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdZFk-0004JM-G9 for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:27:00 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tdZFi-0001Pl-Qu for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:27:00 -0500 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-3863703258fso1477683f8f.1 for ; Thu, 30 Jan 2025 10:26:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738261617; x=1738866417; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DSiba+A4z/eFTmtOIndcY8wTtwzH+kBQH69a+P0DCPY=; b=Is6RaXYmMp71qie+yOf7R8BfthnVaaHJRNpYa1p0NjSuYDXlAHNDpNSjZVPfL8pN9W W8PphtdBgZ22aowP+qbgU16Klxvb4Q0hEyheN9wLgO5eq9PVxF1EGvV4SoOziK0kUjLJ LomGEjMmKE/epAGqUtC+0IukDaRb3Fb14Syd/3ghbGOQK0FEH85try86Q+ge5ODmCTzW ZRq1nrL1o5LNi7oHHzp2NyuFmDz0x4iZM529CR6lre12G+/mIOMi72MCOy/9en+9fmTX ONlsuHixJtzI1UkW23egAlw8seiIscKMO58rpCV/DL/nBNzW5r15IjSIhGM/L96HxkfC UG9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738261617; x=1738866417; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DSiba+A4z/eFTmtOIndcY8wTtwzH+kBQH69a+P0DCPY=; b=APXC/LH6jU2W33ZDkKkpIl9jLDW58NC4cSVOkzTnmlre1CuYcLuvucltr/ZSdGOZqK 1tfnVWyXJoWd5kRL1M+3EwWAd7L3jGZ7zU4lk+TG/D8BjULCZR9hxe7NjFUj+g+boscc i9ijFdXxZQbww3zIPgC2Ff6KFo1ajCDkT73oNrq5/HcIoxw72zdXUTSoCsvJsBdDeyWv hHYdwrZYuuH4jNBghTjfSmkmUuDQJXZlZheDRJSZs4HZdoGX0ZDbzG6PfSiqUHBsZUpq fWmvy4JDL4Kz3+p+31hruFhJMXNhtV0hDVfRUe1sQogiW/KbCKB42MBAdWqs4QJR58/O Yn+w== X-Gm-Message-State: AOJu0YyW7J0JeRIpZiCHBovfSX+yIcRBoIlYpvS26bzYsUwIQUIePCGw ohS6PxSRYl01aqx8qwEvdo4evhvDdY361oyN409I4nL/+H3jMWei8avOSaap+JGp2AFoqDxwnT3 FM5I= X-Gm-Gg: ASbGncu9ZBOCAJ1It28DI9FXNvMX864WpN+QFMek4OsH7ZL73VX5Zk25cjbviwK705P KzxFTYBMM099AmxgR0E70C8agx+c1KMqYaElZSoKtqX2wbbdq87xPW4wHkr68yXcbvrRtG15Okq DQCMsjLRPb1KbjdqUnYhuf5X/DJPpcFX0gKFrDcIQt1CDMY/qo9H6nI7GHRF+P3xYeI8AUXSeoi 6pz653vAPJraOrs6f/ERmlt9+51BZA/puFokAC+mV/orFPfNTeJl/4xmgis6RrZbQKY7pwu1bMb vi+KBP24sR8ojiJPCHmJt7IM2d3G9evAJXjLChMRxp9kFEjaQcRpnXJkcKkePtVEIg== X-Google-Smtp-Source: AGHT+IHPXeUxXPiJEmZ1ZWUQ07iEHs7Er12VLYScLpZSb8JUMfPWww+rGP0/ZwtI7OqIinJtfU9sfQ== X-Received: by 2002:a5d:5984:0:b0:385:f64e:f177 with SMTP id ffacd0b85a97d-38c5a971e63mr3222499f8f.11.1738261617141; Thu, 30 Jan 2025 10:26:57 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c122539sm2730881f8f.46.2025.01.30.10.26.54 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 30 Jan 2025 10:26:56 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Rob Herring , qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Igor Mitsyanko , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 7/8] hw/arm/highbank: Explicit number of GIC external IRQs Date: Thu, 30 Jan 2025 19:24:40 +0100 Message-ID: <20250130182441.40480-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250130182441.40480-1-philmd@linaro.org> References: <20250130182441.40480-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When not specified, Cortex-A9MP configures its GIC with 64 external IRQs, (see commit a32134aad89 "arm:make the number of GIC interrupts configurable"), and Cortex-15MP to 128 (see commit 528622421eb "hw/cpu/a15mpcore: Correct default value for num-irq"). The Caldexa Highbank board however expects a fixed set of 128 interrupts (see the fixed IRQ length when this board was added in commit 2488514cef2 ("arm: SoC model for Calxeda Highbank"). Add the GIC_EXT_IRQS definition (with a comment) to make that explicit. Except explicitly setting a property value to its same implicit value, there is no logical change intended. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/highbank.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 495704d9726..d59f20b88e0 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -45,7 +45,14 @@ #define MVBAR_ADDR 0x200 #define BOARD_SETUP_ADDR (MVBAR_ADDR + 8 * sizeof(uint32_t)) -#define NIRQ_GIC 160 +/* + * The Cortex-A9MP/A15MP may have anything from 0 to 224 external interrupt + * IRQ lines (with another 32 internal). We default to 128+32, which + * is the number provided by the Cortex-A15MP test chip in the + * Versatile Express A15 development board. + * Other boards may differ and should set this property appropriately. + */ +#define GIC_EXT_IRQS 128 /* Board init. */ @@ -180,7 +187,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) { DeviceState *dev = NULL; SysBusDevice *busdev; - qemu_irq pic[128]; + qemu_irq pic[GIC_EXT_IRQS]; int n; unsigned int smp_cpus = machine->smp.cpus; qemu_irq cpu_irq[4]; @@ -260,7 +267,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) break; } qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); - qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC); + qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); @@ -271,7 +278,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) sysbus_connect_irq(busdev, n + 3 * smp_cpus, cpu_vfiq[n]); } - for (n = 0; n < 128; n++) { + for (n = 0; n < GIC_EXT_IRQS; n++) { pic[n] = qdev_get_gpio_in(dev, n); } From patchwork Thu Jan 30 18:24:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13954833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D5E59C02190 for ; Thu, 30 Jan 2025 18:28:07 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdZG3-0005Xa-Qi; Thu, 30 Jan 2025 13:27:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdZG0-00058z-7s for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:27:16 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tdZFy-0001U3-Hw for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:27:15 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-43625c4a50dso8499435e9.0 for ; Thu, 30 Jan 2025 10:27:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738261632; x=1738866432; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XQNs/MO88QA6DkNCjxkxynlmOBFAmoCxktVishKIMrs=; b=uMkq8ODrksmwCYvlOOvoohxo8L9ri9ru6iQJhmCWW1DG8WCtTSsy82rsCHpRZOWT3g iuBjzsxEiS3glSKiMRA5gxaF9vdn4vnU+ny7oL7eKagobtxZkcX9SQ2OcDCM0NDmbUAq P6SehN3p2SJqvZwJ/CMJAIMlU5abeuFrpFN4KsEH+3w+jojPugulTuNYM8mfuVJ4zBLm c4MhYUJVx2V6ZgW3L92KW8JjgyJhkN5h0mt62bNlvoaiTVwxXpX5kLWnfiu0lbM2FwN/ TCvEBlftMFVqdEGaQzYFJwYttfwiSilIyngUPSQSgy1+wqHZkhyzuxQyFFYj5WOW9g/Z VuZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738261632; x=1738866432; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XQNs/MO88QA6DkNCjxkxynlmOBFAmoCxktVishKIMrs=; b=NNCwHyT7bbGoNTXqnYfJ2nQjnTXeBrB9o+V7BF0zgx15R4lYXAhMMlnMrch4QCyYu+ MUZiC5PbliFXJiBUwSw1CyXBls2xc0mPlQrNHx9VVRcUtDrvQks2p9JVqdh0a2AcZJyu 3e+E8pH4VFi7gNuUxF0VnqXBYvlc+6gM6xh9AC+tM9xV3ELsLsUXVpwrEgq1H8L7+hiC urwG5mrgEcj2raWJy/knLcIFp3kYKgL5jtGuubyCAptd3Z1GWL9kuIjeMNWOscKbjq7v g7tbN4ZotDe7aU1bT7tStQ1ZCrNklnPLVWbuFDLYgpkjWG+XCOfL9m8bnktByMHiWdJB FM/w== X-Gm-Message-State: AOJu0YzEFHc8NM7Wf4fCzV/iIY/5o5I/ShPKTcomhuQpILHQ0NfpDB6i 1WQ9XpmmAmZnGk1j8qgcb//mDkA5zjao10lkArc7IvxG9z3JqkkU7JXyUDDmyCIJeb/H7+GmaUL 5r2w= X-Gm-Gg: ASbGncs4mSf+iEHMmB01kHGmjpRtkxKjUQTD/nCi1kk+x6WHX2Pe17epxIKvm7FxyrG rMSipY4ZpZeIRhd6+vVuguccGTPdqqcvVaIpNa1TV+r+HSZCzJFEZwtm5k0JTu4kBlzjqfBXtyb Nr62rowk78g9B1xjSYCb62rr90ClsXkPaPrkMaFbp/eHEVpYsLU3SL0QPqNWXqA/ImrdJ0tRXoM yRkHoxRz84fQiI6Y7c8DSJ2/lHqOOHx8CSPH4JKKT+hLgqVitF7Ed9RDnyLwR+AwbSlIRiKK8LG 0/Ed8dE50NJ31mHwqu0YRSx+GEssNz5wcYxsoKEAh9NxQyT9rOWLAjWHGUrH5kppzQ== X-Google-Smtp-Source: AGHT+IEIBd3+ET4JHUQxgf6RyISaRZpd3bfhmGrq3dWHjkO2/YsqoyrmVAw3P/sJrGH5NUkReu3zKw== X-Received: by 2002:a05:600c:4fc1:b0:434:9d62:aa23 with SMTP id 5b1f17b1804b1-438dc40d296mr67137435e9.20.1738261632676; Thu, 30 Jan 2025 10:27:12 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438e23de2d6sm30922185e9.11.2025.01.30.10.27.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 30 Jan 2025 10:27:12 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Rob Herring , qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Igor Mitsyanko , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 8/8] hw/cpu/arm_mpcore: Remove default values for GIC external IRQs Date: Thu, 30 Jan 2025 19:24:41 +0100 Message-ID: <20250130182441.40480-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250130182441.40480-1-philmd@linaro.org> References: <20250130182441.40480-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Implicit default values are often hard to figure out, better be explicit. Now that all boards explicitly set the number of GIC external IRQs, remove the default values (displaying an error message if it is not set). Signed-off-by: Philippe Mathieu-Daudé --- hw/cpu/a15mpcore.c | 13 ++++++------- hw/cpu/a9mpcore.c | 14 +++++++------- 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index 3b0897e54ee..372b615178f 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -58,6 +58,11 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp) bool has_el2 = false; Object *cpuobj; + if (!s->num_irq) { + error_setg(errp, "Property 'num-irq' not set"); + return; + } + gicdev = DEVICE(&s->gic); qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); @@ -146,13 +151,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp) static const Property a15mp_priv_properties[] = { DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1), - /* The Cortex-A15MP may have anything from 0 to 224 external interrupt - * IRQ lines (with another 32 internal). We default to 128+32, which - * is the number provided by the Cortex-A15MP test chip in the - * Versatile Express A15 development board. - * Other boards may differ and should set this property appropriately. - */ - DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160), + DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 0), }; static void a15mp_priv_class_init(ObjectClass *klass, void *data) diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index 9671585b5f9..c522f8d4b05 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -56,6 +56,12 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) CPUState *cpu0; Object *cpuobj; + + if (!s->num_irq) { + error_setg(errp, "Property 'num-irq' not set"); + return; + } + cpu0 = qemu_get_cpu(0); cpuobj = OBJECT(cpu0); if (strcmp(object_get_typename(cpuobj), ARM_CPU_TYPE_NAME("cortex-a9"))) { @@ -160,13 +166,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) static const Property a9mp_priv_properties[] = { DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), - /* The Cortex-A9MP may have anything from 0 to 224 external interrupt - * IRQ lines (with another 32 internal). We default to 64+32, which - * is the number provided by the Cortex-A9MP test chip in the - * Realview PBX-A9 and Versatile Express A9 development boards. - * Other boards may differ and should set this property appropriately. - */ - DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), + DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 0), }; static void a9mp_priv_class_init(ObjectClass *klass, void *data)