From patchwork Thu Jan 30 18:45:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13954847 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 83A02C0218A for ; Thu, 30 Jan 2025 18:45:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1966F10E089; Thu, 30 Jan 2025 18:45:26 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="FVI9+rV2"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 54E2610E089; Thu, 30 Jan 2025 18:45:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738262724; x=1769798724; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=c8M5s5C/Cn5mx+qroKlABoSaor0aIj8KEsc3xV6qNM0=; b=FVI9+rV2jHh9U16qK0W6xzIfwpNsuiX40JHlIcDqvM7CZ0UpYmAYvJAf NtZrfR1pzE4iI6y8ZeOn/GS7xRTfqHKstZzPPHf9LrdU79NeijO0wge5v t0/mLeOS9vhfjP6zODXi2uAb9z2ugT/LnJQ4bVHL2/zsJ0C/eZTk1zwCT n2iANOfZSigPL2loaARtE6EIUjNaErP2ayWDepbfQd7MlkX2NwUtYXawH fdVGYikk6bd7RtQC+un25GBZA619nrrx0h5eaYYMvbTTTVIsm+tlJ97t4 vL3EyKmlhvXdO3IsTyhQTdeqzSHLNPmE6U1Ru91uoLkisJNyRIgGSzxeO g==; X-CSE-ConnectionGUID: H2OOmZzwRtyy8q2dnZcYlg== X-CSE-MsgGUID: QWTjaHtgSzeURBckUwgzGA== X-IronPort-AV: E=McAfee;i="6700,10204,11331"; a="38068230" X-IronPort-AV: E=Sophos;i="6.13,246,1732608000"; d="scan'208";a="38068230" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2025 10:45:24 -0800 X-CSE-ConnectionGUID: u5pM/kooTBKDE3gk4K3+WA== X-CSE-MsgGUID: UircItbBS6ivLoh/n47Pyw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,246,1732608000"; d="scan'208";a="109561266" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 30 Jan 2025 10:45:22 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 30 Jan 2025 20:45:21 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH 1/3] drm/i915/dsb: Introduce intel_dsb_poll() Date: Thu, 30 Jan 2025 20:45:16 +0200 Message-ID: <20250130184518.22353-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250130184518.22353-1-ville.syrjala@linux.intel.com> References: <20250130184518.22353-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Add a functiuon for emitting a DSB poll instruction. We'll allow the caller to specify the poll parameters. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb.c | 19 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dsb.h | 3 +++ 2 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 2f2812c23972..b68ee125afae 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -452,6 +452,25 @@ void intel_dsb_wait_scanline_out(struct intel_atomic_state *state, start, end); } +void intel_dsb_poll(struct intel_dsb *dsb, + i915_reg_t reg, u32 mask, u32 val, + int wait, int count) +{ + struct intel_crtc *crtc = dsb->crtc; + enum pipe pipe = crtc->pipe; + + intel_dsb_reg_write(dsb, DSB_POLLMASK(pipe, dsb->id), mask); + intel_dsb_reg_write(dsb, DSB_POLLFUNC(pipe, dsb->id), + DSB_POLL_ENABLE | + DSB_POLL_WAIT(wait) | DSB_POLL_COUNT(count)); + + intel_dsb_noop(dsb, 5); + + intel_dsb_emit(dsb, val, + (DSB_OPCODE_POLL << DSB_OPCODE_SHIFT) | + i915_mmio_reg_offset(reg)); +} + static void intel_dsb_align_tail(struct intel_dsb *dsb) { u32 aligned_tail, tail; diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h index da6df07a3c83..4511d1a1a187 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.h +++ b/drivers/gpu/drm/i915/display/intel_dsb.h @@ -54,6 +54,9 @@ void intel_dsb_wait_scanline_out(struct intel_atomic_state *state, int lower, int upper); void intel_dsb_vblank_evade(struct intel_atomic_state *state, struct intel_dsb *dsb); +void intel_dsb_poll(struct intel_dsb *dsb, + i915_reg_t reg, u32 mask, u32 val, + int wait, int count); void intel_dsb_chain(struct intel_atomic_state *state, struct intel_dsb *dsb, struct intel_dsb *chained_dsb, From patchwork Thu Jan 30 18:45:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13954848 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 15EAAC0218A for ; Thu, 30 Jan 2025 18:45:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AEBF410E9C4; Thu, 30 Jan 2025 18:45:28 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="FfGhhETf"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 43FA810E9C2; Thu, 30 Jan 2025 18:45:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738262727; x=1769798727; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+NHH4wgNcSr9gE7esJJy3C5FCrrVmbLLv+10jFZ94Ts=; b=FfGhhETfIwEDzRyB5SZFCaCzzZD38IGeLayHhsFZ1Fjq19jeiXwd7xTV Eza/pLyCFW7qDrfADLlBtTcQRLBh6MAScCfYq4DZ7yY3grZwlzkczg+sJ j+dyb0mkk/T4b38azpT875xNRpXLHuOkiAe7knP13So72WDCTQcHrLG7B gIK5jGtX9dglbJzWav0Oy/tT9GzXYKH7lO0j2nDEgY6udquLIb3lpZ/Ky vgU9fCYIcPt4Kiq7aWxsvimg/9oCFEp7svwKd2UsnuLeL4MdaYnC/4koQ mXALo9aXgzrVDqAU1aQ9CPj+AwWWYySKeIqe6lZ9CxMH2d4Ekc8V3g9/i w==; X-CSE-ConnectionGUID: CkE6y1GCTJyntRWe9t+C6A== X-CSE-MsgGUID: D8HRlEdHQyqkELJAmNOAyQ== X-IronPort-AV: E=McAfee;i="6700,10204,11331"; a="38068238" X-IronPort-AV: E=Sophos;i="6.13,246,1732608000"; d="scan'208";a="38068238" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2025 10:45:27 -0800 X-CSE-ConnectionGUID: CDBbg1beS8y/znn7Bm+lZw== X-CSE-MsgGUID: fNR+xoTDR/a/w2naQr8nrw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,246,1732608000"; d="scan'208";a="109561312" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 30 Jan 2025 10:45:25 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 30 Jan 2025 20:45:24 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH 2/3] drm/i915/vrr: Reorder the DSB "wait for safe window" vs. TRANS_PUSH Date: Thu, 30 Jan 2025 20:45:17 +0200 Message-ID: <20250130184518.22353-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250130184518.22353-1-ville.syrjala@linux.intel.com> References: <20250130184518.22353-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Currently we trigger the push send first, then follow it with a "wait for safe window". That approach no longer works on PTL+ because triggering the push send immediately ends the safe window. On prior hardware the safe window extended past the push being sent (presumably all the way to the pipe's delayed vblank). In order to deal with the new hardware behaviour we must reverse the order of these two operations: first wait for safe window, then trigger the push. The only slight danger with this approach is that if we mess up the vblank evasion around the vmax decision boundary the push might get postponed until after the next frame's vactive. But assuming we don't mess up the vblank evasion this approach is completely safe. As a slight bonus we can perform the push after we've done the LUT writes as well, meaning we no longer have to worry about extending the vblank delay to provide enough time for LUT programming. Instead we will now depend on the vblank evasion at vmax decision boundary to guarantee this. However vblank delay (or framestart delay) is still the only way to provide extra time for the LUT programming in the non-VRR use cases. Let's assume we don't need anything extra for now, but eventually we should come up with some proper estimates on how long the LUT programming can take and configure the vblank delay accordingly for the non-VRR use cases. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_color.c | 2 ++ drivers/gpu/drm/i915/display/intel_display.c | 12 ++---------- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 8400a97f7e43..be2691a80227 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -29,6 +29,7 @@ #include "intel_de.h" #include "intel_display_types.h" #include "intel_dsb.h" +#include "intel_vrr.h" struct intel_color_funcs { int (*color_check)(struct intel_atomic_state *state, @@ -1987,6 +1988,7 @@ void intel_color_prepare_commit(struct intel_atomic_state *state, display->funcs.color->load_luts(crtc_state); + intel_vrr_send_push(crtc_state->dsb_color_vblank, crtc_state); intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color_vblank); intel_dsb_interrupt(crtc_state->dsb_color_vblank); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 60867b5b03ec..69dbb0eb5ca1 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2630,14 +2630,6 @@ static int intel_crtc_vblank_delay(const struct intel_crtc_state *crtc_state) if (intel_crtc_needs_wa_14015401596(crtc_state)) vblank_delay = max(vblank_delay, 1); - /* - * Add a minimal vblank delay to make sure the push - * doesn't race with the "wait for safe window" used - * for frame completion with DSB. - */ - if (intel_vrr_possible(crtc_state)) - vblank_delay = max(vblank_delay, 1); - return vblank_delay; } @@ -7735,10 +7727,10 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, intel_crtc_planes_update_arm(new_crtc_state->dsb_commit, state, crtc); - intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state); - if (!new_crtc_state->dsb_color_vblank) { intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1); + + intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state); intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit); intel_dsb_interrupt(new_crtc_state->dsb_commit); } From patchwork Thu Jan 30 18:45:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13954849 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E81B7C02190 for ; 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X-CSE-ConnectionGUID: hTP9trDRR1KXyrlzKi+OxA== X-CSE-MsgGUID: 9XMuHogxQXKX/9YHQv+xLA== X-IronPort-AV: E=McAfee;i="6700,10204,11331"; a="38068244" X-IronPort-AV: E=Sophos;i="6.13,246,1732608000"; d="scan'208";a="38068244" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2025 10:45:30 -0800 X-CSE-ConnectionGUID: 6YPyiIETRlmc6/OCu+4nMw== X-CSE-MsgGUID: SULywzDHTkWLbN7257vGuw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,246,1732608000"; d="scan'208";a="109561347" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 30 Jan 2025 10:45:28 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 30 Jan 2025 20:45:27 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH 3/3] drm/i915/vrr: Poll for the push send bit to clear on the DSB Date: Thu, 30 Jan 2025 20:45:18 +0200 Message-ID: <20250130184518.22353-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250130184518.22353-1-ville.syrjala@linux.intel.com> References: <20250130184518.22353-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Since we now do the "wait for safe window" before triggering the push send, there is a theoretical possibity that we may have screwed up the vblank evasion and the push has slipped past the vmax decision boundary. In that case the push would only happen after the next frame's vactive, while we've already signalled the flip to have completed via the DSB interrupt immediately after triggering the push. To make sure we catch such screwups let's poll for the push send bit to clear. Assuming vblank delay has been dealt with already it should clear within ~1 scanline. But for safety let's give it ~2 scanlines. If the bit does not clear within that time the DSB will raise the poll error interrupt to inform us that something went wrong. Also I suppose it might generally be a good idea to make sure the send bit has cleared before we complete the commit because we're not supposed to send a new push while the previous one is still pending. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_color.c | 1 + drivers/gpu/drm/i915/display/intel_display.c | 1 + drivers/gpu/drm/i915/display/intel_vrr.c | 31 ++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_vrr.h | 2 ++ 4 files changed, 35 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index be2691a80227..964a4bde3c88 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1990,6 +1990,7 @@ void intel_color_prepare_commit(struct intel_atomic_state *state, intel_vrr_send_push(crtc_state->dsb_color_vblank, crtc_state); intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color_vblank); + intel_vrr_dsb_wait_push_sent(crtc_state->dsb_color_vblank, crtc_state); intel_dsb_interrupt(crtc_state->dsb_color_vblank); intel_dsb_finish(crtc_state->dsb_color_vblank); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 69dbb0eb5ca1..3fc61c1848b3 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7732,6 +7732,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state); intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit); + intel_vrr_dsb_wait_push_sent(new_crtc_state->dsb_commit, new_crtc_state); intel_dsb_interrupt(new_crtc_state->dsb_commit); } } diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index adb51609d0a3..2925a013f708 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -5,6 +5,7 @@ */ #include "i915_reg.h" +#include "intel_crtc.h" #include "intel_de.h" #include "intel_display_types.h" #include "intel_dp.h" @@ -416,6 +417,36 @@ void intel_vrr_send_push(struct intel_dsb *dsb, intel_dsb_nonpost_end(dsb); } +void intel_vrr_dsb_wait_push_sent(struct intel_dsb *dsb, + const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + int wait, count; + + /* not to be used in mmio codepaths */ + if (drm_WARN_ON(display->drm, !dsb)) + return; + + /* + * We always do the send after the "wait for safe window", thus + * the push should happen within ~1 scanline. Poll for ~2 scanlines + * to make sure it does. If the bit does not clear DSB will raise + * the poll error interrupt as an indication that we failed to + * sequence things correctly. + * + * Note that vblank delay does postpone the bit clearing, but + * we can ignore that by assuming that our caller has already + * dealt with it via intel_dsb_wait_vblank_delay() after + * triggering the push. + */ + wait = 2; /* usecs */ + count = DIV_ROUND_UP(intel_scanlines_to_usecs(&crtc_state->hw.adjusted_mode, 2), wait); + + intel_dsb_poll(dsb, TRANS_PUSH(display, cpu_transcoder), + TRANS_PUSH_SEND, 0, wait, count); +} + bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index 899cbf40f880..19a5aa671eae 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -25,6 +25,8 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) void intel_vrr_enable(const struct intel_crtc_state *crtc_state); void intel_vrr_send_push(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state); +void intel_vrr_dsb_wait_push_sent(struct intel_dsb *dsb, + const struct intel_crtc_state *crtc_state); bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state); void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state); void intel_vrr_get_config(struct intel_crtc_state *crtc_state);