From patchwork Thu Jan 30 21:00:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Govindapillai, Vinod" X-Patchwork-Id: 13954964 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F4118C0218D for ; Thu, 30 Jan 2025 21:00:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 98F6810E9D3; Thu, 30 Jan 2025 21:00:45 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="OOQzrb6U"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 147A410E9D3; Thu, 30 Jan 2025 21:00:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738270844; x=1769806844; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XYsyJT8J2OF9pn7ILpJ7PNkcACDwCS/nczJsWSJyF/4=; b=OOQzrb6UhqIzw6ocrcQqbk0JKL0hqRnVEmQiZtqmKML6tbsQA61LrOCx /KhA0z/hYKWxSUlnKIJOs7vb03h3E0GxfqCS3uuWA/0gtxghyXrlR43TB ZHwZORPxJcieFzHLscKtFvaOjnmQEf7v626S+LwFSLEXvMUE/8zSfrQTQ n400DUrDbQEUeuJkdP7TdnUhhIARcdS1mq4c/d8qnLuLUcw08bjtjiKLp afa+zKJeEpEtfEETeXn9PREIOyG+JE4JJSJDlebGg2vaj6pkCFsbYts8m o+ta+3Xl+EEtXSuheZTsw6PnaM4tjc1bP58FNlwFlyrN8UHSkStvUTVtL A==; X-CSE-ConnectionGUID: IjPfcgk5SIWbFa5QDqYk7g== X-CSE-MsgGUID: 9te/fX3rQviNg4DFFvxLFw== X-IronPort-AV: E=McAfee;i="6700,10204,11331"; a="42491525" X-IronPort-AV: E=Sophos;i="6.13,246,1732608000"; d="scan'208";a="42491525" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2025 13:00:43 -0800 X-CSE-ConnectionGUID: 96zW8MgjScy1LsxPJeq48A== X-CSE-MsgGUID: Liq80kkIS9+rJZ2N4sBtBg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,246,1732608000"; d="scan'208";a="110015768" Received: from mwiniars-desk2.ger.corp.intel.com (HELO vgovind2-mobl3.intel.com) ([10.245.246.118]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2025 13:00:41 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, santhosh.reddy.guddati@intel.com, jani.saarinen@intel.com Subject: [PATCH v6 1/7] drm/i915/xe3: add register definitions for fbc dirty rect support Date: Thu, 30 Jan 2025 23:00:20 +0200 Message-ID: <20250130210027.591927-2-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250130210027.591927-1-vinod.govindapillai@intel.com> References: <20250130210027.591927-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Register definitions for FBC dirty rect support Bspec: 71675, 73424 Signed-off-by: Vinod Govindapillai Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_fbc_regs.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h index ae0699c3c2fe..b1d0161a3196 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h @@ -100,6 +100,15 @@ #define FBC_STRIDE_MASK REG_GENMASK(14, 0) #define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x)) +#define XE3_FBC_DIRTY_RECT(fbc_id) _MMIO_PIPE((fbc_id), 0x43230, 0x43270) +#define FBC_DIRTY_RECT_END_LINE_MASK REG_GENMASK(31, 16) +#define FBC_DIRTY_RECT_END_LINE(val) REG_FIELD_PREP(FBC_DIRTY_RECT_END_LINE_MASK, (val)) +#define FBC_DIRTY_RECT_START_LINE_MASK REG_GENMASK(15, 0) +#define FBC_DIRTY_RECT_START_LINE(val) REG_FIELD_PREP(FBC_DIRTY_RECT_START_LINE_MASK, (val)) + +#define XE3_FBC_DIRTY_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x43234, 0x43274) +#define FBC_DIRTY_RECT_EN REG_BIT(31) + #define ILK_FBC_RT_BASE _MMIO(0x2128) #define ILK_FBC_RT_VALID REG_BIT(0) #define SNB_FBC_FRONT_BUFFER REG_BIT(1) From patchwork Thu Jan 30 21:00:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Govindapillai, Vinod" X-Patchwork-Id: 13954965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C0BBEC0218D for ; Thu, 30 Jan 2025 21:00:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 46B1A10E9DB; Thu, 30 Jan 2025 21:00:49 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="cSkW7VeF"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id BFD5910E9D7; Thu, 30 Jan 2025 21:00:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738270847; x=1769806847; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=p9D0KgxcdEtEG9bD9gwKxpec+5GU6H2pYDE8mxM6rvc=; b=cSkW7VeFqXqGUCXDvi1abeggcRthfbBW5cFmzNBlx9Y/343vGGZkV2xr Isp+YCmoXwCxrqbcOvrKsJnJgkvgH+9hTO1ly1CVxr5hv2W6wCJqTKHfQ vxZfXouDQTUt9t+QtyutYkws2ARudr64NvzsJXX8uO0ZO65rFPvIj1LQn JnLvgeVpIpYgPhRt6yQQKhIsP8wBUvPV9yPkUbMj222G98GxGiiy83+Bu mQpdT1tmdlgKVnnTwoTWySgbHaiFG8xGI39rBR9waJOGRYfuziONsLppE UlrPifgPYKO39ChP07raIYdEUqdDA1pZe9mSvNSGILhaX/DjRPBSYlic6 A==; X-CSE-ConnectionGUID: jynXHtZfTMCCDLk1bl7Q8w== X-CSE-MsgGUID: 1KM5Y7WmTxOLuzTou0XURA== X-IronPort-AV: E=McAfee;i="6700,10204,11331"; a="42491533" X-IronPort-AV: E=Sophos;i="6.13,246,1732608000"; d="scan'208";a="42491533" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2025 13:00:47 -0800 X-CSE-ConnectionGUID: OKGGnZneQhKrDaxcGounOg== X-CSE-MsgGUID: fA4k6+JvQnmRzXuLMsL33A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,246,1732608000"; d="scan'208";a="110015825" Received: from mwiniars-desk2.ger.corp.intel.com (HELO vgovind2-mobl3.intel.com) ([10.245.246.118]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2025 13:00:45 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, santhosh.reddy.guddati@intel.com, jani.saarinen@intel.com Subject: [PATCH v6 2/7] drm/i915/xe3: introduce HAS_FBC_DIRTY_RECT() for FBC dirty rect support Date: Thu, 30 Jan 2025 23:00:21 +0200 Message-ID: <20250130210027.591927-3-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250130210027.591927-1-vinod.govindapillai@intel.com> References: <20250130210027.591927-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Introduce a macro to check if the platform supports FBC dirty rect capability. Signed-off-by: Vinod Govindapillai Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_display_device.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index fc33791f02b9..717286981687 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -163,6 +163,7 @@ struct intel_display_platforms { #define HAS_DSC(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dsc) #define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display)) #define HAS_FBC(__display) (DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0) +#define HAS_FBC_DIRTY_RECT(__display) (DISPLAY_VER(__display) >= 30) #define HAS_FPGA_DBG_UNCLAIMED(__display) (DISPLAY_INFO(__display)->has_fpga_dbg) #define HAS_FW_BLC(__display) (DISPLAY_VER(__display) >= 3) #define HAS_GMBUS_IRQ(__display) (DISPLAY_VER(__display) >= 4) From patchwork Thu Jan 30 21:00:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Govindapillai, Vinod" X-Patchwork-Id: 13954966 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8BB9FC0218D for ; Thu, 30 Jan 2025 21:00:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3351410E9D2; Thu, 30 Jan 2025 21:00:53 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="DHs8lBQ7"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5D2CF10E9D2; Thu, 30 Jan 2025 21:00:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738270851; x=1769806851; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=T3RVDVVhqmqzK9z+/Rcfq2H+TPS1qVjh8vsTVSfmpd4=; b=DHs8lBQ7weeWsDphBen3vyCgIJJdiUAw1e9274lHb7eDxybHwn9VQrzM GL2fK/nR1fp2nt1HA96Qc4siXkSuQ2U530OsYzZkvHIUw4nauEoKIPWBD 4OUBee4wYFwTHlQjtls/8C7zsMq7HLYfTLJa0P6T+k69hHekGydSI14Qt pqY/f2ABWLU/CxO8aJW9wgNeRneR+XZKTz1tdNryCfV+RfX3r4qc6/oOC 0gmqYcytkBxMczPikADeBkG5bmr0ESW9I5PWKZinBGUmKFmiXtdUXNpFM RLsZfPqvCPwZah+xMP5ADrMSP1fHw/5GY9g7YKlOwOvi9shqtcR8u1o9j w==; X-CSE-ConnectionGUID: w88cL1ypSyG9jRXjqCxJ0Q== X-CSE-MsgGUID: oJp61w1AQVGmuFHAgnZqhw== X-IronPort-AV: E=McAfee;i="6700,10204,11331"; a="42491547" X-IronPort-AV: E=Sophos;i="6.13,246,1732608000"; d="scan'208";a="42491547" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2025 13:00:51 -0800 X-CSE-ConnectionGUID: OAqrTbhPTrSmlFIJGKAVqw== X-CSE-MsgGUID: +xJ6vPUVTmq80nUp0mWwfg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,246,1732608000"; d="scan'208";a="110015873" Received: from mwiniars-desk2.ger.corp.intel.com (HELO vgovind2-mobl3.intel.com) ([10.245.246.118]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2025 13:00:48 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, santhosh.reddy.guddati@intel.com, jani.saarinen@intel.com Subject: [PATCH v6 3/7] drm/damage-helper: add const qualifier in drm_atomic_helper_damage_merged() Date: Thu, 30 Jan 2025 23:00:22 +0200 Message-ID: <20250130210027.591927-4-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250130210027.591927-1-vinod.govindapillai@intel.com> References: <20250130210027.591927-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a const qualifier for the "state" parameter as well as we could use this helper to get the combined damage in cases of const drm_plane_state as well. Needed mainly for xe driver big joiner cases where we need to track the damage from immutable plane state. Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/drm_damage_helper.c | 2 +- include/drm/drm_damage_helper.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_damage_helper.c b/drivers/gpu/drm/drm_damage_helper.c index afb02aae707b..44a5a36806e3 100644 --- a/drivers/gpu/drm/drm_damage_helper.c +++ b/drivers/gpu/drm/drm_damage_helper.c @@ -308,7 +308,7 @@ EXPORT_SYMBOL(drm_atomic_helper_damage_iter_next); * True if there is valid plane damage otherwise false. */ bool drm_atomic_helper_damage_merged(const struct drm_plane_state *old_state, - struct drm_plane_state *state, + const struct drm_plane_state *state, struct drm_rect *rect) { struct drm_atomic_helper_damage_iter iter; diff --git a/include/drm/drm_damage_helper.h b/include/drm/drm_damage_helper.h index effda42cce31..a58cbcd11276 100644 --- a/include/drm/drm_damage_helper.h +++ b/include/drm/drm_damage_helper.h @@ -78,7 +78,7 @@ bool drm_atomic_helper_damage_iter_next(struct drm_atomic_helper_damage_iter *iter, struct drm_rect *rect); bool drm_atomic_helper_damage_merged(const struct drm_plane_state *old_state, - struct drm_plane_state *state, + const struct drm_plane_state *state, struct drm_rect *rect); #endif From patchwork Thu Jan 30 21:00:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Govindapillai, Vinod" X-Patchwork-Id: 13954967 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F41AC0218D for ; Thu, 30 Jan 2025 21:00:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4CB1F10E0CD; Thu, 30 Jan 2025 21:00:56 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="FSIcQgNO"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id DFC8910E0CD; Thu, 30 Jan 2025 21:00:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738270854; x=1769806854; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MPOOtVdrbXe6uJv3T7ABYN+QqJrHuX3knz6qhvEybqE=; b=FSIcQgNOAq7mm9E0TPztW44cbKcpRYMT/yk5baSseBZnS5/KzHCVFBBp FEnbjpDiWKu9xuZO0ZU7Z0WypMkjCs1kYH4KR2fXdjY2RKwfDHsK0or4z lE1Vr89xEWmlg0CDib5X8J6fk7BCAysz0g24osp0hwnnv2gpVJYNvpFlG sPEgfhX4rkzPua3DEQ9fxagf6m1g78q4EOgWhavCf7I4KBdxnqaIJ4Eiv uGaMqZqMDIHf5QnHWxlr2lKr5qQpIzFadL88y2ZRJT382O88/iEHo+YrI 097e3NISOkJ33mx/+muB/f89MtzkEnYQuY/wVK9tSdhIbDFdIYo7Dnzz2 Q==; X-CSE-ConnectionGUID: Kx9ryzvzRreRSrBctRaqWQ== X-CSE-MsgGUID: HXTvx0DdSyOiA9n6Dz67Bw== X-IronPort-AV: E=McAfee;i="6700,10204,11331"; a="42491561" X-IronPort-AV: E=Sophos;i="6.13,246,1732608000"; d="scan'208";a="42491561" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2025 13:00:54 -0800 X-CSE-ConnectionGUID: GSvaqwYxS+eqoqcKyYlgZg== X-CSE-MsgGUID: Slbc6RmXSW2h9SwaOFLXUA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,246,1732608000"; d="scan'208";a="110015905" Received: from mwiniars-desk2.ger.corp.intel.com (HELO vgovind2-mobl3.intel.com) ([10.245.246.118]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2025 13:00:52 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, santhosh.reddy.guddati@intel.com, jani.saarinen@intel.com Subject: [PATCH v6 4/7] drm/i915/xe3: update and store the plane damage clips Date: Thu, 30 Jan 2025 23:00:23 +0200 Message-ID: <20250130210027.591927-5-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250130210027.591927-1-vinod.govindapillai@intel.com> References: <20250130210027.591927-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Userspace can pass damage area clips per plane to track changes in a plane and some display components can utilze these damage clips for efficiently handling use cases like FBC, PSR etc. A merged damage area is generated and its coordinates are updated relative to viewport and HW and stored in the plane_state. This merged damage areas will be used for FBC dirty rect support in xe3 in the follow-up patch. Big thanks to Ville Syrjala for his contribuitions in shaping up of this series. v1: - Move damage_merged helper to cover bigjoiner case and use the correct plane state for damage find helper (Ville) - Damage handling code under HAS_FBC_DIRTY_RECT() so the the related part will be executed only for xe3+ - Changed dev_priv to i915 in one of the functions Signed-off-by: Vinod Govindapillai --- .../gpu/drm/i915/display/intel_atomic_plane.c | 28 ++++++++++++ .../drm/i915/display/intel_display_types.h | 2 + .../drm/i915/display/skl_universal_plane.c | 45 +++++++++++++++++-- 3 files changed, 71 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index c558143f4f82..f55f7044dc67 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -36,6 +36,7 @@ #include #include +#include #include #include #include @@ -322,6 +323,25 @@ static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state) memset(&plane_state->hw, 0, sizeof(plane_state->hw)); } +static void +intel_plane_check_plane_damage(struct intel_plane_state *new_plane_state, + const struct intel_plane_state *old_primary_plane_state, + const struct intel_plane_state *new_primary_plane_state) +{ + struct intel_display *display = to_intel_display(new_plane_state); + struct drm_rect *damage_merged = &new_plane_state->damage_merged; + + if (!HAS_FBC_DIRTY_RECT(display)) + return; + + if (!drm_atomic_helper_damage_merged(&old_primary_plane_state->uapi, + &new_primary_plane_state->uapi, + damage_merged)) + /* Incase helper fails, mark whole plane region as damage */ + *damage_merged = + drm_plane_state_src(&new_primary_plane_state->uapi); +} + void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state, const struct intel_plane_state *from_plane_state, struct intel_crtc *crtc) @@ -691,6 +711,7 @@ int intel_plane_atomic_check(struct intel_atomic_state *state, const struct intel_plane_state *old_plane_state = intel_atomic_get_old_plane_state(state, plane); const struct intel_plane_state *new_primary_crtc_plane_state; + const struct intel_plane_state *old_primary_crtc_plane_state; struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); @@ -705,10 +726,17 @@ int intel_plane_atomic_check(struct intel_atomic_state *state, new_primary_crtc_plane_state = intel_atomic_get_new_plane_state(state, primary_crtc_plane); + old_primary_crtc_plane_state = + intel_atomic_get_old_plane_state(state, primary_crtc_plane); } else { new_primary_crtc_plane_state = new_plane_state; + old_primary_crtc_plane_state = old_plane_state; } + intel_plane_check_plane_damage(new_plane_state, + old_primary_crtc_plane_state, + new_primary_crtc_plane_state); + intel_plane_copy_uapi_to_hw_state(new_plane_state, new_primary_crtc_plane_state, crtc); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index cb51b7936f93..8d53bcca9614 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -695,6 +695,8 @@ struct intel_plane_state { u64 ccval; const char *no_fbc_reason; + + struct drm_rect damage_merged; }; struct intel_initial_plane_config { diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 301ad3a22c4c..b90a7d52c071 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2249,11 +2249,42 @@ static void check_protection(struct intel_plane_state *plane_state) !plane_state->decrypt; } +static void +skl_plane_check_damage_with_viewport(struct intel_plane_state *plane_state) +{ + struct drm_rect *damage_merged = &plane_state->damage_merged; + const struct drm_framebuffer *fb = plane_state->hw.fb; + unsigned int rotation = plane_state->hw.rotation; + struct drm_rect *src = &plane_state->uapi.src; + + if (drm_rotation_90_or_270(rotation)) { + drm_rect_rotate(damage_merged, fb->width, fb->height, + DRM_MODE_ROTATE_270); + drm_rect_translate(damage_merged, -(src->y1 >> 16), + -(src->x1 >> 16)); + } else { + drm_rect_translate(damage_merged, -(src->x1 >> 16), + -(src->y1 >> 16)); + } +} + +static void +skl_plane_check_damage_with_plane_surf(struct intel_plane_state *plane_state) +{ + struct drm_rect *damage_merged = &plane_state->damage_merged; + struct drm_rect src; + + drm_rect_fp_to_int(&src, &plane_state->uapi.src); + drm_rect_translate(damage_merged, src.x1, src.y1); + drm_rect_intersect(damage_merged, &src); +} + static int skl_plane_check(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct drm_i915_private *i915 = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; int min_scale = DRM_PLANE_NO_SCALING; int max_scale = DRM_PLANE_NO_SCALING; @@ -2266,7 +2297,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state, /* use scaler when colorkey is not required */ if (!plane_state->ckey.flags && skl_fb_scalable(fb)) { min_scale = 1; - max_scale = skl_plane_max_scale(dev_priv, fb); + max_scale = skl_plane_max_scale(i915, fb); } ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, @@ -2274,6 +2305,9 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state, if (ret) return ret; + if (HAS_FBC_DIRTY_RECT(display)) + skl_plane_check_damage_with_viewport(plane_state); + ret = skl_check_plane_surface(plane_state); if (ret) return ret; @@ -2289,6 +2323,9 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state, if (ret) return ret; + if (HAS_FBC_DIRTY_RECT(display)) + skl_plane_check_damage_with_plane_surf(plane_state); + ret = skl_plane_check_nv12_rotation(plane_state); if (ret) return ret; @@ -2301,12 +2338,12 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state, plane_state->ctl = skl_plane_ctl(crtc_state, plane_state); - if (DISPLAY_VER(dev_priv) >= 10) + if (DISPLAY_VER(display) >= 10) plane_state->color_ctl = glk_plane_color_ctl(crtc_state, plane_state); if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && - icl_is_hdr_plane(dev_priv, plane->id)) + icl_is_hdr_plane(i915, plane->id)) /* Enable and use MPEG-2 chroma siting */ plane_state->cus_ctl = PLANE_CUS_ENABLE | PLANE_CUS_HPHASE_0 | From patchwork Thu Jan 30 21:00:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Govindapillai, Vinod" X-Patchwork-Id: 13954968 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A23F5C0218D for ; Thu, 30 Jan 2025 21:00:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4E61910E9D4; Thu, 30 Jan 2025 21:00:59 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="UD5RTOJg"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6B4DA10E9D4; Thu, 30 Jan 2025 21:00:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738270858; x=1769806858; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rcHPEJ5oFP9pjqR6U27o2pJd7HOwDbZseVMKveTyjpQ=; b=UD5RTOJgMBe2kAsDtB/tjQcyngUVLGLNGipfRw0n1Tq0+FV3mhnYgDDv fQX6tx++28KZjTrVvfHwrN/mLkip1YKW9b6AtjMJwrsmbIpxTSilWarHH xz/PXEKrDhLY8PvBRa+uH6j9YcBbT51rziAMEPST6fQ/Si34xuYN5jRr/ /6IYPjmy38m1Hq9RwbFeIWTfchDoDyGKTR2fzMxK5aKvHu1D3lbawrZ2T 68/kAFn/eWhb7U1Jik/5Cp8CqeqhznG1xod/ih+7iBTLrvueTs8A+GcOW X8d0LAwhrjW83J6dnljMq9nT+0OmDYC9ZewBO0JWGn1tSo7wWSCJB/XbW w==; X-CSE-ConnectionGUID: 7UYDQNHqTT6nua0XkFrpqA== X-CSE-MsgGUID: BatkscDhSk23AW19q2XnCw== X-IronPort-AV: E=McAfee;i="6700,10204,11331"; a="42491577" X-IronPort-AV: E=Sophos;i="6.13,246,1732608000"; d="scan'208";a="42491577" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2025 13:00:58 -0800 X-CSE-ConnectionGUID: NU0wsdeXSgSFUNEgTN4jsg== X-CSE-MsgGUID: yCpUPkY4RLelB6eZKBvn5A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,246,1732608000"; d="scan'208";a="110015928" Received: from mwiniars-desk2.ger.corp.intel.com (HELO vgovind2-mobl3.intel.com) ([10.245.246.118]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2025 13:00:56 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, santhosh.reddy.guddati@intel.com, jani.saarinen@intel.com Subject: [PATCH v6 5/7] drm/i915/xe3: dirty rect support for FBC Date: Thu, 30 Jan 2025 23:00:24 +0200 Message-ID: <20250130210027.591927-6-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250130210027.591927-1-vinod.govindapillai@intel.com> References: <20250130210027.591927-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Dirty rectangle feature allows FBC to recompress a subsection of a frame. When this feature is enabled, display will read the scan lines between dirty rectangle start line and dirty rectangle end line in subsequent frames. Use the merged damage clip stored in the plane state to configure the FBC dirty rect areas. v2: - Move dirty rect handling to fbc state (Ville) v3: - Use intel_fbc_dirty_rect_update_noarm (Ville) - Split plane damage collection and dirty rect preparation - Handle case where dirty rect fall outside the visible region v4: - A state variable to check if we need to update dirty rect registers in case intel_fbc_can_flip_nuke() (Ville) Bspec: 68881, 71675, 73424 Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/intel_display.c | 7 + drivers/gpu/drm/i915/display/intel_fbc.c | 132 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_fbc.h | 6 + 3 files changed, 145 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 7d68d652c1bc..33277f892279 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7263,6 +7263,8 @@ static void intel_update_crtc(struct intel_atomic_state *state, commit_pipe_pre_planes(state, crtc); + intel_fbc_dirty_rect_update_noarm(NULL, state, crtc); + intel_crtc_planes_update_arm(NULL, state, crtc); commit_pipe_post_planes(state, crtc); @@ -7723,6 +7725,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, new_crtc_state); intel_crtc_planes_update_noarm(new_crtc_state->dsb_commit, state, crtc); + intel_fbc_dirty_rect_update_noarm(new_crtc_state->dsb_commit, + state, crtc); intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit); @@ -7769,6 +7773,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_atomic_prepare_plane_clear_colors(state); + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) + intel_fbc_prepare_dirty_rect(state, crtc); + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) intel_atomic_dsb_finish(state, crtc); diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index df05904bac8a..24736c7a79a6 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -88,6 +88,10 @@ struct intel_fbc_state { u16 override_cfb_stride; u16 interval; s8 fence_id; + struct { + struct drm_rect rect; + bool valid; + } fbc_dirty_rect; }; struct intel_fbc { @@ -527,6 +531,9 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc) struct intel_display *display = fbc->display; u32 dpfc_ctl; + if (HAS_FBC_DIRTY_RECT(display)) + intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), 0); + /* Disable compression */ dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id)); if (dpfc_ctl & DPFC_CTL_EN) { @@ -670,6 +677,10 @@ static void ivb_fbc_activate(struct intel_fbc *fbc) if (DISPLAY_VER(display) >= 20) intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); + if (HAS_FBC_DIRTY_RECT(display)) + intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), + FBC_DIRTY_RECT_EN); + intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), DPFC_CTL_EN | dpfc_ctl); } @@ -1203,6 +1214,127 @@ static bool tiling_is_valid(const struct intel_plane_state *plane_state) return i8xx_fbc_tiling_valid(plane_state); } +static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state, + struct intel_crtc *crtc, + struct intel_plane *plane); + +static void +intel_fbc_dirty_rect_update(struct intel_dsb *dsb, struct intel_plane *plane) +{ + struct intel_display *display = to_intel_display(plane); + struct intel_fbc *fbc = plane->fbc; + struct intel_fbc_state *fbc_state = &fbc->state; + struct drm_rect *fbc_dirty_rect = &fbc_state->fbc_dirty_rect.rect; + + if (fbc_state->plane != plane) + return; + + if (!fbc_state->fbc_dirty_rect.valid) + return; + + intel_de_write_dsb(display, dsb, XE3_FBC_DIRTY_RECT(fbc->id), + FBC_DIRTY_RECT_START_LINE(fbc_dirty_rect->y1) | + FBC_DIRTY_RECT_END_LINE(fbc_dirty_rect->y2)); + + fbc_state->fbc_dirty_rect.valid = false; +} + +void +intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb, + struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + struct intel_display *display = to_intel_display(state); + struct intel_plane_state *plane_state; + struct intel_plane *plane; + int i; + + if (!HAS_FBC_DIRTY_RECT(display)) + return; + + for_each_new_intel_plane_in_state(state, plane, plane_state, i) { + struct intel_fbc *fbc = plane->fbc; + + if (!fbc || plane->pipe != crtc->pipe) + continue; + + if (!plane_state->uapi.visible) + continue; + + intel_fbc_dirty_rect_update(dsb, plane); + } +} + +static void +validate_and_clip_dirty_rect(struct intel_plane_state *plane_state, + struct drm_rect *dirty_rect) +{ + int y_offset = plane_state->view.color_plane[0].y; + int plane_height = drm_rect_height(&plane_state->uapi.src) >> 16; + int max_endline = y_offset + plane_height - 1; + + dirty_rect->y1 = clamp(dirty_rect->y1, y_offset, max_endline); + dirty_rect->y2 = clamp(dirty_rect->y2, dirty_rect->y1, max_endline); +} + +static void +__intel_fbc_prepare_dirty_rect(struct intel_plane *plane, + struct intel_plane_state *plane_state, + bool fbc_dirty_rect_valid) +{ + struct intel_fbc_state *fbc_state = &plane->fbc->state; + struct drm_rect *fbc_dirty_rect = &fbc_state->fbc_dirty_rect.rect; + struct drm_rect *damage_merged = &plane_state->damage_merged; + int y_offset = plane_state->view.color_plane[0].y; + + fbc_state->fbc_dirty_rect.valid = fbc_dirty_rect_valid; + + if (drm_rect_visible(damage_merged)) { + fbc_dirty_rect->y1 = damage_merged->y1; + fbc_dirty_rect->y2 = damage_merged->y2; + } else { + /* If not visible, we need to set one single line */ + fbc_dirty_rect->y1 = y_offset; + fbc_dirty_rect->y2 = y_offset; + } + fbc_dirty_rect->x1 = damage_merged->x1; + fbc_dirty_rect->x2 = damage_merged->x2; + + validate_and_clip_dirty_rect(plane_state, fbc_dirty_rect); +} + +void +intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + struct intel_display *display = to_intel_display(state); + struct intel_plane_state *plane_state; + struct intel_plane *plane; + int i; + + if (!HAS_FBC_DIRTY_RECT(display)) + return; + + for_each_new_intel_plane_in_state(state, plane, plane_state, i) { + struct intel_fbc *fbc = plane->fbc; + + if (!fbc || plane->pipe != crtc->pipe) + continue; + + if (!fbc->state.plane) + continue; + + /* If plane not visible, dirty rect might have invalid coordinates */ + if (!plane_state->uapi.visible) + continue; + + __intel_fbc_prepare_dirty_rect(plane, plane_state, + intel_fbc_can_flip_nuke(state, + crtc, + plane)); + } +} + static void intel_fbc_update_state(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_plane *plane) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h index ceae55458e14..8f1b11c6f4d2 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.h +++ b/drivers/gpu/drm/i915/display/intel_fbc.h @@ -14,6 +14,7 @@ struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; struct intel_display; +struct intel_dsb; struct intel_fbc; struct intel_plane; struct intel_plane_state; @@ -48,5 +49,10 @@ void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display); void intel_fbc_reset_underrun(struct intel_display *display); void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc); void intel_fbc_debugfs_register(struct intel_display *display); +void intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state, + struct intel_crtc *crtc); +void intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb, + struct intel_atomic_state *state, + struct intel_crtc *crtc); #endif /* __INTEL_FBC_H__ */ From patchwork Thu Jan 30 21:00:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Govindapillai, Vinod" X-Patchwork-Id: 13954969 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E8081C0218A for ; Thu, 30 Jan 2025 21:01:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E65410E9DF; Thu, 30 Jan 2025 21:01:03 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="XHQ7fYrD"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id EA63A10E9DF; Thu, 30 Jan 2025 21:01:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738270862; x=1769806862; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qVHXg3P8M/jwlyXjqgN47/+zJZpeGnPPaTvfAimI77o=; b=XHQ7fYrDFWeEdhuev89bRcXZmd7Y7AUWLTbah0SHPKfPTjis1g3uLaZ8 KH2RZh8toqNr2nG7azQ7JHBPEGR7Z/UC7DMipj/TlN2dbiOPVel1o9bjF AXlwXwETK/o4qu7Tw6sMqfLZFNImrF7u2+4c+GpFuXVfyGx2fIfEhfVee Ncu6HMQSaOtZ665FrCkZFmj8W2lxLuNGF3VCBJ/XFr6ThuasS9iei20AS b8X5ERuMt4JFZ6urDKaNxAQ8w0D5elSQypep7fbB8pLsXsFqBraP7OPsF kZjYJCeHusA6NXKTA7pSsrtC213DGnMQ1LAIbV3i4FlycBjTOnh+G6iR1 A==; X-CSE-ConnectionGUID: u8iQEJ4aQ3iehLyJAi6l/A== X-CSE-MsgGUID: rSy7LdiLSMyjckGWn1XgOA== X-IronPort-AV: E=McAfee;i="6700,10204,11331"; a="42491592" X-IronPort-AV: E=Sophos;i="6.13,246,1732608000"; d="scan'208";a="42491592" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2025 13:01:01 -0800 X-CSE-ConnectionGUID: cJJK/rmsSPuITE5ZPVcXGQ== X-CSE-MsgGUID: dDBtSu7JQnCRpM/6mNQSBg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,246,1732608000"; d="scan'208";a="110015961" Received: from mwiniars-desk2.ger.corp.intel.com (HELO vgovind2-mobl3.intel.com) ([10.245.246.118]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2025 13:00:59 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, santhosh.reddy.guddati@intel.com, jani.saarinen@intel.com Subject: [PATCH v6 6/7] drm/i915/xe3: avoid calling fbc activate if fbc is active Date: Thu, 30 Jan 2025 23:00:25 +0200 Message-ID: <20250130210027.591927-7-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250130210027.591927-1-vinod.govindapillai@intel.com> References: <20250130210027.591927-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" If FBC is already active, we don't need to call FBC activate routine again. This is more relevant in case of dirty rect support in FBC. Xe doesn't support legacy fences. Hence fence programming also not required as part of this fbc_hw_activate. Any FBC related register updates done after enabling the dirty rect support in xe3 will trigger nuke by FBC HW. So avoid calling fbc activate routine again if the FBC is already active. The front buffer rendering sequence will call intel_fbc_flush() and which will call intel_fbc_nuke() or intel_fbc_activate() based on FBC status explicitly and won't get impacted by this change. v2: use HAS_FBC_DIRTY_RECT() move this functionality within intel_fbc_activate() Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/intel_fbc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 24736c7a79a6..b17ee1797118 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -750,8 +750,19 @@ static void intel_fbc_nuke(struct intel_fbc *fbc) static void intel_fbc_activate(struct intel_fbc *fbc) { + struct intel_display *display = fbc->display; + lockdep_assert_held(&fbc->lock); + /* + * When dirty rectangle is enabled, any updates to FBC registers will + * trigger nuke. So avoid calling intel_fbc_activate if fbc is already + * active and for XE3 cases. Xe doesn't support legacy fences. So + * no need to update the fences as well. + */ + if (HAS_FBC_DIRTY_RECT(display) && fbc->active) + return; + intel_fbc_hw_activate(fbc); intel_fbc_nuke(fbc); From patchwork Thu Jan 30 21:00:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Govindapillai, Vinod" X-Patchwork-Id: 13954970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 934D5C0218A for ; Thu, 30 Jan 2025 21:01:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3286010E9DC; Thu, 30 Jan 2025 21:01:07 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Ec26PS/T"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7534010E9E2; Thu, 30 Jan 2025 21:01:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738270865; x=1769806865; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Qj+l+pxyse1z4wwgaK9lg+GZBlYCKWj7TeKSI7Qto8Y=; b=Ec26PS/TXCHJV4weHj0PleegNIRr7lO5l5PsC5NCoD3fwwOgLf2hR48u uxaqG4fnPmBIIPtaYN3Zjpf1iPJ6oHdvWl7NnQUr+TUrJuYrmnSyUC2Vb 2H3nj80mF8sk3WLOh40L1mnaThK+Fh6QmF/NHSt0WDt5qRXp1KKhbsTOq nvCmyX5oBZI3UZ96XCJtpXf8ynEpS0a827its7uNV+TCuJ01UI7Uk5Ib6 /ptkM+tfPV9SVGBCDDFe2xhj0nbkeIXly8nrVuuvURPwjkRA3tAUIIzGC 7Q2UqB1aa3YDGkAPvUImB/ggVmLw0nD8dCX1XH+zSFhgfmuh8i6Wh1gqc g==; X-CSE-ConnectionGUID: pvv3K7puQqSNOv/A00gv8w== X-CSE-MsgGUID: PIa9A806TBOSjFhUxRcM/A== X-IronPort-AV: E=McAfee;i="6700,10204,11331"; a="42491603" X-IronPort-AV: E=Sophos;i="6.13,246,1732608000"; d="scan'208";a="42491603" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2025 13:01:05 -0800 X-CSE-ConnectionGUID: C6knJu7DT7K3QAeK2Q6vKg== X-CSE-MsgGUID: sufbU2VoRPuTx335eSNJCg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,246,1732608000"; d="scan'208";a="110015991" Received: from mwiniars-desk2.ger.corp.intel.com (HELO vgovind2-mobl3.intel.com) ([10.245.246.118]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2025 13:01:03 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, santhosh.reddy.guddati@intel.com, jani.saarinen@intel.com Subject: [PATCH v6 7/7] drm/i915/xe3: disable FBC if PSR2 selective fetch is enabled Date: Thu, 30 Jan 2025 23:00:26 +0200 Message-ID: <20250130210027.591927-8-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250130210027.591927-1-vinod.govindapillai@intel.com> References: <20250130210027.591927-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" It is not recommended to have both FBC dirty rect and PSR2 selective fetch be enabled at the same time. If PSR2 selective fetch or panel replay is on, mark FBC as not possible. v2: fix the condition to disable FBC if PSR2 enabled (Jani) v3: use HAS_FBC_DIRTY_RECT() Bspec: 68881 Signed-off-by: Vinod Govindapillai Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index b17ee1797118..429e213e1dcd 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1481,9 +1481,14 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, * Display 12+ is not supporting FBC with PSR2. * Recommendation is to keep this combination disabled * Bspec: 50422 HSD: 14010260002 + * + * In Xe3, PSR2 selective fetch and FBC dirty rect feature cannot + * coexist. So if PSR2 selective fetch is supported then mark that + * FBC is not supported. + * TODO: Need a logic to decide between PSR2 and FBC Dirty rect */ - if (IS_DISPLAY_VER(display, 12, 14) && crtc_state->has_sel_update && - !crtc_state->has_panel_replay) { + if ((IS_DISPLAY_VER(display, 12, 14) || HAS_FBC_DIRTY_RECT(display)) && + crtc_state->has_sel_update && !crtc_state->has_panel_replay) { plane_state->no_fbc_reason = "PSR2 enabled"; return 0; }