From patchwork Fri Jan 31 10:17:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: mahesh rao X-Patchwork-Id: 13955209 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA0A116EB7C; Fri, 31 Jan 2025 10:17:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738318664; cv=none; b=kN+5/BpMjRNynRGoaV1uL5oppRwZYlPXaCGSwk1JzErqoLMNmW5EEhUpjJU+1y81dIPNmLaW9Elm1DDEpYgf3/jhD4YOAMK09B86l2gJF64uFMiZmTwEtpJ492uqukzX+8KEjtDOFJVmf30OY6MnvEWVCXdgp1STD2vcSuXOcR8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738318664; c=relaxed/simple; bh=xIvHbDqiEdk2VI7vzbiKbjtJ5iQ7i2K3SPDh9KKxMFc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IWjSKTu0K+7BihpK5IGaQy85UWQOqDdqZvBArsR27OPjBBcOfCCS1nJ1sLqI4fs9SCGB/NOd6fITbBDKkIrAnGi/lz0+uGaT809W9lRmu0/oC1r0u3HzePJ7JGARj8gcgHuY7+adpePdMLJafMQbY4LjU3ihpkqZqcMYynknWiU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=AsSZtwRI; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="AsSZtwRI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738318662; x=1769854662; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=xIvHbDqiEdk2VI7vzbiKbjtJ5iQ7i2K3SPDh9KKxMFc=; b=AsSZtwRI8Xt8PfsC41/cVAPyA0AKd6xY8Ytoj3Gx6KtHOkctUgLdH0td HsbYzCeJWs9Fq/9ILyOXWV252GXYldSxRlCcpaYjOjMWoQiMVk1MXkU7a Cip+/7Tbzo5HRfzdJ4z4cVmKs9gQ9jTyo9Pnqgfa+T5h+Xesmaw5DJBY3 NWS3vIZTKezKoDJzERG9DzeC1dMR+9vuwmxpU4GyOKm3s79/NfETM9YKb oymfT/ozu3TY1dke4NUyhbDcLlct3KaDonrRUu1yS1aHgoV1GivYHOQpx xYqhnhaJMbhD1sVh8enzxNltbV+C2A9zf68YMufNFOmzMTnmRQ7MBE6Dl Q==; X-CSE-ConnectionGUID: CSKelIg1TF+8izBjE3IJ1w== X-CSE-MsgGUID: xYn8YRPfTUOsDd7lrjrCbQ== X-IronPort-AV: E=McAfee;i="6700,10204,11331"; a="38777220" X-IronPort-AV: E=Sophos;i="6.13,248,1732608000"; d="scan'208";a="38777220" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2025 02:17:42 -0800 X-CSE-ConnectionGUID: i+VoEgvYQriJ/BYpEZlObg== X-CSE-MsgGUID: N4C1nKNtTtW4A8eX6s+MQA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,248,1732608000"; d="scan'208";a="114596183" Received: from apgcp0c531115.png.altera.com ([10.244.76.209]) by fmviesa004.fm.intel.com with ESMTP; 31 Jan 2025 02:17:39 -0800 From: Mahesh Rao Date: Fri, 31 Jan 2025 18:17:24 +0800 Subject: [PATCH v2 1/3] dt-bindings: fpga: stratix10: Convert to json-schema Precedence: bulk X-Mailing-List: linux-fpga@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250131-socfpga_sip_svc_misc-v2-1-eeed4ebc35f9@intel.com> References: <20250131-socfpga_sip_svc_misc-v2-0-eeed4ebc35f9@intel.com> In-Reply-To: <20250131-socfpga_sip_svc_misc-v2-0-eeed4ebc35f9@intel.com> To: Moritz Fischer , Xu Yilun , Tom Rix , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dinh Nguyen , Krzysztof Kozlowski , Wu Hao , Ho Yin , Niravkumar L Rabara Cc: linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mahesh Rao , Mahesh Rao X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1738318654; l=2648; i=mahesh.rao@intel.com; s=20250107; h=from:subject:message-id; bh=xIvHbDqiEdk2VI7vzbiKbjtJ5iQ7i2K3SPDh9KKxMFc=; b=QnUTHXZLPs6LywnCnvHz1YXuqCAAxbOmQo0NLfsIoNdDq3SqoVeRPgtXYgJSA3KfGJjE5qcTQ AGoJtwArxxgCggm+jyBdjnsbTlltpf6RdhXFiga2hjw28MiNrSz7TnV X-Developer-Key: i=mahesh.rao@intel.com; a=ed25519; pk=tQiFUzoKxHrQLDtWeEeaeTeJTl/UfclUHWZy1fjSiyg= Convert intel,stratix10-soc fpga manager devicetree binding file from freeform format to json-schema. Signed-off-by: Mahesh Rao Reviewed-by: Rob Herring (Arm) --- .../fpga/intel,stratix10-soc-fpga-mgr.yaml | 36 ++++++++++++++++++++++ .../bindings/fpga/intel-stratix10-soc-fpga-mgr.txt | 18 ----------- 2 files changed, 36 insertions(+), 18 deletions(-) diff --git a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml new file mode 100644 index 0000000000000000000000000000000000000000..6e536d6b28a9732c492da5d57f89df648dba7f4b --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Stratix10 SoC FPGA Manager + +maintainers: + - Mahesh Rao + - Adrian Ng Ho Yin + - Niravkumar L Rabara + +description: + The Intel Stratix10 SoC consists of a 64-bit quad-core ARM Cortex A53 hard + processor system (HPS) and a Secure Device Manager (SDM). The Stratix10 + SoC FPGA Manager driver is used to configure/reconfigure the FPGA fabric + on the die.The driver communicates with SDM/ATF via the stratix10-svc + platform driver for performing its operations. + +properties: + compatible: + enum: + - intel,stratix10-soc-fpga-mgr + - intel,agilex-soc-fpga-mgr + +required: + - compatible + +additionalProperties: false + +examples: + - | + fpga-mgr { + compatible = "intel,stratix10-soc-fpga-mgr"; + }; diff --git a/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt deleted file mode 100644 index 0f874137ca4697820341b23eddb882634bb131d1..0000000000000000000000000000000000000000 --- a/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt +++ /dev/null @@ -1,18 +0,0 @@ -Intel Stratix10 SoC FPGA Manager - -Required properties: -The fpga_mgr node has the following mandatory property, must be located under -firmware/svc node. - -- compatible : should contain "intel,stratix10-soc-fpga-mgr" or - "intel,agilex-soc-fpga-mgr" - -Example: - - firmware { - svc { - fpga_mgr: fpga-mgr { - compatible = "intel,stratix10-soc-fpga-mgr"; - }; - }; - }; From patchwork Fri Jan 31 10:17:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: mahesh rao X-Patchwork-Id: 13955210 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 867BD1B21A9; Fri, 31 Jan 2025 10:17:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738318668; cv=none; b=jvKhMl76bfeScd+Fo79VCfop9JMf5nXiC7ICOEXMad80L7Xt4F2amwC767lZREnu2H/df0IryENPksD15plpqLdEr1zLteDUf0EsNiaZL7w35ctIGOO34QKiS2SWZfZCClnB1nUqe61GWzIkCfGKSv5pHq+GR77/3GzEsb7ThVg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738318668; c=relaxed/simple; bh=GHqdxg2DS4YgMXOLBGV+kcxzA37+EhGXDzEY8PqyFNc=; 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31 Jan 2025 02:17:43 -0800 From: Mahesh Rao Date: Fri, 31 Jan 2025 18:17:25 +0800 Subject: [PATCH v2 2/3] dt-bindings: firmware: stratix10: Convert to json-schema Precedence: bulk X-Mailing-List: linux-fpga@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250131-socfpga_sip_svc_misc-v2-2-eeed4ebc35f9@intel.com> References: <20250131-socfpga_sip_svc_misc-v2-0-eeed4ebc35f9@intel.com> In-Reply-To: <20250131-socfpga_sip_svc_misc-v2-0-eeed4ebc35f9@intel.com> To: Moritz Fischer , Xu Yilun , Tom Rix , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dinh Nguyen , Krzysztof Kozlowski , Wu Hao , Ho Yin , Niravkumar L Rabara Cc: linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mahesh Rao , Mahesh Rao X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1738318654; l=6493; i=mahesh.rao@intel.com; s=20250107; h=from:subject:message-id; bh=GHqdxg2DS4YgMXOLBGV+kcxzA37+EhGXDzEY8PqyFNc=; b=UEjLxJvCLnLJnSpySaCufDdLJcmx7nX/CzJTkrWWMoFMQ+zWscduEZITxa+T4HwC2L6ATQl6L MRahfK32CO9Ctnqj/uiNibiGkX5PmQSQrG1yaFjPIVqQzNzaHMChCgS X-Developer-Key: i=mahesh.rao@intel.com; a=ed25519; pk=tQiFUzoKxHrQLDtWeEeaeTeJTl/UfclUHWZy1fjSiyg= Convert intel,stratix10-svc service layer devicetree binding file from freeform format to json-schema. Also added DT binding for optional stratix10-soc FPGA manager child node. Signed-off-by: Mahesh Rao --- .../bindings/firmware/intel,stratix10-svc.txt | 57 ------------- .../bindings/firmware/intel,stratix10-svc.yaml | 94 ++++++++++++++++++++++ 2 files changed, 94 insertions(+), 57 deletions(-) diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt deleted file mode 100644 index 6eff1afd8daf91714d6a18859667d2607e707da7..0000000000000000000000000000000000000000 --- a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt +++ /dev/null @@ -1,57 +0,0 @@ -Intel Service Layer Driver for Stratix10 SoC -============================================ -Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard -processor system (HPS) and Secure Device Manager (SDM). When the FPGA is -configured from HPS, there needs to be a way for HPS to notify SDM the -location and size of the configuration data. Then SDM will get the -configuration data from that location and perform the FPGA configuration. - -To meet the whole system security needs and support virtual machine requesting -communication with SDM, only the secure world of software (EL3, Exception -Layer 3) can interface with SDM. All software entities running on other -exception layers must channel through the EL3 software whenever it needs -service from SDM. - -Intel Stratix10 service layer driver, running at privileged exception level -(EL1, Exception Layer 1), interfaces with the service providers and provides -the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer -driver also manages secure monitor call (SMC) to communicate with secure monitor -code running in EL3. - -Required properties: -------------------- -The svc node has the following mandatory properties, must be located under -the firmware node. - -- compatible: "intel,stratix10-svc" or "intel,agilex-svc" -- method: smc or hvc - smc - Secure Monitor Call - hvc - Hypervisor Call -- memory-region: - phandle to the reserved memory node. See - Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt - for details - -Example: -------- - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - service_reserved: svcbuffer@0 { - compatible = "shared-dma-pool"; - reg = <0x0 0x0 0x0 0x1000000>; - alignment = <0x1000>; - no-map; - }; - }; - - firmware { - svc { - compatible = "intel,stratix10-svc"; - method = "smc"; - memory-region = <&service_reserved>; - }; - }; diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..e30e79d4c3150f90993e728320e9ef90d484a10d --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/intel,stratix10-svc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Service Layer Driver for Stratix10 SoC + +maintainers: + - Dinh Nguyen + - Mahesh Rao + +description: + Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard + processor system (HPS) and Secure Device Manager (SDM). When the FPGA is + configured from HPS, there needs to be a way for HPS to notify SDM the + location and size of the configuration data. Then SDM will get the + configuration data from that location and perform the FPGA configuration. + + To meet the whole system security needs and support virtual machine requesting + communication with SDM, only the secure world of software (EL3, Exception + Layer 3) can interface with SDM. All software entities running on other + exception layers must channel through the EL3 software whenever it needs + service from SDM. + + Intel Stratix10 service layer driver, running at privileged exception level + (EL1, Exception Layer 1), interfaces with the service providers and provides + the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer + driver also manages secure monitor call (SMC) to communicate with secure monitor + code running in EL3. + +properties: + compatible: + enum: + - intel,stratix10-svc + - intel,agilex-svc + + method: + description: | + Supervisory call method to be used to communicate with the + secure service layer. + Permitted values are: + - "smc" : SMC #0, following the SMCCC + - "hvc" : HVC #0, following the SMCCC + + $ref: /schemas/types.yaml#/definitions/string-array + enum: + - smc + - hvc + + memory-region: + maxItems: 1 + description: + phandle to a reserved memory region for the service layer driver to + communicate with the secure device manager. For more details see + Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt. + + fpga-mgr: + $ref: /schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml + description: Optional child node for fpga manager to perform fabric configuration. + +required: + - compatible + - method + - memory-region + +additionalProperties: false + +examples: + - | + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + service_reserved: svcbuffer@0 { + compatible = "shared-dma-pool"; + reg = <0x0 0x0 0x0 0x1000000>; + alignment = <0x1000>; + no-map; + }; + }; + + firmware { + svc { + compatible = "intel,stratix10-svc"; + method = "smc"; + memory-region = <&service_reserved>; + + fpga-mgr { + compatible = "intel,stratix10-soc-fpga-mgr"; + }; + }; + }; + From patchwork Fri Jan 31 10:17:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: mahesh rao X-Patchwork-Id: 13955211 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6342E1B415A; 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a="38777242" X-IronPort-AV: E=Sophos;i="6.13,248,1732608000"; d="scan'208";a="38777242" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2025 02:17:50 -0800 X-CSE-ConnectionGUID: fIveUyynQvCZgPl1LTxW1g== X-CSE-MsgGUID: OT2bVGWzSf2jGK9mdV8hsg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,248,1732608000"; d="scan'208";a="114596205" Received: from apgcp0c531115.png.altera.com ([10.244.76.209]) by fmviesa004.fm.intel.com with ESMTP; 31 Jan 2025 02:17:46 -0800 From: Mahesh Rao Date: Fri, 31 Jan 2025 18:17:26 +0800 Subject: [PATCH v2 3/3] firmware: stratix10-svc: Add of_platform_default_populate() Precedence: bulk X-Mailing-List: linux-fpga@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250131-socfpga_sip_svc_misc-v2-3-eeed4ebc35f9@intel.com> References: <20250131-socfpga_sip_svc_misc-v2-0-eeed4ebc35f9@intel.com> In-Reply-To: <20250131-socfpga_sip_svc_misc-v2-0-eeed4ebc35f9@intel.com> To: Moritz Fischer , Xu Yilun , Tom Rix , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dinh Nguyen , Krzysztof Kozlowski , Wu Hao , Ho Yin , Niravkumar L Rabara Cc: linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mahesh Rao , Mahesh Rao X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1738318654; l=1978; i=mahesh.rao@intel.com; s=20250107; h=from:subject:message-id; bh=T5wOj3s71piKUatOmbSbPqAr7wZL43qmiavckBOkNE8=; b=ZbR8Hn4nMA33JLcFsfEMZY7CrsWIgH++5jix9TNCqxlrPDNM0oDwTmYkFRvKq0ofWwr+DDg+a YQmunFT0KH6CJ9Ls3nHeuSc+U4jvC4AEKqfpWQD0O8axGGAImWm124R X-Developer-Key: i=mahesh.rao@intel.com; a=ed25519; pk=tQiFUzoKxHrQLDtWeEeaeTeJTl/UfclUHWZy1fjSiyg= Add of_platform_default_populate() to stratix10-svc driver as the firmware/svc node was moved out of soc. This fixes the failed probing of child drivers of svc node. Fixes: 23c3ebed382a ("arm64: dts: socfpga: agilex: move firmware out of soc node") Signed-off-by: Mahesh Rao Reviewed-by: Krzysztof Kozlowski --- drivers/firmware/stratix10-svc.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/firmware/stratix10-svc.c b/drivers/firmware/stratix10-svc.c index c5c78b869561b0c1e9602823ad1f501e98e3ce51..6a0419197c9ed2f2ccfc4643baba70340d0934f2 100644 --- a/drivers/firmware/stratix10-svc.c +++ b/drivers/firmware/stratix10-svc.c @@ -1227,22 +1227,28 @@ static int stratix10_svc_drv_probe(struct platform_device *pdev) if (!svc->intel_svc_fcs) { dev_err(dev, "failed to allocate %s device\n", INTEL_FCS); ret = -ENOMEM; - goto err_unregister_dev; + goto err_unregister_rsu_dev; } ret = platform_device_add(svc->intel_svc_fcs); if (ret) { platform_device_put(svc->intel_svc_fcs); - goto err_unregister_dev; + goto err_unregister_rsu_dev; } + ret = of_platform_default_populate(dev_of_node(dev), NULL, dev); + if (ret) + goto err_unregister_fcs_dev; + dev_set_drvdata(dev, svc); pr_info("Intel Service Layer Driver Initialized\n"); return 0; -err_unregister_dev: +err_unregister_fcs_dev: + platform_device_unregister(svc->intel_svc_fcs); +err_unregister_rsu_dev: platform_device_unregister(svc->stratix10_svc_rsu); err_free_kfifo: kfifo_free(&controller->svc_fifo); @@ -1256,6 +1262,8 @@ static void stratix10_svc_drv_remove(struct platform_device *pdev) struct stratix10_svc *svc = dev_get_drvdata(&pdev->dev); struct stratix10_svc_controller *ctrl = platform_get_drvdata(pdev); + of_platform_depopulate(ctrl->dev); + platform_device_unregister(svc->intel_svc_fcs); platform_device_unregister(svc->stratix10_svc_rsu);