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[85.23.190.22]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-307a3423fa1sm6104581fa.92.2025.01.31.05.36.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Jan 2025 05:36:46 -0800 (PST) Date: Fri, 31 Jan 2025 15:36:40 +0200 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Cameron , Lars-Peter Clausen , Matti Vaittinen , Linus Walleij , Nuno Sa , David Lechner , Dumitru Ceclan , Trevor Gamblin , Matteo Martelli , AngeloGioacchino Del Regno , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [RFC PATCH 1/5] dt-bindings: ROHM BD79124 ADC/GPO Message-ID: <90f58229e4ebc5aadd6a38a0671563978e7de4f5.1738328714.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Add binding document for the ROHM BD79124 ADC / GPO. ROHM BD79124 is a 8-channel, 12-bit ADC. The input pins can also be used as general purpose outputs. Switching between ADC and GPO is described using as a pinmux. Signed-off-by: Matti Vaittinen --- .../devicetree/bindings/mfd/rohm,bd79124.yaml | 111 ++++++++++++++++++ 1 file changed, 111 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/rohm,bd79124.yaml diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd79124.yaml b/Documentation/devicetree/bindings/mfd/rohm,bd79124.yaml new file mode 100644 index 000000000000..0d2958e82780 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/rohm,bd79124.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/rohm,bd79124.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROHM BD79124 ADC/GPO + +maintainers: + - Matti Vaittinen + +description: | + The ROHM BD79124 is a 12-bit, 8-channel, SAR ADC. The ADC supports + an automatic measurement mode, with an alarm interrupt for out-of-window + measurements. ADC input pins can be also configured as general purpose + outputs. + +properties: + compatible: + const: rohm,bd79124 + + reg: + description: + I2C slave address. + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 1 + description: + The pin number. + + vdd-supply: true + + iovdd-supply: true + +patternProperties: + "^channel@[0-9a-f]+$": + type: object + $ref: /schemas/iio/adc/adc.yaml# + description: Represents ADC channel. + + properties: + reg: + items: + minimum: 1 + maximum: 8 + + required: + - reg + + additionalProperties: false + + "-pins$": + type: object + $ref: /schemas/pinctrl/pinmux-node.yaml + + properties: + function: + enum: [gpo, adc] + + groups: + description: + List of pin groups affected by the functions specified in this + subnode. + items: + enum: [ain0, ain1, ain2, ain3, ain4, ain5, ain6, ain7] + + pins: + items: + enum: [ain0, ain1, ain2, ain3, ain4, ain5, ain6, ain7] + + additionalProperties: false + +required: + - compatible + - reg + - iovdd-supply + - vdd-supply + +additionalProperties: false + +examples: + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + adc: adc@10 { + compatible = "rohm,bd79124"; + reg = <0x10>; + interrupt-parent = <&gpio1>; + interrupts = <29 8>; + vdd-supply = <&dummyreg>; + iovdd-supply = <&dummyreg>; + + adcpins: adc-pins { + pins = "ain0", "ain1", "ain5", "ain7"; + function = "adc"; + }; + gpopins: gpo-pins { + groups = "ain2", "ain3", "ain4", "ain6"; + function = "gpo"; + }; + }; + }; From patchwork Fri Jan 31 13:37:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matti Vaittinen X-Patchwork-Id: 13955367 Received: from mail-lj1-f169.google.com (mail-lj1-f169.google.com [209.85.208.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B66DD1C8FB5; Fri, 31 Jan 2025 13:37:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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[85.23.190.22]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-307a3069d54sm5496371fa.1.2025.01.31.05.37.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Jan 2025 05:37:17 -0800 (PST) Date: Fri, 31 Jan 2025 15:37:06 +0200 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Cameron , Lars-Peter Clausen , Matti Vaittinen , Linus Walleij , Nuno Sa , David Lechner , Dumitru Ceclan , Trevor Gamblin , Matteo Martelli , AngeloGioacchino Del Regno , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [RFC PATCH 2/5] mfd: Add ROHM BD79124 ADC/GPO Message-ID: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Add core driver for the ROHM BD79124 ADC / GPO. The core driver launches the sub-drivers for the pinmux/GPO and for the IIO ADC. It also provides the regmap, and forwards the IRQ resource to the ADC. Signed-off-by: Matti Vaittinen --- drivers/mfd/Kconfig | 12 +++ drivers/mfd/Makefile | 1 + drivers/mfd/rohm-bd79124.c | 165 +++++++++++++++++++++++++++++++ include/linux/mfd/rohm-bd79124.h | 32 ++++++ 4 files changed, 210 insertions(+) create mode 100644 drivers/mfd/rohm-bd79124.c create mode 100644 include/linux/mfd/rohm-bd79124.h diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index ae23b317a64e..f024256fb180 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -2113,6 +2113,18 @@ config MFD_ROHM_BD71828 also a single-cell linear charger, a Coulomb counter, a real-time clock (RTC), GPIOs and a 32.768 kHz clock gate. +config MFD_ROHM_BD79124 + tristate "Rohm BD79124 core driver" + depends on I2C + select REGMAP_I2C + help + Say yes here to build support for the ROHM BD79124 ADC core. The + ROHM BD79124 is a 12-bit, 8-channel, SAR ADC. The ADC supports + also an automatic measurement mode, with an alarm interrupt for + out-of-window measurements. The window is configurable for each + channel. The ADC inputs can optionally be used as general purpose + outputs. + config MFD_ROHM_BD957XMUF tristate "ROHM BD9576MUF and BD9573MUF Power Management ICs" depends on I2C=y diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index e057d6d6faef..c7d64e933a7d 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -270,6 +270,7 @@ obj-$(CONFIG_MFD_SC27XX_PMIC) += sprd-sc27xx-spi.o obj-$(CONFIG_RAVE_SP_CORE) += rave-sp.o obj-$(CONFIG_MFD_ROHM_BD71828) += rohm-bd71828.o obj-$(CONFIG_MFD_ROHM_BD718XX) += rohm-bd718x7.o +obj-$(CONFIG_MFD_ROHM_BD79124) += rohm-bd79124.o obj-$(CONFIG_MFD_ROHM_BD957XMUF) += rohm-bd9576.o obj-$(CONFIG_MFD_ROHM_BD96801) += rohm-bd96801.o obj-$(CONFIG_MFD_STMFX) += stmfx.o diff --git a/drivers/mfd/rohm-bd79124.c b/drivers/mfd/rohm-bd79124.c new file mode 100644 index 000000000000..c35ab0e03b0b --- /dev/null +++ b/drivers/mfd/rohm-bd79124.c @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Copyright (C) 2025 ROHM Semiconductors +// +// ROHM BD79124 ADC / GPO driver + +#include +#include +#include +#include +#include + +#include +#include + +static struct resource adc_alert; + +enum { + CELL_PINMUX, + CELL_ADC, +}; + +static struct mfd_cell bd79124_cells[] = { + [CELL_PINMUX] = { .name = "bd79124-pinmux", }, + [CELL_ADC] = { .name = "bd79124-adc", }, +}; + +/* Read-only regs */ +static const struct regmap_range bd79124_ro_ranges[] = { + { + .range_min = BD79124_REG_EVENT_FLAG, + .range_max = BD79124_REG_EVENT_FLAG, + }, { + .range_min = BD79124_REG_RECENT_CH0_LSB, + .range_max = BD79124_REG_RECENT_CH7_MSB, + }, +}; + +static const struct regmap_access_table bd79124_ro_regs = { + .no_ranges = &bd79124_ro_ranges[0], + .n_no_ranges = ARRAY_SIZE(bd79124_ro_ranges), +}; + +static const struct regmap_range bd79124_volatile_ranges[] = { + { + .range_min = BD79124_REG_RECENT_CH0_LSB, + .range_max = BD79124_REG_RECENT_CH7_MSB, + }, { + .range_min = BD79124_REG_EVENT_FLAG, + .range_max = BD79124_REG_EVENT_FLAG, + }, { + .range_min = BD79124_REG_EVENT_FLAG_HI, + .range_max = BD79124_REG_EVENT_FLAG_HI, + }, { + .range_min = BD79124_REG_EVENT_FLAG_LO, + .range_max = BD79124_REG_EVENT_FLAG_LO, + }, { + .range_min = BD79124_REG_SYSTEM_STATUS, + .range_max = BD79124_REG_SYSTEM_STATUS, + }, +}; + +static const struct regmap_access_table bd79124_volatile_regs = { + .yes_ranges = &bd79124_volatile_ranges[0], + .n_yes_ranges = ARRAY_SIZE(bd79124_volatile_ranges), +}; + +static const struct regmap_range bd79124_precious_ranges[] = { + { + .range_min = BD79124_REG_EVENT_FLAG_HI, + .range_max = BD79124_REG_EVENT_FLAG_HI, + }, { + .range_min = BD79124_REG_EVENT_FLAG_LO, + .range_max = BD79124_REG_EVENT_FLAG_LO, + }, +}; + +static const struct regmap_access_table bd79124_precious_regs = { + .yes_ranges = &bd79124_precious_ranges[0], + .n_yes_ranges = ARRAY_SIZE(bd79124_precious_ranges), +}; + +static const struct regmap_config bd79124_regmap = { + .reg_bits = 16, + .val_bits = 8, + .read_flag_mask = BD79124_I2C_MULTI_READ, + .write_flag_mask = BD79124_I2C_MULTI_WRITE, + .max_register = BD79124_REG_MAX, + .cache_type = REGCACHE_MAPLE, + .volatile_table = &bd79124_volatile_regs, + .wr_table = &bd79124_ro_regs, + .precious_table = &bd79124_precious_regs, +}; + +static int bd79124_probe(struct i2c_client *i2c) +{ + int ret; + struct regmap *map; + struct device *dev = &i2c->dev; + int *adc_vref; + + adc_vref = devm_kzalloc(dev, sizeof(*adc_vref), GFP_KERNEL); + if (!adc_vref) + return -ENOMEM; + + /* + * Better to enable regulators here so we don't need to worry about the + * order of sub-device instantiation. We also need to deliver the + * reference voltage value to the ADC driver. This is done via + * the MFD driver's drvdata. + */ + *adc_vref = devm_regulator_get_enable_read_voltage(dev, "vdd"); + if (*adc_vref < 0) + return dev_err_probe(dev, ret, "Failed to get the Vdd\n"); + + dev_set_drvdata(dev, adc_vref); + + ret = devm_regulator_get_enable(dev, "iovdd"); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to enable I/O voltage\n"); + + map = devm_regmap_init_i2c(i2c, &bd79124_regmap); + if (IS_ERR(map)) + return dev_err_probe(dev, PTR_ERR(map), + "Failed to initialize Regmap\n"); + + if (i2c->irq) { + adc_alert = DEFINE_RES_IRQ_NAMED(i2c->irq, "thresh-alert"); + bd79124_cells[CELL_ADC].resources = &adc_alert; + bd79124_cells[CELL_ADC].num_resources = 1; + } + + ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, bd79124_cells, + ARRAY_SIZE(bd79124_cells), NULL, 0, NULL); + if (ret) + dev_err_probe(dev, ret, "Failed to create subdevices\n"); + + return ret; +} + +static const struct of_device_id bd79124_of_match[] = { + { .compatible = "rohm,bd79124" }, + { } +}; +MODULE_DEVICE_TABLE(of, bd79124_of_match); + +static const struct i2c_device_id bd79124_id[] = { + { "bd79124", }, + { } +}; +MODULE_DEVICE_TABLE(i2c, bd79124_id); + +static struct i2c_driver bd79124_driver = { + .driver = { + .name = "bd79124", + .of_match_table = bd79124_of_match, + }, + .probe = bd79124_probe, + .id_table = bd79124_id, +}; +module_i2c_driver(bd79124_driver); + +MODULE_AUTHOR("Matti Vaittinen "); +MODULE_DESCRIPTION("Core Driver for ROHM BD79124"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/mfd/rohm-bd79124.h b/include/linux/mfd/rohm-bd79124.h new file mode 100644 index 000000000000..505faeb6f135 --- /dev/null +++ b/include/linux/mfd/rohm-bd79124.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2021 ROHM Semiconductors. + * + * Author: Matti Vaittinen + */ + +#ifndef _MFD_BD79124_H +#define _MFD_BD79124_H + +#define BD79124_I2C_MULTI_READ 0x30 +#define BD79124_I2C_MULTI_WRITE 0x28 +#define BD79124_REG_MAX 0xaf + +#define BD79124_REG_SYSTEM_STATUS 0x0 +#define BD79124_REG_GEN_CFG 0x01 +#define BD79124_REG_OPMODE_CFG 0x04 +#define BD79124_REG_PINCFG 0x05 +#define BD79124_REG_GPO_VAL 0x06 +#define BD79124_REG_SEQUENCE_CFG 0x10 +#define BD79124_REG_MANUAL_CHANNELS 0x11 +#define BD79124_REG_AUTO_CHANNELS 0x12 +#define BD79124_REG_ALERT_CH_SEL 0x14 +#define BD79124_REG_EVENT_FLAG 0x18 +#define BD79124_REG_EVENT_FLAG_HI 0x1a +#define BD79124_REG_EVENT_FLAG_LO 0x1c +#define BD79124_REG_HYSTERESIS_CH0 0x20 +#define BD79124_REG_EVENTCOUNT_CH0 0x22 +#define BD79124_REG_RECENT_CH0_LSB 0xa0 +#define BD79124_REG_RECENT_CH7_MSB 0xaf + +#endif From patchwork Fri Jan 31 13:37:48 2025 Content-Type: text/plain; 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[85.23.190.22]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-543ebebec5esm486551e87.236.2025.01.31.05.37.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Jan 2025 05:38:00 -0800 (PST) Date: Fri, 31 Jan 2025 15:37:48 +0200 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Cameron , Lars-Peter Clausen , Matti Vaittinen , Linus Walleij , Nuno Sa , David Lechner , Dumitru Ceclan , Trevor Gamblin , Matteo Martelli , AngeloGioacchino Del Regno , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [RFC PATCH 3/5] iio: adc: Support ROHM BD79124 ADC Message-ID: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: The ROHM BD79124 is a 12-bit, 8-channel, SAR ADC. The ADC supports an automatic measurement mode, with an alarm interrupt for out-of-window measurements. The window is configurable for each channel. The I2C protocol for manual start of the measurement and data reading is somewhat peculiar. It requires the master to do clock stretching after sending the I2C slave-address until the slave has captured the data. Needless to say this is not well suopported by the I2C controllers. Thus the driver does not support the BD79124's manual measurement mode but implements the measurements using automatic measurement mode relying on the BD79124's ability of storing latest measurements into register. The driver does also support configuring the threshold events for detecting the out-of-window events. The BD79124 keeps asserting IRQ for as long as the measured voltage is out of the configured window. Thus the driver disables the event when first event is handled. This prevents the user-space from choking on the events - but it also requires the user space to reconfigure and re-enable the monitored event when it wants to keep monitoring for new occurrences. It is worth noting that the ADC input pins can be also configured as general purpose outputs. The pin mode should be configured using pincmux driver. Signed-off-by: Matti Vaittinen --- Regarding disabling the event upon reception - is this totally strange? Is regular userspace compeletely unprepared for this, and better prepared for handling large amounts of continuous events? The BD79124 should not cause a total CPU-blocking IRQ storm because the driver uses the autonomous sequencer mode - which has minimum of 0.75 millisecond delay between measurements. So, new IRQs can be raised with this interval. (The 0.75 mS includes handling and acking / status reading delays - so there is still not much time for things done outside of the IRQ handling...) --- drivers/iio/adc/Kconfig | 10 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/rohm-bd79124-adc.c | 890 +++++++++++++++++++++++++++++ 3 files changed, 901 insertions(+) create mode 100644 drivers/iio/adc/rohm-bd79124-adc.c diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 849c90203071..195a61ba5cf4 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1188,6 +1188,16 @@ config RN5T618_ADC This driver can also be built as a module. If so, the module will be called rn5t618-adc. +config ROHM_BD79124 + tristate "Rohm BD79124 ADC driver" + depends on MFD_ROHM_BD79124 + help + Say yes here to build support for the ROHM BD79124 ADC. The + ROHM BD79124 is a 12-bit, 8-channel, SAR ADC. The ADC supports + also an automatic measurement mode, with an alarm interrupt for + out-of-window measurements. The window is configurable for each + channel. + config ROCKCHIP_SARADC tristate "Rockchip SARADC driver" depends on ARCH_ROCKCHIP || COMPILE_TEST diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index ee19afba62b7..7049d984682d 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -107,6 +107,7 @@ obj-$(CONFIG_QCOM_VADC_COMMON) += qcom-vadc-common.o obj-$(CONFIG_RCAR_GYRO_ADC) += rcar-gyroadc.o obj-$(CONFIG_RICHTEK_RTQ6056) += rtq6056.o obj-$(CONFIG_RN5T618_ADC) += rn5t618-adc.o +obj-$(CONFIG_ROHM_BD79124) += rohm-bd79124-adc.o obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o obj-$(CONFIG_RZG2L_ADC) += rzg2l_adc.o obj-$(CONFIG_SC27XX_ADC) += sc27xx_adc.o diff --git a/drivers/iio/adc/rohm-bd79124-adc.c b/drivers/iio/adc/rohm-bd79124-adc.c new file mode 100644 index 000000000000..7c95a1de1e71 --- /dev/null +++ b/drivers/iio/adc/rohm-bd79124-adc.c @@ -0,0 +1,890 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * ROHM ADC driver for BD79124 ADC/GPO device + * https://fscdn.rohm.com/en/products/databook/datasheet/ic/data_converter/dac/bd79124muf-c-e.pdf + * + * Copyright (c) 2025, ROHM Semiconductor. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define BD79124_ADC_BITS 12 +#define BD79124_MASK_CONV_MODE GENMASK(6, 5) +#define BD79124_MASK_AUTO_INTERVAL GENMASK(1, 0) +#define BD79124_CONV_MODE_MANSEQ 0 +#define BD79124_CONV_MODE_AUTO 1 +#define BD79124_INTERVAL_075 0 +#define BD79124_INTERVAL_150 1 +#define BD79124_INTERVAL_300 2 +#define BD79124_INTERVAL_600 3 + +#define BD79124_MASK_DWC_EN BIT(4) +#define BD79124_MASK_STATS_EN BIT(5) +#define BD79124_MASK_SEQ_START BIT(4) +#define BD79124_MASK_SEQ_MODE GENMASK(1, 0) +#define BD79124_MASK_SEQ_MANUAL 0 +#define BD79124_MASK_SEQ_SEQ 1 + +#define BD79124_MASK_HYSTERESIS GENMASK(3, 0) +#define BD79124_LOW_LIMIT_MIN 0 +#define BD79124_HIGH_LIMIT_MAX GENMASK(11, 0) + +/* + * The high limit, low limit and last measurement result are each stored in + * 2 consequtive registers. 4 bits are in the high bits of the 1.st register + * and 8 bits in the next register. + * + * These macros return the address of the 1.st reg for the given channel + */ +#define BD79124_GET_HIGH_LIMIT_REG(ch) (BD79124_REG_HYSTERESIS_CH0 + (ch) * 4) +#define BD79124_GET_LOW_LIMIT_REG(ch) (BD79124_REG_EVENTCOUNT_CH0 + (ch) * 4) +#define BD79124_GET_RECENT_RES_REG(ch) (BD79124_REG_RECENT_CH0_LSB + (ch) * 2) + +/* + * The hysteresis for a channel is stored in the same register where the + * 4 bits of high limit reside. + */ +#define BD79124_GET_HYSTERESIS_REG(ch) BD79124_GET_HIGH_LIMIT_REG(ch) + +enum { + BD79124_CH_0, + BD79124_CH_1, + BD79124_CH_2, + BD79124_CH_3, + BD79124_CH_4, + BD79124_CH_5, + BD79124_CH_6, + BD79124_CH_7, + BD79124_MAX_NUM_CHANNELS +}; + +struct bd79124_data { + s64 timestamp; + struct regmap *map; + struct device *dev; + int vmax; + int alarm_monitored[BD79124_MAX_NUM_CHANNELS]; + /* + * The BD79124 is configured to run the measurements in the background. + * This is done for the event monitoring as well as for the read_raw(). + * Protect the measurement starting/stopping using a mutex. + */ + struct mutex mutex; +}; + +struct bd79124_raw { + u8 bit0_3; /* Is set in high bits of the byte */ + u8 bit4_11; +}; +#define BD79124_RAW_TO_INT(r) ((r.bit4_11 << 4) | (r.bit0_3 >> 4)) + +/* + * The high and low limits as well as the recent result values are stored in + * the same way in 2 consequent registers. The first register contains 4 bits + * of the value. These bits are stored in the high bits [7:4] of register, but + * they represent the low bits [3:0] of the value. + * The value bits [11:4] are stored in the next register. + * + * Read data from register and convert to integer. + */ +static int bd79124_read_reg_to_int(struct bd79124_data *d, int reg, + unsigned int *val) +{ + int ret; + struct bd79124_raw raw; + + ret = regmap_bulk_read(d->map, reg, &raw, sizeof(raw)); + if (ret) + dev_dbg(d->dev, "bulk_read failed %d\n", ret); + *val = BD79124_RAW_TO_INT(raw); + + return ret; +} + +/* + * The high and low limits as well as the recent result values are stored in + * the same way in 2 consequent registers. The first register contains 4 bits + * of the value. These bits are stored in the high bits [7:4] of register, but + * they represent the low bits [3:0] of the value. + * The value bits [11:4] are stored in the next regoster. + * + * Conver the integer to register format and write it using rmw cycle. + */ +static int bd79124_write_int_to_reg(struct bd79124_data *d, int reg, + unsigned int val) +{ + struct bd79124_raw raw; + int ret, tmp; + + raw.bit4_11 = (u8)(val >> 4); + raw.bit0_3 = (u8)(val << 4); + + ret = regmap_read(d->map, reg, &tmp); + if (ret) + return ret; + + raw.bit0_3 |= (0xf & tmp); + + return regmap_bulk_write(d->map, reg, &raw, sizeof(raw)); +} + +static const struct iio_event_spec bd79124_events[] = { + { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_RISING, + .mask_separate = BIT(IIO_EV_INFO_VALUE) | + BIT(IIO_EV_INFO_ENABLE), + }, + { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_FALLING, + .mask_separate = BIT(IIO_EV_INFO_VALUE) | + BIT(IIO_EV_INFO_ENABLE), + }, + { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_EITHER, + .mask_separate = BIT(IIO_EV_INFO_HYSTERESIS), + }, +}; + +#define BD79124_CHAN(idx) { \ + .type = IIO_VOLTAGE, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ + .indexed = 1, \ + .channel = idx, \ +} + +#define BD79124_CHAN_EV(idx) { \ + .type = IIO_VOLTAGE, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ + .indexed = 1, \ + .channel = idx, \ + .event_spec = bd79124_events, \ + .num_event_specs = ARRAY_SIZE(bd79124_events), \ +} + +static const struct iio_chan_spec bd79124_channels[] = { + BD79124_CHAN_EV(0), + BD79124_CHAN_EV(1), + BD79124_CHAN_EV(2), + BD79124_CHAN_EV(3), + BD79124_CHAN_EV(4), + BD79124_CHAN_EV(5), + BD79124_CHAN_EV(6), + BD79124_CHAN_EV(7), +}; + +static const struct iio_chan_spec bd79124_channels_noirq[] = { + BD79124_CHAN(0), + BD79124_CHAN(1), + BD79124_CHAN(2), + BD79124_CHAN(3), + BD79124_CHAN(4), + BD79124_CHAN(5), + BD79124_CHAN(6), + BD79124_CHAN(7), +}; + +/* + * The BD79124 supports muxing the pins as ADC inputs or as a general purpose + * output. This muxing is handled by a pinmux driver. Here we just check the + * settings from the register, and disallow using the pin if pinmux is set to + * GPO. + * + * NOTE: This driver does not perform any locking to ensure the pinmux stays + * toggled to ADC for the duration of the whatever operation is being done. + * It is responsibility of the user to configure the pinmux. + */ +static bool bd79124_chan_is_adc(struct bd79124_data *d, unsigned int offset) +{ + int ret, val; + + ret = regmap_read(d->map, BD79124_REG_PINCFG, &val); + /* If read fails, don't allow using as AIN (to be on a safe side) */ + if (ret) + return 0; + + return !(val & BIT(offset)); +} + +static int bd79124_read_event_value(struct iio_dev *idev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, int *val, + int *val2) +{ + struct bd79124_data *d = iio_priv(idev); + int ret, reg; + + if (chan->channel >= BD79124_MAX_NUM_CHANNELS) + return -EINVAL; + + /* ensure pinmux is set to ADC */ + if (!bd79124_chan_is_adc(d, chan->channel)) + return -EBUSY; + + switch (info) { + case IIO_EV_INFO_VALUE: + if (dir == IIO_EV_DIR_RISING) + reg = BD79124_GET_HIGH_LIMIT_REG(chan->channel); + else if (dir == IIO_EV_DIR_FALLING) + reg = BD79124_GET_LOW_LIMIT_REG(chan->channel); + else + return -EINVAL; + + ret = bd79124_read_reg_to_int(d, reg, val); + if (ret) + return ret; + + return IIO_VAL_INT; + + case IIO_EV_INFO_HYSTERESIS: + reg = BD79124_GET_HYSTERESIS_REG(chan->channel); + ret = regmap_read(d->map, reg, val); + if (ret) + return ret; + /* Mask the non hysteresis bits */ + *val &= BD79124_MASK_HYSTERESIS; + /* + * The data-sheet says the hysteresis register value needs to be + * sifted left by 3 (or multiplied by 8, depending on the + * page :] ) + */ + *val <<= 3; + + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int bd79124_start_measurement(struct bd79124_data *d, int chan) +{ + int val, ret, regval; + + /* ensure pinmux is set to ADC */ + if (!bd79124_chan_is_adc(d, chan)) + return -EBUSY; + + /* See if already started */ + ret = regmap_read(d->map, BD79124_REG_AUTO_CHANNELS, &val); + if (val & BIT(chan)) + return 0; + + /* Stop the sequencer */ + ret = regmap_clear_bits(d->map, BD79124_REG_SEQUENCE_CFG, + BD79124_MASK_SEQ_START); + if (ret) + return ret; + + /* Add the channel to measured channels */ + ret = regmap_write(d->map, BD79124_REG_AUTO_CHANNELS, val | BIT(chan)); + if (ret) + return ret; + + /* Restart the sequencer */ + ret = regmap_set_bits(d->map, BD79124_REG_SEQUENCE_CFG, + BD79124_MASK_SEQ_START); + if (ret) + return ret; + + /* + * Start the measurement at the background. Don't bother checking if + * it was started, regmap has cache + */ + regval = FIELD_PREP(BD79124_MASK_CONV_MODE, BD79124_CONV_MODE_AUTO); + + return regmap_update_bits(d->map, BD79124_REG_OPMODE_CFG, + BD79124_MASK_CONV_MODE, regval); +} + +static int bd79124_stop_measurement(struct bd79124_data *d, int chan) +{ + int val, ret; + + /* Ensure pinmux is set to ADC */ + if (!bd79124_chan_is_adc(d, chan)) + return -EBUSY; + + /* If alarm is requested for the channel we won't stop measurement */ + if (d->alarm_monitored[chan]) + return 0; + + /* See if already stopped */ + ret = regmap_read(d->map, BD79124_REG_AUTO_CHANNELS, &val); + if (!(val & BIT(chan))) + return 0; + + /* Stop the sequencer */ + ret = regmap_clear_bits(d->map, BD79124_REG_SEQUENCE_CFG, + BD79124_MASK_SEQ_START); + + /* Clear the channel from the measured channels */ + ret = regmap_write(d->map, BD79124_REG_AUTO_CHANNELS, + (~BIT(chan)) & val); + if (ret) + return ret; + + /* Stop background conversion if it was the last channel */ + if (!((~BIT(chan)) & val)) { + int regval = FIELD_PREP(BD79124_MASK_CONV_MODE, + BD79124_CONV_MODE_MANSEQ); + + ret = regmap_update_bits(d->map, BD79124_REG_OPMODE_CFG, + BD79124_MASK_CONV_MODE, regval); + if (ret) + return ret; + } + + /* Restart the sequencer */ + return regmap_set_bits(d->map, BD79124_REG_SEQUENCE_CFG, + BD79124_MASK_SEQ_START); +} + +static int bd79124_read_event_config(struct iio_dev *idev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir) +{ + struct bd79124_data *d = iio_priv(idev); + int val, ret, reg, disabled; + + if (chan->channel >= BD79124_MAX_NUM_CHANNELS) + return -EINVAL; + + /* ensure pinmux is set to ADC */ + if (!bd79124_chan_is_adc(d, chan->channel)) + return -EBUSY; + + ret = regmap_read(d->map, BD79124_REG_ALERT_CH_SEL, &val); + if (ret) + return ret; + + /* The event is disabled if alerts for the channel are disabled */ + if (!(val & BIT(chan->channel))) + return 0; + + /* + * If alerts are on, then the event may be disabled if limit is set to + * the one extreme. (HW does not support disabling rising/falling + * thresholds independently. Hence we resort to setting high limit to + * MAX, or low limit to 0 to try effectively disable thresholds). + */ + if (dir == IIO_EV_DIR_RISING) { + reg = BD79124_GET_HIGH_LIMIT_REG(chan->channel); + disabled = BD79124_HIGH_LIMIT_MAX; + } else if (dir == IIO_EV_DIR_FALLING) { + reg = BD79124_GET_LOW_LIMIT_REG(chan->channel); + disabled = BD79124_LOW_LIMIT_MIN; + } else { + return -EINVAL; + } + ret = bd79124_read_reg_to_int(d, reg, &val); + if (ret) + return ret; + + return val != disabled; +} + +static int bd79124_disable_event(struct bd79124_data *d, + enum iio_event_direction dir, int channel) +{ + int dir_bit = BIT(dir), reg; + unsigned int limit; + + d->alarm_monitored[channel] &= (~dir_bit); + /* + * Set thresholds either to 0 or to 2^12 - 1 as appropriate to prevent + * alerts and thus disable event generation. + */ + if (dir == IIO_EV_DIR_RISING) { + reg = BD79124_GET_HIGH_LIMIT_REG(channel); + limit = BD79124_HIGH_LIMIT_MAX; + } else if (dir == IIO_EV_DIR_FALLING) { + reg = BD79124_GET_LOW_LIMIT_REG(channel); + limit = BD79124_LOW_LIMIT_MIN; + } else { + return -EINVAL; + } + + /* + * Stop measurement if there is no more events to monitor. + * We don't bother checking the retval because the limit + * setting should in any case effectively disable the alarm. + */ + if (!d->alarm_monitored[channel]) { + bd79124_stop_measurement(d, channel); + regmap_clear_bits(d->map, BD79124_REG_ALERT_CH_SEL, + BIT(channel)); + } + + return bd79124_write_int_to_reg(d, reg, limit); +} + +/* Do we need to disable the measurement for the duration of the limit conf ? */ +static int bd79124_write_event_config(struct iio_dev *idev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, bool state) +{ + struct bd79124_data *d = iio_priv(idev); + int dir_bit = BIT(dir); + + guard(mutex)(&d->mutex); + + if (chan->channel >= BD79124_MAX_NUM_CHANNELS) + return -EINVAL; + + /* ensure pinmux is set to ADC */ + if (!bd79124_chan_is_adc(d, chan->channel)) + return -EBUSY; + + if (state) { + int ret; + + /* Set channel to be measured */ + ret = bd79124_start_measurement(d, chan->channel); + if (ret) + return ret; + + d->alarm_monitored[chan->channel] |= dir_bit; + + /* Add the channel to the list of monitored channels */ + ret = regmap_set_bits(d->map, BD79124_REG_ALERT_CH_SEL, + BIT(chan->channel)); + if (ret) + return ret; + + /* + * Enable comparator. Trust the regmap cache, no need to check + * if it was already enabled. + * + * We could do this in the hw-init, but there may be users who + * never enable alarms and for them it makes sense to not + * enable the comparator at probe. + */ + return regmap_set_bits(d->map, BD79124_REG_GEN_CFG, + BD79124_MASK_DWC_EN); + } + + return bd79124_disable_event(d, dir, chan->channel); +} + +static int bd79124_write_event_value(struct iio_dev *idev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, int val, + int val2) +{ + struct bd79124_data *d = iio_priv(idev); + int reg; + + if (chan->channel >= BD79124_MAX_NUM_CHANNELS) + return -EINVAL; + + /* ensure pinmux is set to ADC */ + if (!bd79124_chan_is_adc(d, chan->channel)) + return -EBUSY; + + switch (info) { + case IIO_EV_INFO_VALUE: + if (dir == IIO_EV_DIR_RISING) + reg = BD79124_GET_HIGH_LIMIT_REG(chan->channel); + else if (dir == IIO_EV_DIR_FALLING) + reg = BD79124_GET_LOW_LIMIT_REG(chan->channel); + else + return -EINVAL; + + return bd79124_write_int_to_reg(d, reg, val); + + case IIO_EV_INFO_HYSTERESIS: + reg = BD79124_GET_HYSTERESIS_REG(chan->channel); + val >>= 3; + + return regmap_update_bits(d->map, reg, BD79124_MASK_HYSTERESIS, + val); + default: + return -EINVAL; + } +} + +static int bd79124_read_last_result(struct bd79124_data *d, int chan, + int *result) +{ + struct bd79124_raw raw; + int ret; + + ret = regmap_bulk_read(d->map, BD79124_GET_RECENT_RES_REG(chan), &raw, + sizeof(raw)); + if (ret) + return ret; + + *result = BD79124_RAW_TO_INT(raw); + + return 0; +} + +static int bd79124_single_chan_seq(struct bd79124_data *d, int chan, int *old) +{ + int ret; + + /* Stop the sequencer */ + ret = regmap_clear_bits(d->map, BD79124_REG_SEQUENCE_CFG, + BD79124_MASK_SEQ_START); + if (ret) + return ret; + + /* + * It may be we have some channels monitored for alarms so we want to + * cache the old config and return it when the single channel + * measurement has been completed. Read the old config. + */ + ret = regmap_read(d->map, BD79124_REG_AUTO_CHANNELS, old); + if (ret) + return ret; + + ret = regmap_write(d->map, BD79124_REG_AUTO_CHANNELS, BIT(chan)); + if (ret) + return ret; + + /* Restart the sequencer */ + return regmap_set_bits(d->map, BD79124_REG_SEQUENCE_CFG, + BD79124_MASK_SEQ_START); +} + +static int bd79124_single_chan_seq_end(struct bd79124_data *d, int old) +{ + int ret; + + /* Stop the sequencer */ + ret = regmap_clear_bits(d->map, BD79124_REG_SEQUENCE_CFG, + BD79124_MASK_SEQ_START); + if (ret) + return ret; + + ret = regmap_write(d->map, BD79124_REG_AUTO_CHANNELS, old); + if (ret) + return ret; + + /* Restart the sequencer */ + return regmap_set_bits(d->map, BD79124_REG_SEQUENCE_CFG, + BD79124_MASK_SEQ_START); +} + +static int bd79124_read_raw(struct iio_dev *idev, + struct iio_chan_spec const *chan, + int *val, int *val2, long m) +{ + struct bd79124_data *d = iio_priv(idev); + int ret; + + if (chan->channel >= BD79124_MAX_NUM_CHANNELS) + return -EINVAL; + + switch (m) { + case IIO_CHAN_INFO_RAW: + { + int old_chan_cfg, tmp; + int regval = FIELD_PREP(BD79124_MASK_CONV_MODE, + BD79124_CONV_MODE_AUTO); + + guard(mutex)(&d->mutex); + + /* ensure pinmux is set to ADC */ + if (!bd79124_chan_is_adc(d, chan->channel)) + return -EBUSY; + + /* + * Start the automatic conversion. This is needed here if no + * events have been enabled. + */ + ret = regmap_update_bits(d->map, BD79124_REG_OPMODE_CFG, + BD79124_MASK_CONV_MODE, regval); + if (ret) + return ret; + + ret = bd79124_single_chan_seq(d, chan->channel, &old_chan_cfg); + if (ret) + return ret; + + /* + * The maximum conversion time is 6 uS. Ensure the sample is + * ready + */ + udelay(6); + + ret = bd79124_read_last_result(d, chan->channel, val); + /* Try unconditionally returning the chan config */ + tmp = bd79124_single_chan_seq_end(d, old_chan_cfg); + if (tmp) + dev_err(d->dev, + "Failed to return config. Alarms may be disabled\n"); + + if (ret) + return ret; + + return IIO_VAL_INT; + } + case IIO_CHAN_INFO_SCALE: + *val = d->vmax / 1000; + *val2 = BD79124_ADC_BITS; + return IIO_VAL_FRACTIONAL_LOG2; + default: + return -EINVAL; + } +} + +static const struct iio_info bd79124_info = { + .read_raw = bd79124_read_raw, + .read_event_config = &bd79124_read_event_config, + .write_event_config = &bd79124_write_event_config, + .read_event_value = &bd79124_read_event_value, + .write_event_value = &bd79124_write_event_value, +}; + +static irqreturn_t bd79124_event_handler(int irq, void *priv) +{ + int ret, i_hi, i_lo, i; + struct iio_dev *idev = priv; + struct bd79124_data *d = iio_priv(idev); + + /* + * Return IRQ_NONE if bailing-out without acking. This allows the IRQ + * subsystem to disable the offending IRQ line if we get a hardware + * problem. This behaviour has saved my poor bottom a few times in the + * past as, instead of getting unusably unresponsive, the system has + * spilled out the magic words "...nobody cared". + */ + ret = regmap_read(d->map, BD79124_REG_EVENT_FLAG_HI, &i_hi); + if (ret) + return IRQ_NONE; + + ret = regmap_read(d->map, BD79124_REG_EVENT_FLAG_LO, &i_lo); + if (ret) + return IRQ_NONE; + + if (!i_lo && !i_hi) + return IRQ_NONE; + + for (i = 0; i < BD79124_MAX_NUM_CHANNELS; i++) { + u64 ecode; + + if (BIT(i) & i_hi) { + ecode = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, i, + IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING); + + iio_push_event(idev, ecode, d->timestamp); + /* + * The BD79124 keeps the IRQ asserted for as long as + * the voltage exceeds the threshold. It may not serve + * the purpose to keep the IRQ firing and events + * generated in a loop because it may yield the + * userspace to have some problems when event handling + * there is slow. + * + * Thus, we disable the event for the channel. Userspace + * needs to re-enable the event. + * + * We don't check the result as there is not much to do. + * Also, this should not lead to total IRQ storm + * because the BD79124 is running in autonomous mode, + * which means there is by minimum 0.75 mS idle time + * between changing the channels. That should be + * sufficient to show some life on system, even if the + * event handling couldn't keep up. + */ + bd79124_disable_event(d, IIO_EV_DIR_RISING, i); + } + if (BIT(i) & i_lo) { + ecode = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, i, + IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING); + + iio_push_event(idev, ecode, d->timestamp); + } + } + + ret = regmap_write(d->map, BD79124_REG_EVENT_FLAG_HI, i_hi); + if (ret) + return IRQ_NONE; + + ret = regmap_write(d->map, BD79124_REG_EVENT_FLAG_LO, i_lo); + if (ret) + return IRQ_NONE; + + return IRQ_HANDLED; +} + +static irqreturn_t bd79124_irq_handler(int irq, void *priv) +{ + struct iio_dev *idev = priv; + struct bd79124_data *d = iio_priv(idev); + + d->timestamp = iio_get_time_ns(idev); + + return IRQ_WAKE_THREAD; +} + +static int bd79124_hw_init(struct bd79124_data *d) +{ + int ret, regval; + + /* Stop auto sequencer */ + ret = regmap_clear_bits(d->map, BD79124_REG_SEQUENCE_CFG, + BD79124_MASK_SEQ_START); + if (ret) + return ret; + + /* Enable writing the measured values to the regsters */ + ret = regmap_set_bits(d->map, BD79124_REG_GEN_CFG, + BD79124_MASK_STATS_EN); + if (ret) + return ret; + + /* Set no channels to be auto-measured */ + ret = regmap_write(d->map, BD79124_REG_AUTO_CHANNELS, 0x0); + if (ret) + return ret; + + /* Set no channels to be manually measured */ + ret = regmap_write(d->map, BD79124_REG_MANUAL_CHANNELS, 0x0); + if (ret) + return ret; + + /* Set the measurement interval to 0.75 mS */ + + regval = FIELD_PREP(BD79124_MASK_AUTO_INTERVAL, BD79124_INTERVAL_075); + ret = regmap_update_bits(d->map, BD79124_REG_OPMODE_CFG, + BD79124_MASK_AUTO_INTERVAL, regval); + if (ret) + return ret; + + /* Sequencer mode to auto */ + ret = regmap_set_bits(d->map, BD79124_REG_SEQUENCE_CFG, + BD79124_MASK_SEQ_SEQ); + if (ret) + return ret; + + regval = FIELD_PREP(BD79124_MASK_CONV_MODE, BD79124_CONV_MODE_MANSEQ); + /* Don't start the measurement */ + return regmap_update_bits(d->map, BD79124_REG_OPMODE_CFG, + BD79124_MASK_CONV_MODE, BD79124_CONV_MODE_MANSEQ); + +} + +#define BD79124_VDD_MAX 5250000 +#define BD79124_VDD_MIN 2700000 + +static int bd79124_probe(struct platform_device *pdev) +{ + struct bd79124_data *d; + struct iio_dev *idev; + int ret, irq, *parent_data; + + idev = devm_iio_device_alloc(&pdev->dev, sizeof(*d)); + if (!idev) + return -ENOMEM; + + d = iio_priv(idev); + + parent_data = dev_get_drvdata(pdev->dev.parent); + if (!parent_data) + return dev_err_probe(&pdev->dev, -EINVAL, + "reference voltage missing\n"); + + /* + * Recommended VDD voltage from the data-sheet: + * Analog/Digital Supply Voltage VDD 2.70 - 5.25 V + */ + d->vmax = *parent_data; + if (d->vmax < BD79124_VDD_MIN || d->vmax > BD79124_VDD_MAX) { + return dev_err_probe(d->dev, -EINVAL, + "VDD (%d) out of range [%d - %d]\n", + d->vmax, BD79124_VDD_MIN, BD79124_VDD_MAX); + + return -EINVAL; + } + + irq = platform_get_irq_byname_optional(pdev, "thresh-alert"); + if (irq < 0) { + if (irq == -EPROBE_DEFER) + return irq; + + idev->channels = &bd79124_channels_noirq[0]; + idev->num_channels = ARRAY_SIZE(bd79124_channels_noirq); + dev_dbg(d->dev, "No IRQ found, events disabled\n"); + } else { + idev->channels = &bd79124_channels[0]; + idev->num_channels = ARRAY_SIZE(bd79124_channels); + } + + idev->info = &bd79124_info; + idev->name = "bd79124"; + idev->modes = INDIO_DIRECT_MODE; + + d->dev = &pdev->dev; + d->map = dev_get_regmap(d->dev->parent, NULL); + if (!d->map) + return dev_err_probe(d->dev, -ENODEV, "No regmap\n"); + + mutex_init(&d->mutex); + + ret = bd79124_hw_init(d); + if (ret) + return ret; + + if (irq > 0) { + ret = devm_request_threaded_irq(d->dev, irq, bd79124_irq_handler, + &bd79124_event_handler, IRQF_ONESHOT, + "adc-thresh-alert", idev); + if (ret) + return dev_err_probe(d->dev, ret, + "Failed to register IRQ\n"); + } + + return devm_iio_device_register(d->dev, idev); +} + +static const struct platform_device_id bd79124_adc_id[] = { + { "bd79124-adc", }, + { } +}; +MODULE_DEVICE_TABLE(platform, bd79124_adc_id); + +static struct platform_driver bd79124_driver = { + .driver = { + .name = "bd79124-adc", + /* + * Probing explicitly requires a few millisecond of sleep. + * Enabling the VDD regulator may include ramp up rates. + */ + .probe_type = PROBE_PREFER_ASYNCHRONOUS, + }, + .probe = bd79124_probe, + .id_table = bd79124_adc_id, +}; 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[85.23.190.22]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-543ebdf1046sm479993e87.10.2025.01.31.05.38.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Jan 2025 05:38:24 -0800 (PST) Date: Fri, 31 Jan 2025 15:38:15 +0200 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Cameron , Lars-Peter Clausen , Matti Vaittinen , Linus Walleij , Nuno Sa , David Lechner , Dumitru Ceclan , Trevor Gamblin , Matteo Martelli , AngeloGioacchino Del Regno , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [RFC PATCH 4/5] pinctrl: Support ROHM BD79124 pinmux / GPO Message-ID: <3d85fe979fca352bed4d9841e3233c055dfaf154.1738328714.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: The ROHM BD79124 is a 12-bit, 8-channel, SAR ADC. The AIN pins can be used as ADC inputs, or as general purpose outputs. Support changing pin function (GPO / ADC) and the gpo output control. Signed-off-by: Matti Vaittinen --- NOTE: This patch is not properly tested. More thorough testing is to be done prior v2 if this pinmux approach makes sense. drivers/pinctrl/Kconfig | 11 ++ drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-bd79124.c | 276 ++++++++++++++++++++++++++++++ 3 files changed, 288 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-bd79124.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 95a8e2b9a614..7dd9bb0d1ab4 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -145,6 +145,17 @@ config PINCTRL_AW9523 Say yes to enable pinctrl and GPIO support for the AW9523(B). +config PINCTRL_BD79124 + tristate "Rohm BD79124 ADC/GPO" + depends on MFD_ROHM_BD79124 + select PINMUX + select GPIOLIB + help + The Rohm BD79124 is a 12-bit, 8-channel, SAR ADC. The analog input + pins can also be configured to be used as general purpose outputs. + + Say yes to enable the pinmux and GPOs. + config PINCTRL_BM1880 bool "Bitmain BM1880 Pinctrl driver" depends on OF && (ARCH_BITMAIN || COMPILE_TEST) diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index fba1c56624c0..0caf6dc3d2c1 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o obj-$(CONFIG_PINCTRL_AW9523) += pinctrl-aw9523.o obj-$(CONFIG_PINCTRL_AXP209) += pinctrl-axp209.o obj-$(CONFIG_PINCTRL_BM1880) += pinctrl-bm1880.o +obj-$(CONFIG_PINCTRL_BD79124) += pinctrl-bd79124.o obj-$(CONFIG_PINCTRL_CY8C95X0) += pinctrl-cy8c95x0.o obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o obj-$(CONFIG_PINCTRL_DA9062) += pinctrl-da9062.o diff --git a/drivers/pinctrl/pinctrl-bd79124.c b/drivers/pinctrl/pinctrl-bd79124.c new file mode 100644 index 000000000000..8d25b1c5345f --- /dev/null +++ b/drivers/pinctrl/pinctrl-bd79124.c @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * ROHM BD79124 ADC / GPO pinmux. + * + * Copyright (c) 2025, ROHM Semiconductor. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include "pinctrl-utils.h" + +/* + * The driver expects pins top have 1 to 1 mapping to the groups. + * Eg, pin 'ID 0' is AIN0, and can be directly mapped to the group "ain0", which + * also uses group ID 0. The driver mix and match the pin and group IDs. This + * works because we don't have any specific multi-pin groups. If I knew typical + * use cases better I might've been able to create some funtionally meaningful + * groups - but as I don't, I just decided to create per-pin groups for toggling + * and individual pin to ADC-input or GPO mode. I believe this gives the + * flexibility for generic use-cases. + * + * If this is a false assumption and special groups are needed, then the pin <=> + * group mapping in this driver must be reworked. Meanwhile just keep the pin + * and group IDs matching! + */ +static const struct pinctrl_pin_desc bd79124_pins[] = { + PINCTRL_PIN(0, "ain0"), + PINCTRL_PIN(1, "ain1"), + PINCTRL_PIN(2, "ain2"), + PINCTRL_PIN(3, "ain3"), + PINCTRL_PIN(4, "ain4"), + PINCTRL_PIN(5, "ain5"), + PINCTRL_PIN(6, "ain6"), + PINCTRL_PIN(7, "ain7"), +}; + +static const char * const bd79124_pin_groups[] = { + "ain0", + "ain1", + "ain2", + "ain3", + "ain4", + "ain5", + "ain6", + "ain7", +}; + +static int bd79124_get_groups_count(struct pinctrl_dev *pcdev) +{ + return ARRAY_SIZE(bd79124_pin_groups); +} + +static const char *bd79124_get_group_name(struct pinctrl_dev *pctldev, + unsigned int group) +{ + return bd79124_pin_groups[group]; +} + +enum { + BD79124_FUNC_GPO, + BD79124_FUNC_ADC, + BD79124_FUNC_AMOUNT +}; + +static const char * const bd79124_functions[BD79124_FUNC_AMOUNT] = { + [BD79124_FUNC_GPO] = "gpo", + [BD79124_FUNC_ADC] = "adc", +}; + +struct bd79124_mux_data { + struct device *dev; + struct regmap *map; + struct pinctrl_dev *pcdev; + struct gpio_chip gc; +}; + +static int bd79124_pmx_get_functions_count(struct pinctrl_dev *pcdev) +{ + return BD79124_FUNC_AMOUNT; +} + +static const char *bd79124_pmx_get_function_name(struct pinctrl_dev *pcdev, + unsigned int selector) +{ + return bd79124_functions[selector]; +} + +static int bd79124_pmx_get_function_groups(struct pinctrl_dev *pcdev, + unsigned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + *groups = &bd79124_pin_groups[0]; + *num_groups = ARRAY_SIZE(bd79124_pin_groups); + + return 0; +} + +static int bd79124_pmx_set(struct pinctrl_dev *pcdev, unsigned int func, + unsigned int group) +{ + struct bd79124_mux_data *d = pinctrl_dev_get_drvdata(pcdev); + + /* We use 1 to 1 mapping for grp <=> pin */ + if (func == BD79124_FUNC_GPO) + return regmap_set_bits(d->map, BD79124_REG_PINCFG, BIT(group)); + + return regmap_clear_bits(d->map, BD79124_REG_PINCFG, BIT(group)); +} + +/* + * Check that the pinmux has set this pin as GPO before allowing it to be used. + * NOTE: There is no locking in the pinctrl driver to ensure the pin _stays_ + * appropriately muxed. It is the responsibility of the device using this GPO + * (or ADC) to reserve the pin from the pinmux. + */ +static bool bd79124_is_gpo(struct bd79124_mux_data *d, unsigned int offset) +{ + int ret, val; + + ret = regmap_read(d->map, BD79124_REG_PINCFG, &val); + /* + * If read fails, don't allow setting GPO value as we don't know if + * pin is used as AIN. (In which case we might upset the device being + * measured - although I suppose the BD79124 would ignore the set value + * if pin is used as AIN - but better safe than sorry, right? + */ + if (ret) + return 0; + + return (val & BIT(offset)); +} + +static int bd79124gpo_direction_get(struct gpio_chip *gc, unsigned int offset) +{ + struct bd79124_mux_data *d = gpiochip_get_data(gc); + + if (!bd79124_is_gpo(d, offset)) + return -EINVAL; + + return GPIO_LINE_DIRECTION_OUT; +} + +static void bd79124gpo_set(struct gpio_chip *gc, unsigned int offset, int value) +{ + struct bd79124_mux_data *d = gpiochip_get_data(gc); + + if (!bd79124_is_gpo(d, offset)) { + dev_dbg(d->dev, "Bad GPO mux mode\n"); + return; + } + + if (value) + regmap_set_bits(d->map, BD79124_REG_GPO_VAL, BIT(offset)); + + regmap_clear_bits(d->map, BD79124_REG_GPO_VAL, BIT(offset)); +} + +static void bd79124gpo_set_multiple(struct gpio_chip *gc, unsigned long *mask, + unsigned long *bits) +{ + int ret, val; + struct bd79124_mux_data *d = gpiochip_get_data(gc); + + /* Ensure all GPIOs in 'mask' are set to be GPIOs */ + ret = regmap_read(d->map, BD79124_REG_PINCFG, &val); + if (ret) + return; + + if ((val & *mask) != *mask) { + dev_dbg(d->dev, "Invalid mux config. Can't set value.\n"); + /* Do not set value for pins configured as ADC inputs */ + *mask &= val; + } + + regmap_update_bits(d->map, BD79124_REG_GPO_VAL, *mask, *bits); +} + +/* Template for GPIO chip */ +static const struct gpio_chip bd79124gpo_chip = { + .label = "bd79124-gpo", + .get_direction = bd79124gpo_direction_get, + .set = bd79124gpo_set, + .set_multiple = bd79124gpo_set_multiple, + .can_sleep = true, + .ngpio = 8, + .base = -1, +}; + +static const struct pinmux_ops bd79124_pmxops = { + .get_functions_count = bd79124_pmx_get_functions_count, + .get_function_name = bd79124_pmx_get_function_name, + .get_function_groups = bd79124_pmx_get_function_groups, + .set_mux = bd79124_pmx_set, +}; + +static const struct pinctrl_ops bd79124_pctlops = { + .get_groups_count = bd79124_get_groups_count, + .get_group_name = bd79124_get_group_name, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinctrl_utils_free_map, +}; + +static const struct pinctrl_desc bd79124_pdesc = { + .name = "bd79124-pinctrl", + .pins = &bd79124_pins[0], + .npins = ARRAY_SIZE(bd79124_pins), + .pmxops = &bd79124_pmxops, + .pctlops = &bd79124_pctlops, +}; + +static int bd79124_probe(struct platform_device *pdev) +{ + struct bd79124_mux_data *d; + int ret; + + d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL); + if (!d) + return -ENOMEM; + + d->dev = &pdev->dev; + d->map = dev_get_regmap(d->dev->parent, NULL); + if (!d->map) + return dev_err_probe(d->dev, -ENODEV, "No regmap\n"); + + d->gc = bd79124gpo_chip; + + ret = devm_pinctrl_register_and_init(d->dev->parent, + (struct pinctrl_desc *)&bd79124_pdesc, d, &d->pcdev); + if (ret) + return dev_err_probe(d->dev, ret, "pincontrol registration failed\n"); + ret = pinctrl_enable(d->pcdev); + if (ret) + return dev_err_probe(d->dev, ret, "pincontrol enabling failed\n"); + + ret = devm_gpiochip_add_data(d->dev, &d->gc, d); + if (ret) + return dev_err_probe(d->dev, ret, "gpio init Failed\n"); + + return 0; +} + +static const struct platform_device_id bd79124_mux_id[] = { + { "bd79124-pinmux", }, + { } +}; +MODULE_DEVICE_TABLE(platform, bd79124_mux_id); + +static struct platform_driver bd79124_mux_driver = { + .driver = { + .name = "bd79124-pinmux", + /* + * Probing explicitly requires a few millisecond of sleep. + * Enabling the VDD regulator may include ramp up rates. + */ + .probe_type = PROBE_PREFER_ASYNCHRONOUS, + }, + .probe = bd79124_probe, + .id_table = bd79124_mux_id, +}; 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[85.23.190.22]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-307a3428055sm5600751fa.98.2025.01.31.05.38.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Jan 2025 05:38:54 -0800 (PST) Date: Fri, 31 Jan 2025 15:38:45 +0200 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Cameron , Lars-Peter Clausen , Matti Vaittinen , Linus Walleij , Nuno Sa , David Lechner , Dumitru Ceclan , Trevor Gamblin , Matteo Martelli , AngeloGioacchino Del Regno , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [RFC PATCH 5/5] MAINTAINERS: Add ROHM BD79124 ADC/GPO Message-ID: <7b767eede329fc9194925817a7350a76786478a5.1738328714.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Add undersigned as a maintainer for the ROHM BD79124 ADC/GPO driver. Signed-off-by: Matti Vaittinen --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a87ddad78e26..19314bee95b2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20292,6 +20292,14 @@ S: Supported F: drivers/power/supply/bd99954-charger.c F: drivers/power/supply/bd99954-charger.h +ROHM BD79124 ADC / GPO IC +M: Matti Vaittinen +S: Supported +F: drivers/iio/adc/rohm-bd79124-adc.c +F: drivers/mfd/rohm-bd79124.c +F: drivers/pinctrl/pinctrl-bd79124.c +F: include/linux/mfd/rohm-bd79124.h + ROHM BH1745 COLOUR SENSOR M: Mudit Sharma L: linux-iio@vger.kernel.org