From patchwork Fri Jan 31 18:29:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13955644 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89E337081F for ; Fri, 31 Jan 2025 18:30:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738348221; cv=none; b=bbEEDwQjNTtdI423LWgFqUs/5D3aNxwsgkCr8Jjr8UzRImdYwssek3Z25O8y6GJ9CL6/dVWPqmgGqxeenMVNON+o5XrWV8gEDWTwOcs0tFdG2bp9e/Dccgl0rtm+0sxmLAao3iL4k9VU9+BmrHLznlIseBB9WrdLeBkPZnHmWl0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738348221; c=relaxed/simple; bh=E0Rq0Qg/tPg5NuSXgKHce8fejwLFHu6o0/X5AcGaq2g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=blzbOH+rygEniIG8alRMBmFNexDl9QP960slU5zGAFG+9skjnz6E5dKcfPM2IiWJbbiu6Ufxf1rs65ZgS/Vk4UouZIa1Wr5sPzv414FknTxRrekN7OatC09UwrJcW/2UkGMCOyJbbc2Djgn3VVHYr6pALwkVEZQyZ9GNd7bVdQs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZOoO1/Ie; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZOoO1/Ie" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D2DACC4CED1; Fri, 31 Jan 2025 18:30:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738348221; bh=E0Rq0Qg/tPg5NuSXgKHce8fejwLFHu6o0/X5AcGaq2g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZOoO1/IeCLaT3T0JopN75kMlYwH4y1w6BBCtp/0avF08AY3L2CKP/sTzxypmaOhRH ZGbnx6sPHd+5w8usUDUw1t9MdPsSl0OoxOnlzQKDWSH4Bl/HUI/S/twHZ/ViX6ZpJw jsMO606mD3cwO2VuvdG4JV72hwS6PkwMycihgSi2YJKr3bgZwg9gXVywBd1ZVA9eqG EIl0EH9FMWEmCsoEex/SvrMqEFCXkvpCTqpEK0SXzRjNVyVGLGuHZjiROWHHGU+6m6 qQAk5g9VZYlDRgwd5pmb5/hSGuNCYZcF4qHRhrTyLJEHBTzs7yBYs8hLFjlP/qzKta hysAs/SuiiQ4g== From: Niklas Cassel To: Manivannan Sadhasivam , =?utf-8?q?Krzy?= =?utf-8?q?sztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas Cc: Damien Le Moal , Siddharth Vadapalli , Udit Kumar , Vignesh Raghavendra , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v4 1/7] PCI: endpoint: Allow EPF drivers to configure the size of Resizable BARs Date: Fri, 31 Jan 2025 19:29:50 +0100 Message-ID: <20250131182949.465530-10-cassel@kernel.org> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250131182949.465530-9-cassel@kernel.org> References: <20250131182949.465530-9-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3672; i=cassel@kernel.org; h=from:subject; bh=E0Rq0Qg/tPg5NuSXgKHce8fejwLFHu6o0/X5AcGaq2g=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLniq1K5b6zPbO5o/0z44ZVCToF56aqOhRyJl/dFNATv rWma19ZRykLgxgXg6yYIovvD5f9xd3uU44r3rGBmcPKBDKEgYtTACbSaM7wv1Rl3qL2rif8nzu6 zMKZcvPWyQTEuC262L99pxtL+quH9Qz/M/fdOvFxdn/951V+n3kvL5C9oLxqYop/oNY3YbsA3v7 1bAA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA A resizable BAR is different from a normal BAR in a few ways: -The minimum size of a resizable BAR is 1 MB. -Each BAR that is resizable has a Capability and Control register in the Resizable BAR Capability structure. These registers contain the supported sizes and the currently selected size of a resizable BAR. The supported sizes is a bitmap of the supported sizes. The selected size is a single value that is equal to one of the supported sizes. A resizable BAR thus has to be configured differently than a BAR_PROGRAMMABLE BAR, which usually sets the BAR size/mask in a vendor specific way. The PCI endpoint framework currently does not support resizable BARs. Add a BAR type BAR_RESIZABLE, so that an EPC driver can support resizable BARs properly. Note that the pci_epc_set_bar() API takes a struct pci_epf_bar which tells the EPC driver how it wants to configure the BAR. struct pci_epf_bar only has a single size struct member. This means that an EPC driver will only be able to set a single supported size. This is perfectly fine, as we do not need the complexity of allowing a host to change the size of the BAR. If someone ever wants to support resizing a resizable BAR, the pci_epc_set_bar() API can be extended in the future. With these changes, we allow an EPF driver to configure the size of Resizable BARs, rather than forcing them to a 1 MB size. Signed-off-by: Niklas Cassel --- drivers/pci/endpoint/pci-epc-core.c | 4 ++++ drivers/pci/endpoint/pci-epf-core.c | 4 ++++ include/linux/pci-epc.h | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 9e9ca5f8e8f8..10dfc716328e 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -609,6 +609,10 @@ int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, if (!epc_features) return -EINVAL; + if (epc_features->bar[bar].type == BAR_RESIZABLE && + (epf_bar->size < SZ_1M || (u64)epf_bar->size > (SZ_128G * 1024))) + return -EINVAL; + if (epc_features->bar[bar].type == BAR_FIXED && (epc_features->bar[bar].fixed_size != epf_bar->size)) return -EINVAL; diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c index 50bc2892a36c..394395c7f8de 100644 --- a/drivers/pci/endpoint/pci-epf-core.c +++ b/drivers/pci/endpoint/pci-epf-core.c @@ -274,6 +274,10 @@ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar, if (size < 128) size = 128; + /* According to PCIe base spec, min size for a resizable BAR is 1 MB. */ + if (epc_features->bar[bar].type == BAR_RESIZABLE && size < SZ_1M) + size = SZ_1M; + if (epc_features->bar[bar].type == BAR_FIXED && bar_fixed_size) { if (size > bar_fixed_size) { dev_err(&epf->dev, diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index e818e3fdcded..91ce39dc0fd4 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -188,11 +188,15 @@ struct pci_epc { * enum pci_epc_bar_type - configurability of endpoint BAR * @BAR_PROGRAMMABLE: The BAR mask can be configured by the EPC. * @BAR_FIXED: The BAR mask is fixed by the hardware. + * @BAR_RESIZABLE: The BAR implements the PCI-SIG Resizable BAR Capability. + * NOTE: An EPC driver can currently only set a single supported + * size. * @BAR_RESERVED: The BAR should not be touched by an EPF driver. */ enum pci_epc_bar_type { BAR_PROGRAMMABLE = 0, BAR_FIXED, + BAR_RESIZABLE, BAR_RESERVED, }; From patchwork Fri Jan 31 18:29:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13955645 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64EE87081F for ; Fri, 31 Jan 2025 18:30:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738348224; cv=none; b=HcTtDyPAKj2TNWTwI1sqmdrLPE0DceSfOAIjTv5IOjk3Unuakc/XtMJdL4W5Nk5B6GwP5hFPwpaV0PsCdkwiqnVmi/wwVfeNCVj5QB9Baq3NQt2oXXv34YaF6tvrGRj0xKGveECwVxURm1D7AhV7V6EWESKBeiDmK/493PstLCc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738348224; c=relaxed/simple; bh=qqKbQsnS1YsboZzTev6G2t0ujPW9WQvQtYPjJ5GZ0zI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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a=openpgp-sha256; l=2290; i=cassel@kernel.org; h=from:subject; bh=qqKbQsnS1YsboZzTev6G2t0ujPW9WQvQtYPjJ5GZ0zI=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLniq06nT0/9NA+MbFHb4IFuPb+aDr1NjZMy0FE9CK/Y KRXgFBLRykLgxgXg6yYIovvD5f9xd3uU44r3rGBmcPKBDKEgYtTACZiq8nwm01o/psMt8/fXjx+ 1RR8ReTD4QbHuWf3nDSc+vHxrMeV1ZMYfrNMZ53W2PaKMyAvc70V26PaVxG/TWzeF7441P3OS/F HBQMA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Add a helper function to convert a size to the representation used by the Resizable BAR Capability Register. Signed-off-by: Niklas Cassel --- drivers/pci/endpoint/pci-epc-core.c | 27 +++++++++++++++++++++++++++ include/linux/pci-epc.h | 1 + 2 files changed, 28 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 10dfc716328e..5d6aef956b13 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -638,6 +638,33 @@ int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, } EXPORT_SYMBOL_GPL(pci_epc_set_bar); +/** + * pci_epc_bar_size_to_rebar_cap() - convert a size to the representation used + * by the Resizable BAR Capability Register + * @size: the size to convert + * @cap: where to store the result + * + * Returns 0 on success and a negative error code in case of error. + */ +int pci_epc_bar_size_to_rebar_cap(size_t size, u32 *cap) +{ + /* + * According to PCIe base spec, min size for a resizable BAR is 1 MB, + * thus disallow a requested BAR size smaller than 1 MB. + * Disallow a requested BAR size larger than 128 TB. + */ + if (size < SZ_1M || (u64)size > (SZ_128G * 1024)) + return -EINVAL; + + *cap = ilog2(size) - ilog2(SZ_1M); + + /* Sizes in REBAR_CAP start at BIT(4). */ + *cap = BIT(*cap + 4); + + return 0; +} +EXPORT_SYMBOL_GPL(pci_epc_bar_size_to_rebar_cap); + /** * pci_epc_write_header() - write standard configuration header * @epc: the EPC device to which the configuration header should be written diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 91ce39dc0fd4..713348322dea 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -275,6 +275,7 @@ void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf, enum pci_epc_interface_type type); int pci_epc_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epf_header *hdr); +int pci_epc_bar_size_to_rebar_cap(size_t size, u32 *cap); int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epf_bar *epf_bar); void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, From patchwork Fri Jan 31 18:29:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13955646 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8484F7081F for ; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="m8PXNaIx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 87DC4C4CED1; Fri, 31 Jan 2025 18:30:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738348227; bh=rO4LIJQIfHIs43mgpVGBJ2DomywdwncmsQISfke15cw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m8PXNaIxHq0ZN+4KdVie3eFIgXDaq9Wo1b8/psvcPrpJmvi9/QKIaMp9BDfozJ+ak y9cc8tYMwIMSIu+GmzHLFwpizfDqWuB1dd23UV13VBLOepbCvSAIz45QSvCTJqyidq l7HCyyjUXGosUkTIeHe8IOr/o6W4i860VyPcP6Vpwt3iWSy89bK5JEBUzXNvXr+wRT Qr034lveoRPCPXjCq5Fh6hDIHMpksVZChrbaihpAmZvfrYrp8ulQntLUdo8NWljX9u NN3CCKGX1HPPMu7jkiWJqH1jYMYRogCesvAqIOn5balep2thB1MsfnKotuD85OzFrL onTZKAH1Xbgyw== From: Niklas Cassel To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Siddharth Vadapalli , Udit Kumar , Vignesh Raghavendra , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v4 3/7] PCI: dwc: ep: Move dw_pcie_ep_find_ext_capability() Date: Fri, 31 Jan 2025 19:29:52 +0100 Message-ID: <20250131182949.465530-12-cassel@kernel.org> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250131182949.465530-9-cassel@kernel.org> References: <20250131182949.465530-9-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1955; i=cassel@kernel.org; h=from:subject; bh=rO4LIJQIfHIs43mgpVGBJ2DomywdwncmsQISfke15cw=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLniq1aaZJ8aD+bSOC/wqilDs/+C0jPX5rKd8Zr0qebH nsm7bUI7ihlYRDjYpAVU2Tx/eGyv7jbfcpxxTs2MHNYmUCGMHBxCsBEtNgYGfak97dxT5GWZt54 b4POHAHPDxF8q+rm8pjfsVh7arpl7W6G/xHfpnoqL7IRfxq7XvLlfI77+pV7o98v/vz+/5GPhqX OsYwA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Move dw_pcie_ep_find_ext_capability() so that it is located next to dw_pcie_ep_find_capability(). Additionally, a follow-up commit requires this to be defined earlier in order to avoid a forward declaration. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Niklas Cassel --- .../pci/controller/dwc/pcie-designware-ep.c | 36 +++++++++---------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 8e07d432e74f..6b494781da42 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -102,6 +102,24 @@ static u8 dw_pcie_ep_find_capability(struct dw_pcie_ep *ep, u8 func_no, u8 cap) return __dw_pcie_ep_find_next_cap(ep, func_no, next_cap_ptr, cap); } +static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) +{ + u32 header; + int pos = PCI_CFG_SPACE_SIZE; + + while (pos) { + header = dw_pcie_readl_dbi(pci, pos); + if (PCI_EXT_CAP_ID(header) == cap) + return pos; + + pos = PCI_EXT_CAP_NEXT(header); + if (!pos) + break; + } + + return 0; +} + static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epf_header *hdr) { @@ -690,24 +708,6 @@ void dw_pcie_ep_deinit(struct dw_pcie_ep *ep) } EXPORT_SYMBOL_GPL(dw_pcie_ep_deinit); -static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) -{ - u32 header; - int pos = PCI_CFG_SPACE_SIZE; - - while (pos) { - header = dw_pcie_readl_dbi(pci, pos); - if (PCI_EXT_CAP_ID(header) == cap) - return pos; - - pos = PCI_EXT_CAP_NEXT(header); - if (!pos) - break; - } - - return 0; -} - static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci) { unsigned int offset; From patchwork Fri Jan 31 18:29:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13955647 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD3C51F2378 for ; Fri, 31 Jan 2025 18:30:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 31 Jan 2025 18:30:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738348230; bh=pNe97zQy9WdCurXXRQyQVVtshZPJwCYErpRvtX3WeGo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MfcO9y6B70nEYyLuczhuh9jVhR+OsO8MIgGZvMOaBdqpJLzqsl8G1wZwC5t37dVhK zAahu9/PClR+uGUke0Y0YESWSoJmeuvfJFdSEJnlN3pvCJ2NQ+QsK0G5lgnctUy5YD 4i8jPRgzhjdO8isG+5mhnyuTW4u3zeBWsRiJf+kaSZTmQC2RVWULmZ8kILJCGsZuQV nYoPFtSa1PItFhJvvVjgDV0Ce8L6WBAjKG+dckL1naqOjUSF5ce5pg4EzZRhrkZqwm qjFeM8UWLio8HOo5M+WXZGvS3AlEXgvpIk6mX1dmAMqqfkuGClDHxNAvvBvEnK5xA4 16eGb2mYVY+Gg== From: Niklas Cassel To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Siddharth Vadapalli , Udit Kumar , Vignesh Raghavendra , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v4 4/7] PCI: dwc: endpoint: Allow EPF drivers to configure the size of Resizable BARs Date: Fri, 31 Jan 2025 19:29:53 +0100 Message-ID: <20250131182949.465530-13-cassel@kernel.org> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250131182949.465530-9-cassel@kernel.org> References: <20250131182949.465530-9-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=9428; i=cassel@kernel.org; h=from:subject; bh=pNe97zQy9WdCurXXRQyQVVtshZPJwCYErpRvtX3WeGo=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLniq3eNillUamVal/TZ8nzWzOOzDH51j1LsEa61557L evjqOKkjlIWBjEuBlkxRRbfHy77i7vdpxxXvGMDM4eVCWQIAxenAExk9UxGhh6JhpiTD5xza97O 7Ww82FISJLsw3+K0subBH7Pr3W/MuMTwP/DKM93/soYL7zfcL9K4cuyPRc9v9skdHtdvTT/Y82G iEDMA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA The DWC databook specifies three different BARn_SIZING_SCHEME_N - Fixed Mask (0) - Programmable Mask (1) - Resizable BAR (2) Each of these sizing schemes have different instructions for how to initialize the BAR. The DWC driver currently does not support resizable BARs. Instead, in order to somewhat support resizable BARs, the DWC EP driver currently has an ugly hack that force sets a resizable BAR to 1 MB, if such a BAR is detected. Additionally, this hack only works if the DWC glue driver also has lied in their EPC features, and claimed that the resizable BAR is a 1 MB fixed size BAR. This is unintuitive (as you somehow need to know that you need to lie in your EPC features), but other than that it is overly restrictive, since a resizable BAR is capable of supporting sizes different than 1 MB. Add proper support for resizable BARs in the DWC EP driver. Note that the pci_epc_set_bar() API takes a struct pci_epf_bar which tells the EPC driver how it wants to configure the BAR. struct pci_epf_bar only has a single size struct member. This means that an EPC driver will only be able to set a single supported size. This is perfectly fine, as we do not need the complexity of allowing a host to change the size of the BAR. If someone ever wants to support resizing a resizable BAR, the pci_epc_set_bar() API can be extended in the future. With these changes, we allow an EPF driver to configure the size of Resizable BARs, rather than forcing them to a 1 MB size. This means that an EPC driver does not need to lie in EPC features, and an EPF driver will be able to set an arbitrary size (not be forced to a 1 MB size), just like BAR_PROGRAMMABLE. Signed-off-by: Niklas Cassel --- .../pci/controller/dwc/pcie-designware-ep.c | 182 ++++++++++++++++-- 1 file changed, 167 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 6b494781da42..72418160e658 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -223,6 +223,125 @@ static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, ep->bar_to_atu[bar] = 0; } +static unsigned int dw_pcie_ep_get_rebar_offset(struct dw_pcie *pci, + enum pci_barno bar) +{ + u32 reg, bar_index; + unsigned int offset, nbars; + int i; + + offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); + if (!offset) + return offset; + + reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); + nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >> PCI_REBAR_CTRL_NBAR_SHIFT; + + for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) { + reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); + bar_index = reg & PCI_REBAR_CTRL_BAR_IDX; + if (bar_index == bar) + return offset; + } + + return 0; +} + +static int dw_pcie_ep_set_bar_resizable(struct dw_pcie_ep *ep, u8 func_no, + struct pci_epf_bar *epf_bar) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + enum pci_barno bar = epf_bar->barno; + size_t size = epf_bar->size; + int flags = epf_bar->flags; + u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar); + unsigned int rebar_offset; + u32 rebar_cap, rebar_ctrl; + int ret; + + rebar_offset = dw_pcie_ep_get_rebar_offset(pci, bar); + if (!rebar_offset) + return -EINVAL; + + ret = pci_epc_bar_size_to_rebar_cap(size, &rebar_cap); + if (ret) + return ret; + + dw_pcie_dbi_ro_wr_en(pci); + + /* + * A BAR mask should not be written for a resizable BAR. The BAR mask + * is automatically derived by the controller every time the "selected + * size" bits are updated, see "Figure 3-26 Resizable BAR Example for + * 32-bit Memory BAR0" in DWC EP databook 5.96a. We simply need to write + * BIT(0) to set the BAR enable bit. + */ + dw_pcie_ep_writel_dbi2(ep, func_no, reg, BIT(0)); + dw_pcie_ep_writel_dbi(ep, func_no, reg, flags); + + if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) { + dw_pcie_ep_writel_dbi2(ep, func_no, reg + 4, 0); + dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0); + } + + /* + * Bits 31:0 in PCI_REBAR_CAP define "supported sizes" bits for sizes + * 1 MB to 128 TB. Bits 31:16 in PCI_REBAR_CTRL define "supported sizes" + * bits for sizes 256 TB to 8 EB. Disallow sizes 256 TB to 8 EB. + */ + rebar_ctrl = dw_pcie_readl_dbi(pci, rebar_offset + PCI_REBAR_CTRL); + rebar_ctrl &= ~GENMASK(31, 16); + dw_pcie_writel_dbi(pci, rebar_offset + PCI_REBAR_CTRL, rebar_ctrl); + + /* + * The "selected size" (bits 13:8) in PCI_REBAR_CTRL are automatically + * updated when writing PCI_REBAR_CAP, see "Figure 3-26 Resizable BAR + * Example for 32-bit Memory BAR0" in DWC EP databook 5.96a. + */ + dw_pcie_writel_dbi(pci, rebar_offset + PCI_REBAR_CAP, rebar_cap); + + dw_pcie_dbi_ro_wr_dis(pci); + + return 0; +} + +static int dw_pcie_ep_set_bar_programmable(struct dw_pcie_ep *ep, u8 func_no, + struct pci_epf_bar *epf_bar) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + enum pci_barno bar = epf_bar->barno; + size_t size = epf_bar->size; + int flags = epf_bar->flags; + u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar); + + dw_pcie_dbi_ro_wr_en(pci); + + dw_pcie_ep_writel_dbi2(ep, func_no, reg, lower_32_bits(size - 1)); + dw_pcie_ep_writel_dbi(ep, func_no, reg, flags); + + if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) { + dw_pcie_ep_writel_dbi2(ep, func_no, reg + 4, upper_32_bits(size - 1)); + dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0); + } + + dw_pcie_dbi_ro_wr_dis(pci); + + return 0; +} + +static enum pci_epc_bar_type dw_pcie_ep_get_bar_type(struct dw_pcie_ep *ep, + enum pci_barno bar) +{ + const struct pci_epc_features *epc_features; + + if (!ep->ops->get_features) + return BAR_PROGRAMMABLE; + + epc_features = ep->ops->get_features(ep); + + return epc_features->bar[bar].type; +} + static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epf_bar *epf_bar) { @@ -230,9 +349,9 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct dw_pcie *pci = to_dw_pcie_from_ep(ep); enum pci_barno bar = epf_bar->barno; size_t size = epf_bar->size; + enum pci_epc_bar_type bar_type; int flags = epf_bar->flags; int ret, type; - u32 reg; /* * DWC does not allow BAR pairs to overlap, e.g. you cannot combine BARs @@ -264,19 +383,30 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, goto config_atu; } - reg = PCI_BASE_ADDRESS_0 + (4 * bar); - - dw_pcie_dbi_ro_wr_en(pci); - - dw_pcie_ep_writel_dbi2(ep, func_no, reg, lower_32_bits(size - 1)); - dw_pcie_ep_writel_dbi(ep, func_no, reg, flags); - - if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) { - dw_pcie_ep_writel_dbi2(ep, func_no, reg + 4, upper_32_bits(size - 1)); - dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0); + bar_type = dw_pcie_ep_get_bar_type(ep, bar); + switch (bar_type) { + case BAR_FIXED: + /* + * There is no need to write a BAR mask for a fixed BAR (except + * to write 1 to the LSB of the BAR mask register, to enable the + * BAR). Write the BAR mask regardless. (The fixed bits in the + * BAR mask register will be read-only anyway.) + */ + fallthrough; + case BAR_PROGRAMMABLE: + ret = dw_pcie_ep_set_bar_programmable(ep, func_no, epf_bar); + break; + case BAR_RESIZABLE: + ret = dw_pcie_ep_set_bar_resizable(ep, func_no, epf_bar); + break; + default: + ret = -EINVAL; + dev_err(pci->dev, "Invalid BAR type\n"); + break; } - dw_pcie_dbi_ro_wr_dis(pci); + if (ret) + return ret; config_atu: if (!(flags & PCI_BASE_ADDRESS_SPACE)) @@ -710,9 +840,11 @@ EXPORT_SYMBOL_GPL(dw_pcie_ep_deinit); static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci) { + struct dw_pcie_ep *ep = &pci->ep; unsigned int offset; unsigned int nbars; - u32 reg, i; + enum pci_barno bar; + u32 reg, i, val; offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); @@ -727,9 +859,29 @@ static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci) * PCIe r6.0, sec 7.8.6.2 require us to support at least one * size in the range from 1 MB to 512 GB. Advertise support * for 1 MB BAR size only. + * + * For a BAR that has been configured via dw_pcie_ep_set_bar(), + * advertise support for only that size instead. */ - for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) - dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, BIT(4)); + for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) { + /* + * While the RESBAR_CAP_REG_* fields are sticky, the + * RESBAR_CTRL_REG_BAR_SIZE field is non-sticky (it is + * sticky in certain versions of DWC PCIe, but not all). + * + * RESBAR_CTRL_REG_BAR_SIZE is updated automatically by + * the controller when RESBAR_CAP_REG is written, which + * is why RESBAR_CAP_REG is written here. + */ + val = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); + bar = val & PCI_REBAR_CTRL_BAR_IDX; + if (ep->epf_bar[bar]) + pci_epc_bar_size_to_rebar_cap(ep->epf_bar[bar]->size, &val); + else + val = BIT(4); + + dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, val); + } } dw_pcie_setup(pci); From patchwork Fri Jan 31 18:29:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13955648 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B44AD1F2C33 for ; Fri, 31 Jan 2025 18:30:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738348233; cv=none; b=le8PKyI8IGFd5glPDnX021lkkb16YPgRfmKGgh98YVKIgGoq6jMLbm8xgePpSAhTdby1Udq1PX5OtaU3QpWuaFkZ3cHy88jJSYk5oZK3x8+RyhOccwzaeSXj2oTqKG1Kg/upBJfaeWveO+HFLvI6kfY1gr3/KK5PTHgP5YGoLYk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738348233; c=relaxed/simple; bh=Bi1EDc1v8t/I1ufJIhDjHxnt+Ry1rozlhmo2/jK3fSQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EtTdJTm8z9ScdOWU/vG4ENTdWNw416E5AalWajX05wDXBeg+If3DudgBouY6AmQddDdLqWsXvOe7kkjg6FT+KXwBzJrQHEmrR9vrymC7cHfbJyTg1Gal1Ahu1Ldz/mZrBsY/PHhonFk9IdSH72RQ3m5xGELLExecTa+Oaw6ZgFA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XsEC0FJp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XsEC0FJp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E697BC4CED1; Fri, 31 Jan 2025 18:30:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738348233; bh=Bi1EDc1v8t/I1ufJIhDjHxnt+Ry1rozlhmo2/jK3fSQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XsEC0FJpzfKnP9uc+4Yo38ZQXHaym3iM7LzL63lvkAffdXGalf83ctwIBsnk6Q91P e4oWrrb1sMucYni6EAnJP5gt5O3anGDDvjA133I2+UZyG/F9mH/vfApJt0RrDX1XdW MoTViE6qLnx+x46jkC0OyDYeT+gcFyf0E55HDPm7YEt6xBoqN/ZCKUsfrQyzuEBmT5 N5PRT6lCsxooO73GcdVHUt/2z9apJlOZmFcqX512sw3lmh7zOoCgRpdnTegDKTNad9 9Axp9KOna4IcR3KLdkXPrXcFp33xTkcXZFMUzaoaRkD7HGWUHzqyIGOmdQPQa3lIQ4 1sT/GUyS5jy9w== From: Niklas Cassel To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Siddharth Vadapalli , Udit Kumar , Vignesh Raghavendra , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v4 5/7] PCI: keystone: Describe Resizable BARs as Resizable BARs Date: Fri, 31 Jan 2025 19:29:54 +0100 Message-ID: <20250131182949.465530-14-cassel@kernel.org> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250131182949.465530-9-cassel@kernel.org> References: <20250131182949.465530-9-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1357; i=cassel@kernel.org; h=from:subject; bh=Bi1EDc1v8t/I1ufJIhDjHxnt+Ry1rozlhmo2/jK3fSQ=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLniq1+/GhFlFxJSLDZRW+eS9taetxS5GeF/dc7JRzKZ PXJ9FJRRykLgxgXg6yYIovvD5f9xd3uU44r3rGBmcPKBDKEgYtTACayYAfDH36leoZpFpXLjAyW Nu6MM3sS022tXRyak/GPQ+0cd2nAJkaGr4tnrr3twKsZf1d+09/9+pVZvVl/Kie3u245tMejsjG PDwA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Looking at "12.2.2.4.15 PCIe Subsystem BAR Configuration" in the AM65x TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf We can see that BAR2 and BAR5 are not Fixed BARs, but actually Resizable BARs. Now when we actually have support for Resizable BARs, let's configure these BARs as such. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Niklas Cassel --- drivers/pci/controller/dwc/pci-keystone.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 63bd5003da45..fdc610ec7e5e 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -966,10 +966,10 @@ static const struct pci_epc_features ks_pcie_am654_epc_features = { .msix_capable = true, .bar[BAR_0] = { .type = BAR_RESERVED, }, .bar[BAR_1] = { .type = BAR_RESERVED, }, - .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_2] = { .type = BAR_RESIZABLE, }, .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_64K, }, .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256, }, - .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_5] = { .type = BAR_RESIZABLE, }, .align = SZ_1M, }; From patchwork Fri Jan 31 18:29:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13955649 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29B5D4315A for ; Fri, 31 Jan 2025 18:30:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738348237; cv=none; b=DoihIUAwQEFZM7fc5N2LPrV/fMdcYqXIEaX2rC9kegxR4eGLXzV2xp8GgQmPGmWCEzzkUsMM0CIeWW3vxPRgFzj+FbCbg1x7s2zfqMVM0Y3eh/2z6cMSubJ7euLtPgtANAb5Y+lAwH3uKk9XhvZPnW4jhnL9AnLWWVjrinVZzPU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738348237; c=relaxed/simple; bh=Dgj5VNoE5kVgWc76NDWLLdMQe5eoOJ8Xt5A76OaSvQs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=c0HrKgE5irgrKTJ30C+nqODTfZN6fZ82xk83nQZNLyWe+GGxLKzbqv4km+womt0KaO7avHALpjUhhVS8tKqj8Yio4V2SoN6IWiE24jeqGZ/dQj7UFiphdex/6BNqtRpCJVv4CwBl3+9zGvj0aB/yeE9B7b/lqH57CZ78DzUVsJQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=H96lAUHr; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="H96lAUHr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E1BAFC4CED3; Fri, 31 Jan 2025 18:30:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738348236; bh=Dgj5VNoE5kVgWc76NDWLLdMQe5eoOJ8Xt5A76OaSvQs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=H96lAUHrcl0zDCcAiMi4BEDOCUJosQOK7GMWh16PB14yPPEqX/5Lawm95d3dH+Ral NeUeedwbltFM1WoOz+m2uZJjFA7ghbeXdFXyjJMTQDkvl+2X6MryMUF3cbbY9UJwij 9/6x01CXlzO8jZ/zPHGjdzzzILofEgx2NrptPvUtsEBCIxAxCU1rj4YzfY5x9o58E1 Chg7TZyhMXRxHjBLuuB2uZjzkVL0I1UkwhJ2z0QfvpTVU/9gE9M0ZnTLJgxTuyXDKN vV5K89CmsxH9DqHIEMkG6hKghpGTU12mhjvOuQqrQPJrQuqnT2KGwjZuOJIcM1AS0b dUZHNUKPwBFuA== From: Niklas Cassel To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Kishon Vijay Abraham I Cc: Damien Le Moal , Siddharth Vadapalli , Udit Kumar , Vignesh Raghavendra , Niklas Cassel , stable+noautosel@kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v4 6/7] PCI: keystone: Specify correct alignment requirement Date: Fri, 31 Jan 2025 19:29:55 +0100 Message-ID: <20250131182949.465530-15-cassel@kernel.org> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250131182949.465530-9-cassel@kernel.org> References: <20250131182949.465530-9-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1769; i=cassel@kernel.org; h=from:subject; bh=Dgj5VNoE5kVgWc76NDWLLdMQe5eoOJ8Xt5A76OaSvQs=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLniq22c3ixsjnb+p6sz8HJ56pE9O71mvb1Skup7rSxi mz/8XV2RykLgxgXg6yYIovvD5f9xd3uU44r3rGBmcPKBDKEgYtTACZy9h0jw8zump2GK+69mx8o bTHb+W7OQcUC5nPbg6SvhC+5sMnLYwojw7Fvortvd0g1PDy0cq1k9bkJr5lmxxV92dWgNOPg5Jd TdzEDAA== X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA The support for a specific iATU alignment was added in commit 2a9a801620ef ("PCI: endpoint: Add support to specify alignment for buffers allocated to BARs"). This commit specifically mentions both that the alignment by each DWC based EP driver should match CX_ATU_MIN_REGION_SIZE, and that AM65x specifically has a 64 KB alignment. This also matches the CX_ATU_MIN_REGION_SIZE value specified by "12.2.2.4.7 PCIe Subsystem Address Translation" in the AM65x TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf This higher value, 1 MB, was obviously an ugly hack used to be able to handle Resizable BARs which have a minimum size of 1 MB. Now when we actually have support for Resizable BARs, let's configure the iATU alignment requirement to the actual requirement. (BARs described as Resizable will still get aligned to 1 MB.) Cc: stable+noautosel@kernel.org # Depends on PCI endpoint Resizable BARs series Fixes: 23284ad677a9 ("PCI: keystone: Add support for PCIe EP in AM654x Platforms") Signed-off-by: Niklas Cassel --- drivers/pci/controller/dwc/pci-keystone.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index fdc610ec7e5e..76a37368ae4f 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -970,7 +970,7 @@ static const struct pci_epc_features ks_pcie_am654_epc_features = { .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_64K, }, .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256, }, .bar[BAR_5] = { .type = BAR_RESIZABLE, }, - .align = SZ_1M, + .align = SZ_64K, }; static const struct pci_epc_features* From patchwork Fri Jan 31 18:29:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13955650 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B306A1F2C59 for ; Fri, 31 Jan 2025 18:30:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738348240; cv=none; b=igBuYgaXbnt7ux9YRVtQrkfZDjDEviIcMqSR0YDAoWCsRLh9+XIMawcbfqfWQHz5GZu2J7nYpYIvlLFkg6Yrf9bF2ooSO3nxr2sYWNaDM5SdtTevu7PgPz2z0BU0l9HlxqPv4qfotY2Y/fNm43X2GqTUjO3Lwjm7uVYbLcxGewc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738348240; c=relaxed/simple; bh=8uxTceNWzYFB2l9AWmmadxYKBiMHIPtgLjKZiK55GQA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SqiwmY67yp/KnvdQVoGM3k32B8REfl59DM/B6UxhBqUOr91OaYE1RSPdGE5/ft80AUg/c/+SgdMvJ+fkYfZI/QtmECSYieEea9FGxbavu20bWwNXK6aKsGlzcR8Kn6RRSM82QUv/tlr9QfyfH1t4Q7TN3/8iGPw6IsTzjmUz+Cs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NPjkBtf3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NPjkBtf3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 48DE3C4CEE3; Fri, 31 Jan 2025 18:30:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738348240; bh=8uxTceNWzYFB2l9AWmmadxYKBiMHIPtgLjKZiK55GQA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NPjkBtf3Z+Va9MNfHHJ5iBM8ynQpSWaYrIsz7aRMuHfuBNn4tEjrrg5f3cZ995MZk GhIP87E9DbjRw83sOIO8nQFdYUy1lAZ9UQJR9GRTLGFrC/05qprvjyYY9pb0QUnG0N 8Oq51XyUvTZVzbGNpmAsIdRZZSBMbnn7cv0vjH+BH4jnellZ6ujoroFGd8TbLh4n/k TPBn/bkKvKnqNHNffinvgH7BOfRdCD9cw0m7jWpyN91AMTNKXg9N32lje9GASYNB1O LzxPvvUcBZlOzxBETltdiRquh3P96ylkYt5SoDWhfwUKzRIuuaHJzVzJDn73XKx4b4 BCvALBAR8A+UA== From: Niklas Cassel To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner Cc: Damien Le Moal , Siddharth Vadapalli , Udit Kumar , Vignesh Raghavendra , Niklas Cassel , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v4 7/7] PCI: dw-rockchip: Describe Resizable BARs as Resizable BARs Date: Fri, 31 Jan 2025 19:29:56 +0100 Message-ID: <20250131182949.465530-16-cassel@kernel.org> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250131182949.465530-9-cassel@kernel.org> References: <20250131182949.465530-9-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2591; i=cassel@kernel.org; h=from:subject; bh=8uxTceNWzYFB2l9AWmmadxYKBiMHIPtgLjKZiK55GQA=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLniq1pa9vTviDSx3VmySXBn+WLMpglij8XeR1y6j62r ovp+MMlHaUsDGJcDLJiiiy+P1z2F3e7TzmueMcGZg4rE8gQBi5OAZjIb3NGhof7lzHsYtnfGeL1 h4Or47r5Fja/u7v5j9j+VVvxKTUnsJKR4cLODVPXNL/qU508J/rJKc9ts16Uc7jIXFYwPuMgy3O igAUA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Looking at "11.4.4.29 USP_PCIE_RESBAR Registers Summary" in the rk3588 TRM, we can see that none of the BARs are Fixed BARs, but actually Resizable BARs. I couldn't find any reference in the rk3568 TRM, but looking at the downstream PCIe endpoint driver, rk3568 and rk3588 are treated as the same, so the BARs on rk3568 must also be Resizable BARs. Now when we actually have support for Resizable BARs, let's configure these BARs as such. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Niklas Cassel --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 22 +++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 93698abff4d9..df2eaa35d045 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -273,12 +273,12 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = { .msi_capable = true, .msix_capable = true, .align = SZ_64K, - .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_0] = { .type = BAR_RESIZABLE, }, + .bar[BAR_1] = { .type = BAR_RESIZABLE, }, + .bar[BAR_2] = { .type = BAR_RESIZABLE, }, + .bar[BAR_3] = { .type = BAR_RESIZABLE, }, + .bar[BAR_4] = { .type = BAR_RESIZABLE, }, + .bar[BAR_5] = { .type = BAR_RESIZABLE, }, }; /* @@ -293,12 +293,12 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = { .msi_capable = true, .msix_capable = true, .align = SZ_64K, - .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, - .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_0] = { .type = BAR_RESIZABLE, }, + .bar[BAR_1] = { .type = BAR_RESIZABLE, }, + .bar[BAR_2] = { .type = BAR_RESIZABLE, }, + .bar[BAR_3] = { .type = BAR_RESIZABLE, }, .bar[BAR_4] = { .type = BAR_RESERVED, }, - .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_5] = { .type = BAR_RESIZABLE, }, }; static const struct pci_epc_features *