From patchwork Sun Feb 2 19:34:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13956632 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDF748F6C; Sun, 2 Feb 2025 19:34:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738524892; cv=none; b=E3zklR1WmSd7j3FgArooJCY6bJL4BCPJ0IvWjzeiOZEbdILVcS+a3R9j6P8rn2iu+Cdp0WYiYniagEerF9FYQUK/mrpBVDLa72ATcE4+hKUkAlCIa4b2lYztmCGWRLVOrV7rArYVm7jEimTzx08asPRK+m+Uc6rX92YG6NsuuOQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738524892; c=relaxed/simple; bh=MvBbBz0UZOoSGohxLQSCxzUNlNMms+bHXssaD7TA7kM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Qc33qrDPnqyzrZWyaE29FGYVHeIn2mb1vR4x+pm/MERjtrvc+nLA2uTJPaLzjuRn9WMsUnjjogogUIJISnYJDKqSeb+VLpz1s90lx7LhROasAe5tZ1+PK8XVBpP8lfirVQheLuWGCf/TumvSmIdknzKYl8d/nWHYHoSXOGtDHzU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WoQEosl+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WoQEosl+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 22BD8C4CED1; Sun, 2 Feb 2025 19:34:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738524891; bh=MvBbBz0UZOoSGohxLQSCxzUNlNMms+bHXssaD7TA7kM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=WoQEosl+kDVcBNcdo7cvQYIgXbTT5tTmnDqMV9AMJ6djArwFsEsHCXEKfVJQMHZ6L yrE4ceg/FnZd1XyLpM7030LJI/7+cEe2ZJuGPznhVaivGi2CD8723aVX+NfWTfkptq 8fzGuCWhx7oSbxKo7Tl6THLJa31crMZjKZNMKEtNsITK2WJ/7IGBK7C999UL91DUOE BBzDyAhSe6eg2yinOLYbTG96Ut4jUChFEoRKjFzcC8KH/W5kXPssGwdZ1JHhbk1ZHZ 3tTfmbJSw22qW2dfyM6J+Z9pxX91Xza9OQTSFtIxv10Hz9ShQctfXXroKVdc/Qv6bq FcgDBdNPSSaNA== From: Lorenzo Bianconi Date: Sun, 02 Feb 2025 20:34:23 +0100 Subject: [PATCH v2 1/2] dt-bindings: PCI: mediatek-gen3: Add mediatek,pbus-csr phandle property Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250202-en7581-pcie-pbus-csr-v2-1-65dcb201c9a9@kernel.org> References: <20250202-en7581-pcie-pbus-csr-v2-0-65dcb201c9a9@kernel.org> In-Reply-To: <20250202-en7581-pcie-pbus-csr-v2-0-65dcb201c9a9@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 Introduce the mediatek,pbus-csr property for the pbus-csr syscon node available on EN7581 SoC. The airoha pbus-csr block provides a configuration interface for the PBUS controller used to detect if a given address is on PCIE0, PCIE1 or PCIE2. Signed-off-by: Lorenzo Bianconi Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/pci/mediatek-pcie-gen3.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index f05aab2b1addcac91d4685d7d94f421814822b92..02f2cd9bcf007c1f16b18b1330a88ce43807a9be 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -109,6 +109,12 @@ properties: power-domains: maxItems: 1 + mediatek,pbus-csr: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon node used to detect if a given address is on + the PCIe ports. + '#interrupt-cells': const: 1 @@ -168,6 +174,8 @@ allOf: minItems: 1 maxItems: 2 + mediatek,pbus-csr: false + - if: properties: compatible: @@ -197,6 +205,8 @@ allOf: minItems: 1 maxItems: 2 + mediatek,pbus-csr: false + - if: properties: compatible: @@ -224,6 +234,8 @@ allOf: minItems: 1 maxItems: 2 + mediatek,pbus-csr: false + - if: properties: compatible: From patchwork Sun Feb 2 19:34:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13956633 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADD7E8F6C; Sun, 2 Feb 2025 19:34:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738524894; cv=none; b=chD6Hg4uPXHe5mGa3BUyP+4nU+kA40jlHSFlzgnWucwqLONrTHFSszx5Q48vVytiUyBwlGIgfTXenAJx3Y+4L059+WQqpRGlzJtCiQYW4Ka9EV5G7rvciNtqZBPCcKFzniEs4zry6QlPCT294XQgCZ+B+eJKLVErbXPDS2m/Q0Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738524894; c=relaxed/simple; bh=K2iI3AiKvjoEFvWs1oYEwnuQSWAbsXtBtq6KCTpCm8s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=diQy30dKn3LxNF3a1q86irOpKFb3IqCzxbCoCsV+uW9fiarLKrqZqf6Aqt0RONF3LNf53lazSu9uJm8INusb/jn2noB7Dp686ax69WtLzUQcZwtZUzzz887tlMUIGpEFA0fWh0vTPEX+tV4pcqYRKz6wcz30B8n2rTfuR11QK4k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FbN+JRDr; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FbN+JRDr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CD378C4CED1; Sun, 2 Feb 2025 19:34:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738524894; bh=K2iI3AiKvjoEFvWs1oYEwnuQSWAbsXtBtq6KCTpCm8s=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=FbN+JRDrD7nKr2dLBNZOe1qC5aTOv060C1/q8JE2jiFqpQZfLWCDIQ+vBM7WVNPF0 CbNRTCsKPrraZwXbK+C6dIr8cRj8OoVb9fRzlKOqMkm9LWL0FWD7KpDaXQv6PnTzar VYyYAbh0aY7JvMwLHcXdW/SeuLmpwdKUqCHbcN0YrtVzJZpxOZy/I0wErBhtYsTRJm X2FTJAE44lFt05ch1YlEgJpGSE0vyBL87XergSHCM8bjAxtRsL1BGqHaFAZmZmqAXl Myfn6cCiNzhPR32po55YKJNj9dVSeM5yczAgBdD94pJWhv+PV5PgwM7GMTBpvSf7Wt /3kw0y5UnTBoA== From: Lorenzo Bianconi Date: Sun, 02 Feb 2025 20:34:24 +0100 Subject: [PATCH v2 2/2] PCI: mediatek-gen3: Configure PBUS_CSR registers for EN7581 SoC Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250202-en7581-pcie-pbus-csr-v2-2-65dcb201c9a9@kernel.org> References: <20250202-en7581-pcie-pbus-csr-v2-0-65dcb201c9a9@kernel.org> In-Reply-To: <20250202-en7581-pcie-pbus-csr-v2-0-65dcb201c9a9@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 Configure PBus base address and address mask to allow the hw to detect if a given address is on PCIE0, PCIE1 or PCIE2. Signed-off-by: Lorenzo Bianconi --- drivers/pci/controller/pcie-mediatek-gen3.c | 30 ++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index aa24ac9aaecc749b53cfc4faf6399913d20cdbf2..9c2a592cae959de8fbe9ca5c5c2253f8eadf2c76 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -24,6 +25,7 @@ #include #include #include +#include #include #include "../pci.h" @@ -127,6 +129,13 @@ #define PCIE_MTK_RESET_TIME_US 10 +#define PCIE_EN7581_PBUS_ADDR(_n) (0x00 + ((_n) << 3)) +#define PCIE_EN7581_PBUS_ADDR_MASK(_n) (0x04 + ((_n) << 3)) +#define PCIE_EN7581_PBUS_BASE_ADDR(_n) \ + ((_n) == 2 ? 0x28000000 : \ + (_n) == 1 ? 0x24000000 : 0x20000000) +#define PCIE_EN7581_PBUS_BASE_ADDR_MASK GENMASK(31, 26) + /* Time in ms needed to complete PCIe reset on EN7581 SoC */ #define PCIE_EN7581_RESET_TIME_MS 100 @@ -931,7 +940,8 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) { struct device *dev = pcie->dev; - int err; + struct regmap *map; + int err, slot; u32 val; /* @@ -945,6 +955,24 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) /* Wait for the time needed to complete the reset lines assert. */ msleep(PCIE_EN7581_RESET_TIME_MS); + map = syscon_regmap_lookup_by_phandle(dev->of_node, + "mediatek,pbus-csr"); + if (IS_ERR(map)) + return PTR_ERR(map); + + /* + * Configure PBus base address and address mask to allow the + * hw to detect if a given address is on PCIE0, PCIE1 or PCIE2. + */ + slot = of_get_pci_domain_nr(dev->of_node); + if (slot < 0) + return slot; + + regmap_write(map, PCIE_EN7581_PBUS_ADDR(slot), + PCIE_EN7581_PBUS_BASE_ADDR(slot)); + regmap_write(map, PCIE_EN7581_PBUS_ADDR_MASK(slot), + PCIE_EN7581_PBUS_BASE_ADDR_MASK); + /* * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581 * requires PHY initialization and power-on before PHY reset deassert.