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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21de32ea5fesm66894555ad.132.2025.02.02.21.43.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Feb 2025 21:43:48 -0800 (PST) From: Joey Lu To: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mcoquelin.stm32@gmail.com, richardcochran@gmail.com Cc: alexandre.torgue@foss.st.com, joabreu@synopsys.com, ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, peppe.cavallaro@st.com, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com, Joey Lu Subject: [PATCH net-next v8 1/3] dt-bindings: net: nuvoton: Add schema for Nuvoton MA35 family GMAC Date: Mon, 3 Feb 2025 13:41:58 +0800 Message-Id: <20250203054200.21977-2-a0987203069@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250203054200.21977-1-a0987203069@gmail.com> References: <20250203054200.21977-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Create initial schema for Nuvoton MA35 family Gigabit MAC. Reviewed-by: Rob Herring (Arm) Signed-off-by: Joey Lu --- .../bindings/net/nuvoton,ma35d1-dwmac.yaml | 126 ++++++++++++++++++ .../devicetree/bindings/net/snps,dwmac.yaml | 1 + 2 files changed, 127 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/nuvoton,ma35d1-dwmac.yaml diff --git a/Documentation/devicetree/bindings/net/nuvoton,ma35d1-dwmac.yaml b/Documentation/devicetree/bindings/net/nuvoton,ma35d1-dwmac.yaml new file mode 100644 index 000000000000..c3f2ad423cc0 --- /dev/null +++ b/Documentation/devicetree/bindings/net/nuvoton,ma35d1-dwmac.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nuvoton,ma35d1-dwmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton DWMAC glue layer controller + +maintainers: + - Joey Lu + +description: + Nuvoton 10/100/1000Mbps Gigabit Ethernet MAC Controller is based on + Synopsys DesignWare MAC (version 3.73a). + +allOf: + - $ref: snps,dwmac.yaml# + +properties: + compatible: + items: + - enum: + - nuvoton,ma35d1-dwmac + + reg: + maxItems: 1 + description: + Register range should be one of the GMAC interface. + + interrupts: + maxItems: 1 + + clocks: + items: + - description: MAC clock + - description: PTP clock + + clock-names: + items: + - const: stmmaceth + - const: ptp_ref + + nuvoton,sys: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to access syscon registers. + - description: GMAC interface ID. + enum: + - 0 + - 1 + description: + A phandle to the syscon with one argument that configures system registers + for MA35D1's two GMACs. The argument specifies the GMAC interface ID. + + resets: + maxItems: 1 + + reset-names: + items: + - const: stmmaceth + + phy-mode: + enum: + - rmii + - rgmii + - rgmii-id + - rgmii-txid + - rgmii-rxid + + tx-internal-delay-ps: + default: 0 + minimum: 0 + maximum: 2000 + description: + RGMII TX path delay used only when PHY operates in RGMII mode with + internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds. + Allowed values are from 0 to 2000. + + rx-internal-delay-ps: + default: 0 + minimum: 0 + maximum: 2000 + description: + RGMII RX path delay used only when PHY operates in RGMII mode with + internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds. + Allowed values are from 0 to 2000. + +required: + - clocks + - clock-names + - nuvoton,sys + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + ethernet@40120000 { + compatible = "nuvoton,ma35d1-dwmac"; + reg = <0x40120000 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&clk EMAC0_GATE>, <&clk EPLL_DIV8>; + clock-names = "stmmaceth", "ptp_ref"; + + nuvoton,sys = <&sys 0>; + resets = <&sys MA35D1_RESET_GMAC0>; + reset-names = "stmmaceth"; + + phy-mode = "rgmii-id"; + phy-handle = <ð_phy0>; + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + reg = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 91e75eb3f329..c43dcae74495 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -67,6 +67,7 @@ properties: - ingenic,x2000-mac - loongson,ls2k-dwmac - loongson,ls7a-dwmac + - nuvoton,ma35d1-dwmac - nxp,s32g2-dwmac - qcom,qcs404-ethqos - qcom,sa8775p-ethqos From patchwork Mon Feb 3 05:41:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joey Lu X-Patchwork-Id: 13956777 X-Patchwork-Delegate: kuba@kernel.org Received: from mail-pj1-f46.google.com (mail-pj1-f46.google.com [209.85.216.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 223311922F6; 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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21de32ea5fesm66894555ad.132.2025.02.02.21.43.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Feb 2025 21:43:52 -0800 (PST) From: Joey Lu To: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mcoquelin.stm32@gmail.com, richardcochran@gmail.com Cc: alexandre.torgue@foss.st.com, joabreu@synopsys.com, ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, peppe.cavallaro@st.com, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com, Joey Lu Subject: [PATCH net-next v8 2/3] arm64: dts: nuvoton: Add Ethernet nodes Date: Mon, 3 Feb 2025 13:41:59 +0800 Message-Id: <20250203054200.21977-3-a0987203069@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250203054200.21977-1-a0987203069@gmail.com> References: <20250203054200.21977-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Add GMAC nodes for our MA35D1 development boards: two RGMII interfaces for SOM board, and one RGMII and one RMII interface for IoT board. Signed-off-by: Joey Lu --- .../boot/dts/nuvoton/ma35d1-iot-512m.dts | 12 +++++ .../boot/dts/nuvoton/ma35d1-som-256m.dts | 10 ++++ arch/arm64/boot/dts/nuvoton/ma35d1.dtsi | 54 +++++++++++++++++++ 3 files changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts index 9482bec1aa57..5cc712ae92d8 100644 --- a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts @@ -18,6 +18,8 @@ aliases { serial12 = &uart12; serial13 = &uart13; serial14 = &uart14; + ethernet0 = &gmac0; + ethernet1 = &gmac1; }; chosen { @@ -126,3 +128,13 @@ &uart14 { pinctrl-0 = <&pinctrl_uart14>; status = "okay"; }; + +&gmac0 { + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&gmac1 { + phy-mode = "rmii"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts index f6f20a17e501..1d9ac350a1f1 100644 --- a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts @@ -18,6 +18,8 @@ aliases { serial12 = &uart12; serial14 = &uart14; serial16 = &uart16; + ethernet0 = &gmac0; + ethernet1 = &gmac1; }; chosen { @@ -129,3 +131,11 @@ &uart16 { pinctrl-0 = <&pinctrl_uart16>; status = "okay"; }; + +&gmac0 { + status = "okay"; +}; + +&gmac1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi index e51b98f5bdce..89712e262ee6 100644 --- a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi +++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi @@ -379,5 +379,59 @@ uart16: serial@40880000 { clocks = <&clk UART16_GATE>; status = "disabled"; }; + + gmac0: ethernet@40120000 { + compatible = "nuvoton,ma35d1-dwmac"; + reg = <0x0 0x40120000 0x0 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&clk EMAC0_GATE>, <&clk EPLL_DIV8>; + clock-names = "stmmaceth", "ptp_ref"; + + nuvoton,sys = <&sys 0>; + resets = <&sys MA35D1_RESET_GMAC0>; + reset-names = "stmmaceth"; + + phy-mode = "rgmii-id"; + phy-handle = <ð_phy0>; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; + }; + + gmac1: ethernet@40130000 { + compatible = "nuvoton,ma35d1-dwmac"; + reg = <0x0 0x40130000 0x0 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&clk EMAC1_GATE>, <&clk EPLL_DIV8>; + clock-names = "stmmaceth", "ptp_ref"; + + nuvoton,sys = <&sys 1>; + resets = <&sys MA35D1_RESET_GMAC1>; + reset-names = "stmmaceth"; + + phy-mode = "rgmii-id"; + phy-handle = <ð_phy1>; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; }; }; From patchwork Mon Feb 3 05:42:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joey Lu X-Patchwork-Id: 13956778 X-Patchwork-Delegate: kuba@kernel.org Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65C5A1482F2; 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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21de32ea5fesm66894555ad.132.2025.02.02.21.43.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Feb 2025 21:43:56 -0800 (PST) From: Joey Lu To: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mcoquelin.stm32@gmail.com, richardcochran@gmail.com Cc: alexandre.torgue@foss.st.com, joabreu@synopsys.com, ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, peppe.cavallaro@st.com, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com, Joey Lu , Andrew Lunn Subject: [PATCH net-next v8 3/3] net: stmmac: dwmac-nuvoton: Add dwmac glue for Nuvoton MA35 family Date: Mon, 3 Feb 2025 13:42:00 +0800 Message-Id: <20250203054200.21977-4-a0987203069@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250203054200.21977-1-a0987203069@gmail.com> References: <20250203054200.21977-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Add support for Gigabit Ethernet on Nuvoton MA35 series using dwmac driver. The driver has been tested on the NuMaker-HMI-MA35D1-S1 development board, and the log is attached below. For more information about the SoCs, please refer to the MA35D1 series datasheet. [ 0.000000] Machine model: Nuvoton MA35D1-SOM ... [ 1.836386] nuvoton-dwmac 40120000.ethernet: IRQ eth_wake_irq not found [ 1.843039] nuvoton-dwmac 40120000.ethernet: IRQ eth_lpi not found [ 1.849304] nuvoton-dwmac 40120000.ethernet: IRQ sfty not found [ 1.856331] nuvoton-dwmac 40120000.ethernet: User ID: 0x10, Synopsys ID: 0x37 [ 1.863532] nuvoton-dwmac 40120000.ethernet: DWMAC1000 [ 1.868750] nuvoton-dwmac 40120000.ethernet: DMA HW capability register supported [ 1.876190] nuvoton-dwmac 40120000.ethernet: RX Checksum Offload Engine supported [ 1.883696] nuvoton-dwmac 40120000.ethernet: COE Type 2 [ 1.888903] nuvoton-dwmac 40120000.ethernet: TX Checksum insertion supported [ 1.895912] nuvoton-dwmac 40120000.ethernet: Enhanced/Alternate descriptors [ 1.902846] nuvoton-dwmac 40120000.ethernet: Enabled extended descriptors [ 1.909598] nuvoton-dwmac 40120000.ethernet: Ring mode enabled [ 1.915406] nuvoton-dwmac 40120000.ethernet: Enable RX Mitigation via HW Watchdog Timer [ 2.540881] nuvoton-dwmac 40130000.ethernet: IRQ eth_wake_irq not found [ 2.547463] nuvoton-dwmac 40130000.ethernet: IRQ eth_lpi not found [ 2.553626] nuvoton-dwmac 40130000.ethernet: IRQ sfty not found [ 2.560015] nuvoton-dwmac 40130000.ethernet: User ID: 0x10, Synopsys ID: 0x37 [ 2.567116] nuvoton-dwmac 40130000.ethernet: DWMAC1000 [ 2.572300] nuvoton-dwmac 40130000.ethernet: DMA HW capability register supported [ 2.579747] nuvoton-dwmac 40130000.ethernet: RX Checksum Offload Engine supported [ 2.587198] nuvoton-dwmac 40130000.ethernet: COE Type 2 [ 2.592395] nuvoton-dwmac 40130000.ethernet: TX Checksum insertion supported [ 2.599418] nuvoton-dwmac 40130000.ethernet: Enhanced/Alternate descriptors [ 2.606351] nuvoton-dwmac 40130000.ethernet: Enabled extended descriptors [ 2.613109] nuvoton-dwmac 40130000.ethernet: Ring mode enabled [ 2.618918] nuvoton-dwmac 40130000.ethernet: Enable RX Mitigation via HW Watchdog Timer Reviewed-by: Andrew Lunn Signed-off-by: Joey Lu --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 ++ drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../ethernet/stmicro/stmmac/dwmac-nuvoton.c | 182 ++++++++++++++++++ 3 files changed, 195 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-nuvoton.c diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index 4cc85a36a1ab..f083a0e97b75 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -121,6 +121,18 @@ config DWMAC_MESON the stmmac device driver. This driver is used for Meson6, Meson8, Meson8b and GXBB SoCs. +config DWMAC_NUVOTON + tristate "Nuvoton MA35 dwmac support" + default ARCH_MA35 + depends on OF && (ARCH_MA35 || COMPILE_TEST) + select MFD_SYSCON + help + Support for Ethernet controller on Nuvoton MA35 series SoC. + + This selects the Nuvoton MA35 series SoC glue layer support + for the stmmac device driver. The nuvoton-dwmac driver is + used for MA35 series SoCs. + config DWMAC_QCOM_ETHQOS tristate "Qualcomm ETHQOS support" default ARCH_QCOM diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile index b26f0e79c2b3..48e25b85ea06 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_DWMAC_IPQ806X) += dwmac-ipq806x.o obj-$(CONFIG_DWMAC_LPC18XX) += dwmac-lpc18xx.o obj-$(CONFIG_DWMAC_MEDIATEK) += dwmac-mediatek.o obj-$(CONFIG_DWMAC_MESON) += dwmac-meson.o dwmac-meson8b.o +obj-$(CONFIG_DWMAC_NUVOTON) += dwmac-nuvoton.o obj-$(CONFIG_DWMAC_QCOM_ETHQOS) += dwmac-qcom-ethqos.o obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o obj-$(CONFIG_DWMAC_RZN1) += dwmac-rzn1.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-nuvoton.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-nuvoton.c new file mode 100644 index 000000000000..588e2f234c5b --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-nuvoton.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Nuvoton DWMAC specific glue layer + * + * Copyright (C) 2025 Nuvoton Technology Corp. + * + * Author: Joey Lu + */ + +#include +#include +#include +#include +#include +#include + +#include "stmmac.h" +#include "stmmac_platform.h" + +#define NVT_REG_SYS_GMAC0MISCR 0x108 +#define NVT_REG_SYS_GMAC1MISCR 0x10C + +#define NVT_MISCR_RMII BIT(0) + +/* Two thousand picoseconds are evenly mapped to a 4-bit field, + * resulting in each step being 2000/15 picoseconds. + */ +#define NVT_PATH_DELAY_STEP 134 +#define NVT_TX_DELAY_MASK GENMASK(19, 16) +#define NVT_RX_DELAY_MASK GENMASK(23, 20) + +struct nvt_priv_data { + struct platform_device *pdev; + struct regmap *regmap; +}; + +static struct nvt_priv_data * +nvt_gmac_setup(struct platform_device *pdev, struct plat_stmmacenet_data *plat) +{ + struct device *dev = &pdev->dev; + struct nvt_priv_data *bsp_priv; + phy_interface_t phy_mode; + u32 macid, arg, reg; + u32 tx_delay_step; + u32 rx_delay_step; + u32 miscr; + + bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL); + if (!bsp_priv) + return ERR_PTR(-ENOMEM); + + bsp_priv->regmap = + syscon_regmap_lookup_by_phandle_args(dev->of_node, "nuvoton,sys", 1, &macid); + if (IS_ERR(bsp_priv->regmap)) { + dev_err_probe(dev, PTR_ERR(bsp_priv->regmap), "Failed to get sys register\n"); + return ERR_PTR(-ENODEV); + } + if (macid > 1) { + dev_err_probe(dev, -EINVAL, "Invalid sys arguments\n"); + return ERR_PTR(-EINVAL); + } + + if (of_property_read_u32(dev->of_node, "tx-internal-delay-ps", &arg)) { + tx_delay_step = 0; + } else { + if (arg <= 2000) { + tx_delay_step = (arg == 2000) ? 0xf : (arg / NVT_PATH_DELAY_STEP); + dev_dbg(dev, "Set Tx path delay to 0x%x\n", tx_delay_step); + } else { + dev_err(dev, "Invalid Tx path delay argument.\n"); + return ERR_PTR(-EINVAL); + } + } + if (of_property_read_u32(dev->of_node, "rx-internal-delay-ps", &arg)) { + rx_delay_step = 0; + } else { + if (arg <= 2000) { + rx_delay_step = (arg == 2000) ? 0xf : (arg / NVT_PATH_DELAY_STEP); + dev_dbg(dev, "Set Rx path delay to 0x%x\n", rx_delay_step); + } else { + dev_err(dev, "Invalid Rx path delay argument.\n"); + return ERR_PTR(-EINVAL); + } + } + + miscr = (macid == 0) ? NVT_REG_SYS_GMAC0MISCR : NVT_REG_SYS_GMAC1MISCR; + regmap_read(bsp_priv->regmap, miscr, ®); + reg &= ~(NVT_TX_DELAY_MASK | NVT_RX_DELAY_MASK); + + if (of_get_phy_mode(pdev->dev.of_node, &phy_mode)) { + dev_err(dev, "missing phy mode property\n"); + return ERR_PTR(-EINVAL); + } + + switch (phy_mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + reg &= ~NVT_MISCR_RMII; + break; + case PHY_INTERFACE_MODE_RMII: + reg |= NVT_MISCR_RMII; + break; + default: + dev_err(dev, "Unsupported phy-mode (%d)\n", phy_mode); + return ERR_PTR(-EINVAL); + } + + if (!(reg & NVT_MISCR_RMII)) { + reg |= FIELD_PREP(NVT_TX_DELAY_MASK, tx_delay_step); + reg |= FIELD_PREP(NVT_RX_DELAY_MASK, rx_delay_step); + } + + regmap_write(bsp_priv->regmap, miscr, reg); + + bsp_priv->pdev = pdev; + + return bsp_priv; +} + +static int nvt_gmac_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat_dat; + struct stmmac_resources stmmac_res; + struct nvt_priv_data *priv_data; + int ret; + + ret = stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return ret; + + plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat_dat)) + return PTR_ERR(plat_dat); + + /* Nuvoton DWMAC configs */ + plat_dat->has_gmac = 1; + plat_dat->tx_fifo_size = 2048; + plat_dat->rx_fifo_size = 4096; + plat_dat->multicast_filter_bins = 0; + plat_dat->unicast_filter_entries = 8; + plat_dat->flags &= ~STMMAC_FLAG_USE_PHY_WOL; + + priv_data = nvt_gmac_setup(pdev, plat_dat); + if (IS_ERR(priv_data)) + return PTR_ERR(priv_data); + + ret = stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); + if (ret) + return ret; + + /* The PMT flag is determined by the RWK property. + * However, our hardware is configured to support only MGK. + * This is an override on PMT to enable WoL capability. + */ + plat_dat->pmt = 1; + device_set_wakeup_capable(&pdev->dev, 1); + + return 0; +} + +static const struct of_device_id nvt_dwmac_match[] = { + { .compatible = "nuvoton,ma35d1-dwmac"}, + { } +}; +MODULE_DEVICE_TABLE(of, nvt_dwmac_match); + +static struct platform_driver nvt_dwmac_driver = { + .probe = nvt_gmac_probe, + .remove = stmmac_pltfr_remove, + .driver = { + .name = "nuvoton-dwmac", + .pm = &stmmac_pltfr_pm_ops, + .of_match_table = nvt_dwmac_match, + }, +}; +module_platform_driver(nvt_dwmac_driver); + +MODULE_AUTHOR("Joey Lu "); +MODULE_DESCRIPTION("Nuvoton DWMAC specific glue layer"); +MODULE_LICENSE("GPL");