From patchwork Mon Feb 3 16:29:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q3PDs2vDoXMgQmVuY2U=?= X-Patchwork-Id: 13957786 Received: from fw2.prolan.hu (fw2.prolan.hu [193.68.50.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C8A020B1FF; Mon, 3 Feb 2025 16:31:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.68.50.107 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738600305; cv=none; b=hkAg4PNgCaY9E2t3B3NMnZs1jTGAlvkDJjBjY0eHZQOCz61oLOczxg4APjtCOR+fDLtqVzoL/VcllgugFHQ/8uOabawaeQJQaUSVk6Nj7Shc50Je/NQm+TDOQ50tEHgP/Y0/TkrxIOQnHwt+dqQevbxttHXOZCJRVs9Zy5pCml8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738600305; c=relaxed/simple; bh=7WvY97rkPcYSy7FrflV4pcouYWVuho/aOp5zXo4+asI=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=h4CsOGajL+jNNSQPIQDvaqVQ9/vn0EBg14nrNk0TWX3ec55/7RL2qs5RIFhVs3wZ/vwPBsQVZyE0llKiBm6ZmqBOPUOHBiKCSUFCdgy92Gf3QoUExULo9XWVS8yu71jK24uzE9dUgbvg3Q0174hCaEf9nEB8GVtpXZ1o182JTWo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=prolan.hu; spf=pass smtp.mailfrom=prolan.hu; dkim=pass (4096-bit key) header.d=prolan.hu header.i=@prolan.hu header.b=jSafp3RF; arc=none smtp.client-ip=193.68.50.107 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=prolan.hu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=prolan.hu Authentication-Results: smtp.subspace.kernel.org; dkim=pass (4096-bit key) header.d=prolan.hu header.i=@prolan.hu header.b="jSafp3RF" Received: from proxmox-mailgw.intranet.prolan.hu (localhost.localdomain [127.0.0.1]) by proxmox-mailgw.intranet.prolan.hu (Proxmox) with ESMTP id 5ECEBA0E6F; Mon, 3 Feb 2025 17:31:39 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=prolan.hu; h=cc :cc:content-transfer-encoding:content-type:content-type:date :from:from:message-id:mime-version:reply-to:subject:subject:to :to; s=mail; bh=QtYOwxhJTx1c2Lg+XxDXfdFoZZ1VSsrERd5VI5gDt44=; b= jSafp3RFz7Ra9BwVl/pKUEynT3E7/l4NiLaliLgryZiWmxsLgzIFGUNzUdQ2CiYa JLiwItIZfq6Yrnn0MKarPVvo4m4qQZhUX+nzsTdF1WFTWRQQWyu/V3NkNiVv2B8l UWkPRdscvaBMee2YMXxA6eLluDcrOVcuHHOjXlIP8bGK/FSDlWGaGwviakevvOiC eKudxH0iUhOowd/Bd2XAhYFn4Jy+cjnkWATO7nQ/nIPnjA02/2zIYO8AAWyMMpNE 6A9To7onpiUHF1FA5kwZTT9aavToSqGrO7ykKvy4ze8Hot1QuMpu435CdvRUdV/t 4TjHQHroNNmArdsdRK5PlfnxpWFDTWOTnN1eP3FzsoKHZJyTJLXoB6muuss1rlcb AYhyFxGyKLmnHtpSd0nDiEhTl7KwIUkfJyF5146k68s+jGzo/09lk6R78LwecpkR HDbc+uHvk+wdJr2AZhbDEPEdogclvBYepRxdBdybTxpU+ij8IyVK/BjBi3Aw1I8p 23yWESF/1rCNeSGE/HTzXO7TzoMJ0rWBoUKFdim9Jmc+FSaei5SYZO55SfuPObnd m86lAK85FzqM3Y+bkpO1MMkxBQ+C1bDbT5K80RB821Sc5nzfHxe49z/bIqSFFb5w Q5wq8uUy2TclIfZAFQJ/1h9dSp+iLjDzNv8YIDSfLQI= From: =?utf-8?b?QmVuY2UgQ3PDs2vDoXM=?= To: , , CC: =?utf-8?b?QmVuY2UgQ3PDs2vDoXM=?= , "Kamel Bouhara" , William Breathitt Gray Subject: [PATCH v2 1/2] counter: microchip-tcb-capture: Add IRQ handling Date: Mon, 3 Feb 2025 17:29:52 +0100 Message-ID: <20250203162955.102559-1-csokas.bence@prolan.hu> X-Mailer: git-send-email 2.48.1 Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ESET-AS: R=OK;S=0;OP=CALC;TIME=1738600298;VERSION=7984;MC=2545913080;ID=183984;TRN=0;CRV=0;IPC=;SP=0;SIPS=0;PI=3;F=0 X-ESET-Antispam: OK X-EsetResult: clean, is OK X-EsetId: 37303A2980D94852667064 Add interrupt servicing to allow userspace to wait for a trigger event. Signed-off-by: Bence Csókás --- Notes: New in v2 drivers/counter/microchip-tcb-capture.c | 60 +++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/counter/microchip-tcb-capture.c b/drivers/counter/microchip-tcb-capture.c index 2f096a5b973d..316755c7659a 100644 --- a/drivers/counter/microchip-tcb-capture.c +++ b/drivers/counter/microchip-tcb-capture.c @@ -6,10 +6,12 @@ */ #include #include +#include #include #include #include #include +#include #include #include #include @@ -18,6 +20,8 @@ ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_LDBDIS | \ ATMEL_TC_LDBSTOP) +#define ATMEL_TC_DEF_IRQS (ATMEL_TC_ETRGS | ATMEL_TC_COVFS) + #define ATMEL_TC_QDEN BIT(8) #define ATMEL_TC_POSEN BIT(9) @@ -27,6 +31,7 @@ struct mchp_tc_data { int qdec_mode; int num_channels; int channel[2]; + int irq; }; static const enum counter_function mchp_tc_count_functions[] = { @@ -294,6 +299,54 @@ static const struct of_device_id atmel_tc_of_match[] = { { /* sentinel */ } }; +static irqreturn_t mchp_tc_isr(int irq, void *dev_id) +{ + struct counter_device *const counter = dev_id; + struct mchp_tc_data *const priv = counter_priv(counter); + u32 sr, mask; + + regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], SR), &sr); + regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], IMR), &mask); + + sr &= mask; + if (!(sr & ATMEL_TC_ALL_IRQ)) + return IRQ_NONE; + + if (sr & ATMEL_TC_ETRGS) + counter_push_event(counter, COUNTER_EVENT_CHANGE_OF_STATE, 0); + if (sr & ATMEL_TC_COVFS) + counter_push_event(counter, COUNTER_EVENT_OVERFLOW, 0); + + return IRQ_HANDLED; +} + +static void mchp_tc_irq_remove(void *ptr) +{ + struct mchp_tc_data *priv = ptr; + + regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], IDR), ATMEL_TC_DEF_IRQS); +} + +static int mchp_tc_irq_enable(struct counter_device *const counter) +{ + struct mchp_tc_data *const priv = counter_priv(counter); + int ret = devm_request_irq(counter->parent, priv->irq, mchp_tc_isr, 0, + dev_name(counter->parent), counter); + + if (ret < 0) + return ret; + + ret = regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], IER), ATMEL_TC_DEF_IRQS); + if (ret < 0) + return ret; + + ret = devm_add_action_or_reset(counter->parent, mchp_tc_irq_remove, priv); + if (ret < 0) + return ret; + + return 0; +} + static void mchp_tc_clk_remove(void *ptr) { clk_disable_unprepare((struct clk *)ptr); @@ -378,6 +431,13 @@ static int mchp_tc_probe(struct platform_device *pdev) counter->num_signals = ARRAY_SIZE(mchp_tc_count_signals); counter->signals = mchp_tc_count_signals; + priv->irq = of_irq_get(np->parent, 0); + if (priv->irq > 0) { + ret = mchp_tc_irq_enable(counter); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "Failed to set up IRQ"); + } + ret = devm_counter_add(&pdev->dev, counter); if (ret < 0) return dev_err_probe(&pdev->dev, ret, "Failed to add counter\n"); From patchwork Mon Feb 3 16:29:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q3PDs2vDoXMgQmVuY2U=?= X-Patchwork-Id: 13957787 Received: from fw2.prolan.hu (fw2.prolan.hu [193.68.50.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE4D720AF8E; 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arc=none smtp.client-ip=193.68.50.107 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=prolan.hu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=prolan.hu Authentication-Results: smtp.subspace.kernel.org; dkim=pass (4096-bit key) header.d=prolan.hu header.i=@prolan.hu header.b="idGHTcRQ" Received: from proxmox-mailgw.intranet.prolan.hu (localhost.localdomain [127.0.0.1]) by proxmox-mailgw.intranet.prolan.hu (Proxmox) with ESMTP id 6E7D2A0E19; Mon, 3 Feb 2025 17:31:40 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=prolan.hu; h=cc :cc:content-transfer-encoding:content-type:content-type:date :from:from:in-reply-to:message-id:mime-version:references :reply-to:subject:subject:to:to; s=mail; bh=HK4s81J1k83QEgvXWPtd 0kbv6ClLvjUueZlqzkVxOI8=; b=idGHTcRQINOpTLzJwksjtJJDi4dieWUuSG+v gcYcbDKv3TiaHEIYmC8rW+iFS3oCDIoFtIQVHBbySXMk0P3SoFYMs48c1Uj/uSYl EhqmTJ2pzfVLYzuY5flTsnmT8kXNTKlWYsjBmI1PrApj6FTlcy+Z+ywEc0i4qEIR 6ydIRymdwJ/NBCEvAXb/gr6mrRUBoUIYzsOfnv7JB1eEt/9AWXa5D/VvVbHT03X+ XgnIat6UDbOb5e7WRc1TfzJglnxk1EVvbFvqCrIOObME6yaawX473zbWHWvtb7aJ +nmKygQTiK9lwl/saAvKQUFb0jxnYN+GQgXnQiRDTXi5Kzv1cC4oorjKy/g9Ou44 sysmA3h7PDW8iWC1npMiTL92dDSl3ELQQSvmWjOo4ZUciME/bUeWh5b8pqQ6C+LL yqGlrSHhNNTV1PFDIGYl+BiopL5XC6iqKnzpjH7sLiuZZFXl1AIIofdzuWKmqSjG tCQCJzhkKVLiiTELy0Dc8ZpdtyT9MIMx3EifRMvST/VNT1ZCTYT0/rVG/3EP95P4 kFGsZw1RAxzAefT4tJgKDtYB4dSlbfbRysX343AP0oBoZz+9qwFtjxxiv3SO8+R3 i6PTgG5SNEePWOrisksBSj9qceUxmy8Ma20F00okcxUax2Eee/x8FY4PXjArzMWV cfs0OF8= From: =?utf-8?b?QmVuY2UgQ3PDs2vDoXM=?= To: , , CC: =?utf-8?b?QmVuY2UgQ3PDs2vDoXM=?= , "Kamel Bouhara" , William Breathitt Gray Subject: [PATCH v2 2/2] counter: microchip-tcb-capture: Add capture extensions for registers RA-RC Date: Mon, 3 Feb 2025 17:29:53 +0100 Message-ID: <20250203162955.102559-2-csokas.bence@prolan.hu> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250203162955.102559-1-csokas.bence@prolan.hu> References: <20250203162955.102559-1-csokas.bence@prolan.hu> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ESET-AS: R=OK;S=0;OP=CALC;TIME=1738600299;VERSION=7984;MC=3773513757;ID=183986;TRN=0;CRV=0;IPC=;SP=0;SIPS=0;PI=3;F=0 X-ESET-Antispam: OK X-EsetResult: clean, is OK X-EsetId: 37303A2980D94852667064 TCB hardware is capable of capturing the timer value to registers RA and RB. On top, it is capable of triggering on compare against a third register, RC. Add these registers as extensions. Signed-off-by: Bence Csókás --- drivers/counter/microchip-tcb-capture.c | 65 ++++++++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-) diff --git a/drivers/counter/microchip-tcb-capture.c b/drivers/counter/microchip-tcb-capture.c index 316755c7659a..a25b54493c7f 100644 --- a/drivers/counter/microchip-tcb-capture.c +++ b/drivers/counter/microchip-tcb-capture.c @@ -20,7 +20,8 @@ ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_LDBDIS | \ ATMEL_TC_LDBSTOP) -#define ATMEL_TC_DEF_IRQS (ATMEL_TC_ETRGS | ATMEL_TC_COVFS) +#define ATMEL_TC_DEF_IRQS (ATMEL_TC_ETRGS | ATMEL_TC_COVFS | \ + ATMEL_TC_LDRAS | ATMEL_TC_LDRBS) #define ATMEL_TC_QDEN BIT(8) #define ATMEL_TC_POSEN BIT(9) @@ -252,6 +253,62 @@ static int mchp_tc_count_read(struct counter_device *counter, return 0; } +static int mchp_tc_count_cap_read(struct counter_device *counter, + struct counter_count *count, size_t idx, u64 *val) +{ + struct mchp_tc_data *const priv = counter_priv(counter); + u32 cnt; + + switch (idx) { + case 0: + regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], RA), &cnt); + break; + case 1: + regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], RB), &cnt); + break; + case 2: + regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], RC), &cnt); + break; + default: + return -EINVAL; + } + *val = cnt; + + return 0; +} + +static int mchp_tc_count_cap_write(struct counter_device *counter, + struct counter_count *count, size_t idx, u64 val) +{ + struct mchp_tc_data *const priv = counter_priv(counter); + + if (val > U32_MAX) + return -ERANGE; + + switch (idx) { + case 0: + regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], RA), val); + break; + case 1: + regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], RB), val); + break; + case 2: + regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], RC), val); + break; + default: + return -EINVAL; + } + + return 0; +} + +static DEFINE_COUNTER_ARRAY_CAPTURE(mchp_tc_cnt_cap_array, 3); + +static struct counter_comp mchp_tc_count_ext[] = { + COUNTER_COMP_ARRAY_CAPTURE(mchp_tc_count_cap_read, mchp_tc_count_cap_write, + mchp_tc_cnt_cap_array), +}; + static struct counter_count mchp_tc_counts[] = { { .id = 0, @@ -260,6 +317,8 @@ static struct counter_count mchp_tc_counts[] = { .num_functions = ARRAY_SIZE(mchp_tc_count_functions), .synapses = mchp_tc_count_synapses, .num_synapses = ARRAY_SIZE(mchp_tc_count_synapses), + .ext = mchp_tc_count_ext, + .num_ext = ARRAY_SIZE(mchp_tc_count_ext), }, }; @@ -314,6 +373,10 @@ static irqreturn_t mchp_tc_isr(int irq, void *dev_id) if (sr & ATMEL_TC_ETRGS) counter_push_event(counter, COUNTER_EVENT_CHANGE_OF_STATE, 0); + if (sr & ATMEL_TC_LDRAS) + counter_push_event(counter, COUNTER_EVENT_CAPTURE, 0); + if (sr & ATMEL_TC_LDRBS) + counter_push_event(counter, COUNTER_EVENT_CAPTURE, 1); if (sr & ATMEL_TC_COVFS) counter_push_event(counter, COUNTER_EVENT_OVERFLOW, 0);