From patchwork Mon Feb 3 21:29:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 13958264 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 822A121018D; Mon, 3 Feb 2025 21:29:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738618175; cv=none; b=VNIRId72flcw9FjjAwxSoS+HnVr2SIt+8HHqBJUXVKY7vKo1RwelatKjW3WbiD1lCMUnOdt/t8pSi74D7nqff9gRVRwIMRgojIpRVGxfG/1VdF5n1jE7zV1JTF4fW5BrxVHRDpjtX7Ai8KvRsnGxRzwEj341RK3oU5OjLrtInZ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738618175; c=relaxed/simple; bh=BebvpPREciDqkWSJZ64d5uD1fgdX0OpQuYFwZj5JRgM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=H1uzctoeLlAQ6gulEIua4iyk/tJT6+OtfKAVPiUtqrgqn8jBJRqvY7cxGrK/lt2pNr/GGuSpPUHrEztciST7dNjp75x5POe24bnuobWaNClhaz17hHc24zZJ9Gds67mFg0+PN7bvYbu+LWBXJh6F9eG7gzyW6S6dwrHWnLKKtfU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eEm1LcU+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eEm1LcU+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B3E5BC4CEE3; Mon, 3 Feb 2025 21:29:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738618175; bh=BebvpPREciDqkWSJZ64d5uD1fgdX0OpQuYFwZj5JRgM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=eEm1LcU+ACo0yxGrYyt9C4HmP7/4/Qh0O04OBFHKGwkjI+smn3Lb30EyoZOu9yKzj X1pqMpJh/jkO8zqibLiS5IUnsHB1LklGpH2CWQ8o39gqGkdTrkhNzZaLeWKY3OE1m3 691eCwS69+ZYI5WJsU/YmKpSzWT+432adlTzm3dcEyq6xxBEM17h9qBMbQmBd+nZYe N3wDwZt7iZW89jIBGlvwHfnEIpmo4O8bFSCG0UlEUpTNwpVAZP4uOxSIIhOG9iPtDv yP2/XI2mq46aBhDacgiJW4O7tirUECBA2Y/6YIHgPSLbSD5ZJ0JMAoZqzj/P4FNRta ZqSUpng4m16FQ== From: "Rob Herring (Arm)" Date: Mon, 03 Feb 2025 15:29:13 -0600 Subject: [PATCH 1/4] dt-bindings: memory-controllers: Move qcom,ebi2 from bindings/bus/ Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250203-dt-lan9115-fix-v1-1-eb35389a7365@kernel.org> References: <20250203-dt-lan9115-fix-v1-0-eb35389a7365@kernel.org> In-Reply-To: <20250203-dt-lan9115-fix-v1-0-eb35389a7365@kernel.org> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Marek Vasut , Alim Akhtar , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Shawn Guo Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, netdev@vger.kernel.org X-Mailer: b4 0.15-dev The preferred location for external parallel/memory buses is in memory-controllers. 'bus' is generally for internal chip buses. Signed-off-by: Rob Herring (Arm) Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/{bus => memory-controllers}/qcom,ebi2.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/bus/qcom,ebi2.yaml b/Documentation/devicetree/bindings/memory-controllers/qcom,ebi2.yaml similarity index 99% rename from Documentation/devicetree/bindings/bus/qcom,ebi2.yaml rename to Documentation/devicetree/bindings/memory-controllers/qcom,ebi2.yaml index 1b1fb3538e6e..c782bfd7af92 100644 --- a/Documentation/devicetree/bindings/bus/qcom,ebi2.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/qcom,ebi2.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/bus/qcom,ebi2.yaml# +$id: http://devicetree.org/schemas/memory-controllers/qcom,ebi2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm External Bus Interface 2 (EBI2) From patchwork Mon Feb 3 21:29:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 13958265 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27F4021146C; Mon, 3 Feb 2025 21:29:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738618177; cv=none; b=SgnDDDIot/zsritswnk4yjEZrbLjGfBud0qtfOhmom0zs2QP2OUOy16ui0JXlP9Cfr4YbLdgKEEVtWDB+CQpl5dljZgCzuMlVROIOcU4njzlT3UlAPMTJoZ+tFGnn31uQVFR9lEI/tj+o4aKL4ErIiczkcuDZHP1wdKFu7U8XUQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738618177; c=relaxed/simple; bh=cGkVbIvG/XxxfatOLtOOWpw1ze9gCGpJh6mDqiLiBfk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GhoMk43NP1ZG4OwKpq8Lfx1S9A3W9Jmqnq/pMjBcSfmvtDPUc25yREY1i6Q/9Wx17HV614aJAZMvaVSrgivk7P1NSBVi7abq1zw+e7kcs06kcn1AP7Lw+srKyIaMitdky12cZB4TkpZSuYklWpxUdPQpwZ/3yEBGheU58O+NzK4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JK2NiJkJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JK2NiJkJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4D761C4CEE4; Mon, 3 Feb 2025 21:29:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738618176; bh=cGkVbIvG/XxxfatOLtOOWpw1ze9gCGpJh6mDqiLiBfk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=JK2NiJkJCMwecG43ZQb8jKCxFNvHo/NgS2l/fqpkYER+gg9Ec6N3MBVfMkIp0OwFM V7YGfb100Rh3pI9kqDbXIZ7h4uc+oGi8guNy/5bNz/AvxJRfdleVcsjRfAASRTpaVt 2UdPgqlc1T6inuInp0so9hvmkdJRTk1Zb4hGPoQEZ1dmL9mMVuonD3kheF7KCHVPja sAoG724u6WX9tZDcuNhpxokIJizwebziOxjVsMWuBvUYKR3EyrPmLbUjex2BhuF67+ vgOQq6SqITBppXiygN4BrdHfaJrFrAU18c7x/ZxH/bgR5R3sBEvdXF7qLF0dz0J7h8 DIe72yGParx7w== From: "Rob Herring (Arm)" Date: Mon, 03 Feb 2025 15:29:14 -0600 Subject: [PATCH 2/4] dt-bindings: memory-controllers: qcom,ebi2: Split out child node properties Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250203-dt-lan9115-fix-v1-2-eb35389a7365@kernel.org> References: <20250203-dt-lan9115-fix-v1-0-eb35389a7365@kernel.org> In-Reply-To: <20250203-dt-lan9115-fix-v1-0-eb35389a7365@kernel.org> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Marek Vasut , Alim Akhtar , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Shawn Guo Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, netdev@vger.kernel.org X-Mailer: b4 0.15-dev In order to validate devices in child nodes, the device schemas need to reference any child node properties. In order to do that, the properties for child nodes need to be included in mc-peripheral-props.yaml. "reg: { maxItems: 1 }" was also incorrect. It's up to the device schemas how many reg entries they have. Signed-off-by: Rob Herring (Arm) Reviewed-by: Krzysztof Kozlowski --- .../memory-controllers/mc-peripheral-props.yaml | 1 + .../qcom,ebi2-peripheral-props.yaml | 91 ++++++++++++++++++++++ .../bindings/memory-controllers/qcom,ebi2.yaml | 84 -------------------- 3 files changed, 92 insertions(+), 84 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml b/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml index 00deeb09f87d..11bc8a33d022 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml @@ -36,6 +36,7 @@ allOf: - $ref: st,stm32-fmc2-ebi-props.yaml# - $ref: ingenic,nemc-peripherals.yaml# - $ref: intel,ixp4xx-expansion-peripheral-props.yaml# + - $ref: qcom,ebi2-peripheral-props.yaml# - $ref: ti,gpmc-child.yaml# - $ref: fsl/fsl,imx-weim-peripherals.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/qcom,ebi2-peripheral-props.yaml b/Documentation/devicetree/bindings/memory-controllers/qcom,ebi2-peripheral-props.yaml new file mode 100644 index 000000000000..29f8c30e8a88 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/qcom,ebi2-peripheral-props.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/qcom,ebi2-peripheral-props.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Peripheral Properties for Qualcomm External Bus Interface 2 (EBI2) + +maintainers: + - Bjorn Andersson + +properties: + # SLOW chip selects + qcom,xmem-recovery-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The time the memory continues to drive the data bus after OE + is de-asserted, in order to avoid contention on the data bus. + They are inserted when reading one CS and switching to another + CS or read followed by write on the same CS. Minimum value is + actually 1, so a value of 0 will still yield 1 recovery cycle. + minimum: 0 + maximum: 15 + + qcom,xmem-write-hold-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The extra cycles inserted after every write minimum 1. The + data out is driven from the time WE is asserted until CS is + asserted. With a hold of 1 (value = 0), the CS stays active + for 1 extra cycle, etc. + minimum: 0 + maximum: 15 + + qcom,xmem-write-delta-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The initial latency for write cycles inserted for the first + write to a page or burst memory. + minimum: 0 + maximum: 255 + + qcom,xmem-read-delta-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The initial latency for read cycles inserted for the first + read to a page or burst memory. + minimum: 0 + maximum: 255 + + qcom,xmem-write-wait-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The number of wait cycles for every write access. + minimum: 0 + maximum: 15 + + qcom,xmem-read-wait-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The number of wait cycles for every read access. + minimum: 0 + maximum: 15 + + + # FAST chip selects + qcom,xmem-address-hold-enable: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + Holds the address for an extra cycle to meet hold time + requirements with ADV assertion, when set to 1. + enum: [ 0, 1 ] + + qcom,xmem-adv-to-oe-recovery-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The number of cycles elapsed before an OE assertion, with + respect to the cycle where ADV (address valid) is asserted. + minimum: 0 + maximum: 3 + + qcom,xmem-read-hold-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The length in cycles of the first segment of a read transfer. + For a single read transfer this will be the time from CS + assertion to OE assertion. + minimum: 0 + maximum: 15 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/memory-controllers/qcom,ebi2.yaml b/Documentation/devicetree/bindings/memory-controllers/qcom,ebi2.yaml index c782bfd7af92..3e6da1ba460e 100644 --- a/Documentation/devicetree/bindings/memory-controllers/qcom,ebi2.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/qcom,ebi2.yaml @@ -105,90 +105,6 @@ patternProperties: "^.*@[0-5],[0-9a-f]+$": type: object additionalProperties: true - properties: - reg: - maxItems: 1 - - # SLOW chip selects - qcom,xmem-recovery-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The time the memory continues to drive the data bus after OE - is de-asserted, in order to avoid contention on the data bus. - They are inserted when reading one CS and switching to another - CS or read followed by write on the same CS. Minimum value is - actually 1, so a value of 0 will still yield 1 recovery cycle. - minimum: 0 - maximum: 15 - - qcom,xmem-write-hold-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The extra cycles inserted after every write minimum 1. The - data out is driven from the time WE is asserted until CS is - asserted. With a hold of 1 (value = 0), the CS stays active - for 1 extra cycle, etc. - minimum: 0 - maximum: 15 - - qcom,xmem-write-delta-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The initial latency for write cycles inserted for the first - write to a page or burst memory. - minimum: 0 - maximum: 255 - - qcom,xmem-read-delta-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The initial latency for read cycles inserted for the first - read to a page or burst memory. - minimum: 0 - maximum: 255 - - qcom,xmem-write-wait-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The number of wait cycles for every write access. - minimum: 0 - maximum: 15 - - qcom,xmem-read-wait-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The number of wait cycles for every read access. - minimum: 0 - maximum: 15 - - - # FAST chip selects - qcom,xmem-address-hold-enable: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - Holds the address for an extra cycle to meet hold time - requirements with ADV assertion, when set to 1. - enum: [ 0, 1 ] - - qcom,xmem-adv-to-oe-recovery-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The number of cycles elapsed before an OE assertion, with - respect to the cycle where ADV (address valid) is asserted. - minimum: 0 - maximum: 3 - - qcom,xmem-read-hold-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The length in cycles of the first segment of a read transfer. - For a single read transfer this will be the time from CS - assertion to OE assertion. - minimum: 0 - maximum: 15 - - required: - - reg additionalProperties: false From patchwork Mon Feb 3 21:29:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 13958266 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 556AF2116E6; Mon, 3 Feb 2025 21:29:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738618178; cv=none; b=cUV+0glG3Nd11C4kO+vqQZg4lqS/RplNYmYh0Ru0eZw/9Y7/gj8CRbuLkIWVj1vTlc6edMgfWYfIbIjKNo4oAH9Rheg6Xtwse9Ah/CHSqH/kYdxHncyVUFPKgVojoQw/fHCg71XxxBWGFjdlN3jJMjng/ZrkZsUcXRe8/C4ilWo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738618178; c=relaxed/simple; bh=RF8z5IkLWRWlkl8kiu4Ok3ly//aRtzCNoqKbBGSPoZw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iUG2ANQSIay2PStyR4LANFY8up6td0dPSW7EekTLJBysuBotQ2jHZt1pCGYH44m8yKJG6cKdJMtyWsRDqnJRas9DumGeRswJdNkO6N1CYPEyoO90armao11GGLi0jSTyYuMQYDVJySZbMoiM0QU+4Chc1LqH7TedRgXoRNw6jm8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=sjOS3fBu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="sjOS3fBu" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E08E0C4CED2; Mon, 3 Feb 2025 21:29:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738618178; bh=RF8z5IkLWRWlkl8kiu4Ok3ly//aRtzCNoqKbBGSPoZw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=sjOS3fBun6gJfTunSEIpUzeHTTH1z6nualUxXNGopDLxaNuLTyGD1PTwU7RqLk8Qz y46xROZwOOXfauiUtxcGQ5wYu5IUpEt3Uh5uNCrtwabyAtVsg7ULXsGs409bHTOPof goq3qqzEf3S9Hl9MuyC2hMK8iHGSRubR8GmI8JXQE9r9Pm7RZeqmp6rsXau/vQVwdm H4n7ZF8F/gxIJXZejKAalPJYIy+/sAOd2399+iG83srbx+o9jKLA11UtlNRAoyKoF5 I/s/iGaFqFkwyEDzI0MgpvdCdGWA7kpIllSkbaeeaOMGHLPrm3LHpnGPfBTwaW1wmO eCS4k1dHSUOYw== From: "Rob Herring (Arm)" Date: Mon, 03 Feb 2025 15:29:15 -0600 Subject: [PATCH 3/4] dt-bindings: memory-controllers: samsung,exynos4210-srom: Split out child node properties Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250203-dt-lan9115-fix-v1-3-eb35389a7365@kernel.org> References: <20250203-dt-lan9115-fix-v1-0-eb35389a7365@kernel.org> In-Reply-To: <20250203-dt-lan9115-fix-v1-0-eb35389a7365@kernel.org> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Marek Vasut , Alim Akhtar , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Shawn Guo Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, netdev@vger.kernel.org X-Mailer: b4 0.15-dev In order to validate devices in child nodes, the device schemas need to reference any child node properties. In order to do that, the properties for child nodes need to be included in mc-peripheral-props.yaml. "reg: { maxItems: 1 }" was also incorrect. It's up to the device schemas how many reg entries they have. Signed-off-by: Rob Herring (Arm) Reviewed-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/exynos-srom.yaml | 35 ---------------------- .../memory-controllers/mc-peripheral-props.yaml | 1 + .../samsung,exynos4210-srom-peripheral-props.yaml | 35 ++++++++++++++++++++++ 3 files changed, 36 insertions(+), 35 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml b/Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml index a5598ade399f..2267c5107d60 100644 --- a/Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml @@ -39,49 +39,14 @@ patternProperties: "^.*@[0-3],[a-f0-9]+$": type: object additionalProperties: true - description: - The actual device nodes should be added as subnodes to the SROMc node. - These subnodes, in addition to regular device specification, should - contain the following properties, describing configuration - of the relevant SROM bank. properties: - reg: - description: - Bank number, base address (relative to start of the bank) and size - of the memory mapped for the device. Note that base address will be - typically 0 as this is the start of the bank. - maxItems: 1 - reg-io-width: enum: [1, 2] description: Data width in bytes (1 or 2). If omitted, default of 1 is used. - samsung,srom-page-mode: - description: - If page mode is set, 4 data page mode will be configured, - else normal (1 data) page mode will be set. - type: boolean - - samsung,srom-timing: - $ref: /schemas/types.yaml#/definitions/uint32-array - minItems: 6 - maxItems: 6 - description: | - Array of 6 integers, specifying bank timings in the following order: - Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs. - Each value is specified in cycles and has the following meaning - and valid range: - Tacp: Page mode access cycle at Page mode (0 - 15) - Tcah: Address holding time after CSn (0 - 15) - Tcoh: Chip selection hold on OEn (0 - 15) - Tacc: Access cycle (0 - 31, the actual time is N + 1) - Tcos: Chip selection set-up before OEn (0 - 15) - Tacs: Address set-up before CSn (0 - 15) - required: - - reg - samsung,srom-timing required: diff --git a/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml b/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml index 11bc8a33d022..73a6dac946b7 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml @@ -37,6 +37,7 @@ allOf: - $ref: ingenic,nemc-peripherals.yaml# - $ref: intel,ixp4xx-expansion-peripheral-props.yaml# - $ref: qcom,ebi2-peripheral-props.yaml# + - $ref: samsung,exynos4210-srom-peripheral-props.yaml# - $ref: ti,gpmc-child.yaml# - $ref: fsl/fsl,imx-weim-peripherals.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml new file mode 100644 index 000000000000..c474f90846e5 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Peripheral Properties for Samsung Exynos SoC SROM Controller + +maintainers: + - Krzysztof Kozlowski + +properties: + samsung,srom-page-mode: + description: + If page mode is set, 4 data page mode will be configured, + else normal (1 data) page mode will be set. + type: boolean + + samsung,srom-timing: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 6 + maxItems: 6 + description: | + Array of 6 integers, specifying bank timings in the following order: + Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs. + Each value is specified in cycles and has the following meaning + and valid range: + Tacp: Page mode access cycle at Page mode (0 - 15) + Tcah: Address holding time after CSn (0 - 15) + Tcoh: Chip selection hold on OEn (0 - 15) + Tacc: Access cycle (0 - 31, the actual time is N + 1) + Tcos: Chip selection set-up before OEn (0 - 15) + Tacs: Address set-up before CSn (0 - 15) + +additionalProperties: true From patchwork Mon Feb 3 21:29:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 13958267 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EB77211A0E; Mon, 3 Feb 2025 21:29:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738618180; cv=none; b=Cfch91IWsFD78g1Ez55kIkZMN3aO041CPdFMmCBJTRdnbDYflPGEDetO4cyB/wqQIFvqXglZEyn4s1rwoYgV6H0yuPRqMEMAMPPuRCj0i/asL4sGij7n91LhkesiXbbxMShnKxSyAmdfdlJJipwsnnlakya8UhkzcuslViooQzE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738618180; c=relaxed/simple; bh=gH86BnBn1M4iZA8c/LY0iT+xjsDYLG4Lpb3OpxlxBX0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=msVlyi3Uv6ogpETfkLMj2fylAghUKWgD0l8T4mCa3sNGNt6u83+cXfStv1DZEV90Bzc4b+WjDNQngBe9YXYTFYpHRYtTvRIIvs1+z0tTY1A/ofZrmwVZ5iEzUtW6DiPsigpb5KcnXo8kFSWqhhYHrS6KP8QpNbxGPpIjq5Uq/v4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ViNi5+at; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ViNi5+at" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 86F8CC4CEE3; Mon, 3 Feb 2025 21:29:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738618179; bh=gH86BnBn1M4iZA8c/LY0iT+xjsDYLG4Lpb3OpxlxBX0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ViNi5+atd52ZE2v0na/nWMNohfRf5VMWshiKPTgLSEkgGjw1LZ7nzVD41O1hjsP4g njZTdAUeoQ9KSvJwqn2rqtqwiIIMUn0Mj7/nkCwHFGp3MgX1/8RNXBIC7VSthXIVtu t0m7MtdUlj1rgrDQXEUq60TeBAdjRrtYEZv8l8orFj0e25fY7bbCxkSltgrgJuUnOq uHF6tCE+OT/drh+aumnOFYdIZ2T/lErOxoMLacLt0uAk6n34Bvs/aH/azIEbyHvoRc 5iP6zFmUKURefAzd1p7NLHr2l/GpcOXan2C5aYCLCn1BJywy7C74sycMpegqE/cHo/ uQf5wqyD+9Myg== From: "Rob Herring (Arm)" Date: Mon, 03 Feb 2025 15:29:16 -0600 Subject: [PATCH 4/4] dt-bindings: net: smsc,lan9115: Ensure all properties are defined Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250203-dt-lan9115-fix-v1-4-eb35389a7365@kernel.org> References: <20250203-dt-lan9115-fix-v1-0-eb35389a7365@kernel.org> In-Reply-To: <20250203-dt-lan9115-fix-v1-0-eb35389a7365@kernel.org> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Marek Vasut , Alim Akhtar , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Shawn Guo Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, netdev@vger.kernel.org X-Mailer: b4 0.15-dev Device specific schemas should not allow undefined properties which is what 'additionalProperties: true' allows. Add a reference to mc-peripheral-props.yaml which has the additional properties used, and fix this constraint. Signed-off-by: Rob Herring (Arm) Acked-by: Jakub Kicinski Reviewed-by: Krzysztof Kozlowski --- Please ack and I'll take the series. --- Documentation/devicetree/bindings/net/smsc,lan9115.yaml | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/net/smsc,lan9115.yaml b/Documentation/devicetree/bindings/net/smsc,lan9115.yaml index f86667cbcca8..42279ae8c2b9 100644 --- a/Documentation/devicetree/bindings/net/smsc,lan9115.yaml +++ b/Documentation/devicetree/bindings/net/smsc,lan9115.yaml @@ -11,6 +11,7 @@ maintainers: allOf: - $ref: ethernet-controller.yaml# + - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml# properties: compatible: @@ -89,10 +90,7 @@ required: - reg - interrupts -# There are lots of bus-specific properties ("qcom,*", "samsung,*", "fsl,*", -# "gpmc,*", ...) to be found, that actually depend on the compatible value of -# the parent node. -additionalProperties: true +unevaluatedProperties: false examples: - |