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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Jianbo Liu , Moshe Shemesh , Leon Romanovsky , Mark Bloch , Carolina Jubran , Dragos Tatulea , Tariq Toukan Subject: [PATCH net-next 01/15] net/mlx5: Add helper functions for PTP callbacks Date: Mon, 3 Feb 2025 23:35:02 +0200 Message-ID: <20250203213516.227902-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250203213516.227902-1-tariqt@nvidia.com> References: <20250203213516.227902-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002321:EE_|PH7PR12MB7987:EE_ X-MS-Office365-Filtering-Correlation-Id: 3b490361-5a5d-4976-b69e-08dd449ad35b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024; X-Microsoft-Antispam-Message-Info: /H/n99tBjOMebn0yJRw/iIghbE97Y4MXMiQ3O1JkDRTBEj9dEGGivtrG7eu4aqoprLqVDIqHLLixA+tjTV1nXWame2qWWyfvGdgHzb7XiThGkNeASsudAGyfkS3OgOJYUfPTic+0PVuGpifgOwDPv8NUdRlRF4ZJ/go15T4Z5l8fkrYVWP1OyBwgldqzO7q1ZCp4BCOHw2k2RH2NJKcuaJOuugbP/eVjbwNqHCPI1UKlCbWIbpFFZgmvbPgoREZ8/mmsUrHDsf3/sJg6yaWKGafRhPPWq/CMC0oNux0mQ49P4giTyvB2aAGq1OxvYRm60IGYhDi4h+RECSw5rEoCdftJ/jrtUwLPoDRzvMFzFdiVVD5IJUWQ2GKoaRIkbfcYG+3pgL5SD6BwLgZmyeBnTC8do01c57hchJHtvRXYmLU86DFY4ZxNNmrBZpQ6pXSqzj9cXafIQ4dZHrZvFvH4TkoryHbsX9CjNhM8MGR3cl5Fb5vH81ej5Fsa3AMk1OjbIFtG0WAseF38/S+W8cfXKfJjxtzuw4kKlyH97pYz8K8Z6e2C4fM3XGv8pRHZY7/5ehTFpjFSYZ6+MmBY+geyCBJsmNwPWKtZuJa1dfNPQxIOWii9vCIBzD43wEdW8qt7HFfVQAkOvAQBqvfyZoQREHMeTes/XpBLDhTsBTCyB7wqDsRx9wRPQss30cccIQTbIIgCjkICD/oaDXi6Gt7yRcXT6wi/uSzh+GlDahiZdzvhXa3AiWCyn1y1THp9eE5Ywpql/N0JrM/UrFfn6pU2Qt6BROGqk/fdeLjEmzwQBs60QuKVVk5Ly0Z6xsspVQ2Lmp0ctpKExuytTflISnBSrgLESpK7oIK85FiquttaAdmABUDdELFdY50aOgnulIxyayDpMnK+WUNCKkn8H+YQPA9KqLubwkvUTIm1ATJ0l+tjTAHrCJF0kFSS1W0jql6NkC5bloxVPvwSkkXxmyh1o/E82GtiojY2xfRQQlSP0Pu5hDmTXin7Z6O9qAJnkovl3eGB5OON2j3Nc6T+BBLkTYmb5JPnOgBdL4MmodLGLWKtAQnCBxI9aGPaxJu3RobX22YcFNoMUSGuRGdYV+vGZx5uw0kCDbh4coTOT6kLAcNgQqdvdXKxzxPemlNCY6T0J/r5FKLh3Eupz0hWNbxvkIu6sic8XcD/WvBrRzskTcVQLk599sFU+S61fvupng29Q5af4/CfYcrkbUG25Ve7C2dKmfuPvr9nGqPHLsfkGvL1SUjaF86Pto/v1qbD0ccVnsnzLNvzyIMJmWOtWzAEpRkczcsckEOJGuM6PFjWj02TjIeVuQdVPsLvyNm7M76jxc3mU7CgN6rfbkBjdllTWysxys+pLI4VQi/TIf0eVSiW67q7NZ5OkTtcuu5zZVoMn7Hk/jj27fKY3miTUQ1dhCoaKU18Brk6H06CMdTL+Uo448gfu12yamhKhtr+0F/NOFql4IJYVpfLnhADMeoX/2Fk3crLzV9KzAmUEaujmBc= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2025 21:36:31.7665 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3b490361-5a5d-4976-b69e-08dd449ad35b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002321.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7987 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu The PTP callback functions should not be used directly by internal callers. Add helpers that can be used internally and externally. Signed-off-by: Jianbo Liu Reviewed-by: Carolina Jubran Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan Reviewed-by: Mateusz Polchlopek --- .../ethernet/mellanox/mlx5/core/lib/clock.c | 32 +++++++++++++------ 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index d61a1a9297c9..eaf343756026 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -119,6 +119,13 @@ static u32 mlx5_ptp_shift_constant(u32 dev_freq_khz) ilog2((U32_MAX / NSEC_PER_MSEC) * dev_freq_khz)); } +static s32 mlx5_clock_getmaxphase(struct mlx5_core_dev *mdev) +{ + return MLX5_CAP_MCAM_FEATURE(mdev, mtutc_time_adjustment_extended_range) ? + MLX5_MTUTC_OPERATION_ADJUST_TIME_EXTENDED_MAX : + MLX5_MTUTC_OPERATION_ADJUST_TIME_MAX; +} + static s32 mlx5_ptp_getmaxphase(struct ptp_clock_info *ptp) { struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); @@ -126,14 +133,12 @@ static s32 mlx5_ptp_getmaxphase(struct ptp_clock_info *ptp) mdev = container_of(clock, struct mlx5_core_dev, clock); - return MLX5_CAP_MCAM_FEATURE(mdev, mtutc_time_adjustment_extended_range) ? - MLX5_MTUTC_OPERATION_ADJUST_TIME_EXTENDED_MAX : - MLX5_MTUTC_OPERATION_ADJUST_TIME_MAX; + return mlx5_clock_getmaxphase(mdev); } static bool mlx5_is_mtutc_time_adj_cap(struct mlx5_core_dev *mdev, s64 delta) { - s64 max = mlx5_ptp_getmaxphase(&mdev->clock.ptp_info); + s64 max = mlx5_clock_getmaxphase(mdev); if (delta < -max || delta > max) return false; @@ -361,15 +366,12 @@ static int mlx5_ptp_settime_real_time(struct mlx5_core_dev *mdev, return mlx5_set_mtutc(mdev, in, sizeof(in)); } -static int mlx5_ptp_settime(struct ptp_clock_info *ptp, const struct timespec64 *ts) +static int mlx5_clock_settime(struct mlx5_core_dev *mdev, struct mlx5_clock *clock, + const struct timespec64 *ts) { - struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); struct mlx5_timer *timer = &clock->timer; - struct mlx5_core_dev *mdev; unsigned long flags; - mdev = container_of(clock, struct mlx5_core_dev, clock); - if (mlx5_modify_mtutc_allowed(mdev)) { int err = mlx5_ptp_settime_real_time(mdev, ts); @@ -385,6 +387,16 @@ static int mlx5_ptp_settime(struct ptp_clock_info *ptp, const struct timespec64 return 0; } +static int mlx5_ptp_settime(struct ptp_clock_info *ptp, const struct timespec64 *ts) +{ + struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); + struct mlx5_core_dev *mdev; + + mdev = container_of(clock, struct mlx5_core_dev, clock); + + return mlx5_clock_settime(mdev, clock, ts); +} + static struct timespec64 mlx5_ptp_gettimex_real_time(struct mlx5_core_dev *mdev, struct ptp_system_timestamp *sts) @@ -1129,7 +1141,7 @@ static void mlx5_init_timer_clock(struct mlx5_core_dev *mdev) struct timespec64 ts; ktime_get_real_ts64(&ts); - mlx5_ptp_settime(&clock->ptp_info, &ts); + mlx5_clock_settime(mdev, clock, &ts); } } From patchwork Mon Feb 3 21:35:03 2025 Content-Type: text/plain; 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Mon, 3 Feb 2025 13:36:10 -0800 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Jianbo Liu , Moshe Shemesh , Leon Romanovsky , Mark Bloch , Carolina Jubran , Dragos Tatulea , Tariq Toukan Subject: [PATCH net-next 02/15] net/mlx5: Change parameters for PTP internal functions Date: Mon, 3 Feb 2025 23:35:03 +0200 Message-ID: <20250203213516.227902-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250203213516.227902-1-tariqt@nvidia.com> References: <20250203213516.227902-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F61:EE_|CYYPR12MB8653:EE_ X-MS-Office365-Filtering-Correlation-Id: 9f5781b1-3d05-4849-3b69-08dd449ad2f5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014; X-Microsoft-Antispam-Message-Info: 5DpSzFAJAed31Ak9xKFqYSrjJ87/AQhLtUnWmPeVXm172PvR6PO4p9bLX5614d/IvNMiC5b4mN2BzLBZYBBe13V5939+mgNNtP9sIOPnLWYie+tuKX+khh09LeJdtINX79izKzG6RLercd34Q8RvYQdE65BnXrNvVvlGdjiwoOj/PS0TRVg7b5uf5usjNt23DGTO+f3px+8QzZEadxMwsYlWO34Q7NUJBaY5Pb3dCdm0B+Vz1Qir9w/nycYCSXNiKNSHiYnTWPxKv9HpJIbxVuj8gACCnfIUOgCwbhdGummlOs7nXP1uIMX/Mv3TcC+AUF1muH4MVO4Gj6CrV6Lx9uTk/A0NeSp8lzZrXW8O1wFjkGeK7yI74jIEdgLhI/syWdst25Gacc5ZOrbDd7VpzeOSsJSMR9P00eGV1Lw4cJzGdOEy1co6cVu5Oh4zgpf95fcEJkLt1p7HKnfbFKbp7OG8ukSGptEauJbvI+hnXS/Img1JloEW7qnHWoSXdtPYbbJaBvgproZp24lvA0M/FqSpKO/GeiQlxgb/fgKPNY87cDAQM+mxuAmFkz13yr50kiTfX4lGpOU0QyBUXoK+Qd1MQZntXe94ZqZUePSHCq2FjKyVo14V+AYnziFkB9HgPN/UaJ+jq37ojpKxHSiZKfLl39NZ84FmWQq5+h517E6QmZKoemQz6mzwd/Bf9lDDvrsHfGTdNB5m4n8ml0ydQeRCYkOig+58x93UuOCexfZU65kYAPLrUqR1LJhgHcJU0IOqGCf5aUoe7IisK+hhR9HKFxpD2s5p5OzkESXRcKdoIbJU/LHv1ABJH9wMQrLE/OxgBCg7WDyUWQjkMT4GJqwNtbqbugEtZmpiUZimM37+CqkSM82w2k5ObnqRue+2elh0kZqABTYU7FHSIy9gQAPjmRWnLselcWwbbPQqWSOv6+Oh+kGtzphZ7MWmP1FOHnc69sl/bzn79E7BP1pLVNvPSF9saq7Lcsu/gXQrZhzqPvacwTGzdTlLxFc5ub/eRGlxkHDsQWVUIu1NHx3uE8Q3Db5vGeXW32lzW7EQ8ko6h2jRMhHrBa0+HUJbF20oemW4LAAmyhTsVifbHrwEAEJJCiAkQp/rzNoGk4J6miNEdzyUfm6a+pMckbpO+g9ck7VyA+D3fTd+vwT+G5hjTgJPUedmeY0v3raLnqkdlFBKKS9ecfxM1TgttIwA+ukHR3DDm+jL0mnaQC4II4rxdT6qZdfQ8siER22zrcKWfd7gLp3aqpSCs8p7uYuogl6RHWaw5lx+xaNhAJUvMFiAi1qjtqB0nr29hiaxMPoWQPvqhPIDSe/bsMgk7abdDETRugKyoD8f6nr8kxGqoe2MDXEA+DqrPDqOkzi2waBNhi7Ai/kGqSRFTebb3hZYBp+cNG+FGSJ0RGA0tz5vwa7zPFEFQpmkiUMAKJ5bdBsqMHG1k3yoV3iIRD2+9n7IT3UP/4tR7jH5E1ZgR9+gsadHGwqG25e9IU8y8uldRc0DpR8= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2025 21:36:31.0011 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f5781b1-3d05-4849-3b69-08dd449ad2f5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F61.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8653 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu In later patch, the mlx5_clock will be allocated dynamically, its address can be obtained from mlx5_core_dev struct, but mdev can't be obtained from mlx5_clock because it can be shared by multiple interfaces. So change the parameter for such internal functions, only mdev is passed down from the callers. Signed-off-by: Jianbo Liu Reviewed-by: Carolina Jubran Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/lib/clock.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index eaf343756026..e7e4bdba02a3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -878,10 +878,8 @@ static int mlx5_query_mtpps_pin_mode(struct mlx5_core_dev *mdev, u8 pin, mtpps_size, MLX5_REG_MTPPS, 0, 0); } -static int mlx5_get_pps_pin_mode(struct mlx5_clock *clock, u8 pin) +static int mlx5_get_pps_pin_mode(struct mlx5_core_dev *mdev, u8 pin) { - struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, clock); - u32 out[MLX5_ST_SZ_DW(mtpps_reg)] = {}; u8 mode; int err; @@ -900,8 +898,9 @@ static int mlx5_get_pps_pin_mode(struct mlx5_clock *clock, u8 pin) return PTP_PF_NONE; } -static void mlx5_init_pin_config(struct mlx5_clock *clock) +static void mlx5_init_pin_config(struct mlx5_core_dev *mdev) { + struct mlx5_clock *clock = &mdev->clock; int i; if (!clock->ptp_info.n_pins) @@ -922,7 +921,7 @@ static void mlx5_init_pin_config(struct mlx5_clock *clock) sizeof(clock->ptp_info.pin_config[i].name), "mlx5_pps%d", i); clock->ptp_info.pin_config[i].index = i; - clock->ptp_info.pin_config[i].func = mlx5_get_pps_pin_mode(clock, i); + clock->ptp_info.pin_config[i].func = mlx5_get_pps_pin_mode(mdev, i); clock->ptp_info.pin_config[i].chan = 0; } } @@ -1041,10 +1040,10 @@ static void mlx5_timecounter_init(struct mlx5_core_dev *mdev) ktime_to_ns(ktime_get_real())); } -static void mlx5_init_overflow_period(struct mlx5_clock *clock) +static void mlx5_init_overflow_period(struct mlx5_core_dev *mdev) { - struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, clock); struct mlx5_ib_clock_info *clock_info = mdev->clock_info; + struct mlx5_clock *clock = &mdev->clock; struct mlx5_timer *timer = &clock->timer; u64 overflow_cycles; u64 frac = 0; @@ -1135,7 +1134,7 @@ static void mlx5_init_timer_clock(struct mlx5_core_dev *mdev) mlx5_timecounter_init(mdev); mlx5_init_clock_info(mdev); - mlx5_init_overflow_period(clock); + mlx5_init_overflow_period(mdev); if (mlx5_real_time_mode(mdev)) { struct timespec64 ts; @@ -1147,13 +1146,11 @@ static void mlx5_init_timer_clock(struct mlx5_core_dev *mdev) static void mlx5_init_pps(struct mlx5_core_dev *mdev) { - struct mlx5_clock *clock = &mdev->clock; - if (!MLX5_PPS_CAP(mdev)) return; mlx5_get_pps_caps(mdev); - mlx5_init_pin_config(clock); + mlx5_init_pin_config(mdev); } void mlx5_init_clock(struct mlx5_core_dev *mdev) From patchwork Mon Feb 3 21:35:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13958270 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2084.outbound.protection.outlook.com [40.107.94.84]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 558E41F4275 for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Jianbo Liu , Moshe Shemesh , Leon Romanovsky , Mark Bloch , Carolina Jubran , Dragos Tatulea , Tariq Toukan Subject: [PATCH net-next 03/15] net/mlx5: Add init and destruction functions for a single HW clock Date: Mon, 3 Feb 2025 23:35:04 +0200 Message-ID: <20250203213516.227902-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250203213516.227902-1-tariqt@nvidia.com> References: <20250203213516.227902-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002322:EE_|CY8PR12MB7490:EE_ X-MS-Office365-Filtering-Correlation-Id: a55a95c1-ef80-4f07-9d59-08dd449ad860 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; X-Microsoft-Antispam-Message-Info: UvB0/Em16Mn4boAsF1qn+gPwUYxchuAWZPMTrvoHCQB3aRHQ8HVyG8fuPnl4Pb67FtWvDD4ffV7gA3HaHp0G2nk+x9q0Cy1kdHJyKJlyD5bpX3WLNscoyND5J0ewmgrykpctMmn1S4KceqOZ9G4+/Sj+fyWCVxO9unYUjSgICAsJxXls+dn2Ju+QS/sNv4XlVSknpA2YmDkZipn1VuJvTFjO1WzhevrfNJ9EP7dcK2/SBN2F4LzEoQDNg7D6hPDSEevS8VtBXo0M5hO+Tsulb5lfxWArnyY+mSq/89lXcdm5+v1HRb5kgOpe6eWfDW63lTY6CoSPMuwJ4Cxby5sgznMcVuPNLRVXkuO6rJh0ISCPfY4+cWSsQndzrQQ0Kwg5wr2S+zLSho3K32tI2isD+/UAe+/foz9V3GhhiJLuGnx9ULiD5u6HwA1vOytYWyur+rfJhRq7Uns3UyAafjh+F9Y1cf06Yg/I2R6X3vbARM39fZ1QcSTj4gw/2upoBhEC1Qtt0jdfba5W9M2F/cLF6d/bYlD343LLDEeTlJ27zkkJBAEOeh7w7lBQAbYbJY20QGqJYdrhIlZID/To2OhYzD5Y7ywCyQNZdwOn/H//toFxC8Q5u4vmorazGAv+6i7ld0XJORWCNoTmhtdGHvsbz+AfkFTXajtf2yLwVRSuZ0fxP62krM+GSsEXFQafXYzBMaDRR0ZKiKI1EB4pgiM9Fq63xlIpupTXUa2Pdi9/k+TfaAQkPCUfCJL4zKpXbHOhE/ah652vXF9DwakTMgFG1/npogr8epUwaznoXSxZ3yOfqR4pdoW454XA+v+61iPri3sb8E+eALA8trBLS8elZACMzswq5crK/iCBTeiq6dzsmO1Kq0sTrAjS3AALbF/6xhQKMl/djFMZtgPicf5fUEqAtYt8fvgpeRJa1gJtGsBIsk91gMI0p4TFKRvgsqPql5BPMmEz8k3UH9Qpn8lkGhyv6l80z3ocTihEHsVDXb4amA9j5Ufk3dv0eVAbKvpcjDtxRWqb0DyOacbAJLc4Opl2ZZMZRmYPNabAqmp9WOiolPiyuauzQ3Dj4aWMvAhWrLYn3Lvtx4faM8rhDgJQYmQg5PaR4J2Lx+e7Gn/NvbNSeu+d2lMOnkkY9mHeCLP6/VwqaFw/ZU1stRgUONJDB0XPr4MfHYVa79RJ11KoYDO2jlhKKzlGQyQAh1WIPicoWw84DaVBBV7mb1nLD3iP8sPBBuTl1zktc+PUOGrGuSeF7TPA1bvB7QYarrSt7MiawXLIRye6kLqzcIggbDcve4QWBWPHK05plasG7pFDEKWVths5pgdhj9OgDHQbmqXZyGejcTas2O7aBxBjuvigj8CFaEkrVmAVEf80jkXaazbcBjoffhfhboXPgufsn4OJiXcGK0wT83pWxkGrMjrrojnqnETR7LiXE3fNtE8BAepp9aq9LXhpz3E2bahEQ6rE48w/w39/+qvayGYuQk7U2BcnbTESHVPZZqbd4V75xvQ= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2025 21:36:40.2028 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a55a95c1-ef80-4f07-9d59-08dd449ad860 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002322.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7490 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu Move hardware clock initialization and destruction to the functions, which will be used for dynamically allocated clock. Such clock is shared by all the devices if the queried clock identities are same. The out_work is for PPS out event, which can't be triggered when clock is shared, so INIT_WORK is not moved to the initialization function. Besides, we still need to register notifier for each device. Signed-off-by: Jianbo Liu Reviewed-by: Carolina Jubran Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/lib/clock.c | 48 ++++++++++++------- 1 file changed, 31 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index e7e4bdba02a3..cc0a491bf617 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -1153,17 +1153,11 @@ static void mlx5_init_pps(struct mlx5_core_dev *mdev) mlx5_init_pin_config(mdev); } -void mlx5_init_clock(struct mlx5_core_dev *mdev) +static void mlx5_init_clock_dev(struct mlx5_core_dev *mdev) { struct mlx5_clock *clock = &mdev->clock; - if (!MLX5_CAP_GEN(mdev, device_frequency_khz)) { - mlx5_core_warn(mdev, "invalid device_frequency_khz, aborting HW clock init\n"); - return; - } - seqlock_init(&clock->lock); - INIT_WORK(&clock->pps_info.out_work, mlx5_pps_out); /* Initialize the device clock */ mlx5_init_timer_clock(mdev); @@ -1179,28 +1173,19 @@ void mlx5_init_clock(struct mlx5_core_dev *mdev) clock->ptp = NULL; } - MLX5_NB_INIT(&clock->pps_nb, mlx5_pps_event, PPS_EVENT); - mlx5_eq_notifier_register(mdev, &clock->pps_nb); - if (clock->ptp) ptp_schedule_worker(clock->ptp, 0); } -void mlx5_cleanup_clock(struct mlx5_core_dev *mdev) +static void mlx5_destroy_clock_dev(struct mlx5_core_dev *mdev) { struct mlx5_clock *clock = &mdev->clock; - if (!MLX5_CAP_GEN(mdev, device_frequency_khz)) - return; - - mlx5_eq_notifier_unregister(mdev, &clock->pps_nb); if (clock->ptp) { ptp_clock_unregister(clock->ptp); clock->ptp = NULL; } - cancel_work_sync(&clock->pps_info.out_work); - if (mdev->clock_info) { free_page((unsigned long)mdev->clock_info); mdev->clock_info = NULL; @@ -1208,3 +1193,32 @@ void mlx5_cleanup_clock(struct mlx5_core_dev *mdev) kfree(clock->ptp_info.pin_config); } + +void mlx5_init_clock(struct mlx5_core_dev *mdev) +{ + struct mlx5_clock *clock = &mdev->clock; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Jianbo Liu , Moshe Shemesh , Leon Romanovsky , Mark Bloch , Carolina Jubran , Dragos Tatulea , Tariq Toukan Subject: [PATCH net-next 04/15] net/mlx5: Add API to get mlx5_core_dev from mlx5_clock Date: Mon, 3 Feb 2025 23:35:05 +0200 Message-ID: <20250203213516.227902-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250203213516.227902-1-tariqt@nvidia.com> References: <20250203213516.227902-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002324:EE_|MN0PR12MB6224:EE_ X-MS-Office365-Filtering-Correlation-Id: 177102d8-5815-476f-9277-08dd449ada2b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: kKa75SBSaYsNdPQ44cT9OWw4Iyf/Hf/t7n2IsbPXgDdYmKfO2q9823bOnQ++FI43hHyN8pj5tUOC++mD80A3ns1yKtj1q5eNF5rYc+DjbNSxR8PM/woOytV2RxWIeFHCcNyW3h1vlyhovhGoS6ffYsxTDMbH3wSTu2VxazFRRS5EIXLMUfvRDdKTiIOLHO7wzoSma8U3Um/qjA/pbkbTGs4XtcLvN4ofdfQ+NRpbTDUAQ7bivCVEnBlMefhBrqKVEj0S14EX3oVUJn/4qKJZ28waktDBvWh8hIf6LC4yC32ahBYv9FNfdVLfDaWmjHklM14dTwa7e2Idcb4nx75tll3PhPBJWQ6iTK+b9cQ+4QpGcp4mVtYWiyary+VExXuasuS0NgG/uUMwNYMSnc8/nPozdBC/YA8pvMUw3K7/IopBCqB6pvkcLVMgR3t0aKyrQMi6zslPnMXMisGzAZfcIrb5uYx9ENYwCPRy1lO2kJ7gxcljzaw55F64+KmN+ukuGmBU7UXkZasqleH37IMMJjTwqgBOuT9pOsU1l8rz+ekGEVwx+RuiDj5BEOSinNVnaE8sKO3cn20CsOlqJVTtajNePJsUC8R31JHKSW6IvHvoziu5DZfHGczUwHNu2JY/+Zib5aPnmOe40/CVwymU6EMFRVcQG26V9EGpbpgy84cH8APJZ+ozbpXc0q1KKMSBcE5s/c4H0B+ZTyrG7RdwSW2uKIuT11oVU8u/DqCBzSbnnW8zKp9fH/0YBzI58vVut6LicZq3vqSt/ZrtQvsUvfIFACL1ow5eQYFIEmrNH3oJdHlhLDmbv+I8rMkUo7zxVH9AGf8jE7+tOwmrgQBtCtex7XVg+nO0n0nUizwGOgYxftM4mVB+w+WR68ZeH81dmJ4PCRaYto+vSP2JIuxwjafqoX8cA19Th6BoWvzl2OD8v73LG1aZ8iTcCheHzVs14MlYAzyYOci7g+0ln+we4QCPkZ6Si9vBUa8xg/OyZ6MHrsWfE0Kow6A8iJK9kk85PQWbyc2RnW/VX0zIh2eCqzHMvyE5/lCb01zJ+k1LwgSLrkpyd/wTITYFdFTqRF10OeW3twBFHBJEeDB9dUqNMbLjBdmJ3/Ji6vA7Q1bQs6qej0OPNfKTYvU0R7SkJZNeMFTOUPzdpH/ZRjcyF+xI+wp23lyfH6uNnZ77avYEaYQ7OdrJta/sXLMLAJA/3IWi1Wyd16Zp44553qEVazzkY/6uNKC6gucVpcSm/KNyHYS1c9BagIO5wZp9tVDEEc2E7TbUeE50Ab0ZMdqrqwzNPC9/qGMwX/bech3b1/Q4dAs7OcGLItv/d0OO2Z4kFvs4p2eqjGvdDWygHFPOvATmfYnppCaa8/ypG0B6npF3pO/SVSE9FUQVG7yUjkhLrJ5xN7x6ByzoGafk4LE20svmaTs9SM5X+pX2JMdOGbdGNWOTAAlVY1xIBKAqMjV0mCbNzs7IdzSCptKKqI8QmVovRRaIOztl/9meas2tSNS29us= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2025 21:36:43.1950 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 177102d8-5815-476f-9277-08dd449ada2b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002324.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6224 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu The mdev is calculated directly from mlx5_clock, as it's one of the fields in mlx5_core_dev. Move to a function so it can be easily changed in next patch. Signed-off-by: Jianbo Liu Reviewed-by: Carolina Jubran Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/lib/clock.c | 35 ++++++++++--------- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index cc0a491bf617..b2c88050ba36 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -77,6 +77,11 @@ enum { MLX5_MTUTC_OPERATION_ADJUST_TIME_EXTENDED_MAX = 200000, }; +static struct mlx5_core_dev *mlx5_clock_mdev_get(struct mlx5_clock *clock) +{ + return container_of(clock, struct mlx5_core_dev, clock); +} + static bool mlx5_real_time_mode(struct mlx5_core_dev *mdev) { return (mlx5_is_real_time_rq(mdev) || mlx5_is_real_time_sq(mdev)); @@ -131,7 +136,7 @@ static s32 mlx5_ptp_getmaxphase(struct ptp_clock_info *ptp) struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); struct mlx5_core_dev *mdev; - mdev = container_of(clock, struct mlx5_core_dev, clock); + mdev = mlx5_clock_mdev_get(clock); return mlx5_clock_getmaxphase(mdev); } @@ -226,7 +231,7 @@ static int mlx5_ptp_getcrosststamp(struct ptp_clock_info *ptp, struct system_time_snapshot history_begin = {0}; struct mlx5_core_dev *mdev; - mdev = container_of(clock, struct mlx5_core_dev, clock); + mdev = mlx5_clock_mdev_get(clock); if (!mlx5_is_ptm_source_time_available(mdev)) return -EBUSY; @@ -268,8 +273,7 @@ static u64 read_internal_timer(const struct cyclecounter *cc) { struct mlx5_timer *timer = container_of(cc, struct mlx5_timer, cycles); struct mlx5_clock *clock = container_of(timer, struct mlx5_clock, timer); - struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, - clock); + struct mlx5_core_dev *mdev = mlx5_clock_mdev_get(clock); return mlx5_read_time(mdev, NULL, false) & cc->mask; } @@ -304,8 +308,7 @@ static void mlx5_pps_out(struct work_struct *work) out_work); struct mlx5_clock *clock = container_of(pps_info, struct mlx5_clock, pps_info); - struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, - clock); + struct mlx5_core_dev *mdev = mlx5_clock_mdev_get(clock); u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0}; unsigned long flags; int i; @@ -335,7 +338,7 @@ static long mlx5_timestamp_overflow(struct ptp_clock_info *ptp_info) unsigned long flags; clock = container_of(ptp_info, struct mlx5_clock, ptp_info); - mdev = container_of(clock, struct mlx5_core_dev, clock); + mdev = mlx5_clock_mdev_get(clock); timer = &clock->timer; if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) @@ -392,7 +395,7 @@ static int mlx5_ptp_settime(struct ptp_clock_info *ptp, const struct timespec64 struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); struct mlx5_core_dev *mdev; - mdev = container_of(clock, struct mlx5_core_dev, clock); + mdev = mlx5_clock_mdev_get(clock); return mlx5_clock_settime(mdev, clock, ts); } @@ -416,7 +419,7 @@ static int mlx5_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts, struct mlx5_core_dev *mdev; u64 cycles, ns; - mdev = container_of(clock, struct mlx5_core_dev, clock); + mdev = mlx5_clock_mdev_get(clock); if (mlx5_real_time_mode(mdev)) { *ts = mlx5_ptp_gettimex_real_time(mdev, sts); goto out; @@ -457,7 +460,7 @@ static int mlx5_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) struct mlx5_core_dev *mdev; unsigned long flags; - mdev = container_of(clock, struct mlx5_core_dev, clock); + mdev = mlx5_clock_mdev_get(clock); if (mlx5_modify_mtutc_allowed(mdev)) { int err = mlx5_ptp_adjtime_real_time(mdev, delta); @@ -479,7 +482,7 @@ static int mlx5_ptp_adjphase(struct ptp_clock_info *ptp, s32 delta) struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); struct mlx5_core_dev *mdev; - mdev = container_of(clock, struct mlx5_core_dev, clock); + mdev = mlx5_clock_mdev_get(clock); return mlx5_ptp_adjtime_real_time(mdev, delta); } @@ -512,7 +515,7 @@ static int mlx5_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) unsigned long flags; u32 mult; - mdev = container_of(clock, struct mlx5_core_dev, clock); + mdev = mlx5_clock_mdev_get(clock); if (mlx5_modify_mtutc_allowed(mdev)) { int err = mlx5_ptp_freq_adj_real_time(mdev, scaled_ppm); @@ -539,8 +542,7 @@ static int mlx5_extts_configure(struct ptp_clock_info *ptp, { struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); - struct mlx5_core_dev *mdev = - container_of(clock, struct mlx5_core_dev, clock); + struct mlx5_core_dev *mdev = mlx5_clock_mdev_get(clock); u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0}; u32 field_select = 0; u8 pin_mode = 0; @@ -724,8 +726,7 @@ static int mlx5_perout_configure(struct ptp_clock_info *ptp, { struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); - struct mlx5_core_dev *mdev = - container_of(clock, struct mlx5_core_dev, clock); + struct mlx5_core_dev *mdev = mlx5_clock_mdev_get(clock); bool rt_mode = mlx5_real_time_mode(mdev); u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0}; u32 out_pulse_duration_ns = 0; @@ -987,7 +988,7 @@ static int mlx5_pps_event(struct notifier_block *nb, unsigned long flags; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Jianbo Liu , Moshe Shemesh , Leon Romanovsky , Mark Bloch , Carolina Jubran , Dragos Tatulea , Tariq Toukan Subject: [PATCH net-next 05/15] net/mlx5: Change clock in mlx5_core_dev to mlx5_clock pointer Date: Mon, 3 Feb 2025 23:35:06 +0200 Message-ID: <20250203213516.227902-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250203213516.227902-1-tariqt@nvidia.com> References: <20250203213516.227902-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002324:EE_|IA1PR12MB6186:EE_ X-MS-Office365-Filtering-Correlation-Id: d54230ae-4330-4e59-4b2c-08dd449adb47 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: SoO90I7xgFjGca3DcKFospTh2xsxlr+RIqMMFez18QMwsJpS1hL3pbqrxy3qa74rOkEjs2U4aO2nMrftO/KWB/FnP9mQbqWNGNw8RZzF1c7RzxRaV+IUg92Vz5D8ywlSOuQ5TmSIKXCJLE9Xb+nZ9sDFD/7I2RQP+YXgsZY1t5lOhiB361F6+W60r/u2bzxlSGxj0WZzxXQbz5LRZzm0bd81Yvp1GS+QmGJ6rojFVqwmTIxJF5HEp8hnCdfSpjNXVs31b2ve7h0w+syZEwzDwPpP05HTe8RcA6hcm5kLSpVhEvKGylE7ArIMVFEKxyyps1ZNIi3YpvJ7nlTVTePf/Kt+wIjr2lXNwmWAeKJOL5t3/J834Mq8XRy8kJYksLAhOkC3qyuEBIPVO21X3AizEPI0dKqVN2x7XQWTtOhXq0M81pBD3gJ2Mzoic2A/i2nHmQ7ZEiRwfzHOipuEwX5S76b1CUdVtO+sdlkEARy2KvOpGmSOun0g6IcU/WuFwiV6rTkVO3TcbN2F6kZIlRVMchazEh3ohJm+Pvb/Si/14jzrVnWyVvWfFvDgh/DUpap/Ac3zRa5gP5JH5OahkdH85DHMNNvjDdouA4jpDY97bVbBEHOn9+9hdCJCa0JCqj8EHZu+YpNo/20WY+qrhUx7fBWrlySpDtWHsKe5heXC68np5ixGxYN8YMxX1tOA0Z/wm1kcAJRaW664Wd/o0QhNFv3+IB9dG4rZ3X0koKGZ9obtG0SArnQoklOiDiRncRIXhnuIcv/3f+xH/ZUEY1AoMDje4cLl7nda/nKiwHQmJmSZqyvAniNyTqsaf/brO1daJLvTEzPYfeyfB9S9O+2iH0+7Tznyq50GYtDuY002dfmKtUjxQS+mVfPjGHbt03WnlyEB30qR9jESORcx/VDDAbE66i2Sxkut0dfe7/RvMvxEi0sgjfK/YZ7iQLvdIxphFbQ1id2FGhfLlKjYhYAl2tNGSi2KMVgPEJYCvbmREFA7niRcNvviXO5VLG7zWAHtIGACXaA3yUomJY4rxo/bY+/Xp+D2HbY8GIPtVFb6IJXyOokIASIkp5hAaAeVHP917RZGZrgI6SltfVAtMXaQ1MytXi/2o2FFMyJW6ANzB/KlKum9YOW7oijokKHnZBX5vDedp0L6yq/tXHokCnPnQ3fWX+kZC7qSZoFBgTXj6osmItsKgjqpgE8Dibf3ptUFEmeNaTRIHl7NgKTS2ddamXyE55CrWvFW5h7STEEqCt8kuf1167SYJ9m2Vs7LYtuCdMOieCMeh43HsP47CdvM7Yz2HAxngcMExca1KWwx+frCDRz+/RQDFISNKGrez4ieY3oQq5eUsk7+yMWWF3B7PVPgLsZmd7G2xbVmAHCfSI8E6dHmoAnvT2hJdFaWJTsB7MQ2/j/8MuxhvNi2nx1qdBT1tnQ6FJcjQ3rw/meAZOMbe0PUcIY/TR8s/LHgj1Hqb21Cd0YHVcMGHmAjy/Pk4pIEfENQuJ9WHjvHc3oR2fw= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2025 21:36:45.0388 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d54230ae-4330-4e59-4b2c-08dd449adb47 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002324.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6186 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu Change clock member in mlx5_core_dev to a pointer, so it can point to a clock shared by multiple functions in later patch. For now, each function has its own clock, so mdev in mlx5_clock_priv is the back pointer to the function. Later it points to one (normally the first one) of the multiple functions sharing the same clock. Change mlx5_init_clock() to return error if mlx5_clock is not allocated. Besides, a null clock is defined and used when hardware clock is not supported. So, the clock pointer is always pointing to something valid. Signed-off-by: Jianbo Liu Reviewed-by: Carolina Jubran Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en/ptp.c | 4 +- .../net/ethernet/mellanox/mlx5/core/en/trap.c | 2 +- .../net/ethernet/mellanox/mlx5/core/en/xdp.c | 4 +- .../mellanox/mlx5/core/en/xsk/setup.c | 2 +- .../net/ethernet/mellanox/mlx5/core/en_main.c | 4 +- .../ethernet/mellanox/mlx5/core/lib/clock.c | 87 ++++++++++++++----- .../ethernet/mellanox/mlx5/core/lib/clock.h | 35 +++++++- .../net/ethernet/mellanox/mlx5/core/main.c | 11 ++- include/linux/mlx5/driver.h | 31 +------ 9 files changed, 116 insertions(+), 64 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c b/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c index afd654583b6b..131ed97ca997 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c @@ -326,7 +326,7 @@ static int mlx5e_ptp_alloc_txqsq(struct mlx5e_ptp *c, int txq_ix, int node; sq->pdev = c->pdev; - sq->clock = &mdev->clock; + sq->clock = mdev->clock; sq->mkey_be = c->mkey_be; sq->netdev = c->netdev; sq->priv = c->priv; @@ -696,7 +696,7 @@ static int mlx5e_init_ptp_rq(struct mlx5e_ptp *c, struct mlx5e_params *params, rq->pdev = c->pdev; rq->netdev = priv->netdev; rq->priv = priv; - rq->clock = &mdev->clock; + rq->clock = mdev->clock; rq->tstamp = &priv->tstamp; rq->mdev = mdev; rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/trap.c b/drivers/net/ethernet/mellanox/mlx5/core/en/trap.c index 53ca16cb9c41..140606fcd23b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/trap.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/trap.c @@ -46,7 +46,7 @@ static void mlx5e_init_trap_rq(struct mlx5e_trap *t, struct mlx5e_params *params rq->pdev = t->pdev; rq->netdev = priv->netdev; rq->priv = priv; - rq->clock = &mdev->clock; + rq->clock = mdev->clock; rq->tstamp = &priv->tstamp; rq->mdev = mdev; rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c b/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c index 94b291662087..3cc4d55613bf 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c @@ -289,9 +289,9 @@ static u64 mlx5e_xsk_fill_timestamp(void *_priv) ts = get_cqe_ts(priv->cqe); if (mlx5_is_real_time_rq(priv->cq->mdev) || mlx5_is_real_time_sq(priv->cq->mdev)) - return mlx5_real_time_cyc2time(&priv->cq->mdev->clock, ts); + return mlx5_real_time_cyc2time(priv->cq->mdev->clock, ts); - return mlx5_timecounter_cyc2time(&priv->cq->mdev->clock, ts); + return mlx5_timecounter_cyc2time(priv->cq->mdev->clock, ts); } static void mlx5e_xsk_request_checksum(u16 csum_start, u16 csum_offset, void *priv) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c b/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c index 9240cfe25d10..d743e823362a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c @@ -72,7 +72,7 @@ static int mlx5e_init_xsk_rq(struct mlx5e_channel *c, rq->netdev = c->netdev; rq->priv = c->priv; rq->tstamp = c->tstamp; - rq->clock = &mdev->clock; + rq->clock = mdev->clock; rq->icosq = &c->icosq; rq->ix = c->ix; rq->channel = c; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index a814b63ed97e..c754e0c75934 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -737,7 +737,7 @@ static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *param rq->netdev = c->netdev; rq->priv = c->priv; rq->tstamp = c->tstamp; - rq->clock = &mdev->clock; + rq->clock = mdev->clock; rq->icosq = &c->icosq; rq->ix = c->ix; rq->channel = c; @@ -1614,7 +1614,7 @@ static int mlx5e_alloc_txqsq(struct mlx5e_channel *c, int err; sq->pdev = c->pdev; - sq->clock = &mdev->clock; + sq->clock = mdev->clock; sq->mkey_be = c->mkey_be; sq->netdev = c->netdev; sq->mdev = c->mdev; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index b2c88050ba36..da2a21ce8060 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -77,9 +77,19 @@ enum { MLX5_MTUTC_OPERATION_ADJUST_TIME_EXTENDED_MAX = 200000, }; +struct mlx5_clock_priv { + struct mlx5_clock clock; + struct mlx5_core_dev *mdev; +}; + +static struct mlx5_clock_priv *clock_priv(struct mlx5_clock *clock) +{ + return container_of(clock, struct mlx5_clock_priv, clock); +} + static struct mlx5_core_dev *mlx5_clock_mdev_get(struct mlx5_clock *clock) { - return container_of(clock, struct mlx5_core_dev, clock); + return clock_priv(clock)->mdev; } static bool mlx5_real_time_mode(struct mlx5_core_dev *mdev) @@ -219,7 +229,7 @@ static int mlx5_mtctr_syncdevicetime(ktime_t *device_time, if (real_time_mode) *device_time = ns_to_ktime(REAL_TIME_TO_NS(device >> 32, device & U32_MAX)); else - *device_time = mlx5_timecounter_cyc2time(&mdev->clock, device); + *device_time = mlx5_timecounter_cyc2time(mdev->clock, device); return 0; } @@ -281,7 +291,7 @@ static u64 read_internal_timer(const struct cyclecounter *cc) static void mlx5_update_clock_info_page(struct mlx5_core_dev *mdev) { struct mlx5_ib_clock_info *clock_info = mdev->clock_info; - struct mlx5_clock *clock = &mdev->clock; + struct mlx5_clock *clock = mdev->clock; struct mlx5_timer *timer; u32 sign; @@ -599,7 +609,7 @@ static int mlx5_extts_configure(struct ptp_clock_info *ptp, static u64 find_target_cycles(struct mlx5_core_dev *mdev, s64 target_ns) { - struct mlx5_clock *clock = &mdev->clock; + struct mlx5_clock *clock = mdev->clock; u64 cycles_now, cycles_delta; u64 nsec_now, nsec_delta; struct mlx5_timer *timer; @@ -658,7 +668,7 @@ static int mlx5_perout_conf_out_pulse_duration(struct mlx5_core_dev *mdev, struct ptp_clock_request *rq, u32 *out_pulse_duration_ns) { - struct mlx5_pps *pps_info = &mdev->clock.pps_info; + struct mlx5_pps *pps_info = &mdev->clock->pps_info; u32 out_pulse_duration; struct timespec64 ts; @@ -691,7 +701,7 @@ static int perout_conf_npps_real_time(struct mlx5_core_dev *mdev, struct ptp_clo u32 *field_select, u32 *out_pulse_duration_ns, u64 *period, u64 *time_stamp) { - struct mlx5_pps *pps_info = &mdev->clock.pps_info; + struct mlx5_pps *pps_info = &mdev->clock->pps_info; struct ptp_clock_time *time = &rq->perout.start; struct timespec64 ts; @@ -901,7 +911,7 @@ static int mlx5_get_pps_pin_mode(struct mlx5_core_dev *mdev, u8 pin) static void mlx5_init_pin_config(struct mlx5_core_dev *mdev) { - struct mlx5_clock *clock = &mdev->clock; + struct mlx5_clock *clock = mdev->clock; int i; if (!clock->ptp_info.n_pins) @@ -929,8 +939,8 @@ static void mlx5_init_pin_config(struct mlx5_core_dev *mdev) static void mlx5_get_pps_caps(struct mlx5_core_dev *mdev) { - struct mlx5_clock *clock = &mdev->clock; u32 out[MLX5_ST_SZ_DW(mtpps_reg)] = {0}; + struct mlx5_clock *clock = mdev->clock; mlx5_query_mtpps(mdev, out, sizeof(out)); @@ -1025,7 +1035,7 @@ static int mlx5_pps_event(struct notifier_block *nb, static void mlx5_timecounter_init(struct mlx5_core_dev *mdev) { - struct mlx5_clock *clock = &mdev->clock; + struct mlx5_clock *clock = mdev->clock; struct mlx5_timer *timer = &clock->timer; u32 dev_freq; @@ -1044,7 +1054,7 @@ static void mlx5_timecounter_init(struct mlx5_core_dev *mdev) static void mlx5_init_overflow_period(struct mlx5_core_dev *mdev) { struct mlx5_ib_clock_info *clock_info = mdev->clock_info; - struct mlx5_clock *clock = &mdev->clock; + struct mlx5_clock *clock = mdev->clock; struct mlx5_timer *timer = &clock->timer; u64 overflow_cycles; u64 frac = 0; @@ -1077,7 +1087,7 @@ static void mlx5_init_overflow_period(struct mlx5_core_dev *mdev) static void mlx5_init_clock_info(struct mlx5_core_dev *mdev) { - struct mlx5_clock *clock = &mdev->clock; + struct mlx5_clock *clock = mdev->clock; struct mlx5_ib_clock_info *info; struct mlx5_timer *timer; @@ -1100,7 +1110,7 @@ static void mlx5_init_clock_info(struct mlx5_core_dev *mdev) static void mlx5_init_timer_max_freq_adjustment(struct mlx5_core_dev *mdev) { - struct mlx5_clock *clock = &mdev->clock; + struct mlx5_clock *clock = mdev->clock; u32 out[MLX5_ST_SZ_DW(mtutc_reg)] = {}; u32 in[MLX5_ST_SZ_DW(mtutc_reg)] = {}; u8 log_max_freq_adjustment = 0; @@ -1119,7 +1129,7 @@ static void mlx5_init_timer_max_freq_adjustment(struct mlx5_core_dev *mdev) static void mlx5_init_timer_clock(struct mlx5_core_dev *mdev) { - struct mlx5_clock *clock = &mdev->clock; + struct mlx5_clock *clock = mdev->clock; /* Configure the PHC */ clock->ptp_info = mlx5_ptp_clock_info; @@ -1156,7 +1166,7 @@ static void mlx5_init_pps(struct mlx5_core_dev *mdev) static void mlx5_init_clock_dev(struct mlx5_core_dev *mdev) { - struct mlx5_clock *clock = &mdev->clock; + struct mlx5_clock *clock = mdev->clock; seqlock_init(&clock->lock); @@ -1180,7 +1190,7 @@ static void mlx5_init_clock_dev(struct mlx5_core_dev *mdev) static void mlx5_destroy_clock_dev(struct mlx5_core_dev *mdev) { - struct mlx5_clock *clock = &mdev->clock; + struct mlx5_clock *clock = mdev->clock; if (clock->ptp) { ptp_clock_unregister(clock->ptp); @@ -1195,25 +1205,60 @@ static void mlx5_destroy_clock_dev(struct mlx5_core_dev *mdev) kfree(clock->ptp_info.pin_config); } -void mlx5_init_clock(struct mlx5_core_dev *mdev) +static void mlx5_clock_free(struct mlx5_core_dev *mdev) +{ + struct mlx5_clock_priv *cpriv = clock_priv(mdev->clock); + + mlx5_destroy_clock_dev(mdev); + kfree(cpriv); + mdev->clock = NULL; +} + +static int mlx5_clock_alloc(struct mlx5_core_dev *mdev) { - struct mlx5_clock *clock = &mdev->clock; + struct mlx5_clock_priv *cpriv; + struct mlx5_clock *clock; + + cpriv = kzalloc(sizeof(*cpriv), GFP_KERNEL); + if (!cpriv) + return -ENOMEM; + + cpriv->mdev = mdev; + clock = &cpriv->clock; + mdev->clock = clock; + mlx5_init_clock_dev(mdev); + + return 0; +} + +static struct mlx5_clock null_clock; + +int mlx5_init_clock(struct mlx5_core_dev *mdev) +{ + struct mlx5_clock *clock; + int err; if (!MLX5_CAP_GEN(mdev, device_frequency_khz)) { + mdev->clock = &null_clock; mlx5_core_warn(mdev, "invalid device_frequency_khz, aborting HW clock init\n"); - return; + return 0; } - mlx5_init_clock_dev(mdev); + err = mlx5_clock_alloc(mdev); + if (err) + return err; + clock = mdev->clock; INIT_WORK(&clock->pps_info.out_work, mlx5_pps_out); MLX5_NB_INIT(&clock->pps_nb, mlx5_pps_event, PPS_EVENT); mlx5_eq_notifier_register(mdev, &clock->pps_nb); + + return 0; } void mlx5_cleanup_clock(struct mlx5_core_dev *mdev) { - struct mlx5_clock *clock = &mdev->clock; + struct mlx5_clock *clock = mdev->clock; if (!MLX5_CAP_GEN(mdev, device_frequency_khz)) return; @@ -1221,5 +1266,5 @@ void mlx5_cleanup_clock(struct mlx5_core_dev *mdev) mlx5_eq_notifier_unregister(mdev, &clock->pps_nb); cancel_work_sync(&clock->pps_info.out_work); - mlx5_destroy_clock_dev(mdev); + mlx5_clock_free(mdev); } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h index bd95b9f8d143..eca1dd9039be 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h @@ -33,6 +33,35 @@ #ifndef __LIB_CLOCK_H__ #define __LIB_CLOCK_H__ +#include + +#define MAX_PIN_NUM 8 +struct mlx5_pps { + u8 pin_caps[MAX_PIN_NUM]; + struct work_struct out_work; + u64 start[MAX_PIN_NUM]; + u8 enabled; + u64 min_npps_period; + u64 min_out_pulse_duration_ns; +}; + +struct mlx5_timer { + struct cyclecounter cycles; + struct timecounter tc; + u32 nominal_c_mult; + unsigned long overflow_period; +}; + +struct mlx5_clock { + struct mlx5_nb pps_nb; + seqlock_t lock; + struct hwtstamp_config hwtstamp_config; + struct ptp_clock *ptp; + struct ptp_clock_info ptp_info; + struct mlx5_pps pps_info; + struct mlx5_timer timer; +}; + static inline bool mlx5_is_real_time_rq(struct mlx5_core_dev *mdev) { u8 rq_ts_format_cap = MLX5_CAP_GEN(mdev, rq_ts_format); @@ -54,12 +83,12 @@ static inline bool mlx5_is_real_time_sq(struct mlx5_core_dev *mdev) typedef ktime_t (*cqe_ts_to_ns)(struct mlx5_clock *, u64); #if IS_ENABLED(CONFIG_PTP_1588_CLOCK) -void mlx5_init_clock(struct mlx5_core_dev *mdev); +int mlx5_init_clock(struct mlx5_core_dev *mdev); void mlx5_cleanup_clock(struct mlx5_core_dev *mdev); static inline int mlx5_clock_get_ptp_index(struct mlx5_core_dev *mdev) { - return mdev->clock.ptp ? ptp_clock_index(mdev->clock.ptp) : -1; + return mdev->clock->ptp ? ptp_clock_index(mdev->clock->ptp) : -1; } static inline ktime_t mlx5_timecounter_cyc2time(struct mlx5_clock *clock, @@ -87,7 +116,7 @@ static inline ktime_t mlx5_real_time_cyc2time(struct mlx5_clock *clock, return ns_to_ktime(time); } #else -static inline void mlx5_init_clock(struct mlx5_core_dev *mdev) {} +static inline int mlx5_init_clock(struct mlx5_core_dev *mdev) { return 0; } static inline void mlx5_cleanup_clock(struct mlx5_core_dev *mdev) {} static inline int mlx5_clock_get_ptp_index(struct mlx5_core_dev *mdev) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c index ec956c4bcebd..996773521aee 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -1038,7 +1038,11 @@ static int mlx5_init_once(struct mlx5_core_dev *dev) mlx5_init_reserved_gids(dev); - mlx5_init_clock(dev); + err = mlx5_init_clock(dev); + if (err) { + mlx5_core_err(dev, "failed to initialize hardware clock\n"); + goto err_tables_cleanup; + } dev->vxlan = mlx5_vxlan_create(dev); dev->geneve = mlx5_geneve_create(dev); @@ -1046,7 +1050,7 @@ static int mlx5_init_once(struct mlx5_core_dev *dev) err = mlx5_init_rl_table(dev); if (err) { mlx5_core_err(dev, "Failed to init rate limiting\n"); - goto err_tables_cleanup; + goto err_clock_cleanup; } err = mlx5_mpfs_init(dev); @@ -1123,10 +1127,11 @@ static int mlx5_init_once(struct mlx5_core_dev *dev) mlx5_mpfs_cleanup(dev); err_rl_cleanup: mlx5_cleanup_rl_table(dev); -err_tables_cleanup: +err_clock_cleanup: mlx5_geneve_destroy(dev->geneve); mlx5_vxlan_destroy(dev->vxlan); mlx5_cleanup_clock(dev); +err_tables_cleanup: mlx5_cleanup_reserved_gids(dev); mlx5_cq_debugfs_cleanup(dev); mlx5_fw_reset_cleanup(dev); diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index af86097641b0..5dab3d8d05e4 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -54,7 +54,6 @@ #include #include #include -#include #include #define MLX5_ADEV_NAME "mlx5_core" @@ -679,33 +678,7 @@ struct mlx5_rsvd_gids { struct ida ida; }; -#define MAX_PIN_NUM 8 -struct mlx5_pps { - u8 pin_caps[MAX_PIN_NUM]; - struct work_struct out_work; - u64 start[MAX_PIN_NUM]; - u8 enabled; - u64 min_npps_period; - u64 min_out_pulse_duration_ns; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Jianbo Liu , Moshe Shemesh , Leon Romanovsky , Mark Bloch , Carolina Jubran , Dragos Tatulea , Tariq Toukan Subject: [PATCH net-next 06/15] net/mlx5: Add devcom component for the clock shared by functions Date: Mon, 3 Feb 2025 23:35:07 +0200 Message-ID: <20250203213516.227902-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250203213516.227902-1-tariqt@nvidia.com> References: <20250203213516.227902-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002326:EE_|BL3PR12MB6379:EE_ X-MS-Office365-Filtering-Correlation-Id: e08673da-7073-443e-b75e-08dd449add96 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: dOyquUwM2S/HXtYc2C2R8CI+Z8dCnIXk+/fMRk93vOdJItFHuvTi5jfbqVVhRbF3sll8lZkewgE8qmkomAGUbrO1oTA+c8AvTo2CvKBAFP8r6hbAcejYi9whYfQ8Gos2olNKK32FDndAQKSfdHgiWIMyKOsUG/FgBZoJCBmXgaKBF5tmCmrnOYrsx9P5PwJqOKLxaGBo4JB3lZS7mMixtbkL5IthV2xDubODL/fm0yR753ye+YhtHEYKeBJiQvPoCVuM2Bgfpwc9QQTQVOUqYOITyv3T5dg+2wpMXOvC/ldTr2P3VR6K3qYi42YK1FkU2VczwBJse36dNkgnY6GQCS+D0SpOR2irqT4dz7tgcuYN5eG5rTPH2ieu5MCTECLCJwFffnjN5PUa1CIJzuTmPhP6DMj1sPnMUXr6GPsFsVwr9+U72MMQ0rK1MoywJuMDd5lfgAETrN+vnF1vXq4JkcK5fpaJhhTvuQ5+8evgAkkYnKCUT5TZv5qLGpylvF46v6ABSPWQYKDnRO6usIrB4JA+H5IjmtnjsNm9ZwozYkG6blI6rxxaddia/N+/g0QZucuTXRooh10sMaBqJJkGz5IagQeyNapbqHETBiMY8w5XC8Tj8vy+m1XzN+SNGULD9HWLpPvrzqb+VQTX3qHgUVRMlBXms4YOKYKK7ZZLufbTVLkHF13I7ibtolSVltjmFZPRSUtvKwMuGXlMimkInn0Qi6bTC1c3yVrYElOeI8w596BXRps0Tw0cIDDYGgwQw3//CZolb/27auKHlIgipQ5MgDYgz3NXjAuLAnUQxB3XuCUiiZetGOKgL/lwmynwj7jW5mbVmtCDMTkqxTU9hSO72dZcFTRNPn0stLakJG+OMQG6l1N46plLfampK7AJpD29kyvHiOVPCXWdTVQno8J755i+xztmp+qYvWNb90StAfw7ktX8BbGukSGi285M72lKCvuiF/ZpjsKhAti+CGpqpKBaiHOxXpngQ1pOif0siWXATqav3PA/hmSjMCLET8wc3tIQyosIDk3fuwvimI1wjGcXBXfwo5Pn4JGhhisTzoDL0iGaBRMszybFCY10AjEH17296fQ55Rr6mdXhAk9pUOXRptnbOtQzvDf2oe47d/pdJrjhk1h3C44hxFBbYQxabm9Wj/xhQqj1jujRinWUtFQgsNAGQMXJwHk7VV4+jskfYZWzUrV6dopizbsvP9qeEcin3uQk2ehKQ/rpg2cWkcKlQz7D0/gYcb5PONvzG0pMbGxhSRXSotCiSXrC2Yf4IymLZmFrw/y3dWf7HMSzeTJM15MgwA2AP/hbt6Pgjehv0y2DOIFiUprQQ9PkiGw+9F4a+dZ0R73WOsgoE4HhH3Idvkwdk1oObC/V4eHBmL1s/+Dd3v/DprAAvUtsDqCrtndr0qIlfbPYoxg6W/3GGiDKFeqdIEVHSmLc7MSTXT38gMmQfZsVJKC7qJk+uF53yLHuLaFqqcgI1uXi8x7Kd2avV7xSWWvSvyerpU8= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2025 21:36:48.9460 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e08673da-7073-443e-b75e-08dd449add96 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002326.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6379 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu Add new devcom component for hardware clock. When it is running in real time mode, the functions are grouped by the identify they query. According to firmware document, the clock identify size is 64 bits, so it's safe to memcpy to component key, as the key size is also 64 bits. Signed-off-by: Jianbo Liu Reviewed-by: Carolina Jubran Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/lib/clock.c | 59 ++++++++++++++++++- .../ethernet/mellanox/mlx5/core/lib/devcom.h | 1 + include/linux/mlx5/driver.h | 2 + 3 files changed, 61 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index da2a21ce8060..7e5882ea19e0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -43,6 +43,8 @@ #include #endif /* CONFIG_X86 */ +#define MLX5_RT_CLOCK_IDENTITY_SIZE MLX5_FLD_SZ_BYTES(mrtcq_reg, rt_clock_identity) + enum { MLX5_PIN_MODE_IN = 0x0, MLX5_PIN_MODE_OUT = 0x1, @@ -77,6 +79,10 @@ enum { MLX5_MTUTC_OPERATION_ADJUST_TIME_EXTENDED_MAX = 200000, }; +struct mlx5_clock_dev_state { + struct mlx5_devcom_comp_dev *compdev; +}; + struct mlx5_clock_priv { struct mlx5_clock clock; struct mlx5_core_dev *mdev; @@ -109,6 +115,22 @@ static bool mlx5_modify_mtutc_allowed(struct mlx5_core_dev *mdev) return MLX5_CAP_MCAM_FEATURE(mdev, ptpcyc2realtime_modify); } +static int mlx5_clock_identity_get(struct mlx5_core_dev *mdev, + u8 identify[MLX5_RT_CLOCK_IDENTITY_SIZE]) +{ + u32 out[MLX5_ST_SZ_DW(mrtcq_reg)] = {}; + u32 in[MLX5_ST_SZ_DW(mrtcq_reg)] = {}; + int err; + + err = mlx5_core_access_reg(mdev, in, sizeof(in), + out, sizeof(out), MLX5_REG_MRTCQ, 0, 0); + if (!err) + memcpy(identify, MLX5_ADDR_OF(mrtcq_reg, out, rt_clock_identity), + MLX5_RT_CLOCK_IDENTITY_SIZE); + + return err; +} + static u32 mlx5_ptp_shift_constant(u32 dev_freq_khz) { /* Optimal shift constant leads to corrections above just 1 scaled ppm. @@ -1231,11 +1253,26 @@ static int mlx5_clock_alloc(struct mlx5_core_dev *mdev) return 0; } +static void mlx5_shared_clock_register(struct mlx5_core_dev *mdev, u64 key) +{ + mdev->clock_state->compdev = mlx5_devcom_register_component(mdev->priv.devc, + MLX5_DEVCOM_SHARED_CLOCK, + key, NULL, mdev); +} + +static void mlx5_shared_clock_unregister(struct mlx5_core_dev *mdev) +{ + mlx5_devcom_unregister_component(mdev->clock_state->compdev); +} + static struct mlx5_clock null_clock; int mlx5_init_clock(struct mlx5_core_dev *mdev) { + u8 identity[MLX5_RT_CLOCK_IDENTITY_SIZE]; + struct mlx5_clock_dev_state *clock_state; struct mlx5_clock *clock; + u64 key; int err; if (!MLX5_CAP_GEN(mdev, device_frequency_khz)) { @@ -1244,9 +1281,26 @@ int mlx5_init_clock(struct mlx5_core_dev *mdev) return 0; } + clock_state = kzalloc(sizeof(*clock_state), GFP_KERNEL); + if (!clock_state) + return -ENOMEM; + mdev->clock_state = clock_state; + + if (MLX5_CAP_MCAM_REG3(mdev, mrtcq) && mlx5_real_time_mode(mdev)) { + if (mlx5_clock_identity_get(mdev, identity)) { + mlx5_core_warn(mdev, "failed to get rt clock identity, create ptp dev per function\n"); + } else { + memcpy(&key, &identity, sizeof(key)); + mlx5_shared_clock_register(mdev, key); + } + } + err = mlx5_clock_alloc(mdev); - if (err) + if (err) { + kfree(clock_state); + mdev->clock_state = NULL; return err; + } clock = mdev->clock; INIT_WORK(&clock->pps_info.out_work, mlx5_pps_out); @@ -1267,4 +1321,7 @@ void mlx5_cleanup_clock(struct mlx5_core_dev *mdev) cancel_work_sync(&clock->pps_info.out_work); mlx5_clock_free(mdev); + mlx5_shared_clock_unregister(mdev); + kfree(mdev->clock_state); + mdev->clock_state = NULL; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.h b/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.h index d58032dd0df7..c79699b94a02 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.h @@ -11,6 +11,7 @@ enum mlx5_devcom_component { MLX5_DEVCOM_MPV, MLX5_DEVCOM_HCA_PORTS, MLX5_DEVCOM_SD_GROUP, + MLX5_DEVCOM_SHARED_CLOCK, MLX5_DEVCOM_NUM_COMPONENTS, }; diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 5dab3d8d05e4..46bd7550adf8 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -679,6 +679,7 @@ struct mlx5_rsvd_gids { }; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Jianbo Liu , Moshe Shemesh , Leon Romanovsky , Mark Bloch , Carolina Jubran , Dragos Tatulea , Tariq Toukan Subject: [PATCH net-next 07/15] net/mlx5: Move PPS notifier and out_work to clock_state Date: Mon, 3 Feb 2025 23:35:08 +0200 Message-ID: <20250203213516.227902-8-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250203213516.227902-1-tariqt@nvidia.com> References: <20250203213516.227902-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F68:EE_|CH3PR12MB8510:EE_ X-MS-Office365-Filtering-Correlation-Id: b8f4e1a4-20ef-4680-ce89-08dd449adec7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; X-Microsoft-Antispam-Message-Info: C576PNFQlknEpEbSKaDKWLkKMwR2MWORHQ3Woor8vnd/IX4f7tGuZ2xFUA9H2tGNqFukxgCC7S8BKQ5/WwI7WYn5Jk7VkMpdH7EIUYKttNCLVho+1AhXNjera0B9qPoWIysl9bupXEmZ3zR40cAToiZTdbQzKXZxlQ6FNRfxvOcp3xzw4ztten3CWlhAzTLYG8NXxbb3umNNKKX9qkXcw4hQCPH+vAMUtaU01X0VOk9lBo+Ew3oUwAMImZF90q4sssKPe6BRbPNApYktCgn0Td836gwLBxrWnE2lhKMDzRCfY+RfazYOYHKAJWToucrOyxburPG1ek8kFq/cR2ehs057joKknMb/7DsSu/ROAdx9wBot7uKtEHoNf2F/oyQR/n7YpQFQ2w2oMa0ofTQhw73E8huvWMeIvhgO9gQGMJIYTouSFf2gqW0dKOqAR5kqmtSu9wrlDIHanTk3V8ocmAAit1TprduP2J5YN9DNbCeKvQFVUQV8Uv4461yw8m/H5Ky2bQd1DHHC6pFaar6NbUc++FfnaYKBXs31DVlx0lWlI2//D3xNRGDuBEtb6RF0cNmDAHaA+lCuMZjcYT4sofIwzVtpTaX/kv3J2y5Djlo9HDvegXSldjhITrOf1xzO9Tu67lnnRPgZiRxsFlE3OBFUMbbv4WTDDMYzkubSot/6ug3g78HqjItfxTuotSR/p3Tf7gTwE7DmhuHkKf779Tqd+MQJ9zhSJ48kTAMtqGfkJkr0unLRHLlzXkyqRuFNWhUq0yX0BTfNbNiJUseCApEpWmXV5cc7O3bcbKc/xRsV/qIlvGee5s1zbz+aZMUCRyTwl3zOV7OpF+V2WbjrHv6gVs1K/idu0KSV6z4vg2JuSc/CIjVkpINf6qvRjbcFjGCul35TydNDbbghA4DjBrHVz+8fPDvGAVPQdTvBWKDg3cTi9E/2Ybitq9jKl7DjxK+WZAZX918y0DoK1Zk5fpX5GeFuKVDmzdV0K1O3QuwtGizm3R82KnHNEiYA5P5gk2vgPRCKPFtv6stbMELOGRqIImy5hYwbjb/hOeoueNFk+4ELaLXNCc4eLjS1rri4sNIGAn4f0Kpf4jpD5sbEH/4dkpgKo/627ngHscV5wLSDBUIlP5Ln+t8RNRL3Tevr6GxqN6WcCcla3tIG/ooEepzHXF8YUqsUslSpw1fmY5XH0xz78eQlASV921pwKR2tM8QAW8oXeZmvlBIC/o2gPIMK4j1Isg7NGGB3cUrG0VM9EqBoFOYooIHdrK+vvHQkq3aFccOf3vIZOd7vT71NpiKKsr2YAK05ahoEvxJ4S6gcs5FK4cNgOYCu2iwj6popMHZ0PjaGwTavEhV6ltipNEva7lUXQxpvi/+lTftXrUCEgj1Mu352OJzwZcGrc9iedVqfXwyFkOVdryTiV7ds8JfGu9Rxxn17ykbCWLdXfBLsRjQbkOIpsrp+/xFP+F2s0foWlzuqBWFbhYtltRcETKAHVuVEu/jDNxh3KreP8Zc= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2025 21:36:50.8361 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b8f4e1a4-20ef-4680-ce89-08dd449adec7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F68.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8510 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu The PPS notifier is currently in mlx5_clock, and mlx5_clock can be shared in later patch, so the notifier should be registered for each device to avoid any event miss. Besides, the out_work is scheduled by PPS out event which is triggered only when the device is in free running mode. So, both are moved to mlx5_core_dev's clock_state. Signed-off-by: Jianbo Liu Reviewed-by: Carolina Jubran Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/lib/clock.c | 37 +++++++++---------- .../ethernet/mellanox/mlx5/core/lib/clock.h | 2 - 2 files changed, 18 insertions(+), 21 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index 7e5882ea19e0..2586b0788b40 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -80,7 +80,10 @@ enum { }; struct mlx5_clock_dev_state { + struct mlx5_core_dev *mdev; struct mlx5_devcom_comp_dev *compdev; + struct mlx5_nb pps_nb; + struct work_struct out_work; }; struct mlx5_clock_priv { @@ -336,11 +339,10 @@ static void mlx5_update_clock_info_page(struct mlx5_core_dev *mdev) static void mlx5_pps_out(struct work_struct *work) { - struct mlx5_pps *pps_info = container_of(work, struct mlx5_pps, - out_work); - struct mlx5_clock *clock = container_of(pps_info, struct mlx5_clock, - pps_info); - struct mlx5_core_dev *mdev = mlx5_clock_mdev_get(clock); + struct mlx5_clock_dev_state *clock_state = container_of(work, struct mlx5_clock_dev_state, + out_work); + struct mlx5_core_dev *mdev = clock_state->mdev; + struct mlx5_clock *clock = mdev->clock; u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0}; unsigned long flags; int i; @@ -1012,16 +1014,16 @@ static u64 perout_conf_next_event_timer(struct mlx5_core_dev *mdev, static int mlx5_pps_event(struct notifier_block *nb, unsigned long type, void *data) { - struct mlx5_clock *clock = mlx5_nb_cof(nb, struct mlx5_clock, pps_nb); + struct mlx5_clock_dev_state *clock_state = mlx5_nb_cof(nb, struct mlx5_clock_dev_state, + pps_nb); + struct mlx5_core_dev *mdev = clock_state->mdev; + struct mlx5_clock *clock = mdev->clock; struct ptp_clock_event ptp_event; struct mlx5_eqe *eqe = data; int pin = eqe->data.pps.pin; - struct mlx5_core_dev *mdev; unsigned long flags; u64 ns; - mdev = mlx5_clock_mdev_get(clock); - switch (clock->ptp_info.pin_config[pin].func) { case PTP_PF_EXTTS: ptp_event.index = pin; @@ -1045,7 +1047,7 @@ static int mlx5_pps_event(struct notifier_block *nb, write_seqlock_irqsave(&clock->lock, flags); clock->pps_info.start[pin] = ns; write_sequnlock_irqrestore(&clock->lock, flags); - schedule_work(&clock->pps_info.out_work); + schedule_work(&clock_state->out_work); break; default: mlx5_core_err(mdev, " Unhandled clock PPS event, func %d\n", @@ -1271,7 +1273,6 @@ int mlx5_init_clock(struct mlx5_core_dev *mdev) { u8 identity[MLX5_RT_CLOCK_IDENTITY_SIZE]; struct mlx5_clock_dev_state *clock_state; - struct mlx5_clock *clock; u64 key; int err; @@ -1284,6 +1285,7 @@ int mlx5_init_clock(struct mlx5_core_dev *mdev) clock_state = kzalloc(sizeof(*clock_state), GFP_KERNEL); if (!clock_state) return -ENOMEM; + clock_state->mdev = mdev; mdev->clock_state = clock_state; if (MLX5_CAP_MCAM_REG3(mdev, mrtcq) && mlx5_real_time_mode(mdev)) { @@ -1301,24 +1303,21 @@ int mlx5_init_clock(struct mlx5_core_dev *mdev) mdev->clock_state = NULL; return err; } - clock = mdev->clock; - INIT_WORK(&clock->pps_info.out_work, mlx5_pps_out); - MLX5_NB_INIT(&clock->pps_nb, mlx5_pps_event, PPS_EVENT); - mlx5_eq_notifier_register(mdev, &clock->pps_nb); + INIT_WORK(&mdev->clock_state->out_work, mlx5_pps_out); + MLX5_NB_INIT(&mdev->clock_state->pps_nb, mlx5_pps_event, PPS_EVENT); + mlx5_eq_notifier_register(mdev, &mdev->clock_state->pps_nb); return 0; } void mlx5_cleanup_clock(struct mlx5_core_dev *mdev) { - struct mlx5_clock *clock = mdev->clock; - if (!MLX5_CAP_GEN(mdev, device_frequency_khz)) return; - mlx5_eq_notifier_unregister(mdev, &clock->pps_nb); - cancel_work_sync(&clock->pps_info.out_work); + mlx5_eq_notifier_unregister(mdev, &mdev->clock_state->pps_nb); + cancel_work_sync(&mdev->clock_state->out_work); mlx5_clock_free(mdev); mlx5_shared_clock_unregister(mdev); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h index eca1dd9039be..3c5fee246582 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h @@ -38,7 +38,6 @@ #define MAX_PIN_NUM 8 struct mlx5_pps { u8 pin_caps[MAX_PIN_NUM]; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Jianbo Liu , Moshe Shemesh , Leon Romanovsky , Mark Bloch , Carolina Jubran , Dragos Tatulea , Tariq Toukan Subject: [PATCH net-next 08/15] net/mlx5: Support one PTP device per hardware clock Date: Mon, 3 Feb 2025 23:35:09 +0200 Message-ID: <20250203213516.227902-9-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250203213516.227902-1-tariqt@nvidia.com> References: <20250203213516.227902-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002321:EE_|SJ0PR12MB8089:EE_ X-MS-Office365-Filtering-Correlation-Id: 8520dbab-214b-46e9-5f36-08dd449adfee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: ZnI4+4eLBZqaILMgqIvyXpamuCu1oNkEKOC3/VvoaNnTwXOa+5UIdFNKK3tKsrw39sZKMxUJ2cAeJGg+mzN36oOzphRbpbHxi6BPMvXAFOAiNAX8r7lNYQthFc0+VmFniCnH21cbHsi1SZmZlZxvFoDag8X4wurbtK/vrjXiaNowhuijtdo/mVIbQSqDGhvmBUoyO63N6JRJsKSOsL1R42mbqs4+XaxKZP89CpvNkSr7FpZq7yzqBbcGOkf49LgIeKtZKIOesflCHXX3WdeMYcLhZ65BT6coJt0NE+Dv2ysbdBuZBRErxG+zgyUJBAQzVnbVchNimBdt12ELb5a9wJEt7/MWFjvJbFiS19FUFw650bqO+0nhl0R7Ad93ZOhJdXY7hlGfDpFBJufgGixlnA7rgJTqLL6LrSOuN+OT51rZ5CbgGM/QG4zx70y0sLD/sgdRqKaarlIOMmkD8F0I0oxO7uoTW5fppbMHFRYVQ8eugHIo8t1TrmXdzy+BN5lYV+ESg/VmiDBtb/UVCegWp0OwRObtkW4mw9bo+N43m1Raozo3nYUmMMHf7a1kSFc1n1m1Oupwyn+/N8QrG6mGzzfYx3pUb87Djq5OZrP7G248g3wySGhIhzTfHA1y6ldznGVs6yTsoiD7pEjVgsUWk1J205lavIcwZaapqmPGmVflpGqDKE11t+D15cd/f7DmDmxdyhDuIK4O+H7Nm80GvVy0rc6xKVMg1XZqyCla6hI1qxddAUHhrdkyHCC4q2rMoJGmGZ++WyyTin2kxUqDGPeKMiGdFBvk68c/JX4YOLvldfEtp/1iGmn85j3tWJ35gHmjO5ypIm/Lk+vbL7ksv/PRSVeXUvdZ1rMRMlahRvNNFqBwh/6T2G9gZWM7dxG6dDG28XBOMfRA3WQKWuLt9XdmOipIJVyfuG39JS7tBWwjQobOun51e7qLufq+bIwVOGAyLyEwKFhbGXAMd/uizlNFFxDYlutpY+oVFeArMJAOwNbByQNsZhFR4Wlw+YIyrebG/JeY8g22GwH+IjsBtFTuGQ2IPccdaja14/Z6bIZZVOy8gVSMwiM49tUxDdd9rE+Ko5uwPyFNCST/lFI4T9A9puMfuvv1IhlW9VyJgkUk25ZO/88MOTuwesHb1WhUAeoKqEny58AqlWlh5i3mqcupTIf2vvthGEyFOm83PpyKos6U7VZOG6NhjkmtaFR8T3ANKtHmnvrAtkIzT0OVVGasCvstkt8WR2pqJqYHY7wNW/KLh/ledhdpgAxRmseViU8dPGN39+fGMC8Ey8fu5o7GasAooh2VXo+6yWOpMBrBgpTOpgFX2uaJ1eE4baGtcYYNsl14k9bmSRE8BqgnKbNwkgsHJoAAzorWsfU2WgSwgY9J7ApTL8VhRUKU90DXgC6tetAtE5+XWY6WjJaNn2h5M4YhSYmRUzsib3ikng6YTKvJVxdAk7vibn8hlUvhvZRLBIzNRCsrs1hSOvx3jkPY74ytUcjSnUYsPM85OFE= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2025 21:36:52.8446 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8520dbab-214b-46e9-5f36-08dd449adfee X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002321.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB8089 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu Currently, mlx5 driver exposes a PTP device for each network interface, resulting in multiple device nodes representing the same underlying PHC (PTP hardware clock). This causes problem if it is trying to synchronize to itself. For instance, when ptp4l operates on multiple interfaces following different masters, phc2sys attempts to synchronize them in automatic mode. PHC can be configured to work as free running mode or real time mode. All functions can access it directly. In this patch, we create one PTP device for each PHC when it's running in real time mode. All the functions share the same PTP device if the clock identifies they query are same, and they are already grouped by devcom in previous commit. The first mdev in the peer list is chosen when sending MTPPS/MTUTC/MTPPSE/MRTCQ to firmware. Since the function can be unloaded at any time, we need to use a mutex lock to protect the mdev pointer used in PTP and PPS callbacks. Besides, new one should be picked from the peer list when the current is not available. The clock info, which is used by IB, is shared by all the interfaces using the same hardware clock. Signed-off-by: Jianbo Liu Reviewed-by: Carolina Jubran Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/lib/clock.c | 250 ++++++++++++++---- .../ethernet/mellanox/mlx5/core/lib/clock.h | 1 + 2 files changed, 203 insertions(+), 48 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index 2586b0788b40..42df3a6fda93 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -89,6 +89,7 @@ struct mlx5_clock_dev_state { struct mlx5_clock_priv { struct mlx5_clock clock; struct mlx5_core_dev *mdev; + struct mutex lock; /* protect mdev and used in PTP callbacks */ }; static struct mlx5_clock_priv *clock_priv(struct mlx5_clock *clock) @@ -96,11 +97,37 @@ static struct mlx5_clock_priv *clock_priv(struct mlx5_clock *clock) return container_of(clock, struct mlx5_clock_priv, clock); } +static void mlx5_clock_lockdep_assert(struct mlx5_clock *clock) +{ + if (!clock->shared) + return; + + lockdep_assert(lockdep_is_held(&clock_priv(clock)->lock)); +} + static struct mlx5_core_dev *mlx5_clock_mdev_get(struct mlx5_clock *clock) { + mlx5_clock_lockdep_assert(clock); + return clock_priv(clock)->mdev; } +static void mlx5_clock_lock(struct mlx5_clock *clock) +{ + if (!clock->shared) + return; + + mutex_lock(&clock_priv(clock)->lock); +} + +static void mlx5_clock_unlock(struct mlx5_clock *clock) +{ + if (!clock->shared) + return; + + mutex_unlock(&clock_priv(clock)->lock); +} + static bool mlx5_real_time_mode(struct mlx5_core_dev *mdev) { return (mlx5_is_real_time_rq(mdev) || mlx5_is_real_time_sq(mdev)); @@ -170,10 +197,14 @@ static s32 mlx5_ptp_getmaxphase(struct ptp_clock_info *ptp) { struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); struct mlx5_core_dev *mdev; + s32 ret; + mlx5_clock_lock(clock); mdev = mlx5_clock_mdev_get(clock); + ret = mlx5_clock_getmaxphase(mdev); + mlx5_clock_unlock(clock); - return mlx5_clock_getmaxphase(mdev); + return ret; } static bool mlx5_is_mtutc_time_adj_cap(struct mlx5_core_dev *mdev, s64 delta) @@ -265,16 +296,23 @@ static int mlx5_ptp_getcrosststamp(struct ptp_clock_info *ptp, struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); struct system_time_snapshot history_begin = {0}; struct mlx5_core_dev *mdev; + int err; + mlx5_clock_lock(clock); mdev = mlx5_clock_mdev_get(clock); - if (!mlx5_is_ptm_source_time_available(mdev)) - return -EBUSY; + if (!mlx5_is_ptm_source_time_available(mdev)) { + err = -EBUSY; + goto unlock; + } ktime_get_snapshot(&history_begin); - return get_device_system_crosststamp(mlx5_mtctr_syncdevicetime, mdev, - &history_begin, cts); + err = get_device_system_crosststamp(mlx5_mtctr_syncdevicetime, mdev, + &history_begin, cts); +unlock: + mlx5_clock_unlock(clock); + return err; } #endif /* CONFIG_X86 */ @@ -372,6 +410,7 @@ static long mlx5_timestamp_overflow(struct ptp_clock_info *ptp_info) unsigned long flags; clock = container_of(ptp_info, struct mlx5_clock, ptp_info); + mlx5_clock_lock(clock); mdev = mlx5_clock_mdev_get(clock); timer = &clock->timer; @@ -384,6 +423,7 @@ static long mlx5_timestamp_overflow(struct ptp_clock_info *ptp_info) write_sequnlock_irqrestore(&clock->lock, flags); out: + mlx5_clock_unlock(clock); return timer->overflow_period; } @@ -428,10 +468,14 @@ static int mlx5_ptp_settime(struct ptp_clock_info *ptp, const struct timespec64 { struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); struct mlx5_core_dev *mdev; + int err; + mlx5_clock_lock(clock); mdev = mlx5_clock_mdev_get(clock); + err = mlx5_clock_settime(mdev, clock, ts); + mlx5_clock_unlock(clock); - return mlx5_clock_settime(mdev, clock, ts); + return err; } static @@ -453,6 +497,7 @@ static int mlx5_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts, struct mlx5_core_dev *mdev; u64 cycles, ns; + mlx5_clock_lock(clock); mdev = mlx5_clock_mdev_get(clock); if (mlx5_real_time_mode(mdev)) { *ts = mlx5_ptp_gettimex_real_time(mdev, sts); @@ -463,6 +508,7 @@ static int mlx5_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts, ns = mlx5_timecounter_cyc2time(clock, cycles); *ts = ns_to_timespec64(ns); out: + mlx5_clock_unlock(clock); return 0; } @@ -493,14 +539,16 @@ static int mlx5_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) struct mlx5_timer *timer = &clock->timer; struct mlx5_core_dev *mdev; unsigned long flags; + int err = 0; + mlx5_clock_lock(clock); mdev = mlx5_clock_mdev_get(clock); if (mlx5_modify_mtutc_allowed(mdev)) { - int err = mlx5_ptp_adjtime_real_time(mdev, delta); + err = mlx5_ptp_adjtime_real_time(mdev, delta); if (err) - return err; + goto unlock; } write_seqlock_irqsave(&clock->lock, flags); @@ -508,17 +556,23 @@ static int mlx5_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) mlx5_update_clock_info_page(mdev); write_sequnlock_irqrestore(&clock->lock, flags); - return 0; +unlock: + mlx5_clock_unlock(clock); + return err; } static int mlx5_ptp_adjphase(struct ptp_clock_info *ptp, s32 delta) { struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); struct mlx5_core_dev *mdev; + int err; + mlx5_clock_lock(clock); mdev = mlx5_clock_mdev_get(clock); + err = mlx5_ptp_adjtime_real_time(mdev, delta); + mlx5_clock_unlock(clock); - return mlx5_ptp_adjtime_real_time(mdev, delta); + return err; } static int mlx5_ptp_freq_adj_real_time(struct mlx5_core_dev *mdev, long scaled_ppm) @@ -547,15 +601,17 @@ static int mlx5_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) struct mlx5_timer *timer = &clock->timer; struct mlx5_core_dev *mdev; unsigned long flags; + int err = 0; u32 mult; + mlx5_clock_lock(clock); mdev = mlx5_clock_mdev_get(clock); if (mlx5_modify_mtutc_allowed(mdev)) { - int err = mlx5_ptp_freq_adj_real_time(mdev, scaled_ppm); + err = mlx5_ptp_freq_adj_real_time(mdev, scaled_ppm); if (err) - return err; + goto unlock; } mult = (u32)adjust_by_scaled_ppm(timer->nominal_c_mult, scaled_ppm); @@ -567,7 +623,9 @@ static int mlx5_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) write_sequnlock_irqrestore(&clock->lock, flags); ptp_schedule_worker(clock->ptp, timer->overflow_period); - return 0; +unlock: + mlx5_clock_unlock(clock); + return err; } static int mlx5_extts_configure(struct ptp_clock_info *ptp, @@ -576,17 +634,14 @@ static int mlx5_extts_configure(struct ptp_clock_info *ptp, { struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); - struct mlx5_core_dev *mdev = mlx5_clock_mdev_get(clock); u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0}; + struct mlx5_core_dev *mdev; u32 field_select = 0; u8 pin_mode = 0; u8 pattern = 0; int pin = -1; int err = 0; - if (!MLX5_PPS_CAP(mdev)) - return -EOPNOTSUPP; - /* Reject requests with unsupported flags */ if (rq->extts.flags & ~(PTP_ENABLE_FEATURE | PTP_RISING_EDGE | @@ -617,6 +672,14 @@ static int mlx5_extts_configure(struct ptp_clock_info *ptp, field_select = MLX5_MTPPS_FS_ENABLE; } + mlx5_clock_lock(clock); + mdev = mlx5_clock_mdev_get(clock); + + if (!MLX5_PPS_CAP(mdev)) { + err = -EOPNOTSUPP; + goto unlock; + } + MLX5_SET(mtpps_reg, in, pin, pin); MLX5_SET(mtpps_reg, in, pin_mode, pin_mode); MLX5_SET(mtpps_reg, in, pattern, pattern); @@ -625,10 +688,13 @@ static int mlx5_extts_configure(struct ptp_clock_info *ptp, err = mlx5_set_mtpps(mdev, in, sizeof(in)); if (err) - return err; + goto unlock; + + err = mlx5_set_mtppse(mdev, pin, 0, MLX5_EVENT_MODE_REPETETIVE & on); - return mlx5_set_mtppse(mdev, pin, 0, - MLX5_EVENT_MODE_REPETETIVE & on); +unlock: + mlx5_clock_unlock(clock); + return err; } static u64 find_target_cycles(struct mlx5_core_dev *mdev, s64 target_ns) @@ -760,25 +826,18 @@ static int mlx5_perout_configure(struct ptp_clock_info *ptp, { struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); - struct mlx5_core_dev *mdev = mlx5_clock_mdev_get(clock); - bool rt_mode = mlx5_real_time_mode(mdev); u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0}; u32 out_pulse_duration_ns = 0; + struct mlx5_core_dev *mdev; u32 field_select = 0; u64 npps_period = 0; u64 time_stamp = 0; u8 pin_mode = 0; u8 pattern = 0; + bool rt_mode; int pin = -1; int err = 0; - if (!MLX5_PPS_CAP(mdev)) - return -EOPNOTSUPP; - - /* Reject requests with unsupported flags */ - if (mlx5_perout_verify_flags(mdev, rq->perout.flags)) - return -EOPNOTSUPP; - if (rq->perout.index >= clock->ptp_info.n_pins) return -EINVAL; @@ -787,14 +846,29 @@ static int mlx5_perout_configure(struct ptp_clock_info *ptp, if (pin < 0) return -EBUSY; - if (on) { - bool rt_mode = mlx5_real_time_mode(mdev); + mlx5_clock_lock(clock); + mdev = mlx5_clock_mdev_get(clock); + rt_mode = mlx5_real_time_mode(mdev); + + if (!MLX5_PPS_CAP(mdev)) { + err = -EOPNOTSUPP; + goto unlock; + } + + /* Reject requests with unsupported flags */ + if (mlx5_perout_verify_flags(mdev, rq->perout.flags)) { + err = -EOPNOTSUPP; + goto unlock; + } + if (on) { pin_mode = MLX5_PIN_MODE_OUT; pattern = MLX5_OUT_PATTERN_PERIODIC; - if (rt_mode && rq->perout.start.sec > U32_MAX) - return -EINVAL; + if (rt_mode && rq->perout.start.sec > U32_MAX) { + err = -EINVAL; + goto unlock; + } field_select |= MLX5_MTPPS_FS_PIN_MODE | MLX5_MTPPS_FS_PATTERN | @@ -807,7 +881,7 @@ static int mlx5_perout_configure(struct ptp_clock_info *ptp, else err = perout_conf_1pps(mdev, rq, &time_stamp, rt_mode); if (err) - return err; + goto unlock; } MLX5_SET(mtpps_reg, in, pin, pin); @@ -820,13 +894,16 @@ static int mlx5_perout_configure(struct ptp_clock_info *ptp, MLX5_SET(mtpps_reg, in, out_pulse_duration_ns, out_pulse_duration_ns); err = mlx5_set_mtpps(mdev, in, sizeof(in)); if (err) - return err; + goto unlock; if (rt_mode) - return 0; + goto unlock; - return mlx5_set_mtppse(mdev, pin, 0, - MLX5_EVENT_MODE_REPETETIVE & on); + err = mlx5_set_mtppse(mdev, pin, 0, MLX5_EVENT_MODE_REPETETIVE & on); + +unlock: + mlx5_clock_unlock(clock); + return err; } static int mlx5_pps_configure(struct ptp_clock_info *ptp, @@ -1043,6 +1120,10 @@ static int mlx5_pps_event(struct notifier_block *nb, ptp_clock_event(clock->ptp, &ptp_event); break; case PTP_PF_PEROUT: + if (clock->shared) { + mlx5_core_warn(mdev, " Received unexpected PPS out event\n"); + break; + } ns = perout_conf_next_event_timer(mdev, clock); write_seqlock_irqsave(&clock->lock, flags); clock->pps_info.start[pin] = ns; @@ -1201,9 +1282,10 @@ static void mlx5_init_clock_dev(struct mlx5_core_dev *mdev) mlx5_init_pps(mdev); clock->ptp = ptp_clock_register(&clock->ptp_info, - &mdev->pdev->dev); + clock->shared ? NULL : &mdev->pdev->dev); if (IS_ERR(clock->ptp)) { - mlx5_core_warn(mdev, "ptp_clock_register failed %ld\n", + mlx5_core_warn(mdev, "%sptp_clock_register failed %ld\n", + clock->shared ? "shared clock " : "", PTR_ERR(clock->ptp)); clock->ptp = NULL; } @@ -1234,11 +1316,12 @@ static void mlx5_clock_free(struct mlx5_core_dev *mdev) struct mlx5_clock_priv *cpriv = clock_priv(mdev->clock); mlx5_destroy_clock_dev(mdev); + mutex_destroy(&cpriv->lock); kfree(cpriv); mdev->clock = NULL; } -static int mlx5_clock_alloc(struct mlx5_core_dev *mdev) +static int mlx5_clock_alloc(struct mlx5_core_dev *mdev, bool shared) { struct mlx5_clock_priv *cpriv; struct mlx5_clock *clock; @@ -1247,23 +1330,90 @@ static int mlx5_clock_alloc(struct mlx5_core_dev *mdev) if (!cpriv) return -ENOMEM; + mutex_init(&cpriv->lock); cpriv->mdev = mdev; clock = &cpriv->clock; + clock->shared = shared; mdev->clock = clock; + mlx5_clock_lock(clock); mlx5_init_clock_dev(mdev); + mlx5_clock_unlock(clock); + + if (!clock->shared) + return 0; + + if (!clock->ptp) { + mlx5_core_warn(mdev, "failed to create ptp dev shared by multiple functions"); + mlx5_clock_free(mdev); + return -EINVAL; + } return 0; } static void mlx5_shared_clock_register(struct mlx5_core_dev *mdev, u64 key) { + struct mlx5_core_dev *peer_dev, *next = NULL; + struct mlx5_devcom_comp_dev *pos; + mdev->clock_state->compdev = mlx5_devcom_register_component(mdev->priv.devc, MLX5_DEVCOM_SHARED_CLOCK, key, NULL, mdev); + if (IS_ERR(mdev->clock_state->compdev)) + return; + + mlx5_devcom_comp_lock(mdev->clock_state->compdev); + mlx5_devcom_for_each_peer_entry(mdev->clock_state->compdev, peer_dev, pos) { + if (peer_dev->clock) { + next = peer_dev; + break; + } + } + + if (next) { + mdev->clock = next->clock; + /* clock info is shared among all the functions using the same clock */ + mdev->clock_info = next->clock_info; + } else { + mlx5_clock_alloc(mdev, true); + } + mlx5_devcom_comp_unlock(mdev->clock_state->compdev); + + if (!mdev->clock) { + mlx5_devcom_unregister_component(mdev->clock_state->compdev); + mdev->clock_state->compdev = NULL; + } } static void mlx5_shared_clock_unregister(struct mlx5_core_dev *mdev) { + struct mlx5_core_dev *peer_dev, *next = NULL; + struct mlx5_clock *clock = mdev->clock; + struct mlx5_devcom_comp_dev *pos; + + mlx5_devcom_comp_lock(mdev->clock_state->compdev); + mlx5_devcom_for_each_peer_entry(mdev->clock_state->compdev, peer_dev, pos) { + if (peer_dev->clock && peer_dev != mdev) { + next = peer_dev; + break; + } + } + + if (next) { + struct mlx5_clock_priv *cpriv = clock_priv(clock); + + mlx5_clock_lock(clock); + if (mdev == cpriv->mdev) + cpriv->mdev = next; + mlx5_clock_unlock(clock); + } else { + mlx5_clock_free(mdev); + } + + mdev->clock = NULL; + mdev->clock_info = NULL; + mlx5_devcom_comp_unlock(mdev->clock_state->compdev); + mlx5_devcom_unregister_component(mdev->clock_state->compdev); } @@ -1297,11 +1447,13 @@ int mlx5_init_clock(struct mlx5_core_dev *mdev) } } - err = mlx5_clock_alloc(mdev); - if (err) { - kfree(clock_state); - mdev->clock_state = NULL; - return err; + if (!mdev->clock) { + err = mlx5_clock_alloc(mdev, false); + if (err) { + kfree(clock_state); + mdev->clock_state = NULL; + return err; + } } INIT_WORK(&mdev->clock_state->out_work, mlx5_pps_out); @@ -1319,8 +1471,10 @@ void mlx5_cleanup_clock(struct mlx5_core_dev *mdev) mlx5_eq_notifier_unregister(mdev, &mdev->clock_state->pps_nb); cancel_work_sync(&mdev->clock_state->out_work); - mlx5_clock_free(mdev); - mlx5_shared_clock_unregister(mdev); + if (mdev->clock->shared) + mlx5_shared_clock_unregister(mdev); + else + mlx5_clock_free(mdev); kfree(mdev->clock_state); mdev->clock_state = NULL; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h index 3c5fee246582..093fa131014a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h @@ -58,6 +58,7 @@ struct mlx5_clock { struct ptp_clock_info ptp_info; struct mlx5_pps pps_info; struct mlx5_timer timer; + bool shared; }; static inline bool mlx5_is_real_time_rq(struct mlx5_core_dev *mdev) From patchwork Mon Feb 3 21:35:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13958277 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2074.outbound.protection.outlook.com [40.107.243.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20CF520FA9A for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Jianbo Liu , Moshe Shemesh , Leon Romanovsky , Mark Bloch , Carolina Jubran , Dragos Tatulea , Tariq Toukan Subject: [PATCH net-next 09/15] net/mlx5: Generate PPS IN event on new function for shared clock Date: Mon, 3 Feb 2025 23:35:10 +0200 Message-ID: <20250203213516.227902-10-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250203213516.227902-1-tariqt@nvidia.com> References: <20250203213516.227902-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002324:EE_|DM4PR12MB5916:EE_ X-MS-Office365-Filtering-Correlation-Id: c2b87224-d436-4841-8cd4-08dd449ae39f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: QA5p991JMzc6Le+u6OZZVEo2x/gQWCIQkKlNmsJUa4+mbuIvZLG0kJA+sfnzbrMGtP9Wtve5hRCg3bj6x4CM1gWuZ0kqTBFz4YcBSZKDtC/27Rqlu9D49pxVS7mzzZoIJtheOzNfteGhFsWmx3s9ySQcEbUbdeNxdy+lk2nAbIg1gnwC1AflMZ3IVbTiRT/BOm2/5tKD8G4uYDFwq/xXr5lB7CaUmZKRXKnNtuEkfDGMtTpPRPgbToWnIG/Y0i94PBVohI49eUv/f5Jd4V4tdhwASCgioSbXxr/M3VpaGGsv3yyCySXQYDY/pjifxXHNWgoACGa7HH5gLvc29AUVhY4X24hrJ8qFGBP9gJNxP0I5TIeGttkNFCaBv5wzaKxOb/GCho38hOnwfj1FANQvDizXeUva7W1ie57P3QCDPIl+IaqwWMka2s78SKL6ICq4S/K4KxctVdAmtQyuTe02HhgT/uUriUvQ/dlCFvs2CS4KUcUt27+yo7DjOpnlH/nL3ilYaCamCU0C8TckSEwBI5cHrrhBeehAyyIw3el6wIJAItA5GN3G8cU6brNWtuVNOzCW0u6vg16/UJx/zVh3EcJYHJz+oXV4WVKf1OW2IubDD+mDZE+Os6T75o/o+PcIjdKtwVq28jDiogoT35QrsGvbp1rP+kCJfF1gHqnDSZh9xw2MPJVY3L6EEOidfVBJRmOoNt6GTyLVttHJ6l68Ms/uFYyV8vIq5PBIzoV0qeeeUh8QySDfMEEbqAagmK8nJzMnfpXxu+KzntlTD4J7nkmU2LjbJsOgoHPzAJp096r9GIer646w7DFxaCTnCXBWAkqbJ45gSHQa4NGiI6Mi++AgH+ozI3GSvm/NofMnNYiI861NKdfnBFIkLaQAdxgAG5GWEcLN97cBVnUx9e4U7F4VHUUWlohMD6+W/103Fv4dKxTPCwkY+DHiLvNIuDbepoW01p52YqACpWrrRs2WkoaY1TrQH+L2e9g9ZBlmmvuXoJjroqifzB6BONtAMd0U+pMPym/2TjY4Cq+3Iek8SHikdX4FHv4yvVjwBdDCwwLdztAtHVLit8Rjeee82//pELsfL1/ZHfygNQ3Fyw5b0g4M+qKhz3c2ZD+vvfm4I1RN4zpB6fYojUVpRioVTIV5m5pZo+RRXP37OMndBk168umkHTv4xwrlVF8zMoE+vZROCRsVHliAJo1w7vd+FxgAKORM0YoJW7NsPz22M9oOhY46K17EYBI2LMvMPl2oN13byXQTk4nC1XuPXAZdStLDJNNRfUMKcAoE4HQMYX8w2ZYf4HVrgGbyr9iVXWMRGha//swu0YqD+lH1Jr04KnM7eKu71N58treTeg5lnz7tCfOKvYXnJTpguKYQgv0liM5JxXk5shyQTUz1SVg9ag8VbLe0FIBrSaPStkYGaX9F5qhv7SjoEmKPwrA6N/XSzAENScvkWfKrMOZIv2ErRWFYSTOhgFGGoohiZ2gs7DW7bHEybuI3+L2nFSa7HxsE02g= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2025 21:36:59.0702 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c2b87224-d436-4841-8cd4-08dd449ae39f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002324.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5916 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu As a specific function (mdev) is chosen to send MTPPSE command to firmware, the event is generated only on that function. When that function is unloaded, the PPS event can't be forward to PTP device, even when there are other functions in the group, and PTP device is not destroyed. To resolve this problem, need to send MTPPSE again from new function, and dis-arm the event on old function after that. PPS events are handled by EQ notifier. The async EQs and notifiers are destroyed in mlx5_eq_table_destroy() which is called before mlx5_cleanup_clock(). During the period between mlx5_eq_table_destroy() and mlx5_cleanup_clock(), the events can't be handled. To avoid event loss, add mlx5_clock_unload() in mlx5_unload() to arm the event on other available function, and mlx5_clock_load in mlx5_load() for symmetry. Signed-off-by: Jianbo Liu Reviewed-by: Carolina Jubran Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/lib/clock.c | 97 +++++++++++++++++-- .../ethernet/mellanox/mlx5/core/lib/clock.h | 5 + .../net/ethernet/mellanox/mlx5/core/main.c | 4 + 3 files changed, 99 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index 42df3a6fda93..65a94e46edcf 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -90,6 +90,7 @@ struct mlx5_clock_priv { struct mlx5_clock clock; struct mlx5_core_dev *mdev; struct mutex lock; /* protect mdev and used in PTP callbacks */ + struct mlx5_core_dev *event_mdev; }; static struct mlx5_clock_priv *clock_priv(struct mlx5_clock *clock) @@ -691,6 +692,11 @@ static int mlx5_extts_configure(struct ptp_clock_info *ptp, goto unlock; err = mlx5_set_mtppse(mdev, pin, 0, MLX5_EVENT_MODE_REPETETIVE & on); + if (err) + goto unlock; + + clock->pps_info.pin_armed[pin] = on; + clock_priv(clock)->event_mdev = mdev; unlock: mlx5_clock_unlock(clock); @@ -1417,6 +1423,90 @@ static void mlx5_shared_clock_unregister(struct mlx5_core_dev *mdev) mlx5_devcom_unregister_component(mdev->clock_state->compdev); } +static void mlx5_clock_arm_pps_in_event(struct mlx5_clock *clock, + struct mlx5_core_dev *new_mdev, + struct mlx5_core_dev *old_mdev) +{ + struct ptp_clock_info *ptp_info = &clock->ptp_info; + struct mlx5_clock_priv *cpriv = clock_priv(clock); + int i; + + for (i = 0; i < ptp_info->n_pins; i++) { + if (ptp_info->pin_config[i].func != PTP_PF_EXTTS || + !clock->pps_info.pin_armed[i]) + continue; + + if (new_mdev) { + mlx5_set_mtppse(new_mdev, i, 0, MLX5_EVENT_MODE_REPETETIVE); + cpriv->event_mdev = new_mdev; + } else { + cpriv->event_mdev = NULL; + } + + if (old_mdev) + mlx5_set_mtppse(old_mdev, i, 0, MLX5_EVENT_MODE_DISABLE); + } +} + +void mlx5_clock_load(struct mlx5_core_dev *mdev) +{ + struct mlx5_clock *clock = mdev->clock; + struct mlx5_clock_priv *cpriv; + + if (!MLX5_CAP_GEN(mdev, device_frequency_khz)) + return; + + INIT_WORK(&mdev->clock_state->out_work, mlx5_pps_out); + MLX5_NB_INIT(&mdev->clock_state->pps_nb, mlx5_pps_event, PPS_EVENT); + mlx5_eq_notifier_register(mdev, &mdev->clock_state->pps_nb); + + if (!clock->shared) { + mlx5_clock_arm_pps_in_event(clock, mdev, NULL); + return; + } + + cpriv = clock_priv(clock); + mlx5_devcom_comp_lock(mdev->clock_state->compdev); + mlx5_clock_lock(clock); + if (mdev == cpriv->mdev && mdev != cpriv->event_mdev) + mlx5_clock_arm_pps_in_event(clock, mdev, cpriv->event_mdev); + mlx5_clock_unlock(clock); + mlx5_devcom_comp_unlock(mdev->clock_state->compdev); +} + +void mlx5_clock_unload(struct mlx5_core_dev *mdev) +{ + struct mlx5_core_dev *peer_dev, *next = NULL; + struct mlx5_clock *clock = mdev->clock; + struct mlx5_devcom_comp_dev *pos; + + if (!MLX5_CAP_GEN(mdev, device_frequency_khz)) + return; + + if (!clock->shared) { + mlx5_clock_arm_pps_in_event(clock, NULL, mdev); + goto out; + } + + mlx5_devcom_comp_lock(mdev->clock_state->compdev); + mlx5_devcom_for_each_peer_entry(mdev->clock_state->compdev, peer_dev, pos) { + if (peer_dev->clock && peer_dev != mdev) { + next = peer_dev; + break; + } + } + + mlx5_clock_lock(clock); + if (mdev == clock_priv(clock)->event_mdev) + mlx5_clock_arm_pps_in_event(clock, next, mdev); + mlx5_clock_unlock(clock); + mlx5_devcom_comp_unlock(mdev->clock_state->compdev); + +out: + mlx5_eq_notifier_unregister(mdev, &mdev->clock_state->pps_nb); + cancel_work_sync(&mdev->clock_state->out_work); +} + static struct mlx5_clock null_clock; int mlx5_init_clock(struct mlx5_core_dev *mdev) @@ -1456,10 +1546,6 @@ int mlx5_init_clock(struct mlx5_core_dev *mdev) } } - INIT_WORK(&mdev->clock_state->out_work, mlx5_pps_out); - MLX5_NB_INIT(&mdev->clock_state->pps_nb, mlx5_pps_event, PPS_EVENT); - mlx5_eq_notifier_register(mdev, &mdev->clock_state->pps_nb); - return 0; } @@ -1468,9 +1554,6 @@ void mlx5_cleanup_clock(struct mlx5_core_dev *mdev) if (!MLX5_CAP_GEN(mdev, device_frequency_khz)) return; - mlx5_eq_notifier_unregister(mdev, &mdev->clock_state->pps_nb); - cancel_work_sync(&mdev->clock_state->out_work); - if (mdev->clock->shared) mlx5_shared_clock_unregister(mdev); else diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h index 093fa131014a..c18a652c0faa 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h @@ -42,6 +42,7 @@ struct mlx5_pps { u8 enabled; u64 min_npps_period; u64 min_out_pulse_duration_ns; + bool pin_armed[MAX_PIN_NUM]; }; struct mlx5_timer { @@ -84,6 +85,8 @@ typedef ktime_t (*cqe_ts_to_ns)(struct mlx5_clock *, u64); #if IS_ENABLED(CONFIG_PTP_1588_CLOCK) int mlx5_init_clock(struct mlx5_core_dev *mdev); void mlx5_cleanup_clock(struct mlx5_core_dev *mdev); +void mlx5_clock_load(struct mlx5_core_dev *mdev); +void mlx5_clock_unload(struct mlx5_core_dev *mdev); static inline int mlx5_clock_get_ptp_index(struct mlx5_core_dev *mdev) { @@ -117,6 +120,8 @@ static inline ktime_t mlx5_real_time_cyc2time(struct mlx5_clock *clock, #else static inline int mlx5_init_clock(struct mlx5_core_dev *mdev) { return 0; } static inline void mlx5_cleanup_clock(struct mlx5_core_dev *mdev) {} +static inline void mlx5_clock_load(struct mlx5_core_dev *mdev) {} +static inline void mlx5_clock_unload(struct mlx5_core_dev *mdev) {} static inline int mlx5_clock_get_ptp_index(struct mlx5_core_dev *mdev) { return -1; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c index 996773521aee..710633d5fdbe 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -1364,6 +1364,8 @@ static int mlx5_load(struct mlx5_core_dev *dev) goto err_eq_table; } + mlx5_clock_load(dev); + err = mlx5_fw_tracer_init(dev->tracer); if (err) { mlx5_core_err(dev, "Failed to init FW tracer %d\n", err); @@ -1447,6 +1449,7 @@ static int mlx5_load(struct mlx5_core_dev *dev) mlx5_hv_vhca_cleanup(dev->hv_vhca); mlx5_fw_reset_events_stop(dev); mlx5_fw_tracer_cleanup(dev->tracer); + mlx5_clock_unload(dev); mlx5_eq_table_destroy(dev); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Jianbo Liu , Moshe Shemesh , Leon Romanovsky , Mark Bloch , Shahar Shitrit , Tariq Toukan Subject: [PATCH net-next 10/15] ethtool: Add support for 200Gbps per lane link modes Date: Mon, 3 Feb 2025 23:35:11 +0200 Message-ID: <20250203213516.227902-11-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250203213516.227902-1-tariqt@nvidia.com> References: <20250203213516.227902-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002322:EE_|BL3PR12MB6547:EE_ X-MS-Office365-Filtering-Correlation-Id: 3c435356-0963-4030-4139-08dd449ae80d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014; X-Microsoft-Antispam-Message-Info: tKD5rMlZ7afo5GNIh05bQzDMRb8/rtgHyisJ7ej4thWP82qqkHtszClc7YefRNZzmZXnqBpfnKISd2wNyBrqL0N26Fb449K6fo7Rli4vhfeAGFruvW51wc3UOG3ALIWRC94P1O/HoH5Fm4I4XgqwCqqnHjEzW7Jtkp2isvXSskqh8l6vD39mwPgnAhgrxpYF6rd66icH7FugcoNcPaf2ns9lsLTvKd4EjBxmI89P+rRMqF30tjZenUNjSzdyjqZkXiof+gjjZWc2t1paOAXTdxxUEuwH/kej+1L59oJjnTSYo0MU8hEeyGnVTOtudq7ymHUpxLIWGLFpO5Q8Jq28LnZ3pt8kQkepIPURaY2xkF3Sl7PDX+N2I5tPANIpYcojpc0WdPTDQKwhTlV9sF4aagvI/F9ukSALMluYtuV2hfTUZupy3duNu2lMyBfqhvkjPdpeNLkv9yFEZwxkdntUgJLB/OGmKtoYs03A5jk8ZNbL0yqmVPwHIonL4lUhuz1Q+Tiolu60CgGgxmcPDRuajla4rTpZR8G0kaJ6RklvygmlRT8YvjoiCrHcrgzwTxAzl5+C6Obp8E6lj4rIKVJH4wCgCvf4h5MFS4S8SditING+o0PvPPPKAqTmP5oKqSajpF7LHeJOjFQRfn6X4vKwqpuQkdPt/XVhp4k6uo980uhiUqFX5t7E2gZFdxm8HaXevxU7n+5sPl+3beEqL4JzhV5bBsNJf+1RF2jXqEfGlORBHPZ28Vj8g+A5RchuGecZgcAzddyR5RQz3n0nJk10erEMWqr94CTu5F8N6GFMZ+QmvdBdFqe/9KA8zDUCqx4Ij93MyPeC9rayDolsb7wHBLUwGaJjlrZh1BQM3vu45qtPG1VlFoNhyaBL/KaVf8noQtaCAYqYivH1ftQA4GCZAFLZLR/+uSvi2Uwf0bgPfxO62Y8Q6p5i4V0Q5av5qeVi+hTYFyqblhuZWAtPHaexgVEPtRrAz4sDD1/POk/paWOu6r2xDZoDuCd5HnJeseT01cxvoHQUWOjBTHVMw0rIzwMVBWplj2mjRQJpIzaLXnnpb03JEZpz63IMisxqIBQCFJYsqklbk+tLeQGgwnnrjZUYNSsCNf+1Hrsdr0y3xjv8Hp+njNJxo4MkP7RINw/H13bgxHfZg5ub0E9PmuHfsee0oVgYQkr50O7wAUY3HTFYgXQtsskpN2ew1h2dCF9MoZKYpZI+ZhsLsYeEagWhejQmNqYdl7V/0Hd4XtypeT7uiAoZ27qieejfVKpMLr/4W8FezwJyge7X98r+bvejEaa9LsVWmInF1MMvx3NHXZlGutKA4RxR9SKA3Esrhhg+omxsl3BDm5bAX69a5TEMnM6r9x2RXwH9kKTKSyFCgA/rnaTMVtgPQPY+Cuhgs2vCkdrXxlzR3g3JeL/rsXCRIacc4wiZzsEfUDEDXnIdPoFqZo0KdIvU/r3CFvpXrsOmGkSw9l8Xco5y7PeEz22VoqgX2xkPhK58wBaT/UoBNf0= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2025 21:37:06.5157 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3c435356-0963-4030-4139-08dd449ae80d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002322.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6547 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu Define 200G, 400G and 800G link modes using 200Gbps per lane. Signed-off-by: Jianbo Liu Reviewed-by: Shahar Shitrit Signed-off-by: Tariq Toukan --- drivers/net/phy/phy-core.c | 20 ++++++++++++++++- include/uapi/linux/ethtool.h | 18 ++++++++++++++++ net/ethtool/common.c | 42 ++++++++++++++++++++++++++++++++++++ 3 files changed, 79 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c index 6bf3ec985f3d..f181f05cb429 100644 --- a/drivers/net/phy/phy-core.c +++ b/drivers/net/phy/phy-core.c @@ -13,7 +13,7 @@ */ const char *phy_speed_to_str(int speed) { - BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 103, + BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 121, "Enum ethtool_link_mode_bit_indices and phylib are out of sync. " "If a speed or mode has been added please update phy_speed_to_str " "and the PHY settings array.\n"); @@ -169,6 +169,12 @@ static const struct phy_setting settings[] = { PHY_SETTING( 800000, FULL, 800000baseDR8_2_Full ), PHY_SETTING( 800000, FULL, 800000baseSR8_Full ), PHY_SETTING( 800000, FULL, 800000baseVR8_Full ), + PHY_SETTING( 800000, FULL, 800000baseCR4_Full ), + PHY_SETTING( 800000, FULL, 800000baseKR4_Full ), + PHY_SETTING( 800000, FULL, 800000baseDR4_Full ), + PHY_SETTING( 800000, FULL, 800000baseDR4_2_Full ), + PHY_SETTING( 800000, FULL, 800000baseSR4_Full ), + PHY_SETTING( 800000, FULL, 800000baseVR4_Full ), /* 400G */ PHY_SETTING( 400000, FULL, 400000baseCR8_Full ), PHY_SETTING( 400000, FULL, 400000baseKR8_Full ), @@ -180,6 +186,12 @@ static const struct phy_setting settings[] = { PHY_SETTING( 400000, FULL, 400000baseLR4_ER4_FR4_Full ), PHY_SETTING( 400000, FULL, 400000baseDR4_Full ), PHY_SETTING( 400000, FULL, 400000baseSR4_Full ), + PHY_SETTING( 400000, FULL, 400000baseCR2_Full ), + PHY_SETTING( 400000, FULL, 400000baseKR2_Full ), + PHY_SETTING( 400000, FULL, 400000baseDR2_Full ), + PHY_SETTING( 400000, FULL, 400000baseDR2_2_Full ), + PHY_SETTING( 400000, FULL, 400000baseSR2_Full ), + PHY_SETTING( 400000, FULL, 400000baseVR2_Full ), /* 200G */ PHY_SETTING( 200000, FULL, 200000baseCR4_Full ), PHY_SETTING( 200000, FULL, 200000baseKR4_Full ), @@ -191,6 +203,12 @@ static const struct phy_setting settings[] = { PHY_SETTING( 200000, FULL, 200000baseLR2_ER2_FR2_Full ), PHY_SETTING( 200000, FULL, 200000baseDR2_Full ), PHY_SETTING( 200000, FULL, 200000baseSR2_Full ), + PHY_SETTING( 200000, FULL, 200000baseCR_Full ), + PHY_SETTING( 200000, FULL, 200000baseKR_Full ), + PHY_SETTING( 200000, FULL, 200000baseDR_Full ), + PHY_SETTING( 200000, FULL, 200000baseDR_2_Full ), + PHY_SETTING( 200000, FULL, 200000baseSR_Full ), + PHY_SETTING( 200000, FULL, 200000baseVR_Full ), /* 100G */ PHY_SETTING( 100000, FULL, 100000baseCR4_Full ), PHY_SETTING( 100000, FULL, 100000baseKR4_Full ), diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h index d1089b88efc7..e0bd726f84c1 100644 --- a/include/uapi/linux/ethtool.h +++ b/include/uapi/linux/ethtool.h @@ -2057,6 +2057,24 @@ enum ethtool_link_mode_bit_indices { ETHTOOL_LINK_MODE_10baseT1S_Half_BIT = 100, ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT = 101, ETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT = 102, + ETHTOOL_LINK_MODE_200000baseCR_Full_BIT = 103, + ETHTOOL_LINK_MODE_200000baseKR_Full_BIT = 104, + ETHTOOL_LINK_MODE_200000baseDR_Full_BIT = 105, + ETHTOOL_LINK_MODE_200000baseDR_2_Full_BIT = 106, + ETHTOOL_LINK_MODE_200000baseSR_Full_BIT = 107, + ETHTOOL_LINK_MODE_200000baseVR_Full_BIT = 108, + ETHTOOL_LINK_MODE_400000baseCR2_Full_BIT = 109, + ETHTOOL_LINK_MODE_400000baseKR2_Full_BIT = 110, + ETHTOOL_LINK_MODE_400000baseDR2_Full_BIT = 111, + ETHTOOL_LINK_MODE_400000baseDR2_2_Full_BIT = 112, + ETHTOOL_LINK_MODE_400000baseSR2_Full_BIT = 113, + ETHTOOL_LINK_MODE_400000baseVR2_Full_BIT = 114, + ETHTOOL_LINK_MODE_800000baseCR4_Full_BIT = 115, + ETHTOOL_LINK_MODE_800000baseKR4_Full_BIT = 116, + ETHTOOL_LINK_MODE_800000baseDR4_Full_BIT = 117, + ETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT = 118, + ETHTOOL_LINK_MODE_800000baseSR4_Full_BIT = 119, + ETHTOOL_LINK_MODE_800000baseVR4_Full_BIT = 120, /* must be last entry */ __ETHTOOL_LINK_MODE_MASK_NBITS diff --git a/net/ethtool/common.c b/net/ethtool/common.c index 2bd77c94f9f1..5489d0c9d13f 100644 --- a/net/ethtool/common.c +++ b/net/ethtool/common.c @@ -213,6 +213,24 @@ const char link_mode_names[][ETH_GSTRING_LEN] = { __DEFINE_LINK_MODE_NAME(10, T1S, Half), __DEFINE_LINK_MODE_NAME(10, T1S_P2MP, Half), __DEFINE_LINK_MODE_NAME(10, T1BRR, Full), + __DEFINE_LINK_MODE_NAME(200000, CR, Full), + __DEFINE_LINK_MODE_NAME(200000, KR, Full), + __DEFINE_LINK_MODE_NAME(200000, DR, Full), + __DEFINE_LINK_MODE_NAME(200000, DR_2, Full), + __DEFINE_LINK_MODE_NAME(200000, SR, Full), + __DEFINE_LINK_MODE_NAME(200000, VR, Full), + __DEFINE_LINK_MODE_NAME(400000, CR2, Full), + __DEFINE_LINK_MODE_NAME(400000, KR2, Full), + __DEFINE_LINK_MODE_NAME(400000, DR2, Full), + __DEFINE_LINK_MODE_NAME(400000, DR2_2, Full), + __DEFINE_LINK_MODE_NAME(400000, SR2, Full), + __DEFINE_LINK_MODE_NAME(400000, VR2, Full), + __DEFINE_LINK_MODE_NAME(800000, CR4, Full), + __DEFINE_LINK_MODE_NAME(800000, KR4, Full), + __DEFINE_LINK_MODE_NAME(800000, DR4, Full), + __DEFINE_LINK_MODE_NAME(800000, DR4_2, Full), + __DEFINE_LINK_MODE_NAME(800000, SR4, Full), + __DEFINE_LINK_MODE_NAME(800000, VR4, Full), }; static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS); @@ -221,8 +239,11 @@ static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS); #define __LINK_MODE_LANES_CR4 4 #define __LINK_MODE_LANES_CR8 8 #define __LINK_MODE_LANES_DR 1 +#define __LINK_MODE_LANES_DR_2 1 #define __LINK_MODE_LANES_DR2 2 +#define __LINK_MODE_LANES_DR2_2 2 #define __LINK_MODE_LANES_DR4 4 +#define __LINK_MODE_LANES_DR4_2 4 #define __LINK_MODE_LANES_DR8 8 #define __LINK_MODE_LANES_KR 1 #define __LINK_MODE_LANES_KR2 2 @@ -251,6 +272,9 @@ static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS); #define __LINK_MODE_LANES_T1L 1 #define __LINK_MODE_LANES_T1S 1 #define __LINK_MODE_LANES_T1S_P2MP 1 +#define __LINK_MODE_LANES_VR 1 +#define __LINK_MODE_LANES_VR2 2 +#define __LINK_MODE_LANES_VR4 4 #define __LINK_MODE_LANES_VR8 8 #define __LINK_MODE_LANES_DR8_2 8 #define __LINK_MODE_LANES_T1BRR 1 @@ -378,6 +402,24 @@ const struct link_mode_info link_mode_params[] = { __DEFINE_LINK_MODE_PARAMS(10, T1S, Half), __DEFINE_LINK_MODE_PARAMS(10, T1S_P2MP, Half), __DEFINE_LINK_MODE_PARAMS(10, T1BRR, Full), + __DEFINE_LINK_MODE_PARAMS(200000, CR, Full), + __DEFINE_LINK_MODE_PARAMS(200000, KR, Full), + __DEFINE_LINK_MODE_PARAMS(200000, DR, Full), + __DEFINE_LINK_MODE_PARAMS(200000, DR_2, Full), + __DEFINE_LINK_MODE_PARAMS(200000, SR, Full), + __DEFINE_LINK_MODE_PARAMS(200000, VR, Full), + __DEFINE_LINK_MODE_PARAMS(400000, CR2, Full), + __DEFINE_LINK_MODE_PARAMS(400000, KR2, Full), + __DEFINE_LINK_MODE_PARAMS(400000, DR2, Full), + __DEFINE_LINK_MODE_PARAMS(400000, DR2_2, Full), + __DEFINE_LINK_MODE_PARAMS(400000, SR2, Full), + __DEFINE_LINK_MODE_PARAMS(400000, VR2, Full), + __DEFINE_LINK_MODE_PARAMS(800000, CR4, Full), + __DEFINE_LINK_MODE_PARAMS(800000, KR4, Full), + __DEFINE_LINK_MODE_PARAMS(800000, DR4, Full), + __DEFINE_LINK_MODE_PARAMS(800000, DR4_2, Full), + __DEFINE_LINK_MODE_PARAMS(800000, SR4, Full), + __DEFINE_LINK_MODE_PARAMS(800000, VR4, Full), }; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Jianbo Liu , Moshe Shemesh , Leon Romanovsky , Mark Bloch , Shahar Shitrit , Tariq Toukan Subject: [PATCH net-next 11/15] net/mlx5: Add support for 200Gbps per lane link modes Date: Mon, 3 Feb 2025 23:35:12 +0200 Message-ID: <20250203213516.227902-12-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250203213516.227902-1-tariqt@nvidia.com> References: <20250203213516.227902-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F66:EE_|SJ1PR12MB6121:EE_ X-MS-Office365-Filtering-Correlation-Id: 16497318-e9d2-4e4a-2219-08dd449ae829 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: JrTpa39heH1R5UnVJAoxZJl05eguN66MbNlZDoGpF3FLGfOka82+yXalSo1vzJQLi8F8b/3jGKH/rL26caqu19OPriH94KsOryPy1eLq9f6YDZ3HR5X57ADQus4RfJEgnYlLpij6XdeHRw8wb1JAUPX624B18dT8KEMiYT709cYzcPv6+TIWwNdYxe1/vZnVPgIvSsIZwZl3HZd2sPK3EOlgGHaLfKpHR8qEesTHbn/nWQGe/q73NIFJYMlL5HxnkGEf59zvv3ADlYQyvpmQIMNibLOeVrK7CCidPlODCrGUiH92qqJQcbGQAPmjFwJ6P9kCez4h+e3FRTW0g9dNMAunfyWKDyJ8Metfiha3HWR/JVFEs2cZQkbcIEZuMYSOj0niLdt7cQyBJE+5l0WYpuOmjz3CEX/6+Lg5fzANd6+h3GSSpCGwFeyYhVMu6J7YaRuMTwUMvFaKsALn21mLph0QEVblRuxmzxDYPfStIlJsbq4b4JERf1ch1/Un//6lD3t4u8dEifqMEYLGo0zc+DLt8yWEe70VfLWyue1jf8C+6sa4LtM75p4menJveF6nJd5D8dUpckwyOXXzJ3hr5RSVaFUH36kHho2ygvD30GRwIzdX13aSOxsEcjxQz+xyCnvBJ9sQfzjRY8nCUytskKJFdc94sOs4HhMHtCzO4+7pIpdV7HNrEJgnI+6oiCNnn7vUe4GHfddcJPCgqhKMlvB4MdYiNrPlzJ9UWoL7/toBfYQhiqFzFPgizGsxowWlRj5W2Kle+k5ZemVOtKDkoA218Aa+KamOyCrwqnvylKNaV2FqdNfeL3L4fpCQEfnOhyWGBJz3fpszr5/fpkTlJy1n2SfRtYzdMWZhr7lRH+yQ9x928yq8xDD/67RLS+FGKRnRcExsAMCo9ueN/95PjZsJjI0tKiIh331PsLxW14xu9piP7/LzByjfpvR9aLB3rhtcuEzmPBEI/lJz7AKXVgNwjf1ieL/CYNzNwCIUGgeFMq0EijpnLMrIPsJuPl/2LOjMr1XuCzrlmtzr9tTaRqWbakjP8HQ2q0QhTBLMRmpz3UVsli4kTR+xOY/+7Dar+VHTrE0evMi9kIGwMmzkfNe628u8YGIhjrdb6ESTwpaUnTP80xtJj33Sx1NUWbvcD+/P0Jli/dUiWJLIeAjwqPez/xufJAVa8CiTCGjzwKui5abMUaFIoGFuDHKrpVz3sWyzRf9TLt+X3vL08g83c2Z8nHiC0igJco0Lwi6L0dtJ9p58s4bSsOkVtLXeXo8RGqATEC3zHoc0u5PI1gaQdApUVwmYor5Azgsjn8JKqJ3g62CsH5N5XeEyeXhuXTn0OXVLwApEredoiQXNUxhKmpYWrSKaL5CJjU3hCaJxIDgjhE7uDQAcW+6+drkhU12teNmrhjjL6iYvJQSWxvi4s5//AFtCLOGxKBjHExHZom3yHmy7GbJfRPhSJ1KNswwYcxG0EoNhy7WAC+xofNMDA5AO09als1iAAkrA1SnQr+M= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2025 21:37:06.5890 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 16497318-e9d2-4e4a-2219-08dd449ae829 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F66.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6121 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu This patch exposes new link modes using 200Gbps per lane, including 200G, 400G and 800G modes. Signed-off-by: Jianbo Liu Reviewed-by: Shahar Shitrit Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en_ethtool.c | 21 +++++++++++++++++++ .../net/ethernet/mellanox/mlx5/core/port.c | 3 +++ include/linux/mlx5/port.h | 3 +++ 3 files changed, 27 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c index cae39198b4db..9c5fcc699515 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c @@ -237,6 +237,27 @@ void mlx5e_build_ptys2ethtool_map(void) ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT, ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT, ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT); + MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_1_200GBASE_CR1_KR1, ext, + ETHTOOL_LINK_MODE_200000baseCR_Full_BIT, + ETHTOOL_LINK_MODE_200000baseKR_Full_BIT, + ETHTOOL_LINK_MODE_200000baseDR_Full_BIT, + ETHTOOL_LINK_MODE_200000baseDR_2_Full_BIT, + ETHTOOL_LINK_MODE_200000baseSR_Full_BIT, + ETHTOOL_LINK_MODE_200000baseVR_Full_BIT); + MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_2_400GBASE_CR2_KR2, ext, + ETHTOOL_LINK_MODE_400000baseCR2_Full_BIT, + ETHTOOL_LINK_MODE_400000baseKR2_Full_BIT, + ETHTOOL_LINK_MODE_400000baseDR2_Full_BIT, + ETHTOOL_LINK_MODE_400000baseDR2_2_Full_BIT, + ETHTOOL_LINK_MODE_400000baseSR2_Full_BIT, + ETHTOOL_LINK_MODE_400000baseVR2_Full_BIT); + MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_800GAUI_4_800GBASE_CR4_KR4, ext, + ETHTOOL_LINK_MODE_800000baseCR4_Full_BIT, + ETHTOOL_LINK_MODE_800000baseKR4_Full_BIT, + ETHTOOL_LINK_MODE_800000baseDR4_Full_BIT, + ETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT, + ETHTOOL_LINK_MODE_800000baseSR4_Full_BIT, + ETHTOOL_LINK_MODE_800000baseVR4_Full_BIT); } static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/port.c b/drivers/net/ethernet/mellanox/mlx5/core/port.c index 50931584132b..3995df064101 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/port.c @@ -1105,6 +1105,9 @@ static const u32 mlx5e_ext_link_speed[MLX5E_EXT_LINK_MODES_NUMBER] = { [MLX5E_200GAUI_2_200GBASE_CR2_KR2] = 200000, [MLX5E_400GAUI_4_400GBASE_CR4_KR4] = 400000, [MLX5E_800GAUI_8_800GBASE_CR8_KR8] = 800000, + [MLX5E_200GAUI_1_200GBASE_CR1_KR1] = 200000, + [MLX5E_400GAUI_2_400GBASE_CR2_KR2] = 400000, + [MLX5E_800GAUI_4_800GBASE_CR4_KR4] = 800000, }; int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext, diff --git a/include/linux/mlx5/port.h b/include/linux/mlx5/port.h index e68d42b8ce65..fd625e0dd869 100644 --- a/include/linux/mlx5/port.h +++ b/include/linux/mlx5/port.h @@ -115,9 +115,12 @@ enum mlx5e_ext_link_mode { MLX5E_100GAUI_1_100GBASE_CR_KR = 11, MLX5E_200GAUI_4_200GBASE_CR4_KR4 = 12, MLX5E_200GAUI_2_200GBASE_CR2_KR2 = 13, + MLX5E_200GAUI_1_200GBASE_CR1_KR1 = 14, MLX5E_400GAUI_8_400GBASE_CR8 = 15, MLX5E_400GAUI_4_400GBASE_CR4_KR4 = 16, + MLX5E_400GAUI_2_400GBASE_CR2_KR2 = 17, MLX5E_800GAUI_8_800GBASE_CR8_KR8 = 19, + MLX5E_800GAUI_4_800GBASE_CR4_KR4 = 20, MLX5E_EXT_LINK_MODES_NUMBER, }; From patchwork Mon Feb 3 21:35:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13958279 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM02-DM3-obe.outbound.protection.outlook.com (mail-dm3nam02on2052.outbound.protection.outlook.com [40.107.95.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0074720FA9D for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Jianbo Liu , Moshe Shemesh , Leon Romanovsky , Mark Bloch , Shahar Shitrit , Tariq Toukan Subject: [PATCH net-next 12/15] net/mlx5e: Support FEC settings for 200G per lane link modes Date: Mon, 3 Feb 2025 23:35:13 +0200 Message-ID: <20250203213516.227902-13-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250203213516.227902-1-tariqt@nvidia.com> References: <20250203213516.227902-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002324:EE_|SN7PR12MB7275:EE_ X-MS-Office365-Filtering-Correlation-Id: a2d167e5-bca6-443d-d682-08dd449aeb3d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: PjvBl0ZAc8xw0spOSxlZD9RTg77c41VbZBroyYBbCfjCIQiEhCcDl2D+K07+BSuH50moHpwt0DWSpUlKQST6WNJo+DXFICT2i3y0wPcV4tgnxHPglHscYCM60MYkspSSsu7lPmrCMKs69v+OtywvaRTbm7cd1gcYfa4YqWa+LcZYlH2s/NwIEeILEfRoiGX1L23v+dDaHBrLcZxa39Df6dly1L1A5kd5C3OFYzccI/o+toru9rLentJ7tL32QogEsGPacB8TdGP4EmBqHq1g2C8YCkMvA8KVq2tpso1bKmC77FCStTr3yZYo2rgzgQK4hbtKLEQ4FyCUNOZ5JP0uqxsADPcN1/+btKk2l4Ci7+BMfWxQXj47nAGAX0+cs5cC9W3eggL7bGXpVJ8x3yC2BO93Infpy2BTK99+GpA6K+pmdnXmLRt1awoH7cwRKpRQHPkmFOMc+6Cb+XSjfWvUHsfFHNxlDpWDJNbA0paPGe0eHbJ5qIhwpfXOXP8yQkI64TEJBBFEzHTbaxcxuqsdJ7PodPuikj0rysxfcNi4c/kl9eE3vAvKcP/KGpHdCfAyAdZSu8kDcXvacfX396vM08Hw20HiAY7kXC9m0T3x4XJvjLF3HBXVe4tNGNUHhjDdqT896Y5/IKcfbpkIZPy5TrxsdGBGEXbk8u51VG7U2hqu6U1yxEVwTfqyOUeUqsi5gyPkjowJYQAXyAqTJAC4z3AD2rmo0MRlmGDiYldohP69BY6bHS9PeZbvEF63qU0589elLs9a19UzFUNK5B2UFqlh2+OgToXHeJHfaaSsQpWdsHb9luAd2wMAGvi7u0fOQHFwNvsTVOeuM/0zlwLROoJ+C1S85Gtm1XUqraXJLEQ6SdWVWriab+I0t0YP6syyq///vygodShpJCVaMQePOnOLo4w1sgtlbUt1pCncihTFiyXimdqh+n+g8BjdnwpB9pyG3xy5Erm7gSVDucPyP8OcWZNtMcbNNx38gGG79+Qlkhd0Zbs5cy41q7kf2bT54DZQuvasDV0XFB4MCw/OY3I9aysnRwXJKM4Bk3G7mPeuFZefpBHjLqn+hRKfF6UWcBA/ekDjV1LY6as23FmBNDg9Ec+6mTWNtIZz3BCCz0yGmwm++awG+BaXVe2hP7lyOmMCbnlsHyL5ZV3CBlj/2Elq5GCXR/z+FRa7qU4lwtjg/LJrYezrsKBj6ZF/1gfrcAU6r8o6lbURxPmWo151Tv9QFAa+3EyIizkNdJfZSGoiIH5DwS47MCDOqZ1oRphWuUbaXZPb/h2C6O84oFHCDvsD3Nlu/JAgVfWNd7qYtjjTn1EoVBVWKNoeAJ4vJFjqwpLjtILqRm0Ik5Omkc3JnWS1vvrKOkjQdU/WAvUDPEYbMpxkrXNETlWprIT1xAwec8fQGn5i4adv8rm8wjPmmavMGTMaUFgjLk8s1kIS5iMiT0VHM/W/V17w1Bdd+YrLGcx6Fa9749NO2HOQFdPK58qhAtT98OFpJAvImRJ2TRs= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2025 21:37:11.8672 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a2d167e5-bca6-443d-d682-08dd449aeb3d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002324.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7275 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu Add support to show and config FEC by ethtool for 200G/lane link modes. The RS encoding setting is mapped, and can be overridden to FEC_RS_544_514_INTERLEAVED_QUAD for these modes. Signed-off-by: Jianbo Liu Reviewed-by: Shahar Shitrit Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en/port.c | 64 ++++++++++++++++--- .../net/ethernet/mellanox/mlx5/core/en/port.h | 1 + .../ethernet/mellanox/mlx5/core/en_ethtool.c | 1 + 3 files changed, 56 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/port.c b/drivers/net/ethernet/mellanox/mlx5/core/en/port.c index 5f6a0605e4ae..f62fbfb67a1b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/port.c @@ -296,11 +296,16 @@ enum mlx5e_fec_supported_link_mode { MLX5E_FEC_SUPPORTED_LINK_MODE_200G_2X, MLX5E_FEC_SUPPORTED_LINK_MODE_400G_4X, MLX5E_FEC_SUPPORTED_LINK_MODE_800G_8X, + MLX5E_FEC_SUPPORTED_LINK_MODE_200G_1X, + MLX5E_FEC_SUPPORTED_LINK_MODE_400G_2X, + MLX5E_FEC_SUPPORTED_LINK_MODE_800G_4X, + MLX5E_FEC_SUPPORTED_LINK_MODE_1600G_8X, MLX5E_MAX_FEC_SUPPORTED_LINK_MODE, }; #define MLX5E_FEC_FIRST_50G_PER_LANE_MODE MLX5E_FEC_SUPPORTED_LINK_MODE_50G_1X #define MLX5E_FEC_FIRST_100G_PER_LANE_MODE MLX5E_FEC_SUPPORTED_LINK_MODE_100G_1X +#define MLX5E_FEC_FIRST_200G_PER_LANE_MODE MLX5E_FEC_SUPPORTED_LINK_MODE_200G_1X #define MLX5E_FEC_OVERRIDE_ADMIN_POLICY(buf, policy, write, link) \ do { \ @@ -320,8 +325,10 @@ static bool mlx5e_is_fec_supported_link_mode(struct mlx5_core_dev *dev, return link_mode < MLX5E_FEC_FIRST_50G_PER_LANE_MODE || (link_mode < MLX5E_FEC_FIRST_100G_PER_LANE_MODE && MLX5_CAP_PCAM_FEATURE(dev, fec_50G_per_lane_in_pplm)) || - (link_mode >= MLX5E_FEC_FIRST_100G_PER_LANE_MODE && - MLX5_CAP_PCAM_FEATURE(dev, fec_100G_per_lane_in_pplm)); + (link_mode < MLX5E_FEC_FIRST_200G_PER_LANE_MODE && + MLX5_CAP_PCAM_FEATURE(dev, fec_100G_per_lane_in_pplm)) || + (link_mode >= MLX5E_FEC_FIRST_200G_PER_LANE_MODE && + MLX5_CAP_PCAM_FEATURE(dev, fec_200G_per_lane_in_pplm)); } /* get/set FEC admin field for a given speed */ @@ -368,6 +375,18 @@ static int mlx5e_fec_admin_field(u32 *pplm, u16 *fec_policy, bool write, case MLX5E_FEC_SUPPORTED_LINK_MODE_800G_8X: MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 800g_8x); break; + case MLX5E_FEC_SUPPORTED_LINK_MODE_200G_1X: + MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 200g_1x); + break; + case MLX5E_FEC_SUPPORTED_LINK_MODE_400G_2X: + MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 400g_2x); + break; + case MLX5E_FEC_SUPPORTED_LINK_MODE_800G_4X: + MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 800g_4x); + break; + case MLX5E_FEC_SUPPORTED_LINK_MODE_1600G_8X: + MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 1600g_8x); + break; default: return -EINVAL; } @@ -421,6 +440,18 @@ static int mlx5e_get_fec_cap_field(u32 *pplm, u16 *fec_cap, case MLX5E_FEC_SUPPORTED_LINK_MODE_800G_8X: *fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 800g_8x); break; + case MLX5E_FEC_SUPPORTED_LINK_MODE_200G_1X: + *fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 200g_1x); + break; + case MLX5E_FEC_SUPPORTED_LINK_MODE_400G_2X: + *fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 400g_2x); + break; + case MLX5E_FEC_SUPPORTED_LINK_MODE_800G_4X: + *fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 800g_4x); + break; + case MLX5E_FEC_SUPPORTED_LINK_MODE_1600G_8X: + *fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 1600g_8x); + break; default: return -EINVAL; } @@ -494,6 +525,26 @@ int mlx5e_get_fec_mode(struct mlx5_core_dev *dev, u32 *fec_mode_active, return 0; } +static u16 mlx5e_remap_fec_conf_mode(enum mlx5e_fec_supported_link_mode link_mode, + u16 conf_fec) +{ + /* RS fec in ethtool is originally mapped to MLX5E_FEC_RS_528_514. + * For link modes up to 25G per lane, the value is kept. + * For 50G or 100G per lane, it's remapped to MLX5E_FEC_RS_544_514. + * For 200G per lane, remapped to MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD. + */ + if (conf_fec != BIT(MLX5E_FEC_RS_528_514)) + return conf_fec; + + if (link_mode >= MLX5E_FEC_FIRST_200G_PER_LANE_MODE) + return BIT(MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD); + + if (link_mode >= MLX5E_FEC_FIRST_50G_PER_LANE_MODE) + return BIT(MLX5E_FEC_RS_544_514); + + return conf_fec; +} + int mlx5e_set_fec_mode(struct mlx5_core_dev *dev, u16 fec_policy) { bool fec_50g_per_lane = MLX5_CAP_PCAM_FEATURE(dev, fec_50G_per_lane_in_pplm); @@ -530,14 +581,7 @@ int mlx5e_set_fec_mode(struct mlx5_core_dev *dev, u16 fec_policy) if (!mlx5e_is_fec_supported_link_mode(dev, i)) break; - /* RS fec in ethtool is mapped to MLX5E_FEC_RS_528_514 - * to link modes up to 25G per lane and to - * MLX5E_FEC_RS_544_514 in the new link modes based on - * 50G or 100G per lane - */ - if (conf_fec == (1 << MLX5E_FEC_RS_528_514) && - i >= MLX5E_FEC_FIRST_50G_PER_LANE_MODE) - conf_fec = (1 << MLX5E_FEC_RS_544_514); + conf_fec = mlx5e_remap_fec_conf_mode(i, conf_fec); mlx5e_get_fec_cap_field(out, &fec_caps, i); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/port.h b/drivers/net/ethernet/mellanox/mlx5/core/en/port.h index d1da225f35da..fa2283dd383b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/port.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/port.h @@ -61,6 +61,7 @@ enum { MLX5E_FEC_NOFEC, MLX5E_FEC_FIRECODE, MLX5E_FEC_RS_528_514, + MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD = 4, MLX5E_FEC_RS_544_514 = 7, MLX5E_FEC_LLRS_272_257_1 = 9, }; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Jianbo Liu , Moshe Shemesh , Leon Romanovsky , Mark Bloch , Tariq Toukan Subject: [PATCH net-next 13/15] net/mlx5: Remove stray semicolon in LAG port selection table creation Date: Mon, 3 Feb 2025 23:35:14 +0200 Message-ID: <20250203213516.227902-14-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250203213516.227902-1-tariqt@nvidia.com> References: <20250203213516.227902-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F61:EE_|SA0PR12MB7464:EE_ X-MS-Office365-Filtering-Correlation-Id: 3c7131b2-c2b4-4bbb-6640-08dd449aec51 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: BQW0VydO5Mwf/KoeUMKMf0UTED1CWWJmZPM45UKGB1f0RWnMv55ZUCs4DOeA+ossc8JrCSsIELj1XaaVIlWeUlwRffKZ9/w7SyyZ8SAreUqCI2q6+iatfpBaNK9jbc7QX6zJvFd7Uv19PLw3TCvx13B9NCI28S8Vdk6d0WEwH5pchTyaU0JaUgmWCyXetUFIZbCDhhKi3Vn31wk1DqFfX//GZNBUb7nEsTXBLKWfc6ocKzq4wCiArI5X4gfMJt7fU8AJlBf9jMwsNozNAMGO9ac+QS7hEkrqjc5MkXN8c567Y1Gd0V8+fYAc4uRM07NpyTlwqFlLkBtSFBHtWxbJaCN4hybEeZrHV8evnhwFZHw91NnBRbVr6jfhNlSS5F8giJWMDdm5I/lOvohdVzNpMx1NmTQFEn8Wj5SPJEMzs+QC1qbDwplZ/ULeO0KAaIylrnXKED/7myYkWUFJ1bgDvyNZbTtf/na3/W68gv0FYdgZMPcDI1wbd/z0gV9pb31x0cXxoIgR8GDHwY71lLMdrRzDEVhuWwU86byt7LgE60q9xLHh89E3qPx7eceUy6s4r/3cb3yH4N8vVTeJ0Z+YhEziSLGe3VK4ownYjTjfBg2bEf3HI03PfLeN6/T7wh4k74jb1c6tw4piFMgbEKmN+MqadxpMNCIeuGz+NiZBwc3wNcCuvwbaF2ZWtWASyUzXIgV4UlF/ZefDjxyi4UFEBh1XpFPF2/QONWNRSZp+NgURZSE59L/t/y2WReTh1tiV64/ipnvYRs28fLQB1fP9IzuvEgHXBAOE7N191Q4AZHDohDJBbu8Xc43RyFURIT8Ha2FBCjoLogDBbyGOjDF4zkiozd9DrIPO25dgZHcq8VzD5tbMLjfRUZqhjCkZuK8qoIwmYYHwbDk7m3IC7WFNPj/oUiDHB2dCJ1cKrNOuFEkwQ96b9UIESTBia8XafDT1feV4UXYZDhFl6m/iRwOyoYHmw/J4tJ+R9Vsq8nGJrKD3O0IrO90c+eCWnZ+XkQ0gOFjs8/4GWP1tnm3Kk/x1zN2JPi1qIZsO1gdbjBlX//TmKrYByDiXx4KAj7RgSTcFR+embxJG67RyJadp14CbrUw0HXCbPv7ODaYzomAbTAjnuYsg9EwIXxwoAdRZHAIDQyJto4pvuL+6t1snLdrDdcdn8dXBoTpnxuvOVP+jhjdE2Wky1tWfyNwOaExuEA41tCLrh+M3ECm47T4mHNQorKmFFMxtjNQjO3Qm2667Rybrq8QqQxTVbu3Q+EGgowWwc08NXT3ymNMhI3QS0VcR/jHGjvhIBxW9zH9QsLmkp1fqJnZe8zBwlv5YNpqUQMa3+V2nrVzuCx6HvMdiihhmvSJGfbSGu6kzO6ZOo9msGH+q+b53zKEV0Kv4hxfvUp2V5I6/F6v28mk6A37hEwCeoBcJCp0H7e98ysg8pocKMv9XpJGLKj0ICKaXeKhadZAzHdAeVITKDiZ6PaUZsro5GRwgUrXSmAr9gdu7XutS4bg= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2025 21:37:13.5482 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3c7131b2-c2b4-4bbb-6640-08dd449aec51 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F61.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB7464 X-Patchwork-Delegate: kuba@kernel.org From: Gal Pressman Remove the stray semicolon in the mlx5_ldev_for_each_reverse() loop. Signed-off-by: Gal Pressman Signed-off-by: Tariq Toukan Reviewed-by: Kalesh AP --- drivers/net/ethernet/mellanox/mlx5/core/lag/port_sel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/port_sel.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/port_sel.c index bde79cac33a9..d832a12ffec0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/port_sel.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/port_sel.c @@ -97,7 +97,7 @@ static int mlx5_lag_create_port_sel_table(struct mlx5_lag *ldev, mlx5_del_flow_rules(lag_definer->rules[idx]); } j = ldev->buckets; - }; + } goto destroy_fg; } } From patchwork Mon Feb 3 21:35:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13958282 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2080.outbound.protection.outlook.com [40.107.237.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C97A1200BB4 for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Jianbo Liu , Moshe Shemesh , Leon Romanovsky , Mark Bloch , Cosmin Ratiu , Tariq Toukan Subject: [PATCH net-next 14/15] net/mlx5e: Remove unused mlx5e_tc_flow_action struct Date: Mon, 3 Feb 2025 23:35:15 +0200 Message-ID: <20250203213516.227902-15-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250203213516.227902-1-tariqt@nvidia.com> References: <20250203213516.227902-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002321:EE_|SN7PR12MB8601:EE_ X-MS-Office365-Filtering-Correlation-Id: b0ec5422-68b8-4583-ed77-08dd449af073 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: js8zgT5+U71t9MtGmEBqZV2up/OIx6E4xiOK3nVdwd14YR4KpIJ8IwQLjzO3piHxCvpXPheE4BiZ23m1ftJTKMsZs+ncwgobFfAhd96mAyXlf+A6sqdn77XZ6oqmRR3IkB9fG6Y6aHzRzCu5aTdnSSjRtQlRJK2a16v/a6QB91tB3J97DlFUevdduedQU3T2HZai+8UOQXciVrbBvh45JQZo3P0gzT4TX7dOoftNaZmdH93hnA4VSNUtIXvlixbg1nIdGxT3CvutHZgzXb6RpxxISmxt7ozY0DX+P7KGOppaSoABBGyHsVzUqnQsTGMsPDDkBnaBcmRv4zzT61YcqRpxCYQYJhGs2PptNX43MGWWvzaCtGRe41uDkNSXXPLR15Dh74F82XD3YivQ216aUDZ1HLYFxRdX/SNBhQBg7JRBaxav0AYeUZw6q493RJwK2Yv5YSxdavhMidF/i7IHNXXI/oWlIMlbsZIhDaq737mte7E7oTjZaxwwJfPt8eVzdJGc5OhAcR3f9KIErfpfbynb4yxmTIg00rHOCR6vaDppd/8uG6F75fwcIwSeDLZuST7ChooXcxBNc9W0i4ESrgG/VOjhmEGgHghvqGGfZ7ZyXoTFjHYLnSqy7tj496ruY4EZ2hbefsT7x5CJxOlTojHpM7rgvu6bDyZscK2dyArlrEMr/5t1Zz7mYCJoDFngbO/ZZt2Hb2GxhkTGPNzsonuWqEhUlGzMWYTLwtmyTqN9d4i8HrseWvh80dhSKjoYLJeD9kavAQ2TvF9s7Rix9NekJdQ22gNCD2MlIRgE5JhWZWTvdomUneGMuzSRmEY8oGK2hGUwiKQRcHW5QmCDwrZaAjJ4HsIy5tdMhfgIYVUuZBkUBrDqpI+KYwu+MjMAxyYOqwHazl4D9yTr/+z1j76aun6Ct0Dm4UjW4ErVD3PG9py85AP17vr/DJI11BZQoN8ttGSmaRnd9YCsml1Wa9wMNWjVPO4OiwaYCMGnnpOZZMk38dIg5EfmTrAHii3OHrWLUU/zPxCq8jbnch2F6IH8/LP22MZhgEZRyI1kbUaG8YarErl6s1N44N1Sk3KsOvW1OYwdgfqyUkOGHZr1GDkkrR5E5KTkOVXwYbDbzxkX897JwPF51KMv01G3P3c6MHfxa9u0lEN+9gnScN/Ut092Fp2afaAzvS1P9r2y8oFaYkmDjfvWovdTGHmO/Kh6aTE2tez+B+H68F4Di8bK8mY7HOP9M6E0ONCZQesxiKbZ8kzf7IZBZp5Em3Tm+zFHXS6fWEUcbTR58OG8/PhQj/Zp3O5XAEDtAKCvyplwotEcsl4kneO5h+eY93Ef5JPESxN+Om8H8SQ77pnJao5ntfRC3ywoYPo/RHC03bSOL1neIKRtc5D00hjS4konO6kClCS9SdqGj8SP5sEkMqlHx2f1SyG/jmuYPgX+GQse1mhkRpOlKFM53RNOwSeL1JWk6boy+h3Nfj52U7XcyChccacGyusxPsnKRlY3rYyI2vk= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2025 21:37:20.5791 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b0ec5422-68b8-4583-ed77-08dd449af073 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002321.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8601 X-Patchwork-Delegate: kuba@kernel.org From: Gal Pressman Commit 67efaf45930d ("net/mlx5e: TC, Remove CT action reordering") removed the usage of mlx5e_tc_flow_action struct, remove the struct as well. Signed-off-by: Gal Pressman Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan Reviewed-by: Kalesh AP --- drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/act.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/act.h b/drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/act.h index d6c12d0ea55b..2e528b2c34d6 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/act.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/act.h @@ -73,11 +73,6 @@ struct mlx5e_tc_act { bool is_terminating_action; }; -struct mlx5e_tc_flow_action { - unsigned int num_entries; - struct flow_action_entry **entries; -}; - extern struct mlx5e_tc_act mlx5e_tc_act_drop; extern struct mlx5e_tc_act mlx5e_tc_act_trap; extern struct mlx5e_tc_act mlx5e_tc_act_accept; From patchwork Mon Feb 3 21:35:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13958283 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2067.outbound.protection.outlook.com [40.107.94.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21E15211269 for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Jianbo Liu , Moshe Shemesh , Leon Romanovsky , Mark Bloch , Carolina Jubran , Yael Chemla , Cosmin Ratiu , Tariq Toukan Subject: [PATCH net-next 15/15] net/mlx5e: Avoid WARN_ON when configuring MQPRIO with HTB offload enabled Date: Mon, 3 Feb 2025 23:35:16 +0200 Message-ID: <20250203213516.227902-16-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250203213516.227902-1-tariqt@nvidia.com> References: <20250203213516.227902-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002326:EE_|DS0PR12MB8368:EE_ X-MS-Office365-Filtering-Correlation-Id: b6b3113c-cb30-4d47-869a-08dd449af299 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: 1bddiwG9R9COXJfESnpgYW9DxZ7US8DDTwjSqTK7mO0vkFJKNaT8hElnWH+nEvlL/HLMlpti13UZ+mtHWA7tSUzb62Cyoqrw/BSyMYwwKWJkv8UjV1Pzvi7zF9kyRdXbzzA/2oVeVJfBqcdJvU81jzL/iwGRlt2S1VPwoOpzp0uYfhsH3KZppyEipVEcQ5y2ynIDBhYydCuHXCLXYcJz3bFc2GpTZz7P/6SBTKbaGD2ugOu1Ft0ufZrL1KQl+Ok9uPtRXlZV3wbCWqH7M1pa5g/ATwpSLsasATi/xp8d+cGjbXkHPkYdtXe/lpHEAzC6DKclzPYjh9kk8uovc4yENLudSYUDmY4X2d7UgRHS1OdLle+FEw9qK3b/dhqcHYkPzP2Mip+1MmNEZ5jqGTIoAPYzJ87bLAeZcfWgr2dFEkFh3Jpt+X9J7o4nBETaRcwkE0U72aBPE7Z6so9ORK9/SU3zqUFxdr5+p8lKipMVnRiNlqDrbua6zT6IVqVtpW7MAYfssoVyaUpuf3DsVkaghOVPezwEjN3EJ8HG4zjDA3tT9FRVyjuMJdCpsvtyw6DZZeM+YX5+iz6pTh6UWav4xmF2Z2dgDerrBVcf0ktvbHOXXxCpfbiLfKHv1UDSE62SVOuB2j3SlCN/qKScNck9QfDm0A120vtQwoKKSdDQMACJ9EykMpNPyYeeGH3wMlxh9c280w+rMPywyZZAlMM9/LnVtDN2TEPQMHLcs2ld2/pMTorxFS2XHZXu+4IPfILMisMR7Gu2AeFcb1ZDTCghrQyErtS5FIUUSN+O6jzFVtr5zp4+mhKqMT/jxxGqo4E92MrTmplqOp5mGmrpcLjpGwrcULY8hEn/hM1qDcCGb51A+dRkev7yuYL5zu4+5dw/zThPFX3lG6TsKM0d3yfmEkrDGza6J80zP6JEc7sTZlkwBGhEloo2x7Wh3aOI6P8bKD0SUJUN4UMlvFZ7TYob3vSLhxceEv0eyrMqpHgv9hel9tn+wXe59XmhTyGd2SgA8YQ4i0czKTIJrwQpv+K7x2O5dZB7vsBcQ37b9wRj7bZKO/BYUfd1GT7w+f98QXrPBFDXNkqgxKynA8jEHH9QVptHA36qs9AyiiazbEhnd260SdzrYJcHGRAUhODnONzzbvz1M/0ctwiF4KWk9aVNmDAppHU8BXH0GeR1LKYn1IyUHYne40XK8hKqqpH/eJ1tJ3rPog+EzHKUrWgIJeEkVZzaJ7+pkjFJl3+5T8PzyYb8n0sAkYXsWqcsmOMBA+yvmjANHjvMXAfu6VuMZnRp73uqjFm1qcIrO+onP2Ql9k8Xnp4cXI9hY3pd8k4rMqptrYW0T+TVuulVPtemDmsAfmdbbodMWP1XrYMdMXSGogNpE3WTeWquduP2CDBV2HDnY2jCBAc65QUUyiXJRzbiJRQcOJK5CrcFOv767uwKCIm1MaXRpPBMOV7reF1svT1EBzA955i7nEl8/Ke3p7H+eoC2xNZudGkSEnn9rxg5mL4= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2025 21:37:24.1965 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b6b3113c-cb30-4d47-869a-08dd449af299 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002326.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8368 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran When attempting to enable MQPRIO while HTB offload is already configured, the driver currently returns `-EINVAL` and triggers a `WARN_ON`, leading to an unnecessary call trace. Update the code to handle this case more gracefully by returning `-EOPNOTSUPP` instead, while also providing a helpful user message. Signed-off-by: Carolina Jubran Reviewed-by: Yael Chemla Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan Reviewed-by: Kalesh AP --- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index c754e0c75934..2fdc86432ac0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -3816,8 +3816,11 @@ static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv, /* MQPRIO is another toplevel qdisc that can't be attached * simultaneously with the offloaded HTB. */ - if (WARN_ON(mlx5e_selq_is_htb_enabled(&priv->selq))) - return -EINVAL; + if (mlx5e_selq_is_htb_enabled(&priv->selq)) { + NL_SET_ERR_MSG_MOD(mqprio->extack, + "MQPRIO cannot be configured when HTB offload is enabled."); + return -EOPNOTSUPP; + } switch (mqprio->mode) { case TC_MQPRIO_MODE_DCB: