From patchwork Tue Feb 4 03:02:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13958543 X-Patchwork-Delegate: kuba@kernel.org Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90B37155326 for ; Tue, 4 Feb 2025 03:03:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738638186; cv=none; b=ph56Fy3702Hzuf55V8joKqVDwzU5bveLXcMGNbZq1yjwAATFppAMUqBtBB5NM2dHAQpuZ+HwYsccItN7tshR120gI2dxGcvDYK9VpJR7E/+irfnBPIjECoySxuhfTefB46bv5iiPSc28Nh8YzjU3h0oBW6NSiiclF90u44hMwHo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738638186; c=relaxed/simple; bh=4NVEG24S4MtnR561mcuGQPAwmnJeTKnXo93/3XsAu0U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QHvwNJjl1vdTTKrFCtCLE2aX+GeBzubHoG3VTQEQQMZS0HEcmI03Mxc8gbyl4I1e9PH2rPUSmYTQB4T+xfo7tmyaTKQc4ULj6w8+dPUU1MasRlw9bPbCSjsRrHoTEnbuzaOJJuPnv2VX2Xz7aH1r5qoiXMnC+8hsLB0DOopodIE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz; spf=pass smtp.mailfrom=alliedtelesis.co.nz; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b=fDrffdl/; arc=none smtp.client-ip=202.36.163.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="fDrffdl/" Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 3EE642C0452; Tue, 4 Feb 2025 16:03:02 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1738638182; bh=u64i3jFqbMHZWq2p115UYRUBBE2H5S+EJln0sSX5xb4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fDrffdl/57DWKFxD2Hs8WmJUH8pqzX+kPp42pQmaVrgI5igBX3UirkmUF8pMAjPD5 /pG7K126cdpDJdDKLuMDKQAWOuJNSNEO2y7mryVu7xQti9RbnXwPpVfZm2l5NuAFY7 eug60AmKVTqSV/EHjrV0YZGt65aYUdA3C+AKCJpGoFcgLqz9yGsnEhtiBo160hSR90 FEMb9YBLxX/QJxKZ13N2eZuGA8TVrz6+42+cD+b5I1xPDHZzdPHi6wLAhVlL25R7xX cS1mNkEhtJqzVlFyEqBcZQc6aDConOZ95T8m/6ld2w8bTrDwgqW8LKUw1lhsS9Oiqe DYfZPJrfU4Gmw== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Tue, 04 Feb 2025 16:03:02 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 1238513EE36; Tue, 4 Feb 2025 16:03:02 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 0D0682804B6; Tue, 4 Feb 2025 16:03:02 +1300 (NZDT) From: Chris Packham To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, tsbogend@alpha.franken.de, hkallweit1@gmail.com, linux@armlinux.org.uk, sander@svanheule.net, daniel@makrotopia.org, markus.stockhausen@gmx.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-mips@vger.kernel.org, Chris Packham Subject: [PATCH net-next v6 1/6] dt-bindings: mfd: Add switch to RTL9300 Date: Tue, 4 Feb 2025 16:02:44 +1300 Message-ID: <20250204030249.1965444-2-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250204030249.1965444-1-chris.packham@alliedtelesis.co.nz> References: <20250204030249.1965444-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=QNvLRRLL c=1 sm=1 tr=0 ts=67a18366 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=T2h4t0Lz3GQA:10 a=LEuThzscFrWOTlmK_W8A:9 a=3ZKOabzyN94A:10 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat X-Patchwork-Delegate: kuba@kernel.org Add bindings for the ethernet-switch portion of the RTL9300. Signed-off-by: Chris Packham --- Notes: Changes in v6: - New - I'd like to enforce the property being "ethernet-ports" but I see the generic binding allows "ports" as well. Can I just add ethernet-ports: type: object here or does by driver need to handle both "ports" and "ethernet-ports" (I see some do and some don't). .../bindings/mfd/realtek,rtl9301-switch.yaml | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/realtek,rtl9301-switch.yaml b/Documentation/devicetree/bindings/mfd/realtek,rtl9301-switch.yaml index f053303ab1e6..cb54abda5e6a 100644 --- a/Documentation/devicetree/bindings/mfd/realtek,rtl9301-switch.yaml +++ b/Documentation/devicetree/bindings/mfd/realtek,rtl9301-switch.yaml @@ -14,6 +14,8 @@ description: number of different peripherals are accessed through a common register block, represented here as a syscon node. +$ref: /schemas/net/ethernet-switch.yaml# + properties: compatible: items: @@ -45,7 +47,7 @@ required: - compatible - reg -additionalProperties: false +unevaluatedProperties: false examples: - | @@ -110,5 +112,17 @@ examples: }; }; }; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + }; }; From patchwork Tue Feb 4 03:02:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13958544 X-Patchwork-Delegate: kuba@kernel.org Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D15CB14F9FB for ; Tue, 4 Feb 2025 03:03:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738638192; cv=none; b=eRZ0jaspRLAxsXm12yEMEsA1gsN2+VQKh1nR0+uKy19x9HeGxf+QiFutVY+AAzxXcSIJ1tt3mSFrjkHXmx6ivF9R+D36qrcCzo9+3lOVoa9iYfRfGZxENn3ygOkbvNe6iOJ+jUGhWPD+SkSLfl9T1AnvFpQGIt+07v7VKgZ7UXA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738638192; c=relaxed/simple; bh=VJrFUmicDNq1FSMCfrXKd+XEUvG35Vndia3CKOxt9ks=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EE+Yl5GUHLdtNLQ0Gea+ecSHOz55Xy4L3ay9CLNCCMOc2+trK8D7WrbREiBKHzlP77jVMBmEHjPSdcnZ6Le2SNsl/942lRD4NQBuwiO5RhfWyblSHW8PrO8te1Otl9fU9P5r7p7stvDLtAiQeorzHxD4eU/gfsOvhGhXktwjqyM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz; spf=pass smtp.mailfrom=alliedtelesis.co.nz; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b=2uZfn7td; arc=none smtp.client-ip=202.36.163.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="2uZfn7td" Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 76FD02C0477; Tue, 4 Feb 2025 16:03:09 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1738638189; bh=MOrA0n6MqVeIkJa6qf2corfGZHZBrFT3MtdqsxEWvrs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=2uZfn7tdfZjA5HeIcGr2Zc0e1n8oT3EHdPqK0wi0SY0/I9TP5u4LBUKqIV6SaHFBP hiEGY3lsa1/6PjCEujpticDFnTje/alb9d6fO7qg2xFCvrYuUg63ChR66ivY070D75 bMFEYAQDIwAj8VG1L9DE3hZyhZmfvenFJWbBvpbqJoQt5qfstNO/b1mnFdMXIUijPJ DAkmECcw4KDNxOEfTYGNcJL/4mdakhyAhDMs0Xq4Z7Xp8xzd9zSH14pltK616ZfCwM wABX8GqEEUyx1Xkg/tqC96ZpsLDWli2hLmLpLcB8Q5UWBGD/rDyA4wsEjnNObn9sy2 KuIHHGOTLu0Tw== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Tue, 04 Feb 2025 16:03:09 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 213A613EE36; Tue, 4 Feb 2025 16:03:09 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 1C8332804B6; Tue, 4 Feb 2025 16:03:09 +1300 (NZDT) From: Chris Packham To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, tsbogend@alpha.franken.de, hkallweit1@gmail.com, linux@armlinux.org.uk, sander@svanheule.net, daniel@makrotopia.org, markus.stockhausen@gmx.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-mips@vger.kernel.org, Chris Packham Subject: [PATCH net-next v6 2/6] dt-bindings: net: Add Realtek MDIO controller Date: Tue, 4 Feb 2025 16:02:45 +1300 Message-ID: <20250204030249.1965444-3-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250204030249.1965444-1-chris.packham@alliedtelesis.co.nz> References: <20250204030249.1965444-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=QNvLRRLL c=1 sm=1 tr=0 ts=67a1836d a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=T2h4t0Lz3GQA:10 a=gEfo2CItAAAA:8 a=h0k0zCsF0n2ckjRL4XMA:9 a=3ZKOabzyN94A:10 a=k4rVKtLH5ZiPiG3jzTle:22 a=sptkURWiP4Gy88Gu7hUp:22 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat X-Patchwork-Delegate: kuba@kernel.org Add dtschema for the MDIO controller found in the RTL9300 SoCs. The controller is slightly unusual in that direct MDIO communication is not possible. We model the MDIO controller with the MDIO buses as child nodes and the PHYs as children of the buses. The mapping of switch port number to MDIO bus/addr requires the ethernet-ports sibling to provide the mapping via the phy-handle property. Signed-off-by: Chris Packham Reviewed-by: Rob Herring (Arm) --- Notes: Changes in v6: - Remove realtek,port property. The driver will parse the ethernet-ports sibling node to figure out the mapping (do I need to mention that somewhere in this binding?). - Correct number of mdio buses. 4 possible buses numbered 0-3. Changes in v5: - Add back reg property to mdio-controller node - Make unit address in the node name required - Andrew suggested perhaps doing away with the realtek,port property and providing the overall mapping via an array of phandles. I've explored this a little, it is doable but I'm not sure it actually makes things any clearer when the portmap has gaps so I haven't made this change. Changes in v4: - Model the MDIO controller with the buses as child nodes. We still need to deal with the switch port number so this is represented with the "realtek,port" property which needs to be added to the MDIO bus children (i.e. the PHYs) - Because the above is quite a departure from earlier I've dropped the r-by Changes in v3: - Add r-by from Connor Changes in v2: - None .../bindings/net/realtek,rtl9301-mdio.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml diff --git a/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml new file mode 100644 index 000000000000..02e4e33e9969 --- /dev/null +++ b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/realtek,rtl9301-mdio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek RTL9300 MDIO Controller + +maintainers: + - Chris Packham + +properties: + compatible: + oneOf: + - items: + - enum: + - realtek,rtl9302b-mdio + - realtek,rtl9302c-mdio + - realtek,rtl9303-mdio + - const: realtek,rtl9301-mdio + - const: realtek,rtl9301-mdio + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + maxItems: 1 + +patternProperties: + '^mdio-bus@[0-3]$': + $ref: mdio.yaml# + + properties: + reg: + maxItems: 1 + + required: + - reg + + patternProperties: + '^ethernet-phy@[a-f0-9]+$': + type: object + $ref: ethernet-phy.yaml# + unevaluatedProperties: false + + unevaluatedProperties: false + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + mdio-controller@ca00 { + compatible = "realtek,rtl9301-mdio"; + reg = <0xca00 0x200>; + #address-cells = <1>; + #size-cells = <0>; + + mdio-bus@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0>; + }; + }; + + mdio-bus@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0>; + }; + }; + }; From patchwork Tue Feb 4 03:02:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13958545 X-Patchwork-Delegate: kuba@kernel.org Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76D141993B2 for ; Tue, 4 Feb 2025 03:03:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738638199; cv=none; b=Qg0q0LNwpbu1KDkJs5/vUEZmziXu0Bpe2J0tiAJCM0F8vlAc2PuXhs0mWO9nUJ4Tsq87kadUGSFFRB69kUEs4XwFIPdF9/R2KS30HqMluAd3bE1FWrhEQOetosmG3V0xjLpKftHx699U0Yegs3qeJG3wR1uBcfirQp7REqQ4akg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738638199; c=relaxed/simple; bh=N+a3DuHfCv0TS8UCtJAPb3qNmDiJqlPUXVW3aGDVgWM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SmQ9pZBodkNKFk2tFJMxFU7llBwzIbhW1K9LPf9fjn7ukJKTc7NiPFvbCEgIOYpU8xR1LzlkQem+IWyn0GYm0Y1JRNckd4Bnwii1ySNE2ngBpCTOawrtNjbNI+VoX3TzC6xZTiumzBXdtKdqVNuBBZWagpaIr3ibXe8XmCyTZtk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz; spf=pass smtp.mailfrom=alliedtelesis.co.nz; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b=CX2VrDh1; arc=none smtp.client-ip=202.36.163.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="CX2VrDh1" Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 2E81D2C047F; Tue, 4 Feb 2025 16:03:16 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1738638196; bh=9EHrD9kV/69Up1jT2dF8LXwgTVXgnSyjYGIkM/TNGaQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CX2VrDh10nd4porvvj/knTwp+EpEAx98dCU6uoCtASorOP9GAYJnK/07ix7jwlWL6 5sKc0/hN+z+NjilxdXILaBX6yGtRVdkO2P/Bl7A/aEuM+S9XFgtyyyU5V/M1nsuLnA H+tU8mv4A2M2TvagZLAkHkyv2KnmovBxaO8o22uTLzCbEi2FrmZLYOok1S60RJ7Zu7 /KHXecdJPmoo/I/IH6xT5Sggd904ngJ7ExcqxRmKs0AswznNJ9nBWHHw8mLN7pEVrS vrkaMjdNu0WzT++qHcHoehjT632qz7XO5FeihjIcMnVVdc8AbTKfBQaMGL299UMYSu 1VPai9PTo6pvg== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Tue, 04 Feb 2025 16:03:16 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 019BA13EE36; Tue, 4 Feb 2025 16:03:16 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id F141E2804B6; Tue, 4 Feb 2025 16:03:15 +1300 (NZDT) From: Chris Packham To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, tsbogend@alpha.franken.de, hkallweit1@gmail.com, linux@armlinux.org.uk, sander@svanheule.net, daniel@makrotopia.org, markus.stockhausen@gmx.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-mips@vger.kernel.org, Chris Packham Subject: [PATCH net-next v6 3/6] dt-bindings: mfd: Add MDIO interface to rtl9301-switch Date: Tue, 4 Feb 2025 16:02:46 +1300 Message-ID: <20250204030249.1965444-4-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250204030249.1965444-1-chris.packham@alliedtelesis.co.nz> References: <20250204030249.1965444-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=QNvLRRLL c=1 sm=1 tr=0 ts=67a18374 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=T2h4t0Lz3GQA:10 a=5cQCLpD8v2SGHUEG_dEA:9 a=3ZKOabzyN94A:10 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat X-Patchwork-Delegate: kuba@kernel.org The MDIO controller is part of the switch on the RTL9300 family of devices. Add a $ref to the mfd binding for these devices. Signed-off-by: Chris Packham --- Notes: This patch is dependent on "dt-bindings: net: Add Realtek MDIO controller" which adds the realtek,rtl9301-mdio.yaml binding. Changes in v6: - Remove realtek,port property - Remove leftover mdio-controller node. - Fix some style issues. - Fuller example including the port to phy-handle mapping Changes in v5: - Note dependency on realtek,rtl9301-mdio.yaml patch - Add back reg property to the mdio-controller node. Changes in v4: - There is a single MDIO controller that has MDIO buses as children Changes in v3: - None Changes in v2: - None .../bindings/mfd/realtek,rtl9301-switch.yaml | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/realtek,rtl9301-switch.yaml b/Documentation/devicetree/bindings/mfd/realtek,rtl9301-switch.yaml index cb54abda5e6a..587fc3cf2524 100644 --- a/Documentation/devicetree/bindings/mfd/realtek,rtl9301-switch.yaml +++ b/Documentation/devicetree/bindings/mfd/realtek,rtl9301-switch.yaml @@ -43,6 +43,9 @@ patternProperties: 'i2c@[0-9a-f]+$': $ref: /schemas/i2c/realtek,rtl9301-i2c.yaml# + 'mdio-controller@[0-9a-f]+$': + $ref: /schemas/net/realtek,rtl9301-mdio.yaml# + required: - compatible - reg @@ -113,15 +116,43 @@ examples: }; }; + mdio-controller@ca00 { + compatible = "realtek,rtl9301-mdio"; + reg = <0xca00 0x200>; + #address-cells = <1>; + #size-cells = <0>; + + mdio-bus@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@0 { + reg = <0>; + }; + }; + mdio-bus@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + phy2: ethernet-phy@0 { + reg = <0>; + }; + }; + }; + ethernet-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; + phy-handle = <&phy1>; }; port@1 { reg = <1>; + phy-handle = <&phy2>; }; }; }; From patchwork Tue Feb 4 03:02:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13958546 X-Patchwork-Delegate: kuba@kernel.org Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B27A41487FA for ; Tue, 4 Feb 2025 03:03:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738638207; cv=none; b=sNV9TDzkyMd/pEsVVfsrnMkEo6VCikuPk8quNTKvOCibZZ8Py5kCtkahmxETjvgZPbZYwOldagjl5YFCDw3+grbRquVYC1w+cxzQ+p4GxUJ9yyrSy0tCTMG4EZywojDZ1Xy9xERVGPV2oihhkNM6uowpeKI2WwTzVJOCjW2VOoI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738638207; c=relaxed/simple; bh=gqWzk2vJFqCFmLA9fBt/eppweJz0sIn0vkRCKS8H3x8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Mp8vvBzEuBpfAas8gBzpWVLsM2/7boxKOKatHjNfo6NDI5yrrIraTssN6y4XL8kcxDa07AfaU2RxEaAlbWXQL/FurcC9CaM2cK0PN/pGjahLrIUfhkmddR5r/T/HjoYWWS4qMtBb0/k2oY4JWDqqUK47nbLjb6+HVAro3JiyHiU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz; spf=pass smtp.mailfrom=alliedtelesis.co.nz; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b=aHC6Z59Q; arc=none smtp.client-ip=202.36.163.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="aHC6Z59Q" Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 804192C0477; Tue, 4 Feb 2025 16:03:24 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1738638204; bh=4NP4DlDT6DNAoR+WN/+6tvYrmdcjTr4+ZaUipXuaX48=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aHC6Z59Qe1rK2KHSzVSZ1hSspEhiJFmquv+BunCyq0Qt7CeGnGbcgB9VRMXEGYiZ4 gbcQMSeUcjTDvfQ4LtxYNa4QJNxO6lVoeEtS4+j1C4qzTpKUpEBwZl33WRsoUqXkrx KAR1PC3rldazLQaGV+OJja9B7vyONrC0b9XjfrMgr9vVopoAF6K7LnW7g4smmvD6BE /9P9U67nrLYDaPDkGJBi64mYNMPmTFMuF2yFLvKRwnvzg0FoARIF5ddkE3B8KbJ4Yz kFw6fTcupYoMc7gGw1HRzIli48YBatpgpwv1MMHwxNa3uL9Wm+PGgBORl1qN5qPksY R6W1lf3mPOemA== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Tue, 04 Feb 2025 16:03:24 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 480E113EE36; Tue, 4 Feb 2025 16:03:24 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 437702804B6; Tue, 4 Feb 2025 16:03:24 +1300 (NZDT) From: Chris Packham To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, tsbogend@alpha.franken.de, hkallweit1@gmail.com, linux@armlinux.org.uk, sander@svanheule.net, daniel@makrotopia.org, markus.stockhausen@gmx.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-mips@vger.kernel.org, Chris Packham Subject: [PATCH net-next v6 4/6] net: mdio: Add RTL9300 MDIO driver Date: Tue, 4 Feb 2025 16:02:47 +1300 Message-ID: <20250204030249.1965444-5-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250204030249.1965444-1-chris.packham@alliedtelesis.co.nz> References: <20250204030249.1965444-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=QNvLRRLL c=1 sm=1 tr=0 ts=67a1837c a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=T2h4t0Lz3GQA:10 a=K5f48OwZufGdpAPWNvYA:9 a=3ZKOabzyN94A:10 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat X-Patchwork-Delegate: kuba@kernel.org Add a driver for the MDIO controller on the RTL9300 family of Ethernet switches with integrated SoC. There are 4 physical SMI interfaces on the RTL9300 however access is done using the switch ports. The driver takes the MDIO bus hierarchy from the DTS and uses this to configure the switch ports so they are associated with the correct PHY. This mapping is also used when dealing with software requests from phylib. Signed-off-by: Chris Packham --- Notes: Changes in v6: - Parse port->phy mapping from devicetree removing the need for the realtek,port property - Remove erroneous code dealing with SMI_POLL_CTRL. When actually implemented this stops the LED unit from updating correctly. Changes in v5: - Reword out of date comment - Use GENMASK/FIELD_PREP where appropriate - Introduce port validity bitmap. - Use more obvious names for PHY_CTRL_READ/WRITE and PHY_CTRL_TYPE_C45/C22 Changes in v4: - rename to realtek-rtl9300 - s/realtek_/rtl9300_/ - add locking to support concurrent access - The dtbinding now represents the MDIO bus hierarchy so we consume this information and use it to configure the switch port to MDIO bus+addr. Changes in v3: - Fix (another) off-by-one error Changes in v2: - Add clause 22 support - Remove commented out code - Formatting cleanup - Set MAX_PORTS correctly for MDIO interface - Fix off-by-one error in pn check drivers/net/mdio/Kconfig | 7 + drivers/net/mdio/Makefile | 1 + drivers/net/mdio/mdio-realtek-rtl9300.c | 472 ++++++++++++++++++++++++ 3 files changed, 480 insertions(+) create mode 100644 drivers/net/mdio/mdio-realtek-rtl9300.c diff --git a/drivers/net/mdio/Kconfig b/drivers/net/mdio/Kconfig index 4a7a303be2f7..058fcdaf6c18 100644 --- a/drivers/net/mdio/Kconfig +++ b/drivers/net/mdio/Kconfig @@ -185,6 +185,13 @@ config MDIO_IPQ8064 This driver supports the MDIO interface found in the network interface units of the IPQ8064 SoC +config MDIO_REALTEK_RTL9300 + tristate "Realtek RTL9300 MDIO interface support" + depends on MACH_REALTEK_RTL || COMPILE_TEST + help + This driver supports the MDIO interface found in the Realtek + RTL9300 family of Ethernet switches with integrated SoC. + config MDIO_REGMAP tristate help diff --git a/drivers/net/mdio/Makefile b/drivers/net/mdio/Makefile index 1015f0db4531..c23778e73890 100644 --- a/drivers/net/mdio/Makefile +++ b/drivers/net/mdio/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o obj-$(CONFIG_MDIO_MVUSB) += mdio-mvusb.o obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o +obj-$(CONFIG_MDIO_REALTEK_RTL9300) += mdio-realtek-rtl9300.o obj-$(CONFIG_MDIO_REGMAP) += mdio-regmap.o obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.o obj-$(CONFIG_MDIO_THUNDER) += mdio-thunder.o diff --git a/drivers/net/mdio/mdio-realtek-rtl9300.c b/drivers/net/mdio/mdio-realtek-rtl9300.c new file mode 100644 index 000000000000..177163af1a1b --- /dev/null +++ b/drivers/net/mdio/mdio-realtek-rtl9300.c @@ -0,0 +1,472 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * MDIO controller for RTL9300 switches with integrated SoC. + * + * The MDIO communication is abstracted by the switch. At the software level + * communication uses the switch port to address the PHY. We work out the + * mapping based on the MDIO bus described in device tree and the realtek,port + * property. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SMI_GLB_CTRL 0xca00 +#define GLB_CTRL_INTF_SEL(intf) BIT(16 + (intf)) +#define SMI_PORT0_15_POLLING_SEL 0xca08 +#define SMI_ACCESS_PHY_CTRL_0 0xcb70 +#define SMI_ACCESS_PHY_CTRL_1 0xcb74 +#define PHY_CTRL_WRITE BIT(2) +#define PHY_CTRL_READ 0 +#define PHY_CTRL_TYPE_C45 BIT(1) +#define PHY_CTRL_TYPE_C22 0 +#define PHY_CTRL_CMD BIT(0) +#define PHY_CTRL_FAIL BIT(25) +#define SMI_ACCESS_PHY_CTRL_2 0xcb78 +#define SMI_ACCESS_PHY_CTRL_3 0xcb7c +#define SMI_PORT0_5_ADDR_CTRL 0xcb80 + +#define MAX_PORTS 28 +#define MAX_SMI_BUSSES 4 +#define MAX_SMI_ADDR 0x1f + +struct rtl9300_mdio_priv { + struct regmap *regmap; + struct mutex lock; /* protect HW access */ + DECLARE_BITMAP(valid_ports, MAX_PORTS); + u8 smi_bus[MAX_PORTS]; + u8 smi_addr[MAX_PORTS]; + bool smi_bus_is_c45[MAX_SMI_BUSSES]; + struct mii_bus *bus[MAX_SMI_BUSSES]; +}; + +struct rtl9300_mdio_chan { + struct rtl9300_mdio_priv *priv; + u8 mdio_bus; +}; + +static int rtl9300_mdio_phy_to_port(struct mii_bus *bus, int phy_id) +{ + struct rtl9300_mdio_chan *chan = bus->priv; + struct rtl9300_mdio_priv *priv = chan->priv; + int i; + + for (i = find_first_bit(priv->valid_ports, MAX_PORTS); + i < MAX_PORTS; + i = find_next_bit(priv->valid_ports, MAX_PORTS, i + 1)) + if (priv->smi_bus[i] == chan->mdio_bus && + priv->smi_addr[i] == phy_id) + return i; + + return -ENOENT; +} + +static int rtl9300_mdio_wait_ready(struct rtl9300_mdio_priv *priv) +{ + struct regmap *regmap = priv->regmap; + u32 val; + + lockdep_assert_held(&priv->lock); + + return regmap_read_poll_timeout(regmap, SMI_ACCESS_PHY_CTRL_1, + val, !(val & PHY_CTRL_CMD), 10, 1000); +} + +static int rtl9300_mdio_read_c22(struct mii_bus *bus, int phy_id, int regnum) +{ + struct rtl9300_mdio_chan *chan = bus->priv; + struct rtl9300_mdio_priv *priv = chan->priv; + struct regmap *regmap = priv->regmap; + int port; + u32 val; + int err; + + guard(mutex)(&priv->lock); + + port = rtl9300_mdio_phy_to_port(bus, phy_id); + if (port < 0) + return port; + + err = rtl9300_mdio_wait_ready(priv); + if (err) + return err; + + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_2, port << 16); + if (err) + return err; + + val = FIELD_PREP(GENMASK(24, 20), regnum) | + FIELD_PREP(GENMASK(19, 15), 0x1f) | + FIELD_PREP(GENMASK(14, 3), 0xfff) | + PHY_CTRL_READ | PHY_CTRL_TYPE_C22 | PHY_CTRL_CMD; + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_1, val); + if (err) + return err; + + err = rtl9300_mdio_wait_ready(priv); + if (err) + return err; + + err = regmap_read(regmap, SMI_ACCESS_PHY_CTRL_2, &val); + if (err) + return err; + + return FIELD_GET(GENMASK(15, 0), val); +} + +static int rtl9300_mdio_write_c22(struct mii_bus *bus, int phy_id, int regnum, u16 value) +{ + struct rtl9300_mdio_chan *chan = bus->priv; + struct rtl9300_mdio_priv *priv = chan->priv; + struct regmap *regmap = priv->regmap; + int port; + u32 val; + int err; + + guard(mutex)(&priv->lock); + + port = rtl9300_mdio_phy_to_port(bus, phy_id); + if (port < 0) + return port; + + err = rtl9300_mdio_wait_ready(priv); + if (err) + return err; + + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_0, BIT(port)); + if (err) + return err; + + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_2, value << 16); + if (err) + return err; + + val = FIELD_PREP(GENMASK(24, 20), regnum) | + FIELD_PREP(GENMASK(19, 15), 0x1f) | + FIELD_PREP(GENMASK(14, 3), 0xfff) | + PHY_CTRL_WRITE | PHY_CTRL_TYPE_C22 | PHY_CTRL_CMD; + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_1, val); + if (err) + return err; + + err = regmap_read_poll_timeout(regmap, SMI_ACCESS_PHY_CTRL_1, + val, !(val & PHY_CTRL_CMD), 10, 100); + if (err) + return err; + + if (val & PHY_CTRL_FAIL) + return -ENXIO; + + return 0; +} + +static int rtl9300_mdio_read_c45(struct mii_bus *bus, int phy_id, int dev_addr, int regnum) +{ + struct rtl9300_mdio_chan *chan = bus->priv; + struct rtl9300_mdio_priv *priv = chan->priv; + struct regmap *regmap = priv->regmap; + int port; + u32 val; + int err; + + guard(mutex)(&priv->lock); + + port = rtl9300_mdio_phy_to_port(bus, phy_id); + if (port < 0) + return port; + + err = rtl9300_mdio_wait_ready(priv); + if (err) + return err; + + val = FIELD_PREP(GENMASK(31, 16), port); + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_2, val); + if (err) + return err; + + val = FIELD_PREP(GENMASK(20, 16), dev_addr) | + FIELD_PREP(GENMASK(15, 0), regnum); + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_3, val); + if (err) + return err; + + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_1, + PHY_CTRL_READ | PHY_CTRL_TYPE_C45 | PHY_CTRL_CMD); + if (err) + return err; + + err = rtl9300_mdio_wait_ready(priv); + if (err) + return err; + + err = regmap_read(regmap, SMI_ACCESS_PHY_CTRL_2, &val); + if (err) + return err; + + return FIELD_GET(GENMASK(15, 0), val); +} + +static int rtl9300_mdio_write_c45(struct mii_bus *bus, int phy_id, int dev_addr, + int regnum, u16 value) +{ + struct rtl9300_mdio_chan *chan = bus->priv; + struct rtl9300_mdio_priv *priv = chan->priv; + struct regmap *regmap = priv->regmap; + int port; + u32 val; + int err; + + guard(mutex)(&priv->lock); + + port = rtl9300_mdio_phy_to_port(bus, phy_id); + if (port < 0) + return port; + + err = rtl9300_mdio_wait_ready(priv); + if (err) + return err; + + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_0, BIT(port)); + if (err) + return err; + + val = FIELD_PREP(GENMASK(31, 16), value); + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_2, val); + if (err) + return err; + + val = FIELD_PREP(GENMASK(20, 16), dev_addr) | + FIELD_PREP(GENMASK(15, 0), regnum); + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_3, val); + if (err) + return err; + + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_1, + PHY_CTRL_TYPE_C45 | PHY_CTRL_WRITE | PHY_CTRL_CMD); + if (err) + return err; + + err = regmap_read_poll_timeout(regmap, SMI_ACCESS_PHY_CTRL_1, + val, !(val & PHY_CTRL_CMD), 10, 100); + if (err) + return err; + + if (val & PHY_CTRL_FAIL) + return -ENXIO; + + return 0; +} + +static int rtl9300_mdiobus_init(struct rtl9300_mdio_priv *priv) +{ + u32 glb_ctrl_mask = 0, glb_ctrl_val = 0; + struct regmap *regmap = priv->regmap; + u32 port_addr[5] = { 0 }; + u32 poll_sel[2] = { 0 }; + int i, err; + + /* Associate the port with the SMI interface and PHY */ + for (i = find_first_bit(priv->valid_ports, MAX_PORTS); + i < MAX_PORTS; + i = find_next_bit(priv->valid_ports, MAX_PORTS, i + 1)) { + int pos; + + pos = (i % 6) * 5; + port_addr[i / 6] |= (priv->smi_addr[i] & 0x1f) << pos; + + pos = (i % 16) * 2; + poll_sel[i / 16] |= (priv->smi_bus[i] & 0x3) << pos; + } + + /* Put the interfaces into C45 mode if required */ + glb_ctrl_mask = GENMASK(19, 16); + for (i = 0; i < MAX_SMI_BUSSES; i++) + if (priv->smi_bus_is_c45[i]) + glb_ctrl_val |= GLB_CTRL_INTF_SEL(i); + + err = regmap_bulk_write(regmap, SMI_PORT0_5_ADDR_CTRL, + port_addr, 5); + if (err) + return err; + + err = regmap_bulk_write(regmap, SMI_PORT0_15_POLLING_SEL, + poll_sel, 2); + if (err) + return err; + + err = regmap_update_bits(regmap, SMI_GLB_CTRL, + glb_ctrl_mask, glb_ctrl_val); + if (err) + return err; + + return 0; +} + +static int rtl9300_mdiobus_probe_one(struct device *dev, struct rtl9300_mdio_priv *priv, + struct fwnode_handle *node) +{ + struct rtl9300_mdio_chan *chan; + struct fwnode_handle *child; + struct mii_bus *bus; + u32 mdio_bus; + int err; + + err = fwnode_property_read_u32(node, "reg", &mdio_bus); + if (err) + return err; + + fwnode_for_each_child_node(node, child) + if (fwnode_device_is_compatible(child, "ethernet-phy-ieee802.3-c45")) + priv->smi_bus_is_c45[mdio_bus] = true; + + bus = devm_mdiobus_alloc_size(dev, sizeof(*chan)); + if (!bus) + return -ENOMEM; + + bus->name = "Reaktek Switch MDIO Bus"; + bus->read = rtl9300_mdio_read_c22; + bus->write = rtl9300_mdio_write_c22; + bus->read_c45 = rtl9300_mdio_read_c45; + bus->write_c45 = rtl9300_mdio_write_c45; + bus->parent = dev; + chan = bus->priv; + chan->mdio_bus = mdio_bus; + chan->priv = priv; + + snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", dev_name(dev), mdio_bus); + + err = devm_of_mdiobus_register(dev, bus, to_of_node(node)); + if (err) + return dev_err_probe(dev, err, "cannot register MDIO bus\n"); + + return 0; +} + +/* The mdio-controller is part of a switch block so we parse the sibling + * ethernet-ports node and build a mapping of the switch port to MDIO bus/addr + * based on the phy-handle. + */ +static int rtl9300_mdiobus_map_ports(struct device *dev) +{ + struct rtl9300_mdio_priv *priv = dev_get_drvdata(dev); + struct device *parent = dev->parent; + struct fwnode_handle *port; + int err; + + struct fwnode_handle *ports __free(fwnode_handle) = + device_get_named_child_node(parent, "ethernet-ports"); + if (!ports) + return dev_err_probe(dev, -EINVAL, "%pfwP missing ethernet-ports\n", + dev_fwnode(parent)); + + fwnode_for_each_child_node(ports, port) { + struct device_node *mdio_dn; + u32 addr; + u32 bus; + u32 pn; + + struct device_node *phy_dn __free(device_node) = + of_parse_phandle(to_of_node(port), "phy-handle", 0); + /* skip ports without phys */ + if (!phy_dn) + continue; + + mdio_dn = phy_dn->parent; + /* only map ports that are connected to this mdio-controller */ + if (mdio_dn->parent != dev->of_node) + continue; + + err = fwnode_property_read_u32(port, "reg", &pn); + if (err) + return err; + + if (pn >= MAX_PORTS) + return dev_err_probe(dev, -EINVAL, "illegal port number %d\n", pn); + + err = of_property_read_u32(mdio_dn, "reg", &bus); + if (err) + return err; + + if (bus >= MAX_SMI_BUSSES) + return dev_err_probe(dev, -EINVAL, "illegal smi bus number %d\n", bus); + + err = of_property_read_u32(phy_dn, "reg", &addr); + if (err) + return err; + + bitmap_set(priv->valid_ports, pn, 1); + priv->smi_bus[pn] = bus; + priv->smi_addr[pn] = addr; + } + + return 0; +} + +static int rtl9300_mdiobus_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rtl9300_mdio_priv *priv; + struct fwnode_handle *child; + int err; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + err = devm_mutex_init(dev, &priv->lock); + if (err) + return err; + + priv->regmap = syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + + platform_set_drvdata(pdev, priv); + + err = rtl9300_mdiobus_map_ports(dev); + if (err) + return err; + + device_for_each_child_node(dev, child) { + err = rtl9300_mdiobus_probe_one(dev, priv, child); + if (err) + return err; + } + + err = rtl9300_mdiobus_init(priv); + if (err) + return dev_err_probe(dev, err, "failed to initialise MDIO bus controller\n"); + + return 0; +} + +static const struct of_device_id rtl9300_mdio_ids[] = { + { .compatible = "realtek,rtl9301-mdio" }, + {} +}; +MODULE_DEVICE_TABLE(of, rtl9300_mdio_ids); + +static struct platform_driver rtl9300_mdio_driver = { + .probe = rtl9300_mdiobus_probe, + .driver = { + .name = "mdio-rtl9300", + .of_match_table = rtl9300_mdio_ids, + }, +}; + +module_platform_driver(rtl9300_mdio_driver); + +MODULE_DESCRIPTION("RTL9300 MDIO driver"); +MODULE_LICENSE("GPL"); From patchwork Tue Feb 4 03:02:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13958547 X-Patchwork-Delegate: kuba@kernel.org Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 941BF165F1F for ; Tue, 4 Feb 2025 03:03:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738638217; cv=none; b=MxJ7a1BJqV9w+pjq8h6CigBAai/1PnUo69ILyTog5JMONqOupbIVAV4s+EwSIpdDm+C2+KHtW8/0dR+T4Ty9Lpynjvka7j5nppAZwvWxshFRHz6QGU4QOWptsj/GPK+WB+hn9MEpcvM0XZt8shTe5m6Sy78Oxg2qWWb3F0MFPlg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738638217; c=relaxed/simple; bh=t4LfaX3CkasCiB8shsAKsuF3aUvx+SQvcPch27gP2pc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mnJ3QuBOjTYCwfJMR5IxnDSSVuWlP8YyQp/YVkLh1pfNkn7jJq6eadRRq6VUZKLF/w7zD8dQlGbSqqWLMXx5DSxteZmv02yzSYiN+KZMxJT5WWPvXkoEj356IoJrbUHOtO0ig3bSvmUlQek8tQzTHrUIZsW2duHsfhEugvRS26k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz; spf=pass smtp.mailfrom=alliedtelesis.co.nz; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b=Ykeg0JA6; arc=none smtp.client-ip=202.36.163.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="Ykeg0JA6" Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 264392C022F; Tue, 4 Feb 2025 16:03:34 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1738638214; bh=gq1Ia62W3STA/wuPVKuerKNFHpoRmtL8AcD76Hwures=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ykeg0JA63eWmIRmLxnYoMkNEB6t5Z51HUaovvsQxuKVe+DEbBQMieQINTIjtSLWFg coYG1cf2LDidyvfjV7ZWZwWOWqJfPwOHotM0ME2fWPYOMUC4VnvSbL0BMG6tHxUL/b QiH1T0SsxvtThF7p6n4OjUUVgARoQqIvQZooYkpvx+1eC97ITDjv1zY9XT6/amMqKK gKEoYScWoEWYH1s3tvBPHO+kRQJFeIoDM37HTa+fJ7Dz+AFQ0Sq2hmHOwd4RUkfIHz tjMqtjjbddOO+USxleUOhng0MtET2Taby5LBbay0eaeiLb7Z7EcpE+aBst9kPFw9Oj GydmV51x2Qbyg== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Tue, 04 Feb 2025 16:03:33 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id EE0AE13EE36; Tue, 4 Feb 2025 16:03:33 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id E98722804B6; Tue, 4 Feb 2025 16:03:33 +1300 (NZDT) From: Chris Packham To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, tsbogend@alpha.franken.de, hkallweit1@gmail.com, linux@armlinux.org.uk, sander@svanheule.net, daniel@makrotopia.org, markus.stockhausen@gmx.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-mips@vger.kernel.org, Chris Packham Subject: [PATCH net-next v6 5/6] mips: dts: realtek: Add MDIO controller Date: Tue, 4 Feb 2025 16:02:48 +1300 Message-ID: <20250204030249.1965444-6-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250204030249.1965444-1-chris.packham@alliedtelesis.co.nz> References: <20250204030249.1965444-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=QNvLRRLL c=1 sm=1 tr=0 ts=67a18385 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=T2h4t0Lz3GQA:10 a=Vd_wJYyKU8c0xNhbhIwA:9 a=3ZKOabzyN94A:10 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat X-Patchwork-Delegate: kuba@kernel.org Add a device tree node for the MDIO controller on the RTL9300 chips. Signed-off-by: Chris Packham --- Notes: Changes in v6: - None Changes in v5: - Add reg property to mdio-controller Changes in v4: - Have a single mdio-controller with the individual buses as child nodes Changes in v3: - None Changes in v2: - None arch/mips/boot/dts/realtek/rtl930x.dtsi | 33 +++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/mips/boot/dts/realtek/rtl930x.dtsi b/arch/mips/boot/dts/realtek/rtl930x.dtsi index f2e57ea3a60c..101bab72a95f 100644 --- a/arch/mips/boot/dts/realtek/rtl930x.dtsi +++ b/arch/mips/boot/dts/realtek/rtl930x.dtsi @@ -69,6 +69,39 @@ i2c1: i2c@388 { #size-cells = <0>; status = "disabled"; }; + + mdio_controller: mdio-controller@ca00 { + compatible = "realtek,rtl9301-mdio"; + reg = <0xca00 0x200>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + mdio0: mdio-bus@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + mdio1: mdio-bus@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + mdio2: mdio-bus@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + mdio3: mdio-bus@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; }; soc: soc@18000000 { From patchwork Tue Feb 4 03:02:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13958548 X-Patchwork-Delegate: kuba@kernel.org Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED814200100 for ; Tue, 4 Feb 2025 03:03:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738638227; cv=none; b=m4viWXuxNy7LdFyc8wQnUR9blRDB4Vs9ASWy0x0PfpIXZ2FbyVBtWtdelSVyZWv/u//0f+SAAEmfezySYRLKuYDO9qz3wmxMBWwLHN3+Lt6Qanezh0dW+RlYIu+8q7cOJGcRSABTBJLiNdcVVe6ixAbbJc7GHDYk950Mc3jDYa4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738638227; c=relaxed/simple; bh=ayBIXbeoO+bcNseOdW5iN3U/7YIqlyA3LzBqND89pXY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=djN8Kzead9W524rVzsrKTRAkupfBQncuVsx/9TApJLrbGfCMVlNKnDgC+gQXf+66nMpe8Zk2ph12JMWGbNniGkvLNZaX2tXouheS7MmpcxePr1ns3LCK+H/fc0sUU1rRvvfRsX+dqd0ZrS77eZrMOBMurKtBTxzQTr22l/6M9CQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz; spf=pass smtp.mailfrom=alliedtelesis.co.nz; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b=iSG+MrxL; arc=none smtp.client-ip=202.36.163.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="iSG+MrxL" Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 6E8BD2C022F; Tue, 4 Feb 2025 16:03:44 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1738638224; bh=q84Fy4g6qKHM8sKjt/XoJeIMA8/NoGzGazA/6/MaXwA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iSG+MrxLfdqn+GYIMMnd4jlkCi8X4eOYIlQsLrP3X+12sr4tDOxCVgIke874X+OJ6 W/42nWmJSTKZ1qXTBf/U7pL04vR8gfT7IzHBoNk9gbcOJQV7DL5IIqp+tKXlbs1wuI 9y+mFAI/9mB26DlFu+9dw43GIhWE4q7P9/fIqgHCsLMLlAf6t/0HMUfROvCmWH3zDl UcpJkU6jIQzXLLsNkKQjz7K0cjVFQTCI8jr9pukAYaA9aTeA14Isg3WtE3Cv+IkGW+ UhPPLGnb+HAswvfFJ5f/n0rLEkw0HbxanapIxUuVtkVpdoz6U48L3xEnmXCLX33ggi uiejDVBnW08SA== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Tue, 04 Feb 2025 16:03:44 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 3473213EE36; Tue, 4 Feb 2025 16:03:44 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 300082804B6; Tue, 4 Feb 2025 16:03:44 +1300 (NZDT) From: Chris Packham To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, tsbogend@alpha.franken.de, hkallweit1@gmail.com, linux@armlinux.org.uk, sander@svanheule.net, daniel@makrotopia.org, markus.stockhausen@gmx.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-mips@vger.kernel.org, Chris Packham Subject: [PATCH net-next v6 6/6] mips: dts: cameo-rtl9302c: Add switch block Date: Tue, 4 Feb 2025 16:02:49 +1300 Message-ID: <20250204030249.1965444-7-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250204030249.1965444-1-chris.packham@alliedtelesis.co.nz> References: <20250204030249.1965444-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=QNvLRRLL c=1 sm=1 tr=0 ts=67a18390 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=T2h4t0Lz3GQA:10 a=FnvEQtqmOLBUJeBfsr8A:9 a=3ZKOabzyN94A:10 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat X-Patchwork-Delegate: kuba@kernel.org Add the switch port and phys to the cameo-rtl9302c-2x-rtl8224-2xge board. Signed-off-by: Chris Packham --- Notes: Changes in v6: - New. This is needed to comply with the updated bindings. It could possibly be split to add the ports then the PHYs. Technically the ports are the required property that dtbs_check will complain about but it didn't seem worth separating out the PHYs. .../cameo-rtl9302c-2x-rtl8224-2xge.dts | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/mips/boot/dts/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts b/arch/mips/boot/dts/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts index 6789bf374044..28ab2442b37a 100644 --- a/arch/mips/boot/dts/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts +++ b/arch/mips/boot/dts/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts @@ -71,3 +71,99 @@ partition@1180000 { }; }; }; + +&mdio0 { + /* External RTL8224 */ + phy0: ethernet-phy@0 { + reg = <0>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + phy1: ethernet-phy@1 { + reg = <1>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + phy2: ethernet-phy@2 { + reg = <2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + phy3: ethernet-phy@3 { + reg = <3>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; +}; + +&mdio1 { + /* External RTL8224 */ + phy4: ethernet-phy@0 { + reg = <0>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + phy5: ethernet-phy@1 { + reg = <1>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + phy6: ethernet-phy@2 { + reg = <2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + phy7: ethernet-phy@3 { + reg = <3>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; +}; + +&switch0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + phy-handle = <&phy0>; + phy-mode = "usxgmii"; + }; + port@1 { + reg = <1>; + phy-handle = <&phy1>; + phy-mode = "usxgmii"; + }; + port@2 { + reg = <2>; + phy-handle = <&phy2>; + phy-mode = "usxgmii"; + }; + port@3 { + reg = <3>; + phy-handle = <&phy3>; + phy-mode = "usxgmii"; + }; + port@16 { + reg = <16>; + phy-handle = <&phy4>; + phy-mode = "usxgmii"; + }; + port@17 { + reg = <17>; + phy-handle = <&phy5>; + phy-mode = "usxgmii"; + }; + port@18 { + reg = <18>; + phy-handle = <&phy6>; + phy-mode = "usxgmii"; + }; + port@19 { + reg = <19>; + phy-handle = <&phy7>; + phy-mode = "usxgmii"; + }; + port@24{ + reg = <24>; + phy-mode = "10gbase-r"; + }; + port@25{ + reg = <25>; + phy-mode = "10gbase-r"; + }; + }; +};