From patchwork Tue Feb 4 06:10:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Choong Yong Liang X-Patchwork-Id: 13958664 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB4C125A624; Tue, 4 Feb 2025 06:11:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738649481; cv=none; b=mdg1fMdEBMowFbI5Lwqvrn+q+hE2Co/B2CMXkYcg2UrNQtuti1w+4gsa2FnmcKz9vNn6hkH7XJUnsTcWc85Gh46EmEd2a3xR1wgyP3e0dFU1s6IltiF/Pf8Yw/Vfp/cb6VLqjL0d1Ndi7HM3RZNWTBbm9Fg0EnkVxvV0OSbCrYk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738649481; c=relaxed/simple; bh=7n0vam23Uf784ublbhVBP5AsWpQxp+3QLHvPVC2Ki4w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BXbMMeN6ooxSfVPWcW1d3fUIAcRTN9j3pGtg4VG2bxs73I8CsiXnPQrkzqa6NMSPmGioEXw/yleVFjIOlLXE2OPW7Yvy3MF0ZdfgeJzLJWyZ4PVZVwvETh54f433fukFID2OBKimqgixrHmUgpmIFbJ5n7VXHAqfUI1oUxZmqJA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=gN7EDLaV; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="gN7EDLaV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738649480; x=1770185480; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7n0vam23Uf784ublbhVBP5AsWpQxp+3QLHvPVC2Ki4w=; b=gN7EDLaVd5nvMlmWD1a5Pjby7SNPLnGFmNPamKfOrV789u7aAmFwaCH7 rAgGXzkDSNH79V4D40TZsJWEBFMSqHwzlc+uIGlkHrnR71hNmnDwb4eqW fVtJyBqRen52/MqIhUhlGurFo/WnvGPoQf15FFU+osj+Tkibjrrn6Uy3e PIMmeICAWoVXUW7DXKQBNnf5/EZCNtF4EHa/Wkd3zqo8einJWlCgZ/GD1 fsNF5+K8c3wax2AOpAZThTjMs2BGE5Q03obiME+UYa/WAouf+kq2UK9pM 6zQj7CVGct/zfr7MRawStEJMJsoUP9W+J0ABv2VJOGVhyNxdN/nXsmRKe A==; X-CSE-ConnectionGUID: xDQDcwSjQBCjsu2KzfdHoA== X-CSE-MsgGUID: Fr4aKB0VQ/u1Y92AKBiwww== X-IronPort-AV: E=McAfee;i="6700,10204,11314"; a="50579608" X-IronPort-AV: E=Sophos;i="6.12,310,1728975600"; d="scan'208";a="50579608" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2025 22:11:19 -0800 X-CSE-ConnectionGUID: YinZviaxTTyrV7MlNpzCpw== X-CSE-MsgGUID: sbOtTjAqTG2arJW7fGx7uw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,258,1732608000"; d="scan'208";a="110279153" Received: from yongliang-ubuntu20-ilbpg12.png.intel.com ([10.88.227.39]) by orviesa009.jf.intel.com with ESMTP; 03 Feb 2025 22:11:12 -0800 From: Choong Yong Liang To: Simon Horman , Jose Abreu , Jose Abreu , David E Box , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H . Peter Anvin" , Rajneesh Bhardwaj , David E Box , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Jiawen Wu , Mengyuan Lou , Heiner Kallweit , Russell King , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Richard Cochran , Andrew Halaney , Serge Semin Cc: x86@kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH net-next v6 1/7] net: phylink: use act_link_an_mode to determine PHY Date: Tue, 4 Feb 2025 14:10:14 +0800 Message-Id: <20250204061020.1199124-2-yong.liang.choong@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250204061020.1199124-1-yong.liang.choong@linux.intel.com> References: <20250204061020.1199124-1-yong.liang.choong@linux.intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org When the interface mode is SGMII and act_link_an_mode is MLO_AN_INBAND, switching to the 2500BASE-X interface mode will trigger phylink_major_config, and act_link_an_mode will be updated to MLO_AN_PHY in phylink_pcs_neg_mode when the PCS does not support in-band mode. The MAC and PCS will configure according to the interface mode and act_link_an_mode. However, when the interface goes link down and then link up again, the MAC will attempt to attach the PHY. The interface mode remains as 2500BASE-X, but cfg_link_an_mode still holds MLO_AN_INBAND. This causes a failure to attach the PHY. This patch uses act_link_an_mode to determine if there is a PHY to attach. Signed-off-by: Choong Yong Liang --- drivers/net/phy/phylink.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 214b62fba991..b0f9725e0494 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -1903,6 +1903,7 @@ int phylink_set_fixed_link(struct phylink *pl, pl->cfg_link_an_mode = MLO_AN_FIXED; pl->req_link_an_mode = pl->cfg_link_an_mode; + pl->act_link_an_mode = pl->cfg_link_an_mode; return 0; } @@ -2002,6 +2003,7 @@ struct phylink *phylink_create(struct phylink_config *config, } pl->req_link_an_mode = pl->cfg_link_an_mode; + pl->act_link_an_mode = pl->cfg_link_an_mode; ret = phylink_register_sfp(pl, fwnode); if (ret < 0) { @@ -2044,8 +2046,8 @@ EXPORT_SYMBOL_GPL(phylink_destroy); */ bool phylink_expects_phy(struct phylink *pl) { - if (pl->cfg_link_an_mode == MLO_AN_FIXED || - (pl->cfg_link_an_mode == MLO_AN_INBAND && + if (pl->act_link_an_mode == MLO_AN_FIXED || + (pl->act_link_an_mode == MLO_AN_INBAND && phy_interface_mode_is_8023z(pl->link_config.interface))) return false; return true; @@ -2280,8 +2282,8 @@ static int phylink_attach_phy(struct phylink *pl, struct phy_device *phy, { u32 flags = 0; - if (WARN_ON(pl->cfg_link_an_mode == MLO_AN_FIXED || - (pl->cfg_link_an_mode == MLO_AN_INBAND && + if (WARN_ON(pl->act_link_an_mode == MLO_AN_FIXED || + (pl->act_link_an_mode == MLO_AN_INBAND && phy_interface_mode_is_8023z(interface) && !pl->sfp_bus))) return -EINVAL; From patchwork Tue Feb 4 06:10:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Choong Yong Liang X-Patchwork-Id: 13958665 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 090D725A655; Tue, 4 Feb 2025 06:11:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738649490; cv=none; b=LQlMp6XRtVSEUd+LkzKbROFmEmVDq3J52yRw4mqzQ2/rZuOAtS6+NvRYFj97QmxSkQTySYfLMFW/qeSgQ6Zv6IZH5Akpw9xDYKMmm3D4Xlgp9UiLChrvNQaDQvbvvy/YaWYVJHPBPxf7TWJ8jvc4qrkJSWmCD3m7vEExYDoSWoU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738649490; c=relaxed/simple; bh=5bkc6SzUBfdWPSB7gExlTFthIkT/D4tk+mfb1mANDSw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=VlEHFs6Lbrb55bnE8jPK5yU0bSo3/pbmZUQTvB/ssN3vX7DcDMG+gtlF/mvP35giqWdw6Lfn1R2k213CKalzXNi+9hGxSJpFE/xTM4vPwI1UqgreOSVj5klxbuHWmhJUw2ThOguhha0mPeR+azNhcI/6XXvpX5zZiufgScS/Dxo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=TDavNKB0; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TDavNKB0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738649489; x=1770185489; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5bkc6SzUBfdWPSB7gExlTFthIkT/D4tk+mfb1mANDSw=; b=TDavNKB0rEbAy9dzaPq3nbZ3LB2bADvHGza0FXHSwIlxvkAAB1TYwVSn wD2lBbuikdnLu56HWH783N2y0CAYVbLfNIBDNZX0lclLqnmJ3t5k+9o7q vQ+6AzNrFdv7rFShfjxj3KwjoBKBG6HJs9vETw6EUt44ANIZBPKS7jRRH Q5K2THN04hXJzSRXsMs+kEpdrR8IooocBz7XDs/s1jTBaxh/x1+Mo8kgd /CE/t6zq+jlUA9+GTTF7WuOpiRJ7rQ4yebFAqjtllMJTdp7T3xz+FBi6S 55hdRhCivx7HEvivD3IM6rlKLP8DeRGRolGYc89t16JRcz1juAV9XPC3A A==; X-CSE-ConnectionGUID: l4iJNY5qQP6n7ZO3yZ25Ow== X-CSE-MsgGUID: Omid1IApRHi5ev0UQ0y8xg== X-IronPort-AV: E=McAfee;i="6700,10204,11314"; a="50579618" X-IronPort-AV: E=Sophos;i="6.12,310,1728975600"; d="scan'208";a="50579618" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2025 22:11:28 -0800 X-CSE-ConnectionGUID: E7pjPBh+SXql8izvLDPYnA== X-CSE-MsgGUID: W0QC9zuwTHOMThr5y0eVlw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,258,1732608000"; d="scan'208";a="110279173" Received: from yongliang-ubuntu20-ilbpg12.png.intel.com ([10.88.227.39]) by orviesa009.jf.intel.com with ESMTP; 03 Feb 2025 22:11:20 -0800 From: Choong Yong Liang To: Simon Horman , Jose Abreu , Jose Abreu , David E Box , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H . Peter Anvin" , Rajneesh Bhardwaj , David E Box , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Jiawen Wu , Mengyuan Lou , Heiner Kallweit , Russell King , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Richard Cochran , Andrew Halaney , Serge Semin Cc: x86@kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH net-next v6 2/7] net: pcs: xpcs: re-initiate clause 37 Auto-negotiation Date: Tue, 4 Feb 2025 14:10:15 +0800 Message-Id: <20250204061020.1199124-3-yong.liang.choong@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250204061020.1199124-1-yong.liang.choong@linux.intel.com> References: <20250204061020.1199124-1-yong.liang.choong@linux.intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org The xpcs_switch_interface_mode function was introduced to handle interface switching. According to the XPCS datasheet, a soft reset is required to initiate Clause 37 auto-negotiation when the XPCS switches interface modes. When the interface mode is set to 2500BASE-X, Clause 37 auto-negotiation is turned off. Subsequently, when the interface mode switches from 2500BASE-X to SGMII, re-initiating Clause 37 auto-negotiation is required for the SGMII interface mode to function properly. Signed-off-by: Choong Yong Liang --- drivers/net/pcs/pcs-xpcs-wx.c | 4 +-- drivers/net/pcs/pcs-xpcs.c | 60 ++++++++++++++++++++++++++++++++--- 2 files changed, 57 insertions(+), 7 deletions(-) diff --git a/drivers/net/pcs/pcs-xpcs-wx.c b/drivers/net/pcs/pcs-xpcs-wx.c index fc52f7aa5f59..f73ab04d09f0 100644 --- a/drivers/net/pcs/pcs-xpcs-wx.c +++ b/drivers/net/pcs/pcs-xpcs-wx.c @@ -172,11 +172,9 @@ int txgbe_xpcs_switch_mode(struct dw_xpcs *xpcs, phy_interface_t interface) return 0; } - if (xpcs->interface == interface && !txgbe_xpcs_mode_quirk(xpcs)) + if (!txgbe_xpcs_mode_quirk(xpcs)) return 0; - xpcs->interface = interface; - ret = txgbe_pcs_poll_power_up(xpcs); if (ret < 0) return ret; diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c index 1faa37f0e7b9..fb3d1548a8e0 100644 --- a/drivers/net/pcs/pcs-xpcs.c +++ b/drivers/net/pcs/pcs-xpcs.c @@ -817,6 +817,58 @@ static int xpcs_config_2500basex(struct dw_xpcs *xpcs) BMCR_SPEED1000); } +static int xpcs_switch_to_aneg_c37_sgmii(const struct dw_xpcs_compat *compat, + struct dw_xpcs *xpcs, + unsigned int neg_mode) +{ + bool an_c37_enabled; + int ret, mdio_ctrl; + + if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { + mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); + if (mdio_ctrl < 0) + return mdio_ctrl; + + an_c37_enabled = mdio_ctrl & BMCR_ANENABLE; + if (!an_c37_enabled) { + //Perform soft reset to initiate C37 auto-negotiation + ret = xpcs_soft_reset(xpcs, compat); + if (ret) + return ret; + } + } + return 0; +} + +static int xpcs_switch_interface_mode(const struct dw_xpcs_compat *compat, + struct dw_xpcs *xpcs, + phy_interface_t interface, + unsigned int neg_mode) +{ + int ret = 0; + + if (xpcs->interface != interface) { + if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { + ret = txgbe_xpcs_switch_mode(xpcs, interface); + } else { + switch (compat->an_mode) { + case DW_AN_C37_SGMII: + ret = xpcs_switch_to_aneg_c37_sgmii(compat, xpcs, neg_mode); + break; + default: + break; + } + } + + if (ret) + return ret; + + xpcs->interface = interface; + } + + return 0; +} + static int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface, const unsigned long *advertising, unsigned int neg_mode) @@ -828,11 +880,11 @@ static int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface, if (!compat) return -ENODEV; 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d="scan'208";a="50579654" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2025 22:11:37 -0800 X-CSE-ConnectionGUID: geDbVlmFRpG8R7JE1vBE6A== X-CSE-MsgGUID: 1fvJTpkLQ/ChcQ5xOSlLOw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,258,1732608000"; d="scan'208";a="110279183" Received: from yongliang-ubuntu20-ilbpg12.png.intel.com ([10.88.227.39]) by orviesa009.jf.intel.com with ESMTP; 03 Feb 2025 22:11:29 -0800 From: Choong Yong Liang To: Simon Horman , Jose Abreu , Jose Abreu , David E Box , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H . Peter Anvin" , Rajneesh Bhardwaj , David E Box , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Jiawen Wu , Mengyuan Lou , Heiner Kallweit , Russell King , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Richard Cochran , Andrew Halaney , Serge Semin Cc: x86@kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH net-next v6 3/7] arch: x86: add IPC mailbox accessor function and add SoC register access Date: Tue, 4 Feb 2025 14:10:16 +0800 Message-Id: <20250204061020.1199124-4-yong.liang.choong@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250204061020.1199124-1-yong.liang.choong@linux.intel.com> References: <20250204061020.1199124-1-yong.liang.choong@linux.intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org From: "David E. Box" - Exports intel_pmc_ipc() for host access to the PMC IPC mailbox - Add support to use IPC command allows host to access SoC registers through PMC firmware that are otherwise inaccessible to the host due to security policies. Signed-off-by: David E. Box Signed-off-by: Chao Qin Signed-off-by: Choong Yong Liang --- MAINTAINERS | 2 + arch/x86/Kconfig | 9 +++ arch/x86/platform/intel/Makefile | 1 + arch/x86/platform/intel/pmc_ipc.c | 75 +++++++++++++++++++ .../linux/platform_data/x86/intel_pmc_ipc.h | 34 +++++++++ 5 files changed, 121 insertions(+) create mode 100644 arch/x86/platform/intel/pmc_ipc.c create mode 100644 include/linux/platform_data/x86/intel_pmc_ipc.h diff --git a/MAINTAINERS b/MAINTAINERS index d1086e53a317..7a0681f83449 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11862,8 +11862,10 @@ M: Rajneesh Bhardwaj M: David E Box L: platform-driver-x86@vger.kernel.org S: Maintained +F: arch/x86/platform/intel/pmc_ipc.c F: Documentation/ABI/testing/sysfs-platform-intel-pmc F: drivers/platform/x86/intel/pmc/ +F: linux/platform_data/x86/intel_pmc_ipc.h INTEL PMIC GPIO DRIVERS M: Andy Shevchenko diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 87198d957e2f..631c1f10776c 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -688,6 +688,15 @@ config X86_AMD_PLATFORM_DEVICE I2C and UART depend on COMMON_CLK to set clock. GPIO driver is implemented under PINCTRL subsystem. +config INTEL_PMC_IPC + tristate "Intel Core SoC Power Management Controller IPC mailbox" + depends on ACPI + help + This option enables sideband register access support for Intel SoC + power management controller IPC mailbox. + + If you don't require the option or are in doubt, say N. + config IOSF_MBI tristate "Intel SoC IOSF Sideband support for SoC platforms" depends on PCI diff --git a/arch/x86/platform/intel/Makefile b/arch/x86/platform/intel/Makefile index dbee3b00f9d0..2f1805556d0c 100644 --- a/arch/x86/platform/intel/Makefile +++ b/arch/x86/platform/intel/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_IOSF_MBI) += iosf_mbi.o +obj-$(CONFIG_INTEL_PMC_IPC) += pmc_ipc.o diff --git a/arch/x86/platform/intel/pmc_ipc.c b/arch/x86/platform/intel/pmc_ipc.c new file mode 100644 index 000000000000..a96234982710 --- /dev/null +++ b/arch/x86/platform/intel/pmc_ipc.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel Core SoC Power Management Controller IPC mailbox + * + * Copyright (c) 2023, Intel Corporation. + * All Rights Reserved. + * + * Authors: Choong Yong Liang + * David E. Box + */ +#include +#include +#include + +#define PMC_IPCS_PARAM_COUNT 7 + +int intel_pmc_ipc(struct pmc_ipc_cmd *ipc_cmd, u32 *rbuf) +{ + struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; + union acpi_object params[PMC_IPCS_PARAM_COUNT] = { + {.type = ACPI_TYPE_INTEGER,}, + {.type = ACPI_TYPE_INTEGER,}, + {.type = ACPI_TYPE_INTEGER,}, + {.type = ACPI_TYPE_INTEGER,}, + {.type = ACPI_TYPE_INTEGER,}, + {.type = ACPI_TYPE_INTEGER,}, + {.type = ACPI_TYPE_INTEGER,}, + }; + struct acpi_object_list arg_list = { PMC_IPCS_PARAM_COUNT, params }; + union acpi_object *obj; + int status; + + if (!ipc_cmd || !rbuf) + return -EINVAL; + + /* + * 0: IPC Command + * 1: IPC Sub Command + * 2: Size + * 3-6: Write Buffer for offset + */ + params[0].integer.value = ipc_cmd->cmd; + params[1].integer.value = ipc_cmd->sub_cmd; + params[2].integer.value = ipc_cmd->size; + params[3].integer.value = ipc_cmd->wbuf[0]; + params[4].integer.value = ipc_cmd->wbuf[1]; + params[5].integer.value = ipc_cmd->wbuf[2]; + params[6].integer.value = ipc_cmd->wbuf[3]; + + status = acpi_evaluate_object(NULL, "\\IPCS", &arg_list, &buffer); + if (ACPI_FAILURE(status)) + return -ENODEV; + + obj = buffer.pointer; + /* Check if the number of elements in package is 5 */ + if (obj && obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 5) { + const union acpi_object *objs = obj->package.elements; + + if ((u8)objs[0].integer.value != 0) + return -EINVAL; + + rbuf[0] = objs[1].integer.value; + rbuf[1] = objs[2].integer.value; + rbuf[2] = objs[3].integer.value; + rbuf[3] = objs[4].integer.value; + } else { + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL(intel_pmc_ipc); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Intel PMC IPC Mailbox accessor"); diff --git a/include/linux/platform_data/x86/intel_pmc_ipc.h b/include/linux/platform_data/x86/intel_pmc_ipc.h new file mode 100644 index 000000000000..d47b89f873fc --- /dev/null +++ b/include/linux/platform_data/x86/intel_pmc_ipc.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Intel Core SoC Power Management Controller Header File + * + * Copyright (c) 2023, Intel Corporation. + * All Rights Reserved. + * + * Authors: Choong Yong Liang + * David E. Box + */ +#ifndef INTEL_PMC_IPC_H +#define INTEL_PMC_IPC_H + +#define IPC_SOC_REGISTER_ACCESS 0xAA +#define IPC_SOC_SUB_CMD_READ 0x00 +#define IPC_SOC_SUB_CMD_WRITE 0x01 + +struct pmc_ipc_cmd { + u32 cmd; + u32 sub_cmd; + u32 size; + u32 wbuf[4]; +}; + +/** + * intel_pmc_ipc() - PMC IPC Mailbox accessor + * @ipc_cmd: struct pmc_ipc_cmd prepared with input to send + * @rbuf: Allocated u32[4] array for returned IPC data + * + * Return: 0 on success. Non-zero on mailbox error + */ +int intel_pmc_ipc(struct pmc_ipc_cmd *ipc_cmd, u32 *rbuf); + +#endif /* INTEL_PMC_IPC_H */ From patchwork Tue Feb 4 06:10:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Choong Yong Liang X-Patchwork-Id: 13958667 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4B3E2045A4; Tue, 4 Feb 2025 06:11:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738649508; cv=none; b=DtDiPivgQzgfiLdJvy9XhlxCIksQC/JCIgqBvpRwcQZWSs+vUmWjOI6fsuzhuPoO45lPLamMRHzuvO7c4eKtgwSpkyRHCaE6Z4hOBO+P4sN4jnDpstqCrk0RqI9moogL3Om3yOrVtf1/NqqZl1Ogd+rgn8liHhH5y1SHpgDbjMM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738649508; c=relaxed/simple; bh=i/5Nw9DcOEvUaA0ALLwLsRihB+exMJdJm2u3+qh564I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Uqv7oTQ03DUCPZ14N0mxEaJ2wsOS3qZ+ArTIHP1racuAkc6G6XE5JooTWy07MAoOp/5JNt7LBcyHsX3ggIBJfVPpS1ymUThcNm9cNjMGfjvf38oMaBvaci1EFahCLlGnSoCZrImBhI9XhN/8n7P4bxVvTOakkMEXgeSDxGFleHw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Fne9/7i8; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Fne9/7i8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738649507; x=1770185507; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=i/5Nw9DcOEvUaA0ALLwLsRihB+exMJdJm2u3+qh564I=; b=Fne9/7i8Q6bzLnURp3+bjlw6s4AjMjF+DOQD4oYEGuQtbrxG12jxVLse cojvHYj9K97gHK3D0KuGpQISQyG0Impp7NIGFDo209KIc/0UojF/nTp1S rWWZ8X5aOaxHM6HWgWVFzp0h+UD1NS08UwB3lvHGw6u/onXLKJC5OKOFP BV0KhhVQn3AXsWVx6/azhyXf3MOGkStLOAtD01/AMH3b4A15xi20FHF/9 UbRPy1f37mbDay0/20/JkCfmLqctIChRGm2RvA20oMTk9VRYP4kKe+S0K PYnI9dDcC4fK/8UuD6w6i5S/eom6Hz+0Pklhf0iiHc8OKN2mdA4NBXEzA Q==; X-CSE-ConnectionGUID: UFCXJGkhSfeIg2bVdu3sbg== X-CSE-MsgGUID: aDbdo9FHTCK9To6ef2cx9w== X-IronPort-AV: E=McAfee;i="6700,10204,11314"; a="50579679" X-IronPort-AV: E=Sophos;i="6.12,310,1728975600"; d="scan'208";a="50579679" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2025 22:11:46 -0800 X-CSE-ConnectionGUID: /5raw8aWR8esBToOEqzwqQ== X-CSE-MsgGUID: /q5QUsz5QpqTXa4uYB+9/A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,258,1732608000"; d="scan'208";a="110279196" Received: from yongliang-ubuntu20-ilbpg12.png.intel.com ([10.88.227.39]) by orviesa009.jf.intel.com with ESMTP; 03 Feb 2025 22:11:38 -0800 From: Choong Yong Liang To: Simon Horman , Jose Abreu , Jose Abreu , David E Box , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H . Peter Anvin" , Rajneesh Bhardwaj , David E Box , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Jiawen Wu , Mengyuan Lou , Heiner Kallweit , Russell King , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Richard Cochran , Andrew Halaney , Serge Semin Cc: x86@kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH net-next v6 4/7] stmmac: intel: configure SerDes according to the interface mode Date: Tue, 4 Feb 2025 14:10:17 +0800 Message-Id: <20250204061020.1199124-5-yong.liang.choong@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250204061020.1199124-1-yong.liang.choong@linux.intel.com> References: <20250204061020.1199124-1-yong.liang.choong@linux.intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Intel platform will configure the SerDes through PMC api based on the provided interface mode. This patch adds several new functions below:- - intel_tsn_lane_is_available(): This new function reads FIA lane ownership registers and common lane registers through IPC commands to know which lane the mGbE port is assigned to. - intel_config_serdes(): To configure the SerDes based on the assigned lane and latest interface mode, it sends IPC command to the PMC through PMC driver/API. The PMC acts as a proxy for R/W on behalf of the driver. - intel_set_reg_access(): Set the register access to the available TSN interface. Signed-off-by: Choong Yong Liang --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 2 + .../net/ethernet/stmicro/stmmac/dwmac-intel.c | 107 +++++++++++++++++- .../net/ethernet/stmicro/stmmac/dwmac-intel.h | 75 ++++++++++++ include/linux/stmmac.h | 3 + 4 files changed, 185 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index 4cc85a36a1ab..25154b915b02 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -307,6 +307,8 @@ config DWMAC_INTEL default X86 depends on X86 && STMMAC_ETH && PCI depends on COMMON_CLK + depends on ACPI + select INTEL_PMC_IPC help This selects the Intel platform specific bus support for the stmmac driver. This driver is used for Intel Quark/EHL/TGL. diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c index 48acba5eb178..347dd75bcdcd 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c @@ -5,6 +5,7 @@ #include #include #include +#include #include "dwmac-intel.h" #include "dwmac4.h" #include "stmmac.h" @@ -14,6 +15,9 @@ struct intel_priv_data { int mdio_adhoc_addr; /* mdio address for serdes & etc */ unsigned long crossts_adj; bool is_pse; + const int *tsn_lane_registers; + int max_tsn_lane_registers; + int pid_modphy; }; /* This struct is used to associate PCI Function of MAC controller on a board, @@ -93,7 +97,7 @@ static int intel_serdes_powerup(struct net_device *ndev, void *priv_data) data &= ~SERDES_RATE_MASK; data &= ~SERDES_PCLK_MASK; - if (priv->plat->max_speed == 2500) + if (priv->plat->phy_interface == PHY_INTERFACE_MODE_2500BASEX) data |= SERDES_RATE_PCIE_GEN2 << SERDES_RATE_PCIE_SHIFT | SERDES_PCLK_37p5MHZ << SERDES_PCLK_SHIFT; else @@ -415,6 +419,103 @@ static void intel_mgbe_pse_crossts_adj(struct intel_priv_data *intel_priv, } } +static bool intel_tsn_lane_is_available(struct net_device *ndev, + struct intel_priv_data *intel_priv) +{ + struct stmmac_priv *priv = netdev_priv(ndev); + struct pmc_ipc_cmd tmp = {0}; + u32 rbuf[4] = {0}; + int ret, i, j; + + if (priv->plat->serdes_powerup) { + tmp.cmd = IPC_SOC_REGISTER_ACCESS; + tmp.sub_cmd = IPC_SOC_SUB_CMD_READ; + + for (i = 0; i < 5; i++) { + tmp.wbuf[0] = R_PCH_FIA_15_PCR_LOS1_REG_BASE + i; + + ret = intel_pmc_ipc(&tmp, rbuf); + if (ret < 0) { + netdev_info(priv->dev, + "Failed to read from PMC.\n"); + return false; + } + + for (j = 0; j <= intel_priv->max_tsn_lane_registers; j++) + if ((rbuf[0] >> + (4 * (intel_priv->tsn_lane_registers[j] % 8)) & + B_PCH_FIA_PCR_L0O) == 0xB) + return true; + } + } + return false; +} + +static int intel_set_reg_access(const struct pmc_serdes_regs *regs, int max_regs) +{ + int ret = 0, i; + + for (i = 0; i < max_regs; i++) { + struct pmc_ipc_cmd tmp = {0}; + u32 buf[4] = {0}; + + tmp.cmd = IPC_SOC_REGISTER_ACCESS; + tmp.sub_cmd = IPC_SOC_SUB_CMD_WRITE; + tmp.wbuf[0] = (u32)regs[i].index; + tmp.wbuf[1] = regs[i].val; + + ret = intel_pmc_ipc(&tmp, buf); + if (ret < 0) + return ret; + } + + return ret; +} + +static int intel_config_serdes(struct net_device *ndev, + void *intel_data, + phy_interface_t interface) +{ + struct intel_priv_data *intel_priv = intel_data; + struct stmmac_priv *priv = netdev_priv(ndev); + int ret = 0; + + if (!intel_tsn_lane_is_available(ndev, intel_priv)) { + netdev_info(priv->dev, + "No TSN lane available to set the registers.\n"); + goto pmc_read_error; + } + + if (intel_priv->pid_modphy == PID_MODPHY1) { + if (interface == PHY_INTERFACE_MODE_2500BASEX) { + ret = intel_set_reg_access(pid_modphy1_2p5g_regs, + ARRAY_SIZE(pid_modphy1_2p5g_regs)); + } else { + ret = intel_set_reg_access(pid_modphy1_1g_regs, + ARRAY_SIZE(pid_modphy1_1g_regs)); + } + } else { + if (interface == PHY_INTERFACE_MODE_2500BASEX) { + ret = intel_set_reg_access(pid_modphy3_2p5g_regs, + ARRAY_SIZE(pid_modphy3_2p5g_regs)); + } else { + ret = intel_set_reg_access(pid_modphy3_1g_regs, + ARRAY_SIZE(pid_modphy3_1g_regs)); + } + } + + priv->plat->phy_interface = interface; + + if (ret < 0) + goto pmc_read_error; + +pmc_read_error: + intel_serdes_powerdown(ndev, intel_priv); + intel_serdes_powerup(ndev, intel_priv); + + return ret; +} + static void common_default_data(struct plat_stmmacenet_data *plat) { plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ @@ -650,7 +751,7 @@ static int ehl_sgmii_data(struct pci_dev *pdev, plat->speed_mode_2500 = intel_speed_mode_2500; plat->serdes_powerup = intel_serdes_powerup; plat->serdes_powerdown = intel_serdes_powerdown; - + plat->config_serdes = intel_config_serdes; plat->clk_ptp_rate = 204800000; return ehl_common_data(pdev, plat); @@ -709,6 +810,7 @@ static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev, plat->speed_mode_2500 = intel_speed_mode_2500; plat->serdes_powerup = intel_serdes_powerup; plat->serdes_powerdown = intel_serdes_powerdown; + plat->config_serdes = intel_config_serdes; return ehl_pse0_common_data(pdev, plat); } @@ -750,6 +852,7 @@ static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev, plat->speed_mode_2500 = intel_speed_mode_2500; plat->serdes_powerup = intel_serdes_powerup; plat->serdes_powerdown = intel_serdes_powerdown; + plat->config_serdes = intel_config_serdes; return ehl_pse1_common_data(pdev, plat); } diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h index 0a37987478c1..79c35ba969ea 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h @@ -50,4 +50,79 @@ #define PCH_PTP_CLK_FREQ_19_2MHZ (GMAC_GPO0) #define PCH_PTP_CLK_FREQ_200MHZ (0) +#define PID_MODPHY1 0xAA +#define PID_MODPHY3 0xA8 + +#if IS_ENABLED(CONFIG_INTEL_PMC_IPC) +struct pmc_serdes_regs { + u8 index; + u32 val; +}; + +/* Modphy Register index */ +#define R_PCH_FIA_15_PCR_LOS1_REG_BASE 8 +#define R_PCH_FIA_15_PCR_LOS2_REG_BASE 9 +#define R_PCH_FIA_15_PCR_LOS3_REG_BASE 10 +#define R_PCH_FIA_15_PCR_LOS4_REG_BASE 11 +#define R_PCH_FIA_15_PCR_LOS5_REG_BASE 12 +#define B_PCH_FIA_PCR_L0O GENMASK(3, 0) +#define PID_MODPHY1_B_MODPHY_PCR_LCPLL_DWORD0 13 +#define PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD2 14 +#define PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD7 15 +#define PID_MODPHY1_N_MODPHY_PCR_LPPLL_DWORD10 16 +#define PID_MODPHY1_N_MODPHY_PCR_CMN_ANA_DWORD30 17 +#define PID_MODPHY3_B_MODPHY_PCR_LCPLL_DWORD0 18 +#define PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD2 19 +#define PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD7 20 +#define PID_MODPHY3_N_MODPHY_PCR_LPPLL_DWORD10 21 +#define PID_MODPHY3_N_MODPHY_PCR_CMN_ANA_DWORD30 22 + +#define B_MODPHY_PCR_LCPLL_DWORD0_1G 0x46AAAA41 +#define N_MODPHY_PCR_LCPLL_DWORD2_1G 0x00000139 +#define N_MODPHY_PCR_LCPLL_DWORD7_1G 0x002A0003 +#define N_MODPHY_PCR_LPPLL_DWORD10_1G 0x00170008 +#define N_MODPHY_PCR_CMN_ANA_DWORD30_1G 0x0000D4AC +#define B_MODPHY_PCR_LCPLL_DWORD0_2P5G 0x58555551 +#define N_MODPHY_PCR_LCPLL_DWORD2_2P5G 0x0000012D +#define N_MODPHY_PCR_LCPLL_DWORD7_2P5G 0x001F0003 +#define N_MODPHY_PCR_LPPLL_DWORD10_2P5G 0x00170008 +#define N_MODPHY_PCR_CMN_ANA_DWORD30_2P5G 0x8200ACAC + +static const struct pmc_serdes_regs pid_modphy3_1g_regs[] = { + { PID_MODPHY3_B_MODPHY_PCR_LCPLL_DWORD0, B_MODPHY_PCR_LCPLL_DWORD0_1G }, + { PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD2, N_MODPHY_PCR_LCPLL_DWORD2_1G }, + { PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD7, N_MODPHY_PCR_LCPLL_DWORD7_1G }, + { PID_MODPHY3_N_MODPHY_PCR_LPPLL_DWORD10, N_MODPHY_PCR_LPPLL_DWORD10_1G }, + { PID_MODPHY3_N_MODPHY_PCR_CMN_ANA_DWORD30, N_MODPHY_PCR_CMN_ANA_DWORD30_1G }, + {} +}; + +static const struct pmc_serdes_regs pid_modphy3_2p5g_regs[] = { + { PID_MODPHY3_B_MODPHY_PCR_LCPLL_DWORD0, B_MODPHY_PCR_LCPLL_DWORD0_2P5G }, + { PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD2, N_MODPHY_PCR_LCPLL_DWORD2_2P5G }, + { PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD7, N_MODPHY_PCR_LCPLL_DWORD7_2P5G }, + { PID_MODPHY3_N_MODPHY_PCR_LPPLL_DWORD10, N_MODPHY_PCR_LPPLL_DWORD10_2P5G }, + { PID_MODPHY3_N_MODPHY_PCR_CMN_ANA_DWORD30, N_MODPHY_PCR_CMN_ANA_DWORD30_2P5G }, + {} +}; + +static const struct pmc_serdes_regs pid_modphy1_1g_regs[] = { + { PID_MODPHY1_B_MODPHY_PCR_LCPLL_DWORD0, B_MODPHY_PCR_LCPLL_DWORD0_1G }, + { PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD2, N_MODPHY_PCR_LCPLL_DWORD2_1G }, + { PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD7, N_MODPHY_PCR_LCPLL_DWORD7_1G }, + { PID_MODPHY1_N_MODPHY_PCR_LPPLL_DWORD10, N_MODPHY_PCR_LPPLL_DWORD10_1G }, + { PID_MODPHY1_N_MODPHY_PCR_CMN_ANA_DWORD30, N_MODPHY_PCR_CMN_ANA_DWORD30_1G }, + {} +}; + +static const struct pmc_serdes_regs pid_modphy1_2p5g_regs[] = { + { PID_MODPHY1_B_MODPHY_PCR_LCPLL_DWORD0, B_MODPHY_PCR_LCPLL_DWORD0_2P5G }, + { PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD2, N_MODPHY_PCR_LCPLL_DWORD2_2P5G }, + { PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD7, N_MODPHY_PCR_LCPLL_DWORD7_2P5G }, + { PID_MODPHY1_N_MODPHY_PCR_LPPLL_DWORD10, N_MODPHY_PCR_LPPLL_DWORD10_2P5G }, + { PID_MODPHY1_N_MODPHY_PCR_CMN_ANA_DWORD30, N_MODPHY_PCR_CMN_ANA_DWORD30_2P5G }, + {} +}; +#endif /* CONFIG_INTEL_PMC_IPC */ + #endif /* __DWMAC_INTEL_H__ */ diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index c9878a612e53..dcfa5f423d1c 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -236,6 +236,9 @@ struct plat_stmmacenet_data { int (*serdes_powerup)(struct net_device *ndev, void *priv); void (*serdes_powerdown)(struct net_device *ndev, void *priv); void (*speed_mode_2500)(struct net_device *ndev, void *priv); + int (*config_serdes)(struct net_device *ndev, + void *priv, + phy_interface_t interface); void (*ptp_clk_freq_config)(struct stmmac_priv *priv); int (*init)(struct platform_device *pdev, void *priv); void (*exit)(struct platform_device *pdev, void *priv); From patchwork Tue Feb 4 06:10:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Choong Yong Liang X-Patchwork-Id: 13958668 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 482492036FA; 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X-CSE-ConnectionGUID: LrneNs02TKWkB2l8errDmw== X-CSE-MsgGUID: 9syP7mY3ThGYVAI5jlVIIQ== X-IronPort-AV: E=McAfee;i="6700,10204,11314"; a="50579706" X-IronPort-AV: E=Sophos;i="6.12,310,1728975600"; d="scan'208";a="50579706" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2025 22:11:55 -0800 X-CSE-ConnectionGUID: V4pNTJViR/aO46ZVaN4gXA== X-CSE-MsgGUID: 1qabNu9eTZmZe3YSwJRivQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,258,1732608000"; d="scan'208";a="110279209" Received: from yongliang-ubuntu20-ilbpg12.png.intel.com ([10.88.227.39]) by orviesa009.jf.intel.com with ESMTP; 03 Feb 2025 22:11:47 -0800 From: Choong Yong Liang To: Simon Horman , Jose Abreu , Jose Abreu , David E Box , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H . Peter Anvin" , Rajneesh Bhardwaj , David E Box , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Jiawen Wu , Mengyuan Lou , Heiner Kallweit , Russell King , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Richard Cochran , Andrew Halaney , Serge Semin Cc: x86@kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH net-next v6 5/7] net: stmmac: configure SerDes on mac_finish Date: Tue, 4 Feb 2025 14:10:18 +0800 Message-Id: <20250204061020.1199124-6-yong.liang.choong@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250204061020.1199124-1-yong.liang.choong@linux.intel.com> References: <20250204061020.1199124-1-yong.liang.choong@linux.intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org SerDes will configure according to the provided interface mode after finish a major reconfiguration of the interface mode. Signed-off-by: Choong Yong Liang --- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index d04543e5697b..56efc475e51c 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -1124,6 +1124,18 @@ static int stmmac_mac_enable_tx_lpi(struct phylink_config *config, u32 timer, return 0; } +static int stmmac_mac_finish(struct phylink_config *config, unsigned int mode, + phy_interface_t interface) +{ + struct net_device *ndev = to_net_dev(config->dev); + struct stmmac_priv *priv = netdev_priv(ndev); + + if (priv->plat->config_serdes) + priv->plat->config_serdes(ndev, priv->plat->bsp_priv, interface); + + return 0; +} + static const struct phylink_mac_ops stmmac_phylink_mac_ops = { .mac_get_caps = stmmac_mac_get_caps, .mac_select_pcs = stmmac_mac_select_pcs, @@ -1132,6 +1144,7 @@ static const struct phylink_mac_ops stmmac_phylink_mac_ops = { .mac_link_up = stmmac_mac_link_up, .mac_disable_tx_lpi = stmmac_mac_disable_tx_lpi, .mac_enable_tx_lpi = stmmac_mac_enable_tx_lpi, + .mac_finish = stmmac_mac_finish, }; /** From patchwork Tue Feb 4 06:10:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Choong Yong Liang X-Patchwork-Id: 13958669 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30C941FC118; Tue, 4 Feb 2025 06:12:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738649526; cv=none; b=TGIWVoc4pq6H0DE0rr562hO11Paj/CQPfmOo5Ig1BXSrFI2vG31U7zJbYPQW8D6BCx3hgGOnodGxx15V1JAlyNktGnDnoNEccmgNtrYOfiZ8tUqfYTjinPCzz35nmH24ce0AAMQhi8ZdpR1W17pet7YXvLbiEack0Q+jyk/GaKo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738649526; c=relaxed/simple; bh=82UEmrGcqIRTD9c+4ZQMVIZ2fp+t3hC55QdfOJWinGY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HRbQxifIgoyuPP5YxEMX2DYvr2coFC/ubDuXdkVZ0XLY93XPKci+k375uIaky18/5M8QEsJW8DgdZKW/B2k3a94UHCzAAwk5/xfFMX9Hod5Ms0DOCgkaMK1WsKNdBfWMhE/R1TR6vbsR63ke/w9z6ZTqBH/SJI6JlCeKBzc6w/k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=SYDottw4; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="SYDottw4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738649525; x=1770185525; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=82UEmrGcqIRTD9c+4ZQMVIZ2fp+t3hC55QdfOJWinGY=; b=SYDottw4S+SsHIDYbVEXD24y8RPOJNXZrCZLy6jkBUJ10q0IBAnjtnxY 1SGMrJ3D2wkqnCrdqR7EJ57tlKyfmduGJRBdh46bxQDaHmoE26Y9V3S7f HYNkoeULsE6GWdFVrhHBTUqhSu6V0CV7FVkAHPvI5O2X+vWdZRQUidXMu lI1ZWXW2G7qrVAiXuULX3sCOkKRXrC83GuN7cnSNXZMuP0fJIZsIhGf8b Sg2mTmTU772hj18JvS6xhJwGcaaDUn/FSpG0psGCiojgvvZbqVmHRE8Ki v0tpGTo/KhaU5qlCriIsLATpWe99SCL1FikwIQVYM8sUWua1RDNoKYdOV w==; X-CSE-ConnectionGUID: Z1/10hnzSr6ix+p4A2Oj2w== X-CSE-MsgGUID: 6S3MDnFcSEGTJqX69pT9cA== X-IronPort-AV: E=McAfee;i="6700,10204,11314"; a="50579728" X-IronPort-AV: E=Sophos;i="6.12,310,1728975600"; d="scan'208";a="50579728" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2025 22:12:04 -0800 X-CSE-ConnectionGUID: J0CzH2+rTdKGCS3vuxO4GQ== X-CSE-MsgGUID: 0KWbPcpmSpSgk9rDWTyr/Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,258,1732608000"; d="scan'208";a="110279224" Received: from yongliang-ubuntu20-ilbpg12.png.intel.com ([10.88.227.39]) by orviesa009.jf.intel.com with ESMTP; 03 Feb 2025 22:11:57 -0800 From: Choong Yong Liang To: Simon Horman , Jose Abreu , Jose Abreu , David E Box , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H . Peter Anvin" , Rajneesh Bhardwaj , David E Box , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Jiawen Wu , Mengyuan Lou , Heiner Kallweit , Russell King , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Richard Cochran , Andrew Halaney , Serge Semin Cc: x86@kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH net-next v6 6/7] stmmac: intel: interface switching support for EHL platform Date: Tue, 4 Feb 2025 14:10:19 +0800 Message-Id: <20250204061020.1199124-7-yong.liang.choong@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250204061020.1199124-1-yong.liang.choong@linux.intel.com> References: <20250204061020.1199124-1-yong.liang.choong@linux.intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org The intel_config_serdes function was provided to handle interface mode changes for the ADL-N platform. The Modphy register lane was provided to configure the serdes when changing interface modes. Signed-off-by: Choong Yong Liang --- .../net/ethernet/stmicro/stmmac/dwmac-intel.c | 19 ++++++++++++++++--- .../net/ethernet/stmicro/stmmac/dwmac-intel.h | 4 ++++ 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c index 347dd75bcdcd..de561a00f902 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c @@ -725,6 +725,8 @@ static int intel_mgbe_common_data(struct pci_dev *pdev, static int ehl_common_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { + struct intel_priv_data *intel_priv = plat->bsp_priv; + plat->rx_queues_to_use = 8; plat->tx_queues_to_use = 8; plat->flags |= STMMAC_FLAG_USE_PHY_WOL; @@ -740,19 +742,24 @@ static int ehl_common_data(struct pci_dev *pdev, plat->safety_feat_cfg->prtyen = 0; plat->safety_feat_cfg->tmouten = 0; + intel_priv->tsn_lane_registers = ehl_tsn_lane_registers; + intel_priv->max_tsn_lane_registers = ARRAY_SIZE(ehl_tsn_lane_registers); + return intel_mgbe_common_data(pdev, plat); } static int ehl_sgmii_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { + struct intel_priv_data *intel_priv = plat->bsp_priv; + plat->bus_id = 1; plat->phy_interface = PHY_INTERFACE_MODE_SGMII; - plat->speed_mode_2500 = intel_speed_mode_2500; plat->serdes_powerup = intel_serdes_powerup; plat->serdes_powerdown = intel_serdes_powerdown; plat->config_serdes = intel_config_serdes; plat->clk_ptp_rate = 204800000; + intel_priv->pid_modphy = PID_MODPHY3; return ehl_common_data(pdev, plat); } @@ -806,11 +813,14 @@ static struct stmmac_pci_info ehl_pse0_rgmii1g_info = { static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { + struct intel_priv_data *intel_priv = plat->bsp_priv; + plat->phy_interface = PHY_INTERFACE_MODE_SGMII; - plat->speed_mode_2500 = intel_speed_mode_2500; plat->serdes_powerup = intel_serdes_powerup; plat->serdes_powerdown = intel_serdes_powerdown; plat->config_serdes = intel_config_serdes; + intel_priv->pid_modphy = PID_MODPHY1; + return ehl_pse0_common_data(pdev, plat); } @@ -848,11 +858,14 @@ static struct stmmac_pci_info ehl_pse1_rgmii1g_info = { static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { + struct intel_priv_data *intel_priv = plat->bsp_priv; + plat->phy_interface = PHY_INTERFACE_MODE_SGMII; - plat->speed_mode_2500 = intel_speed_mode_2500; plat->serdes_powerup = intel_serdes_powerup; plat->serdes_powerdown = intel_serdes_powerdown; plat->config_serdes = intel_config_serdes; + intel_priv->pid_modphy = PID_MODPHY1; + return ehl_pse1_common_data(pdev, plat); } diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h index 79c35ba969ea..093eed977ab0 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h @@ -123,6 +123,10 @@ static const struct pmc_serdes_regs pid_modphy1_2p5g_regs[] = { { PID_MODPHY1_N_MODPHY_PCR_CMN_ANA_DWORD30, N_MODPHY_PCR_CMN_ANA_DWORD30_2P5G }, {} }; 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d="scan'208";a="110279244" Received: from yongliang-ubuntu20-ilbpg12.png.intel.com ([10.88.227.39]) by orviesa009.jf.intel.com with ESMTP; 03 Feb 2025 22:12:06 -0800 From: Choong Yong Liang To: Simon Horman , Jose Abreu , Jose Abreu , David E Box , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H . Peter Anvin" , Rajneesh Bhardwaj , David E Box , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Jiawen Wu , Mengyuan Lou , Heiner Kallweit , Russell King , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Richard Cochran , Andrew Halaney , Serge Semin Cc: x86@kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH net-next v6 7/7] stmmac: intel: interface switching support for ADL-N platform Date: Tue, 4 Feb 2025 14:10:20 +0800 Message-Id: <20250204061020.1199124-8-yong.liang.choong@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250204061020.1199124-1-yong.liang.choong@linux.intel.com> References: <20250204061020.1199124-1-yong.liang.choong@linux.intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org The intel_config_serdes function was provided to handle interface mode changes for the ADL-N platform. The Modphy register lane was provided to configure the serdes when changing interface modes. Signed-off-by: Michael Sit Wei Hong Signed-off-by: Choong Yong Liang --- .../net/ethernet/stmicro/stmmac/dwmac-intel.c | 47 ++++++++++++++++++- .../net/ethernet/stmicro/stmmac/dwmac-intel.h | 2 + 2 files changed, 48 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c index de561a00f902..b5180cf303e2 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c @@ -951,6 +951,51 @@ static int adls_sgmii_phy1_data(struct pci_dev *pdev, static struct stmmac_pci_info adls_sgmii1g_phy1_info = { .setup = adls_sgmii_phy1_data, }; + +static int adln_common_data(struct pci_dev *pdev, + struct plat_stmmacenet_data *plat) +{ + struct intel_priv_data *intel_priv = plat->bsp_priv; + + plat->rx_queues_to_use = 6; + plat->tx_queues_to_use = 4; + plat->clk_ptp_rate = 204800000; + + plat->safety_feat_cfg->tsoee = 1; + plat->safety_feat_cfg->mrxpee = 0; + plat->safety_feat_cfg->mestee = 1; + plat->safety_feat_cfg->mrxee = 1; + plat->safety_feat_cfg->mtxee = 1; + plat->safety_feat_cfg->epsi = 0; + plat->safety_feat_cfg->edpp = 0; + plat->safety_feat_cfg->prtyen = 0; + plat->safety_feat_cfg->tmouten = 0; + + intel_priv->tsn_lane_registers = adln_tsn_lane_registers; + intel_priv->max_tsn_lane_registers = ARRAY_SIZE(adln_tsn_lane_registers); + + return intel_mgbe_common_data(pdev, plat); +} + +static int adln_sgmii_phy0_data(struct pci_dev *pdev, + struct plat_stmmacenet_data *plat) +{ + struct intel_priv_data *intel_priv = plat->bsp_priv; + + plat->bus_id = 1; + plat->phy_interface = PHY_INTERFACE_MODE_SGMII; + plat->serdes_powerup = intel_serdes_powerup; + plat->serdes_powerdown = intel_serdes_powerdown; + plat->config_serdes = intel_config_serdes; + intel_priv->pid_modphy = PID_MODPHY1; + + return adln_common_data(pdev, plat); +} + +static struct stmmac_pci_info adln_sgmii1g_phy0_info = { + .setup = adln_sgmii_phy0_data, +}; + static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = { { .func = 6, @@ -1333,7 +1378,7 @@ static const struct pci_device_id intel_eth_pci_id_table[] = { { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1, &tgl_sgmii1g_phy1_info) }, { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0, &adls_sgmii1g_phy0_info) }, { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1, &adls_sgmii1g_phy1_info) }, - { PCI_DEVICE_DATA(INTEL, ADLN_SGMII1G, &tgl_sgmii1g_phy0_info) }, + { PCI_DEVICE_DATA(INTEL, ADLN_SGMII1G, &adln_sgmii1g_phy0_info) }, { PCI_DEVICE_DATA(INTEL, RPLP_SGMII1G, &tgl_sgmii1g_phy0_info) }, {} }; diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h index 093eed977ab0..2c6b50958988 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h @@ -124,8 +124,10 @@ static const struct pmc_serdes_regs pid_modphy1_2p5g_regs[] = { {} }; +static const int adln_tsn_lane_registers[] = {6}; static const int ehl_tsn_lane_registers[] = {7, 8, 9, 10, 11}; #else +static const int adln_tsn_lane_registers[] = {}; static const int ehl_tsn_lane_registers[] = {}; #endif /* CONFIG_INTEL_PMC_IPC */