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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , CC: Amit Cohen , Ido Schimmel , "Petr Machata" , Alexei Starovoitov , "Daniel Borkmann" , Jesper Dangaard Brouer , John Fastabend , , Subject: [PATCH net-next 01/12] mlxsw: core: Remove debug prints Date: Tue, 4 Feb 2025 12:04:56 +0100 Message-ID: <8aa8bc610c5c5e58b4535235300e9afca312950d.1738665783.git.petrm@nvidia.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000F:EE_|IA0PR12MB8864:EE_ X-MS-Office365-Filtering-Correlation-Id: 46b4cabf-776b-413b-9c6d-08dd450bf608 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: 0vUcqejogkStCuulGzzwPqpV8a0eqmYC0fbngfu3YbrjRWryDLr9YD81E22gUDScruhYqTw4AFbmfm32RsTn+BnlHYMdLcd2BGMcbC95J7PtJ+ugLpHbEQdc/CnaqN0KyZOyh9+8VjehAEGY3Ron26ywNuglY1Am2iwsGfMcHLq+STZ2EK0nZZQG7f0jxKx0bbb0AfkO6pIt9LtejBdqUPanHdnfnururvJYRaIcBJRiH0/ffsMC06NAuSGCav5Zw982oSmsJg1JGq+ESVqaiukI8jt9PxlQk+5KQZQHlA2iQdXH6o/PqzAfFD/AcPJfNVPKoSqVWGk4L1RQxhz8FgyYkMGQibKKlRWceOmEtZ3CaO4lyZro8GWphxlOSOTpgPQCrZQe3k2uhFyPt4Vlhu0jaIXA6zRYVODSi4Ig+B7pTV1cdVdDRuXEcjAwBlPAIZeGP9a1WAyedIga3Z4QxyWdXOf5jwH0pF0xv7ANjnctnT9YixE8ooP8yBcFPoQcrze5WT/gDEG27TjBjb/Tr3PAWjqCkCLN0/M9qbBymWlMd1LPygVUFv2L4T+pEzSsb1oyqrRFhn0uzvhv+NFSGuxcOt3mn+WNdJoOCLIoCFEOjCWf3TXZJvNm4PYu4LQlRzAyKttvAj9oDeiLmVuNTTS42eccQzvrRrlckHFeT/DFCbbJSobxpY1BOthn0hzhTF1mUDf/yETtYwqgc1U934VDAxlHfh48LIdbbRjSBbpsTAflwrgN8tOaPbU0onpVYyDFby9Ypj6RyjZIwKj1uFuID/dvJTJm44ArOldMgpfB8pyU3LxjllryQYAmDJEfKOcwpGdDbf3u3KfpI9fBMPzWwqBvet6G3J64xKL/cQK/1/2uequApjIK4TAYjiwhlb/bo008H6HyQnSk3ILoQgX/tt01l2kjdVpLj1SztqWWco0WkEV+htYGiaJX7i8Um8S90f6vAXiMDtcp8hpAL2l7BXb1hD65CPSLbA18dxN0u7o3sBpgHISbnMwcI1avaFYfwvs+8aDCy4Pm/kX2ZT7rEyiRLaJOh3TEuBz13OnQj1/IqRXT5I6Npf3/FwHQdIpRyfDH8m7ZlkQXMNo/aKBfSrT9uitPcU31FHA/0xaFO8t6dTUujtMwD7i21cQz0pSiV5EgbSJwd6lqp/YZyccLSoNCNVp/u8VXCYjvGkMh0zY212dqWaOmVRTOo7JlZaKhOucBRCk9FLk9fYD5hqpKH24gz8o7s9Q4xV3Y26t505TqgA6vKYQVr9gqxMCmURvElPtmvb47yDM9s2Ya4HTzqZ021HrQCaYZOYzgsCwOsi8gEJBA3xVSLVIDB4xWGxELsmck0euxJ76F6F7ywH6C5hQU4DqE5ZwdsHyBgkxrj73JPjDzu9kfcKuaqrsC0EgBc25xqaDmqGFsGe3wiM8z7cZzHK4RNOe56mQAE+A0i+BrjKjxJOL9CvDgo9vJsC5/h5h1ryD+TTCCV5fJ6lsEaxPAWETk69kqHWvFuaQ= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2025 11:06:22.9944 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 46b4cabf-776b-413b-9c6d-08dd450bf608 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8864 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen dev_dbg_ratelimited() is used as part of mlxsw_core_skb_receive(), the printed info can be achieved using simple tracing. Remove such calls to clean up the code. A next patch will change 'rx_info' fields, without these prints, some fields will become unnecessary and can be removed. Signed-off-by: Amit Cohen Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/core.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.c b/drivers/net/ethernet/mellanox/mlxsw/core.c index 2bb2b77351bd..8becb08984a6 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/core.c +++ b/drivers/net/ethernet/mellanox/mlxsw/core.c @@ -2948,9 +2948,6 @@ void mlxsw_core_skb_receive(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, bool found = false; if (rx_info->is_lag) { - dev_dbg_ratelimited(mlxsw_core->bus_info->dev, "%s: lag_id = %d, lag_port_index = 0x%x\n", - __func__, rx_info->u.lag_id, - rx_info->trap_id); /* Upper layer does not care if the skb came from LAG or not, * so just get the local_port for the lag port and push it up. */ @@ -2961,9 +2958,6 @@ void mlxsw_core_skb_receive(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, local_port = rx_info->u.sys_port; } - dev_dbg_ratelimited(mlxsw_core->bus_info->dev, "%s: local_port = %d, trap_id = 0x%x\n", - __func__, local_port, rx_info->trap_id); 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , CC: Amit Cohen , Ido Schimmel , "Petr Machata" , Alexei Starovoitov , "Daniel Borkmann" , Jesper Dangaard Brouer , John Fastabend , , Subject: [PATCH net-next 02/12] mlxsw: Check Rx local port in PCI code Date: Tue, 4 Feb 2025 12:04:57 +0100 Message-ID: <1178743340cfb52bb763d5c671d4c9bf320534f8.1738665783.git.petrm@nvidia.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397AF:EE_|CYXPR12MB9318:EE_ X-MS-Office365-Filtering-Correlation-Id: 33eb6693-5ad3-46e3-b8fe-08dd450bf928 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: hB8o8Gq2H+1Ap0ZcLW+dsk78OeDbbE1AL9sudLMAom5m+AhSXCheIKFC2RhK6Q1Ji1aEHsqLAB2HH2AdJKE/dZpzHpeK9izMyLYj61eN9+NlYBoJ1FiccYCApjFeRwgPBC6+P7LSRMALHOcM2/eFkTizkVyw03xQpH2pQL7DpUW4/aUk7GA4ConkIRzs7thzknq5F4hfIt6fiITUHSjaEllKA3wmBEwG1r7BM22gvaFGI8oXLe0UQgQnI50ltza5kWcnRq2Qe0kOe2S4eIyAISsoWAyZtsGoblEyo6WL1zdLlujxjF/wE5xJrIJIJ0ToV4hg1aFhnTMFcheOHkhhav1t8bLndnq2DZD5Ri69tUjlw8YaTNxTG/AQxEUFMVRIQx6o/z9j+uZvkwfiqpDho9GswxvUh5y8kQA+eZnoF92UmMFAKQoQJGnEYAK87Qt+8DMIB/wwtJQVsEFfXJ9Ku7IR4e96EiJ0IxkBTSPxvQ1xu1pUM61EkiLfIk4WOhjgivvltzdeNX3w7M3JH80cWOqY8GKM35j8SCDcUfThK0A2fvcjS/75dhBtEBTp39PLhWhHE+2286BDXGHnxO1KdMCHP1J3eoG96BGQ4LK0ccBFZ20uuBZisVWvacZVSfnmWM2oCz5/DcWx6ssiHr0puCTTTLcLEZxoT2pVqDgIElv/rBil9lwV6dYle2Q0nE+dsX1KC5Qec1tz5M6yAr+nm5GzJ0twGxW0cHLhsaEDyF786ex3/n8gdvo6MZgqS9QrUySLUchUpxzQVxzz+9eIKWBQ979rYKnOn4h/BwvtRdi38Y2kQ8uYqpbLEWQuCQY8D5nDjDMDcAgIs2qXGLZ4qCSQc4F30sH5cOIh9ARa5/S6Txkr8nPBrPyqiJdTfEudZEWiLKjit8bfhyy7WdHujS7P86egR8Gnvam5S8gkfj0BscJuRSkNzhn7N34sv3pdz4EEQYUseiKlYDoNOMdUcq/VQAUkAJi6KuAWSJUxl9aTT3TiZy/H0+i2UW2g+hV+yZNC2Kvz+W7FecU7F3h5wk+4Ng6c5bAGYX2gsFgdAbXDTjZJFOIAxHFgmAyws3PgpyP8OS8LAg8wwfYkE9j+qMmUWvc4lOrYiKxuSnZArW22/wJ/vprTvrTs7gnISxufd9UJvDeCryfET+YS+NE5W1c2+wX9auRmc7HX9wxAHGgPudBd9WjzyjxaSa/xkUjk97YuPm1RJmEhbaUkxcLSM4fdXONMBPrkfM5GzLYiugpI6t5mY548JTXNsEvYkBe1Zpgf2LOIkPCQCi6gmPfd0uFRLQV9CfVvU0t60op3rAsRY2o7W6I0AEyi3sjiQGRFBdLioWdpm2GkBOeu+R+TmJGQ1wFv0Gq1qUwNL8xlUAR3dyqWql2GgZcZ0LPyKCk/wkwgyakbbJjsEPEokYn2RyGcCfQgXXNDTgTttebwkfq/YFsBicI5vF4gm2suM+fYftQ5s3ZI2aAvqbi7Lb5G1BAKyuNEvvdubjLnP9grZ7E= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2025 11:06:28.2224 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 33eb6693-5ad3-46e3-b8fe-08dd450bf928 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397AF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9318 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen In case that a packet is received from port in a LAG, the CQE contains info about the LAG and later, core code checks which local port is the Rx port. To support XDP, such checking should be done also as part of PCI code, to get the relevant XDP program according to Rx netdevice. There is no point to check the mapping twice, as preparation for XDP support, check which is the Rx local port as part of PCI code and fill this info in 'rx_info'. Remove the unnecessary fields from 'rx_info'. Handle 'rx_info.local_port' earlier in the code, as this info will be used for XDP running, XDP will be handled in the code after handling local port. Signed-off-by: Amit Cohen Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/core.c | 18 +++--------------- drivers/net/ethernet/mellanox/mlxsw/core.h | 7 +------ drivers/net/ethernet/mellanox/mlxsw/pci.c | 22 ++++++++++++---------- 3 files changed, 16 insertions(+), 31 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.c b/drivers/net/ethernet/mellanox/mlxsw/core.c index 8becb08984a6..392c0355d589 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/core.c +++ b/drivers/net/ethernet/mellanox/mlxsw/core.c @@ -2944,29 +2944,17 @@ void mlxsw_core_skb_receive(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, { struct mlxsw_rx_listener_item *rxl_item; const struct mlxsw_rx_listener *rxl; - u16 local_port; bool found = false; - if (rx_info->is_lag) { - /* Upper layer does not care if the skb came from LAG or not, - * so just get the local_port for the lag port and push it up. - */ - local_port = mlxsw_core_lag_mapping_get(mlxsw_core, - rx_info->u.lag_id, - rx_info->lag_port_index); - } else { - local_port = rx_info->u.sys_port; - } - if ((rx_info->trap_id >= MLXSW_TRAP_ID_MAX) || - (local_port >= mlxsw_core->max_ports)) + (rx_info->local_port >= mlxsw_core->max_ports)) goto drop; rcu_read_lock(); list_for_each_entry_rcu(rxl_item, &mlxsw_core->rx_listener_list, list) { rxl = &rxl_item->rxl; if ((rxl->local_port == MLXSW_PORT_DONT_CARE || - rxl->local_port == local_port) && + rxl->local_port == rx_info->local_port) && rxl->trap_id == rx_info->trap_id && rxl->mirror_reason == rx_info->mirror_reason) { if (rxl_item->enabled) @@ -2979,7 +2967,7 @@ void mlxsw_core_skb_receive(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, goto drop; } - rxl->func(skb, local_port, rxl_item->priv); + rxl->func(skb, rx_info->local_port, rxl_item->priv); rcu_read_unlock(); return; diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.h b/drivers/net/ethernet/mellanox/mlxsw/core.h index 1a871397a6df..72eb7dbf57ce 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/core.h +++ b/drivers/net/ethernet/mellanox/mlxsw/core.h @@ -242,12 +242,7 @@ int mlxsw_reg_write(struct mlxsw_core *mlxsw_core, const struct mlxsw_reg_info *reg, char *payload); struct mlxsw_rx_info { - bool is_lag; - union { - u16 sys_port; - u16 lag_id; - } u; - u16 lag_port_index; + u16 local_port; u8 mirror_reason; int trap_id; }; diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 5b44c931b660..55ef185c9f5a 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -761,6 +761,18 @@ static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, if (mlxsw_pci_cqe_crc_get(cqe_v, cqe)) byte_count -= ETH_FCS_LEN; + if (mlxsw_pci_cqe_lag_get(cqe_v, cqe)) { + u16 lag_id, lag_port_index; + + lag_id = mlxsw_pci_cqe_lag_id_get(cqe_v, cqe); + lag_port_index = mlxsw_pci_cqe_lag_subport_get(cqe_v, cqe); + rx_info.local_port = mlxsw_core_lag_mapping_get(mlxsw_pci->core, + lag_id, + lag_port_index); + } else { + rx_info.local_port = mlxsw_pci_cqe_system_port_get(cqe); + } + err = mlxsw_pci_elem_info_pages_ref_store(q, elem_info, byte_count, pages, &num_sg_entries); if (err) @@ -779,16 +791,6 @@ static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, skb_mark_for_recycle(skb); - if (mlxsw_pci_cqe_lag_get(cqe_v, cqe)) { - rx_info.is_lag = true; - rx_info.u.lag_id = mlxsw_pci_cqe_lag_id_get(cqe_v, cqe); - rx_info.lag_port_index = - mlxsw_pci_cqe_lag_subport_get(cqe_v, cqe); - } else { - rx_info.is_lag = false; - rx_info.u.sys_port = mlxsw_pci_cqe_system_port_get(cqe); - } - rx_info.trap_id = mlxsw_pci_cqe_trap_id_get(cqe); if (rx_info.trap_id == MLXSW_TRAP_ID_DISCARD_INGRESS_ACL || From patchwork Tue Feb 4 11:04:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Machata X-Patchwork-Id: 13958896 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2048.outbound.protection.outlook.com [40.107.223.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F68B16B3A1; Tue, 4 Feb 2025 11:06:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , CC: Amit Cohen , Ido Schimmel , "Petr Machata" , Alexei Starovoitov , "Daniel Borkmann" , Jesper Dangaard Brouer , John Fastabend , , Subject: [PATCH net-next 03/12] mlxsw: Add struct mlxsw_pci_rx_pkt_info Date: Tue, 4 Feb 2025 12:04:58 +0100 Message-ID: <67e4b6dbb35d1e977b56e1a40e8227704ba353a3.1738665783.git.petrm@nvidia.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B0:EE_|MN0PR12MB5906:EE_ X-MS-Office365-Filtering-Correlation-Id: 00016004-5e78-439e-90de-08dd450bfbdb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: KcOWS+dmy5ibopCPr5YKbQQc3EY+ofw8cml3ctw/RQBZGGHOsrgOKWZid8Uv/XBvQVSvU4UJFLYaDO5611Q1/Mzykg5nJ59OQJBuG+yoQpuQlcswAPHp9qUwZvfc8pFqI0HiLC0jnzMfF2XVhoOCdq5KC/QhEPyaalsHPpzXUlOlTTLPsH84TpTlICbeDKaEcWeGQZOrYnS1ejYoPqFWrN2lYuFCm7IXlmijvt6gh46zZ4EqH1eRNPchOyAQ79pfhqZwGeAYNRaD01L6Lqed/u/lxnwMqlkDY0sba9JNygN29v2MqBXIT51SGLIIfQjfK/bxCgQSVi+11dARIjCx4HKUSzlBscvYEYMFxcp+Xryl1p9+Mny/ytdkpit3IZB5Qwk61uo+fWUQPA7+gN3OOSGyqptLDJDxVJGEJjLFKxG2w1nq5Y5zrKF+ukggHW0Vz20Ayi9GLp7OQ3NphexlGiO9kGjUkkUynTz2qBwrv9p0gzecR4VtwCFM83cZP9/2cJOccAdjtjew0k1/a4xg31aDC0mpraxJ5T9ZCeHtHEDCwyHZPXm5Y5r9wYpMfLXDjtjXYzdoap6JC8f/c1JVDki7HDt/yX1iABRaetdqg528/hpJ/JboVm9qQglLOeHtq2ZGF1XY527cDdQ6pgqU2GIC/GujI4oqK1c+z2rcH/kOMIn5XOOnKeWvW4UAppjpnY2ewOnclsIySERbwpNPo706BXHn0pAw4kYI6VUBskgozfckHiSnVOLpic/SGmgnSYp7X27lsG0M6JzOrn0q+4Nt1/6cyvDU6ZVd4nDcjtPkOfiD00Kmo7UjAEaIqUniOvtItO2i+UaEWbash09YeSbIe1zLn7JZzBS7d58DxfaNRdRGQ29V2gD6tr7/LXwPrMJ9Qh6zEAPlnYYwx7G1KvOWG1B1DN4ujPWZoc8LK4GADPifcuhztr7J9xCFGm/A65S3bvItgRd92dR6z7YF09q2kDLASVTmP4wWvusdtxCPi6bqqbAw5QTw5xA/4SsoJpbb+BNA+/y1TGRTkRTj6F6/tRkN4KmHtj2HZlKq0EXQziAfs5KYBOc7yiaYg5xX8TWJ5o8vBLLNNH9qW1UEgHSxDpS8MfNJxYHd1sCsbbOG/zoFHYYDf89vOuSzA7GjcY9xE1BPeXzWj9F24aZ8Vl0JIOmviWkTRCXGXFTadqIwOwMRKIxbG/O5RKmZ9oHA0awDN+mOCWP9zwc3SaRFJqE6KzWPKcRHvoSRsW5fre5acT9AA7Oaqh7WE92Ityd7yZZnUueKS7Ech2j+jgsoVBfYb5JbxwyGRaFpG/6zGl3M0fJ8LETQw9q2UDKXeUDTRGqFC71/5SG6tIa3JeCjnMpp8rNosFVBEiFp9Se4BrrgiYU93giMoo5z0Ot0WW+BBYkhrb1F03RLSpuE5GdI6aMR6/n/Sw7esYgNg+yHuIqbxn8zUQsizlbJiED9mw8wSBnCuDJkbSUg5Bd5cNllbufkYAssaqwlhYDdaBKoriY= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(82310400026)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2025 11:06:32.7655 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 00016004-5e78-439e-90de-08dd450bfbdb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5906 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen When Rx packet is received, given byte_count value from the CQE, we calculate how many scatter/gather entries are used and the size of each entry. Such calculation is used for syncing the buffers for CPU and for building SKB. When XDP will be supported, these values will be used also to create XDP buffer. To avoid recalculating number of scatter/gather entries and size of each entry, add a dedicated structure to hold such info. Store also pointers to pages. Initialize the new structure once Rx packet is received. This patch only initializes the structure, next patches will use it. Add struct mlxsw_pci_rx_pkt_info in pci.h as next patch in this set will use it from another file. Signed-off-by: Amit Cohen Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 57 +++++++++++++++++--- drivers/net/ethernet/mellanox/mlxsw/pci.h | 8 +++ drivers/net/ethernet/mellanox/mlxsw/pci_hw.h | 1 - 3 files changed, 57 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 55ef185c9f5a..aca1857a4e70 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -390,6 +390,49 @@ static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe, dma_unmap_single(&pdev->dev, mapaddr, frag_len, direction); } +static u8 mlxsw_pci_num_sg_entries_get(u16 byte_count) +{ + return DIV_ROUND_UP(byte_count + MLXSW_PCI_RX_BUF_SW_OVERHEAD, + PAGE_SIZE); +} + +static int +mlxsw_pci_rx_pkt_info_init(const struct mlxsw_pci *pci, + const struct mlxsw_pci_queue_elem_info *elem_info, + u16 byte_count, + struct mlxsw_pci_rx_pkt_info *rx_pkt_info) +{ + unsigned int linear_data_size; + u8 num_sg_entries; + bool linear_only; + int i; + + num_sg_entries = mlxsw_pci_num_sg_entries_get(byte_count); + if (WARN_ON_ONCE(num_sg_entries > pci->num_sg_entries)) + return -EINVAL; + + rx_pkt_info->num_sg_entries = num_sg_entries; + + linear_only = byte_count + MLXSW_PCI_RX_BUF_SW_OVERHEAD <= PAGE_SIZE; + linear_data_size = linear_only ? byte_count : + PAGE_SIZE - + MLXSW_PCI_RX_BUF_SW_OVERHEAD; + + for (i = 0; i < num_sg_entries; i++) { + unsigned int sg_entry_size; + + sg_entry_size = i ? min(byte_count, PAGE_SIZE) : + linear_data_size; + + rx_pkt_info->sg_entries_size[i] = sg_entry_size; + rx_pkt_info->pages[i] = elem_info->pages[i]; + + byte_count -= sg_entry_size; + } + + return 0; +} + static struct sk_buff *mlxsw_pci_rdq_build_skb(struct mlxsw_pci_queue *q, struct page *pages[], u16 byte_count) @@ -470,12 +513,6 @@ static void mlxsw_pci_rdq_page_free(struct mlxsw_pci_queue *q, false); } -static u8 mlxsw_pci_num_sg_entries_get(u16 byte_count) -{ - return DIV_ROUND_UP(byte_count + MLXSW_PCI_RX_BUF_SW_OVERHEAD, - PAGE_SIZE); -} - static int mlxsw_pci_elem_info_pages_ref_store(const struct mlxsw_pci_queue *q, const struct mlxsw_pci_queue_elem_info *el, @@ -486,8 +523,6 @@ mlxsw_pci_elem_info_pages_ref_store(const struct mlxsw_pci_queue *q, int i; num_sg_entries = mlxsw_pci_num_sg_entries_get(byte_count); - if (WARN_ON_ONCE(num_sg_entries > q->pci->num_sg_entries)) - return -EINVAL; for (i = 0; i < num_sg_entries; i++) pages[i] = el->pages[i]; @@ -743,6 +778,7 @@ static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, u16 consumer_counter_limit, enum mlxsw_pci_cqe_v cqe_v, char *cqe) { + struct mlxsw_pci_rx_pkt_info rx_pkt_info = {}; struct pci_dev *pdev = mlxsw_pci->pdev; struct page *pages[MLXSW_PCI_WQE_SG_ENTRIES]; struct mlxsw_pci_queue_elem_info *elem_info; @@ -773,6 +809,11 @@ static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, rx_info.local_port = mlxsw_pci_cqe_system_port_get(cqe); } + err = mlxsw_pci_rx_pkt_info_init(q->pci, elem_info, byte_count, + &rx_pkt_info); + if (err) + goto out; + err = mlxsw_pci_elem_info_pages_ref_store(q, elem_info, byte_count, pages, &num_sg_entries); if (err) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.h b/drivers/net/ethernet/mellanox/mlxsw/pci.h index cacc2f9fa1d4..74677feacbb5 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.h +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.h @@ -11,11 +11,19 @@ #define PCI_DEVICE_ID_MELLANOX_SPECTRUM3 0xcf70 #define PCI_DEVICE_ID_MELLANOX_SPECTRUM4 0xcf80 +#define MLXSW_PCI_WQE_SG_ENTRIES 3 + #if IS_ENABLED(CONFIG_MLXSW_PCI) int mlxsw_pci_driver_register(struct pci_driver *pci_driver); void mlxsw_pci_driver_unregister(struct pci_driver *pci_driver); +struct mlxsw_pci_rx_pkt_info { + struct page *pages[MLXSW_PCI_WQE_SG_ENTRIES]; + unsigned int sg_entries_size[MLXSW_PCI_WQE_SG_ENTRIES]; + u8 num_sg_entries; +}; + #else static inline int diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h b/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h index 6bed495dcf0f..83d25f926287 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h +++ b/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h @@ -64,7 +64,6 @@ #define MLXSW_PCI_EQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_EQE_SIZE) #define MLXSW_PCI_EQE_UPDATE_COUNT 0x80 -#define MLXSW_PCI_WQE_SG_ENTRIES 3 #define MLXSW_PCI_WQE_TYPE_ETHERNET 0xA /* pci_wqe_c From patchwork Tue Feb 4 11:04:59 2025 Content-Type: text/plain; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , CC: Amit Cohen , Ido Schimmel , "Petr Machata" , Alexei Starovoitov , "Daniel Borkmann" , Jesper Dangaard Brouer , John Fastabend , , Subject: [PATCH net-next 04/12] mlxsw: pci: Use mlxsw_pci_rx_pkt_info Date: Tue, 4 Feb 2025 12:04:59 +0100 Message-ID: X-Mailer: git-send-email 2.48.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B1:EE_|SJ1PR12MB6362:EE_ X-MS-Office365-Filtering-Correlation-Id: 274f7aad-6e74-4e2d-e911-08dd450c0353 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: vNDTUlu1V0afwLnxOnwasYGz353b3E/18JpwRKbCyoW6rGSTbvcYeh7s4FyQYD4c0B8Jde+PEdQGZbO9MvIgKBaWEzy8g6ZBZfW4KluhWVmIXpWDDisbBFlxg1FUchz7zwU9m0qJLgTAgPhwyc0pmRnwH/ZtotKs3C53jzqcmLapJsMZepiym8KaD9c1hutoyelT2HRyp4pGjA4xWuObp2KTW1npm6J0uzoFITnKyvC4Z9DEUuaZRGpNXyONqU+D3gEQDhfxWiWSEk19Gx1pXybuSXAbHO4WCm0Vqne+ru69N8ReOT0/5++JacMRN0EN7qjxxh+JX73uvpgZHtEBz1vwNqf8wIuKHco1XRG6lL+h1OM79/oK2gpXYWEz6tP42QHIsVLhPs+bsBFP8uW5WfCMT2Cm++l+Kee7NEhKNvwEwCjm7SE6KlnFnEoW+v/eXVztlc5k0m97fNDjLrv7+5q6ZsEr25wDGsa74US+yXguzm1N1mlL6TxisVxRzLi75fQZ5YlY9gJeQg4qRrGhycN/FcGtYMofrGxp1Va8AIwkQ331UwMIq/Nc/C4FWrSC88LHkZ5IcJjyOjhhP/e6wIkmOkCWAKHRWK62x/wzKT6h2Yk4dd6WLNRrC1GBP6BbO2uOWBraQjJKOFBiqcp8XED4VpFt+DdxeMRBsh1T2y4MxKUE7OOnsyRH8PnPGwygw7UorVNMT6pW7labQXiUZOTUiPZHWDykadc3ALDKtINFCJ7IArDsmHRepvsWF2V595gjsBnmlDOcqSgyvbdzafE548OKFc6OA4urb/NKo/fUD5RZ1yENC9SXS0vwQ0LulUUhO8ZhGkchmzHuLQ+2TzgZfJoJ8Wtzf1iFV0hERpI8uFa0ljsqiFeR0TPP1Nc894gv6gTaX5p4g2V4cJkvsJSc6bmmFYdO8AKuVhHBDfjAKcgCDz3yrOGsULdM3Za+7LIqHdGPuzFA0ryXZGyMYszKcsjEDO/cKIx7n117SX5gKGII+Ff+/oLc5wTvOO09b51+WrxLoA4MG8OIEy7ftqwWKOEbd+DFMjkBLjU70CmNPaOK//R0AhjKi1l6HPFA+OR+hPKO2a+b+2aPNQ+ves2QOr7CBxZCPtnmsGhLGLLUrEh12jHujQDmaQh+CZ0uFhOej64/pApGx5S9nznq16qSElZgtdKfNdKScUJj/ZvjpbwtPgIwbOKkxHR3b+rBbALfUoRpPGTfXM1bUZ6G0TplrQkcDORbzHHQRzeOnZ1oAEMejPYboXHRWXZCG6iynYfxmzJ3hgcR6G0YHCtJc+Jw1FTG0FZ5gMnS5tWerD0tIYbz27Qax30JCm5ur1AECCao+ZONoOY0Q3xens+vKmeqpzgsXVNqOnEC0dSAS2dIXe84MIylITukxtw9qZCV070HOcz2U9SPlGo9mW7EK1c9MMHgGELKVqBxPdbrbobNAQ+MAOC/q4Oi4ug89/ZWXv73Abcle2YjlK3b0zsDnHASn5170C4gcnlT1O9ypTA= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2025 11:06:45.2827 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 274f7aad-6e74-4e2d-e911-08dd450c0353 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6362 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen Pass the newly added structure as an argument for mlxsw_pci_rdq_build_skb() and use it. Remove mlxsw_pci_elem_info_pages_ref_store(), as mlxsw_pci_rx_pkt_info stores pointers to pages. Pass to mlxsw_pci_rdq_pages_alloc() number of scatter/gather entries which is stored in mlxsw_pci_rx_pkt_info. Signed-off-by: Amit Cohen Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 65 ++++++----------------- 1 file changed, 16 insertions(+), 49 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index aca1857a4e70..374b3f2f117d 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -433,28 +433,23 @@ mlxsw_pci_rx_pkt_info_init(const struct mlxsw_pci *pci, return 0; } -static struct sk_buff *mlxsw_pci_rdq_build_skb(struct mlxsw_pci_queue *q, - struct page *pages[], - u16 byte_count) +static struct sk_buff * +mlxsw_pci_rdq_build_skb(struct mlxsw_pci_queue *q, + const struct mlxsw_pci_rx_pkt_info *rx_pkt_info) { struct mlxsw_pci_queue *cq = q->u.rdq.cq; unsigned int linear_data_size; struct page_pool *page_pool; struct sk_buff *skb; - int page_index = 0; - bool linear_only; void *data; + int i; - linear_only = byte_count + MLXSW_PCI_RX_BUF_SW_OVERHEAD <= PAGE_SIZE; - linear_data_size = linear_only ? byte_count : - PAGE_SIZE - - MLXSW_PCI_RX_BUF_SW_OVERHEAD; - + linear_data_size = rx_pkt_info->sg_entries_size[0]; page_pool = cq->u.cq.page_pool; - page_pool_dma_sync_for_cpu(page_pool, pages[page_index], + page_pool_dma_sync_for_cpu(page_pool, rx_pkt_info->pages[0], MLXSW_PCI_SKB_HEADROOM, linear_data_size); - data = page_address(pages[page_index]); + data = page_address(rx_pkt_info->pages[0]); net_prefetch(data); skb = napi_build_skb(data, PAGE_SIZE); @@ -464,23 +459,18 @@ static struct sk_buff *mlxsw_pci_rdq_build_skb(struct mlxsw_pci_queue *q, skb_reserve(skb, MLXSW_PCI_SKB_HEADROOM); skb_put(skb, linear_data_size); - if (linear_only) + if (rx_pkt_info->num_sg_entries == 1) return skb; - byte_count -= linear_data_size; - page_index++; - - while (byte_count > 0) { + for (i = 1; i < rx_pkt_info->num_sg_entries; i++) { unsigned int frag_size; struct page *page; - page = pages[page_index]; - frag_size = min(byte_count, PAGE_SIZE); + page = rx_pkt_info->pages[i]; + frag_size = rx_pkt_info->sg_entries_size[i]; page_pool_dma_sync_for_cpu(page_pool, page, 0, frag_size); skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 0, frag_size, PAGE_SIZE); - byte_count -= frag_size; - page_index++; } return skb; @@ -513,24 +503,6 @@ static void mlxsw_pci_rdq_page_free(struct mlxsw_pci_queue *q, false); } -static int -mlxsw_pci_elem_info_pages_ref_store(const struct mlxsw_pci_queue *q, - const struct mlxsw_pci_queue_elem_info *el, - u16 byte_count, struct page *pages[], - u8 *p_num_sg_entries) -{ - u8 num_sg_entries; - int i; - - num_sg_entries = mlxsw_pci_num_sg_entries_get(byte_count); - - for (i = 0; i < num_sg_entries; i++) - pages[i] = el->pages[i]; - - *p_num_sg_entries = num_sg_entries; - return 0; -} - static int mlxsw_pci_rdq_pages_alloc(struct mlxsw_pci_queue *q, struct mlxsw_pci_queue_elem_info *elem_info, @@ -780,11 +752,9 @@ static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, { struct mlxsw_pci_rx_pkt_info rx_pkt_info = {}; struct pci_dev *pdev = mlxsw_pci->pdev; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , CC: Amit Cohen , Ido Schimmel , "Petr Machata" , Alexei Starovoitov , "Daniel Borkmann" , Jesper Dangaard Brouer , John Fastabend , , Subject: [PATCH net-next 05/12] mlxsw: pci: Add a separate function for syncing buffers for CPU Date: Tue, 4 Feb 2025 12:05:00 +0100 Message-ID: <7674318d47d36fb91a64351ca64a491ec61d5284.1738665783.git.petrm@nvidia.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B3:EE_|SA1PR12MB7344:EE_ X-MS-Office365-Filtering-Correlation-Id: 3bc2ce18-b815-4690-6095-08dd450c0807 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: 2TK/K3P5epWp/BWapbqR8ZtEtKK24A3CbPKHxeD30Z+BReRtQK5Q50Zy1+YaicOuNTdiwiwmsQPFSemSLFqW0EvjWvQx4PNYG8lyyDxiteyOxe3aVeOTbaOn6eHbqzawiVUNKm2Eg4MnIwttzy4yKs1X705Lf+e76F48ho0gicF0BWllmXNRcf+wO7Vxu9SQJoPF+IwrcQbrQ6evayiosU73TO72aD3sUZeXGNHxotSibHh+PdkEsEqZoOrnJAFFKWokAMvPNPy7ElvunlivGkzep7aP8pDxeW2NXKpqy9uOcvZcpbqhNcVMat3a5CCWaSGIj5q3cKIGqehan+PO8qUIWUpI1q4YvgwNkgd8Ibf42phJUEsv7k5EgvzrD68Tat9fnS/QHFnMjxBA5nWXkAAYh5gj9EJAylg2LlyJtVOaPHAEXLP+EcQuttaza8g7LvBvJnwQEGYEYVSHzqEZfsHmU/Arb1NsWlKsI0MF02jWugHtnBvVCJ1o1J4l5a8zbs4U3SQhqJusotakXbrfFq4xjjsgxJer5g4gD1ZfTuGYKMZLrvO3uviX7qFbcB/6OInAgSrD6oT1kwmORMOXf8pSV1wNeJyECNcKlwT6frzsiowc9VoldCsoOET7yfQ8pROkQ3Y3wl9O9QKi+pSbniV5d/VYmXnFtQ+HMcFdvgTFnv7zG3ErVZHV6JdHJNcDhZqWKyR2LyJPb12szLo5Gr2buGulKeO+Alplb1seuNNe6wg9HGLcTtvt6ByodXkrKDOjr986tucslwX5359pwRQvv2lYEfX/DPBZcjG+B7jhh6mFbeycFNrXgM9kpS6p/9GHAFZFQOVO8eN08zLaQGshVmz6nfrvYbB7V7YuElL675eFBCTQn/cmKnq7gPYtFhVTfd7nHFfxemyyR0OSZ3NecpLkRV5Vo0fFtPjBzxUVZJnmLtv4zKaDp5zrEFtDLwYVyACXtuVExRCtE6U1ObDs4sa/jn4B9w/oS3T1duR4m8PxH8L3W3HNpOsYbbLic51jFhWTa9myMxcBa64IAx4F9Y21mjt8i0rX4MCDfwIz7cGj6uxn7IB9zxrZcKxgGRmIXrbpjTwaIBT560+rBNFaOmcvflZoZ4698LQ3wTBLI0orV4DxhrJClaIoxiPCNw9bL7u/OemctLWn6lzaSRCJqFRzjNZnRZzlonxKac4eShZUrAw4V5G/Zacp4RIoyTFV3J86mPXh8pT7axHXsaSUvSyDOFFi1/J6lw+k7arfr2z3TLhUYefAFBlFrFFD+lYx9ZYwFEyy4dvtOCh8h5r31PhFjPc8t6XPDgOz1HtNPPH4U31i5LN0jVPJJUBxunK5UoTOt0Ty4V6ZeMhcBBZsOguya5fI85wfiV8jywaqkvQc4/QXxmfWxgP9NbLRids0cryzoiNNT4/JrCVTygY6wtC9gEHUtmACoW4PjDWqev4jQaFqH8Qt8Oec0I9vXSTHmApc5pCykdI0uUPfnNSEJiBfA30NEY31l0T2Qqo= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2025 11:06:53.1541 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3bc2ce18-b815-4690-6095-08dd450c0807 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7344 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen Currently, sync for CPU is done as part of building SKB. When XDP will be supported, such sync should be done earlier, before creating XDP buffer. Add a function for syncing buffers for CPU and call it early in mlxsw_pci_cqe_rdq_handle(), as in future patch, the driver will handle XDP there. Signed-off-by: Amit Cohen Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 30 +++++++++++++++++------ 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 374b3f2f117d..5796d836a7ee 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -433,22 +433,34 @@ mlxsw_pci_rx_pkt_info_init(const struct mlxsw_pci *pci, return 0; } +static void +mlxsw_pci_sync_for_cpu(const struct mlxsw_pci_queue *q, + const struct mlxsw_pci_rx_pkt_info *rx_pkt_info) +{ + struct mlxsw_pci_queue *cq = q->u.rdq.cq; + struct page_pool *page_pool; + int i; + + page_pool = cq->u.cq.page_pool; + + for (i = 0; i < rx_pkt_info->num_sg_entries; i++) { + u32 offset = i ? 0 : MLXSW_PCI_SKB_HEADROOM; + + page_pool_dma_sync_for_cpu(page_pool, rx_pkt_info->pages[i], + offset, + rx_pkt_info->sg_entries_size[i]); + } +} + static struct sk_buff * mlxsw_pci_rdq_build_skb(struct mlxsw_pci_queue *q, const struct mlxsw_pci_rx_pkt_info *rx_pkt_info) { - struct mlxsw_pci_queue *cq = q->u.rdq.cq; unsigned int linear_data_size; - struct page_pool *page_pool; struct sk_buff *skb; void *data; int i; - linear_data_size = rx_pkt_info->sg_entries_size[0]; - page_pool = cq->u.cq.page_pool; - page_pool_dma_sync_for_cpu(page_pool, rx_pkt_info->pages[0], - MLXSW_PCI_SKB_HEADROOM, linear_data_size); - data = page_address(rx_pkt_info->pages[0]); net_prefetch(data); @@ -457,6 +469,7 @@ mlxsw_pci_rdq_build_skb(struct mlxsw_pci_queue *q, return ERR_PTR(-ENOMEM); skb_reserve(skb, MLXSW_PCI_SKB_HEADROOM); + linear_data_size = rx_pkt_info->sg_entries_size[0]; skb_put(skb, linear_data_size); if (rx_pkt_info->num_sg_entries == 1) @@ -468,7 +481,6 @@ mlxsw_pci_rdq_build_skb(struct mlxsw_pci_queue *q, page = rx_pkt_info->pages[i]; frag_size = rx_pkt_info->sg_entries_size[i]; - page_pool_dma_sync_for_cpu(page_pool, page, 0, frag_size); skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 0, frag_size, PAGE_SIZE); } @@ -784,6 +796,8 @@ static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, if (err) goto out; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , CC: Amit Cohen , Ido Schimmel , "Petr Machata" , Alexei Starovoitov , "Daniel Borkmann" , Jesper Dangaard Brouer , John Fastabend , , Subject: [PATCH net-next 06/12] mlxsw: pci: Store maximum number of ports Date: Tue, 4 Feb 2025 12:05:01 +0100 Message-ID: <1ae1ff81fcf24324e0371ba983bfbf121f923523.1738665783.git.petrm@nvidia.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000B:EE_|DS7PR12MB6312:EE_ X-MS-Office365-Filtering-Correlation-Id: 17a97c71-726d-4c01-1bf4-08dd450c0dd0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: 0Rps/n7+bFovjMWRMwFrRyswOcnijp5lDG17PR4DEQPc5E0s6cDkAMMCbyZN4SJlRwkt9nMokdSgn7k80/Lib+fK2MtYF4hNdsjQk0R2YktI7uti/1+JmPt+BqRUmopEm8w0ATzX6R2kWYYfOYOAMbI+2PvfwLyXk2AswhHVOwJz2GyWc2NdP8oLooCc+OSEm0b3L8ruyoMW/s7RIKs23aIHwBh4+Kr0/H09eQsCJVslZN9gegLBUvymrhD0UU8c3KPLTUiaDYTsqb/Lu1ALmdhR9NXMTM8KCxO+gzqVetQIqm/lF1x0BLb8YMCNrzy2aiPLb6KWrPhyJqMzf5oOncMWdL8fyiMpyvSd3wfK04+gKQvk6Rb2dl26APDnWZGCPy5QwHLH9J8v/qiLLsEM9NNe5AqZUnS4c1XJiD/xQOBVJWkTbaC5kpr/HUiO+UJ/sAal0r1PaW25uQsWhCGRqqS7dn1M+WHgKJ4DV+2TOkVZVAPuHz89bu4GpnxwaNNhqYsufqrlLB8P5psXuCRLQeRrDWP2MnOGBPpiqTIJct8ZYGM93S8xWcHT+KNc/xEWp/kin7QXi5xPd0ComLC2SBNCeR+UgkZnpySfL3zZ0yfLRRhTqp0+otZlvmYwJecf0r2Btnyzf6fwym9g1BpnUgedr9MQbyC4Y8nztaG2GruM7hxaMX4EoqU05Lgm3WvJOKDeT0bBp/K1qfEmE000LiZr5XOvFc7tjJyjZaPPEEsvXHAC/KK2j6ZXriZUm7Exn2LZ7ExackpU+fs9w/Bbgb2MFYpNwYuy/IBuMm79mONT4a1wAWSIQR2rABKfGhHemxpwG+a00wGlY/72wEHbI/m5ypjkhcEV6SvicOPHJa42C3At259c/K4v4HV7m14Y0jI7KadycccK+7AauU6TlwRxiMwEBWwqTEZqQ72bKVF3kTATI3rMsmiVAsVF7EEhrSeZcYdPGj60zVF5MoW/hiJZ1rimivOUKWfePup5p+orgB2tgAbtxF0VngathJXJYgvlC8YeivlEpbhO8kIazH4Zm9fkWjf4OcgSm7vHP2LBydK5ZPc0kBOS8/WhTkr7M7wCKiwH2U1nZmET53Dcj2ZJFmc6r2TUG0FFjxFxB8ZecGU2N6P7oYCc1GFApe3CWOe0j6OljqFbLF0NnhFKxCFzlyHW6CuegxfLdFcPhW78X7sAIShPtqjpgUAVY9aG1fyuOqAbj5wM/HORmse6ZYZsSdk/GqMaxCM/zYN5gHSRSdySfNJ66+fVnfTMTIYZMLH9L6du3auP6eeiJEk7g/2KODCSyc9ufi8aITaF1/K7PSeXFw9xERNppvoetqNIDGqLwnYYna0XIyE63qppjC6QXunp8RFHCLWB24rHnNoXngXNpHtyuyhZW/aAgbbGtt/LJocNu5bJB80YorsCpPePlzsf741lJNgyA+BtTre7CM1YBqtNUypmFuIMWJCpiYg6ysIWHOVIm8Y7ukbmmJeLUdkjohi0HA7/nlFV11Q= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2025 11:07:02.8582 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 17a97c71-726d-4c01-1bf4-08dd450c0dd0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6312 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen A next patch will store mapping between local port to netdevice in PCI driver. The motivation is to allow quick access to XDP program. When a packet is received, the Rx local port is known, to run XDP program we need to map Rx local port to netdevice, as XDP program is set per netdevice. As preparation, store the maximum number of ports as part of mlxsw_pci structure, this value is queried from firmware. Signed-off-by: Amit Cohen Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 5796d836a7ee..8af4050d5fc6 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -137,6 +137,7 @@ struct mlxsw_pci { bool skip_reset; struct net_device *napi_dev_tx; struct net_device *napi_dev_rx; + unsigned int max_ports; }; static int mlxsw_pci_napi_devs_init(struct mlxsw_pci *mlxsw_pci) @@ -171,6 +172,20 @@ static void mlxsw_pci_napi_devs_fini(struct mlxsw_pci *mlxsw_pci) free_netdev(mlxsw_pci->napi_dev_tx); } +static int mlxsw_pci_max_ports_set(struct mlxsw_pci *mlxsw_pci) +{ + struct mlxsw_core *mlxsw_core = mlxsw_pci->core; + unsigned int max_ports; + + if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_SYSTEM_PORT)) + return -EINVAL; + + /* Switch ports are numbered from 1 to queried value */ + max_ports = MLXSW_CORE_RES_GET(mlxsw_core, MAX_SYSTEM_PORT) + 1; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , CC: Amit Cohen , Ido Schimmel , "Petr Machata" , Alexei Starovoitov , "Daniel Borkmann" , Jesper Dangaard Brouer , John Fastabend , , Subject: [PATCH net-next 07/12] mlxsw: pci: Add PCI ports array Date: Tue, 4 Feb 2025 12:05:02 +0100 Message-ID: <45fad23a5d21df36ef77b3a5c3e8f9d8e09540f9.1738665783.git.petrm@nvidia.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000E:EE_|CH2PR12MB4247:EE_ X-MS-Office365-Filtering-Correlation-Id: 8dbf0236-4c16-4d23-e94b-08dd450c10ef X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: u3JEwqJC4OdJBk5iVyc5wnIP9f4DbtqE7EaUi5zPx+qpaAPlceUt5UUnUY41Pwuku8cUQEdPNxgnXHgTs6EnX8aiYn/dZ67v6wnkejpfbkLhg0ZGsH9RKGcXxqLAGIwnHBzy/2O6lZ1Lk4iJWfnurd0mI9vkCatImFMCnRjBSWe4WmXEtsfht1d7ZNZ8RL4GH0riSJFj7v1LX9RbdSowrZH8QmduzdSjtJdayDVugSxhMrhUuL4vrA84MYgkS6zhVEIh7bqbwPUsXm6KaiPPiNSXbG78+bDNJ53+J6yy3b8yT0YuZWiUT+/VkoA1NrSHw2Vr+DQBsuj7/ue4d0nLdn+lx23hmjaTyeQzcMdxaTysg6ybLhkfB+m8ueSk8eeGk39lBdrsJJW4B/xwm7CxjCSWdThMVPcnxo9g4JVFjLhR4nLIQrNfbOHCmzvLbotQSJL8Ke9kpZN8oBlAB6XT7DfPd2zC3xA8JbnB3xqz2mba8ARyjv4+unzxYDwEGbX910tHIRaj7p8dcA1h5yifaU/xv0a/WDFJzA40bRqOP9Lq5/+CESAf05L2f2Bihp/sH6tUckyhSMxXrMku9/LYjDjwfMIK9fN4OBRdZXsfkev4f/yb4437gP12O6Z1/rC6BLaiMqxsZrdzkDF26YX4Lh25OAaSiZ7SIt7z063AU3njsNQh3EJp7OGfCbNr2YnWys8jdeFM6cnQiOMB6YBqkEo2aIH97q1PXNjewMGVjhzh7AiPZH+KtWrFcqL/GfsNszRdvhLgyUjiCL59Sky47Di8qhH0a5690IvfJkW7vjdXNl+anhAdFlDhg6/SOVOhc6E39J/dFs/zMlMhtkGZDMuq9i1JRSg0+9EoGdFUzWQCz5YBy/i4UJ+7NrPrs89vlDbd9XKWfgkEJmL+do/n90oIBLBSbmFR+9d6nthZjnYW5LHphWLLjQJDnVKRTbfAC5yeGiEEqewUW6AMcnL/NJZNDKa6Z18R2y9CzuHtkitYpbqBYkk9G+zkAuuzH3VtDVjuExHtAPXSe5EE3b44Hf4V/xC9dGsW06xlLhJ+vofUQGDu3+aJ8xPCtZUx/z+nTjxIWIodb6At7P+noGzYEendpCMo/dRlnzOSy9Gxp9kEg0Ku53RxHUO7lJ2O+Jp644frHLU4ktS2FbUtNtVTiU/duCJI/i7I3ciFtJrYxN1hDEGIJZqcrQTfN5O52RgSKZlXARVum5DbAjpAdiq02Ww/CsdbMpohOCgWqfsmU0k7mYj6WvgAYTNCg+GlzaKDKGfnsBoXLM5TStSCS1fwL6yr9mf59YrPTT1wx9WAUxxRR/vqa3dCpyv+kch3eCtwZHUflCTUhVJp3LSfOnDIQiA1nHbm4BUimCRSVw4VI316CQGULuKHOFdLkf34WxEgMKi8q4XEYJ8eiNfdrwTTwvG9KZYWdi3sjdOP9URYVhCYo2PAxiFdWxmZGNuQCwTKdatg4zao0hBN/92zV12Mmr+JJSPgXlJXoBY5gjg93oE= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2025 11:07:08.0998 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8dbf0236-4c16-4d23-e94b-08dd450c10ef X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4247 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen A future patch set will add support for XDP in mlxsw driver. When a packet is received, the Rx local port is provided by the CQE, and we should check if an XDP program is configured for this port. To allow quick mapping between local port to netdevice and XDP program, add an array of mlxsw_pci_port structure. Allocate the array as part of init, according to maximum number of ports. For now, this structure only contains pointer to netdevice. Next patches will extend the structure. Signed-off-by: Amit Cohen Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 30 +++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 8af4050d5fc6..563b9c0578f8 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -102,6 +102,10 @@ struct mlxsw_pci_queue_type_group { u8 count; /* number of queues in group */ }; +struct mlxsw_pci_port { + struct net_device *netdev; +}; + struct mlxsw_pci { struct pci_dev *pdev; u8 __iomem *hw_addr; @@ -138,6 +142,7 @@ struct mlxsw_pci { struct net_device *napi_dev_tx; struct net_device *napi_dev_rx; unsigned int max_ports; + struct mlxsw_pci_port *pci_ports; }; static int mlxsw_pci_napi_devs_init(struct mlxsw_pci *mlxsw_pci) @@ -186,6 +191,24 @@ static int mlxsw_pci_max_ports_set(struct mlxsw_pci *mlxsw_pci) return 0; } +static int mlxsw_pci_ports_init(struct mlxsw_pci *mlxsw_pci) +{ + struct mlxsw_pci_port *pci_ports; + + pci_ports = kcalloc(mlxsw_pci->max_ports, + sizeof(struct mlxsw_pci_port), GFP_KERNEL); + if (!pci_ports) + return -ENOMEM; + + mlxsw_pci->pci_ports = pci_ports; + return 0; +} + +static void mlxsw_pci_ports_fini(struct mlxsw_pci *mlxsw_pci) +{ + kfree(mlxsw_pci->pci_ports); +} + static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, size_t elem_size, int elem_index) { @@ -2088,6 +2111,10 @@ static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core, if (err) goto err_max_ports_set; + err = mlxsw_pci_ports_init(mlxsw_pci); + if (err) + goto err_ports_init; + err = mlxsw_pci_aqs_init(mlxsw_pci, mbox); if (err) goto err_aqs_init; @@ -2105,6 +2132,8 @@ static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core, err_request_eq_irq: mlxsw_pci_aqs_fini(mlxsw_pci); err_aqs_init: + mlxsw_pci_ports_fini(mlxsw_pci); +err_ports_init: err_max_ports_set: mlxsw_pci_napi_devs_fini(mlxsw_pci); err_napi_devs_init: @@ -2135,6 +2164,7 @@ static void mlxsw_pci_fini(void *bus_priv) free_irq(pci_irq_vector(mlxsw_pci->pdev, 0), mlxsw_pci); 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , CC: Amit Cohen , Ido Schimmel , "Petr Machata" , Alexei Starovoitov , "Daniel Borkmann" , Jesper Dangaard Brouer , John Fastabend , , Subject: [PATCH net-next 08/12] mlxsw: Add APIs to init/fini PCI port Date: Tue, 4 Feb 2025 12:05:03 +0100 Message-ID: <6189497bf72fc28c44c55195f7f7759755014dc4.1738665783.git.petrm@nvidia.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B0:EE_|SA1PR12MB7221:EE_ X-MS-Office365-Filtering-Correlation-Id: c723be0c-1494-4281-3447-08dd450c16f3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: tiK21lPUhQJ8C0y7Yeg6e3hBvXgrpH8QWt/x7ZeBLPD9LmRXrymjM6JGsqK9e48hylaFVyNqe2K3a+cqTGMbdE0uygvczxH4TzL/Frb4Kl0auQ7JLEFg7cHpPeddwgxcHadYy9OhvFVD470uvtGiRP6sdojRt6skl6yXoNm5qa6DWSj1FDdath+GQ5wIyBpt1ZUKkSjjv7JYBfP6hy8YdogvtaOEnjzgJsP3cz7qWe9vedaryulC0cCSD3tBppU1tsaXEXZeTGdrzFBgBirJtDKB7UVkFMBHnNBl4yZ3qwefMWZaj1BkkdR5joVZ3gQtAbX7HJ0s2APjQYgbf8pXHxhZLSrCk+KxW0GHsqvligEcDh3ZHxtBJ+zAWyVOpbfthQkBIIZuE2rBFiiRdbb5tkpWb/oaKoUioX7MoM9yVcJ+cD/+SUPuBnRlcRnnzIBc3H+hCX687ownRBpeTKwzxBU8KNwedpdI/GhPUkEnhyiCzSMwyicFHYpGKpXHFEHxh/E1MWXmHndRoaLiverZxDzfmy3OgwWCX+aMKWynXR0dzAjfQqDml/6pevQrShkkk6IAvrhgIhNNiNNUd7qwqDx1mFV8RszbEPBwlE3OfUrm5d2aDQM8DDn8YVfBfhPGtq5pJtKZBP1VULiti7C72XESK2QIg1h8cr44mJsqDLUBMDewnMENzoHZqoXjz/xRJ4tEFsnVCqAMrCPLRO6VrzqNXaxfzEqLCnUQzIPdF9BI5xe6xBJOsUyzBJr2Av8/k2Z/M9B7FZdm1gjaZ10ABrHtEvPYuTIN2x5FuHGmsyAN2HA9lSemeaBiGOyX41dIXskiA9qY9BA5J4ncDDb9vK8jmpxWG+VFajVWM8ABEIz+QBeK8f+4GKAhzVbIkpcRVZkFKnCmYr6GV4jy+aYwYm36IBsiUx+hCRyEI9VSBEfTVlCjs8ZDPm176tZa2ujJGIy5V6bMwOINH277LLV/RZQA6KL4igXsCzTlonpyc+Cs+xfpGVT0ZcE1mB8SfLbRTLayyU2T2zg4hMU1iOQAGS8L+99ESKRbK5iVRlPP2+DRpPpw+qaKGWrpab/P+QPoIE/c4aaZFm+TrFSaH1vX1kBY0/TRDsV06obrbNt6O5uNIXcZ/0WFDgYMmySyxczjVIuGUSB/rknFFPo9HecvohsrhkruVtJWrdbxh+JhuZY5BwwRqjwPy6F3iT1uEwvHIK7T6VqFh/gk1MKkIrSGtsSFAHqABsEN0G3CmOJMgIxFxBU1mffe+71u7k5PkrvQpii2eIi8GndzX8lM3g80LgHJO8pZB3v42qoalRUa/gaNcHI7y0HPviXlDhZJWDu6DN7lak+L5/7fxA8Xn0EbbRIE+s31wfmqpxuJ0yezKlzRZkavhRvIfZa1/OIzWvFG8hR+sTA3hPAsQAM2xF3iERyHMRALiA8w7IVbtVRBwRP74utx/of6gyWtieaM4P4+B2l3XpEMq/LeVUXpkKRS9Pg8VOJLfvxRHHoC5jKKLdA= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2025 11:07:18.2033 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c723be0c-1494-4281-3447-08dd450c16f3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7221 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen The previous patch added PCI ports array, to store the associated netdevice for each local port. Add APIs which set/unset netdevice for specific local port, these APIs will be used from mlxsw_sp_port_create() and mlxsw_sp_port_remove(). For now, store only netdevice pointer, next patches will extend this structure. Signed-off-by: Amit Cohen Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/core.c | 13 +++++++++++++ drivers/net/ethernet/mellanox/mlxsw/core.h | 6 ++++++ drivers/net/ethernet/mellanox/mlxsw/pci.c | 21 +++++++++++++++++++++ 3 files changed, 40 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.c b/drivers/net/ethernet/mellanox/mlxsw/core.c index 392c0355d589..628530e01b19 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/core.c +++ b/drivers/net/ethernet/mellanox/mlxsw/core.c @@ -219,6 +219,19 @@ mlxsw_core_flood_mode(struct mlxsw_core *mlxsw_core) } EXPORT_SYMBOL(mlxsw_core_flood_mode); +void mlxsw_core_bus_port_init(struct mlxsw_core *mlxsw_core, u16 local_port, + struct net_device *netdev) +{ + mlxsw_core->bus->port_init(mlxsw_core->bus_priv, local_port, netdev); +} +EXPORT_SYMBOL(mlxsw_core_bus_port_init); + +void mlxsw_core_bus_port_fini(struct mlxsw_core *mlxsw_core, u16 local_port) +{ + mlxsw_core->bus->port_fini(mlxsw_core->bus_priv, local_port); +} +EXPORT_SYMBOL(mlxsw_core_bus_port_fini); + void *mlxsw_core_driver_priv(struct mlxsw_core *mlxsw_core) { return mlxsw_core->driver_priv; diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.h b/drivers/net/ethernet/mellanox/mlxsw/core.h index 72eb7dbf57ce..506fe50acdec 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/core.h +++ b/drivers/net/ethernet/mellanox/mlxsw/core.h @@ -40,6 +40,9 @@ enum mlxsw_cmd_mbox_config_profile_lag_mode mlxsw_core_lag_mode(struct mlxsw_core *mlxsw_core); enum mlxsw_cmd_mbox_config_profile_flood_mode mlxsw_core_flood_mode(struct mlxsw_core *mlxsw_core); +void mlxsw_core_bus_port_init(struct mlxsw_core *mlxsw_core, u16 local_port, + struct net_device *netdev); +void mlxsw_core_bus_port_fini(struct mlxsw_core *mlxsw_core, u16 local_port); void *mlxsw_core_driver_priv(struct mlxsw_core *mlxsw_core); @@ -495,6 +498,9 @@ struct mlxsw_bus { u32 (*read_frc_l)(void *bus_priv); u32 (*read_utc_sec)(void *bus_priv); u32 (*read_utc_nsec)(void *bus_priv); + void (*port_init)(void *bus_priv, u16 local_port, + struct net_device *netdev); + void (*port_fini)(void *bus_priv, u16 local_port); enum mlxsw_cmd_mbox_config_profile_lag_mode (*lag_mode)(void *bus_priv); enum mlxsw_cmd_mbox_config_profile_flood_mode (*flood_mode)(void *priv); u8 features; diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 563b9c0578f8..bd6c772a3384 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -2434,6 +2434,25 @@ mlxsw_pci_flood_mode(void *bus_priv) return mlxsw_pci->flood_mode; } +static void mlxsw_pci_port_init(void *bus_priv, u16 local_port, + struct net_device *netdev) +{ + struct mlxsw_pci *mlxsw_pci = bus_priv; + struct mlxsw_pci_port *pci_port; + + pci_port = &mlxsw_pci->pci_ports[local_port]; + pci_port->netdev = netdev; +} + +static void mlxsw_pci_port_fini(void *bus_priv, u16 local_port) +{ + struct mlxsw_pci *mlxsw_pci = bus_priv; + struct mlxsw_pci_port *pci_port; + + pci_port = &mlxsw_pci->pci_ports[local_port]; + pci_port->netdev = NULL; +} + static const struct mlxsw_bus mlxsw_pci_bus = { .kind = "pci", .init = mlxsw_pci_init, @@ -2445,6 +2464,8 @@ static const struct mlxsw_bus mlxsw_pci_bus = { .read_frc_l = mlxsw_pci_read_frc_l, .read_utc_sec = mlxsw_pci_read_utc_sec, .read_utc_nsec = mlxsw_pci_read_utc_nsec, + .port_init = mlxsw_pci_port_init, + .port_fini = mlxsw_pci_port_fini, .lag_mode = mlxsw_pci_lag_mode, .flood_mode = mlxsw_pci_flood_mode, .features = MLXSW_BUS_F_TXRX | MLXSW_BUS_F_RESET, From patchwork Tue Feb 4 11:05:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Machata X-Patchwork-Id: 13958902 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2056.outbound.protection.outlook.com [40.107.220.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B8A420C015; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , CC: Amit Cohen , Ido Schimmel , "Petr Machata" , Alexei Starovoitov , "Daniel Borkmann" , Jesper Dangaard Brouer , John Fastabend , , Subject: [PATCH net-next 09/12] mlxsw: pci: Initialize XDP Rx queue info per RDQ Date: Tue, 4 Feb 2025 12:05:04 +0100 Message-ID: <56b84bd23f1745fad0547b62e0da17b656fd3f4c.1738665783.git.petrm@nvidia.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000009:EE_|LV3PR12MB9141:EE_ X-MS-Office365-Filtering-Correlation-Id: 52b62449-a42d-4335-ba0d-08dd450c1a9f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|7416014|82310400026; X-Microsoft-Antispam-Message-Info: pnjKjkM/CPcERhJWA2tPiuN92Tdiy6E+aqONmA/pYaIv4snsgh2GZTMwkHLk2KmSk0Y+SJl8HfQXnEa3SblFTruQgqww0uL/m35G0iWQ1r9DotZKDV7sfih9YGnj18sYi1LrzzwUbQlV7N7GZgCj69g1JdgS2WGSuxjhTuI3+TlAN3AHORrHtH4Htog8u5TMgKAjKSKLbV8RpZOpOQ4YLbImOihwMioWeuHEYZoferYma7pISov75dMvjzK/CIix9TNP4oMZGYv0l+v0wBFc4R9B9WNxvSa+vVwvdOahPuHsixl7AHKMPJdCW03LQNugAupaURY/5WfVbH5ZpyVZnx6ydLTLqbtugLpr3FtlVq42HveUl2IfTeL44M9IUlb9xSTI+t4ctFygyUqmMBuo9mi9kR4C9FogIvd2MRwe7eyoKOUX2oI4sH1VbVinjV3iH56kKs3C0HenpLbssQJoSAMIQJdg1F8o3NypIpMDm0VBCQ2+ECxACpUOQeYqMUD8L3drnOl2qZFLDfDpjomG1IFDmkMpAQDA1qwAUsrkQ6K1PaOg6gRVtE0hcG6UDbSqKLHXsInn4Zv1glxW6FYU8tXvCExfETgUbnoSrYgSPIjHdqPDmMdVOUM3jU9u3Fu+O0K4YOK7AnyzoOGTo/8GfOOWRygax6TqpFuD+TXZm4SQAlLwXC8RoW49HVGryAggi+aE3kvosFKqgKKNI/HNkLpcqCr12aEjuFp6qxiihWCWQsy1xHtCu2EGpEaZ4X2CNd+DQB70h507uTu6/oxrW1lfR58/M5T+grT2LebE/iwctqO74yvq48cudNUaiQWIyskxFSPJgZCe/fh/uEtZDsxRIuGLm22Wwc/t6Xb3FR3s9uGRZc1v86UOcpkN/4hvgo1jkzC72U/qeBTAeGssdhFCVfODPHTSqgViqnHor7n5hhGJcXhUFQoFCirvAUCrpPwe9eKA2pbUk06KqBay6GXO2hPsSn5da55EhGluOVM1kgpOlYef8uFtOpkMZenR7MGkLUQJhDGV0pLt/9Ny25mOZwT+waoHi93y595sxOnB91PPMZP4u7zufeE8wKhqtDJ8EGDYft2KUJ74SrN7C3Gb8q3ZSKt5sEeNZkrmT5nuMjBPaO0EYd3gPBtW9r8ulc3q74ABfUfosdv0vYN6Tnl6hz/HEy+7YianPJdUAo7rynXCdHNHzlhEvydOEv/Ny2eXlZtApGo7tcASq+rFEXtHEiqvad5h9aUvyHOHLLvqj2IxVT4bfbTVj27bbLCR+HmFTkROv0idoeewzXtlI3G1ETRqK7P7SAL14/HlASvVmr6maLAWbbKmyp/eDIykBYSvVqjtBWWymqYnw4FfbnjE7aTzTL9pzHYsQgqIae1f7jazop5/XyqeUazTzTPHutiEqJ4m+OHwiDlpDXAFXIZVdRduiQ7nSdlWX/L6F5pJ2Yb7o8P0xAwqUsfGjM8fQM94Nv7HoOMW++JOsM11sGdv8PKvfOxTl68O2awfU+8= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(7416014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2025 11:07:24.3359 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 52b62449-a42d-4335-ba0d-08dd450c1a9f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000009.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9141 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen In preparation for XDP support, register an Rx queue info structure for each receive queue. Each Rx queue is used by multiple net devices so pass a dummy net device (unregistered, 0 ifindex) as the device. Pass a queue index of 0 since the net devices are registered by the driver as single queue. Signed-off-by: Amit Cohen Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index bd6c772a3384..b102be38d29d 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -14,6 +14,7 @@ #include #include #include +#include #include "pci_hw.h" #include "pci.h" @@ -93,6 +94,7 @@ struct mlxsw_pci_queue { } eq; struct { struct mlxsw_pci_queue *cq; + struct xdp_rxq_info xdp_rxq; } rdq; } u; }; @@ -624,6 +626,11 @@ static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, cq->u.cq.dq = q; q->u.rdq.cq = cq; + err = __xdp_rxq_info_reg(&q->u.rdq.xdp_rxq, mlxsw_pci->napi_dev_rx, 0, + cq->u.cq.napi.napi_id, PAGE_SIZE); + if (err) + goto err_xdp_rxq_info_reg; + mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); for (i = 0; i < q->count; i++) { @@ -633,7 +640,7 @@ static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, for (j = 0; j < mlxsw_pci->num_sg_entries; j++) { err = mlxsw_pci_rdq_page_alloc(q, elem_info, j); if (err) - goto rollback; + goto err_rdq_page_alloc; } /* Everything is set up, ring doorbell to pass elem to HW */ q->producer_counter++; @@ -642,13 +649,15 @@ static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, return 0; -rollback: +err_rdq_page_alloc: for (i--; i >= 0; i--) { elem_info = mlxsw_pci_queue_elem_info_get(q, i); for (j--; j >= 0; j--) mlxsw_pci_rdq_page_free(q, elem_info, j); j = mlxsw_pci->num_sg_entries; } + xdp_rxq_info_unreg(&q->u.rdq.xdp_rxq); +err_xdp_rxq_info_reg: q->u.rdq.cq = NULL; cq->u.cq.dq = NULL; mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num); @@ -663,6 +672,7 @@ static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci, int i, j; mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num); + xdp_rxq_info_unreg(&q->u.rdq.xdp_rxq); for (i = 0; i < q->count; i++) { elem_info = mlxsw_pci_queue_elem_info_get(q, i); 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , CC: Amit Cohen , Ido Schimmel , "Petr Machata" , Alexei Starovoitov , "Daniel Borkmann" , Jesper Dangaard Brouer , John Fastabend , , Subject: [PATCH net-next 10/12] mlxsw: spectrum: Initialize PCI port with the relevant netdevice Date: Tue, 4 Feb 2025 12:05:05 +0100 Message-ID: X-Mailer: git-send-email 2.48.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000009:EE_|CY8PR12MB8315:EE_ X-MS-Office365-Filtering-Correlation-Id: 25979221-4e4f-41b0-2c85-08dd450c1e7d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026|7416014; X-Microsoft-Antispam-Message-Info: XSPFWWOcFILM4QKlGW6pDDk98y9UNIGUmck9llab3jMHSJ5grllyqCf9jkA/1VaOJGCfzOF4yBBsl1YJN+AvVMuDLo832FUEn6lS/ThrOv14W+qy+U3rWY+ZLjdH+Hk0fP8G7VoE6/Cgj6/t32vIILrWrQlcrwllt/y6CGWFPafDAQcqnvq7y84gI4fXPWT4V8MQgOsSz6F03/AR6e1KCKAS8CgKLtevZ6mszC+Fpgx1TK6DztCN7XWsBzftGdyURGpHo1Ox1wJPHZXEsEe8wHblflXHODwkSiQh8lKkiqXpFvX/fry3+m9eIGGhjyvwCB98GS8RbsTDFiG1LYzOvIuJMvJNyC1S0DJZ8kT954L0L8HKcm5FmcuEkXDdhdfMYTPT2gvIPRuaEQg45n1O2CGO4QHAv3Hd6OSYeGJ0wd0Z4TxXxERLmDOz08JZB9x20papMg5uptyyXtDboXAAhhBWVAK+itXrtaKzaDbJKP2h1Af/EFd87uB4PY7wWVxax/5SWyAf4/+s4T8Yq1NLgqrPX7133Ggp9CUFjDPPXkhYIFqYFUw9efbyAHPL/CcxkGuEHxq6fd+jngRUUm3EhI9i6A+mVvPVpivsEkrQgLkyDIisWNoz1I5ITaILN/sta5PllOVa7uCQAVSXIEs6BeomkN2dcSs0gw/yzr84zlLcyaBw+rkiuODf43rjW6ufEPDtUQKDFKkcvOlKgTb8Xnsu+3AFQQHJ0Cu1o4B6Lw5V/Gz1/29RjgztSfYnN2yOW5CoOx+MSkVWOyJtxJgHciFP+6D64seFYx1+wPP3P7b7Zpry0M4Lslf6pmoKhfmWnJ9fdTlFNhmGFtxOznP6VqJYDOfZ090iKA5b92Z5Js0SB9I5J7LzjcQX2PHk195rzZ5yypiXxWtp6tRAgce+bb8uoLWqQ3Ip+v5Li3YK+6o82rEbcIBdWUjURPSDCZ3hvGXY1oYpiqZNB8hNpj2OFrVnRrT7g84Slckb+my9YiILP5664XkOXHt/6B0yvzk0Qr2Qib7NezCWSOYX1rZxxmE9JrN1iyv2vEOZWY/53ulmZ+lztpdk3MJ4KwwT5lPF5ZYFrblTFQNV7Ly7B+X5EOGrtb2CIIE9a4gERopF/p2h+7xxkDHD3eoh2JueOHJ0fp5kFitdnmbJpXT6DQwYU2dm3yMno3oPZz/7jL0HcECmDky7POcbNHaF925LzOJrxb2eLHHmmRS4SREq5RRO4/c3LvNmMzFCAWx/Wm97u1J0TvylO5EAcC5RLLYNg2FM66QDgVZE0Y7YcW6c+SdXHfbWINb6HM0dexdosuCuS4z/YRP/kDxqr+oaML3O4FbmTLFRspSoREZ+S39opEIgWkywFSCC4kCYPDeyFq0yqvoLBBLxOEcNIgxDcQGPs4ioHE3MnixS0uTEodlWMfbdCP1aDOtmTLm707k0pPYt0vy1fkHvByEcaHrHLLJHBJFBeYKkoSBeQUfRMqhNpWI6/ql31BnHnWV8nQuXBouZOXs= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2025 11:07:30.8672 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 25979221-4e4f-41b0-2c85-08dd450c1e7d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000009.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8315 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen When a netdevice is associated with local port, set the netdevice as part of PCI ports array. When a port is removed, unset the relevant netdevice. This will be useful for XDP support, to allow quick access to the relevant netdevice given local port from CQE. Init is done before the netdevice is registered and de-init is done after the netdevice is unregistered, so there is never concurrent access to the array between the control path and the data path. Signed-off-by: Amit Cohen Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/spectrum.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c index d714311fd884..6b77e087fe47 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c @@ -1543,6 +1543,7 @@ static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u16 local_port, mlxsw_core_port_netdev_link(mlxsw_sp->core, local_port, mlxsw_sp_port, dev); mlxsw_sp_port->dev = dev; + mlxsw_core_bus_port_init(mlxsw_sp->core, local_port, dev); mlxsw_sp_port->mlxsw_sp = mlxsw_sp; mlxsw_sp_port->local_port = local_port; mlxsw_sp_port->pvid = MLXSW_SP_DEFAULT_VID; @@ -1758,6 +1759,7 @@ static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u16 local_port, err_dev_addr_init: free_percpu(mlxsw_sp_port->pcpu_stats); err_alloc_stats: + mlxsw_core_bus_port_fini(mlxsw_sp->core, local_port); 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , CC: Amit Cohen , Ido Schimmel , "Petr Machata" , Alexei Starovoitov , "Daniel Borkmann" , Jesper Dangaard Brouer , John Fastabend , , Subject: [PATCH net-next 11/12] mlxsw: Set some SKB fields in bus driver Date: Tue, 4 Feb 2025 12:05:06 +0100 Message-ID: X-Mailer: git-send-email 2.48.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000010:EE_|LV3PR12MB9410:EE_ X-MS-Office365-Filtering-Correlation-Id: 41857f90-f179-4999-3193-08dd450c2390 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: TV3zSNjo8v06tkiQqFHfN39ZwABUA5GBK2K3OlzeSyMdpPT6H/11H2p4HU9eP3CzkawREjd/ajlVHSIEqhrvQ82lU5t58whP9ZqxfRkfpnU6ZHvTQFAJZ0sVS5bF0+I9/U0vupvpvSs7G5UEi41g4HpwxW0rFQ/mPEdvUC1BmGILAB+uzZNsb/CT+kh8R5Yy5ZMdMTwS6k+4OLYmwFN12ymtKP2AkHOX/YYgnQMthkdwKb7ob68TVxqoYQR8Jspb39H67/MjVgbmX3QfpXTKg5g8BUtALX79YG/A5ODNuYjjUzbTAJFtPDZLe+WxRrUaohR+ZzJ///R4aMaOxHg6ql5swP52N3gzBDguWhJ7w3ceYOXgHsnH2XtcnexhGItOFAJHcPbqQ5dgcKmzHooxF1TLHzw9lSjB2e6w0TNRwWhAOvB0TRVHme3hccPZCorTLijpagK0bdT4/z3nNUJ1hPO1d+i0g36z33kLB0MxZfXmBpwhdVoqbbvK+Ryany9/x9G77x8GEsPkj7rjAKS29BLVyDlzKhhMMRPPIwnMzUUjURxajiY4NwSOEtKJlfFo/u2b+M5vrRkpZS5loREnYG8xuYNzk5GGnUxLylHjLCIS4doW4wXJIUFgegJBLLO7LHW8UrdWuV5DWRDLytj0ayas5ULnQFIGjl6CRE0pxw7+4TesYESS5Pvi8L79QTOTD+Qd9gb6sRXHVW99u/f1H9Q8y2JvO5DcuWmbQveelvLp0FSCFX7hbuggoUfkTp2ARZvAe6knupAARTJ7Y5qv+Ve9rSB3V1ffP64emSmrHg89GmSFNgIimC44/L0pNbt1d88c0AjOA2XkoeZNcvOuCSD8xo5FVep+0rIr8wpR1Atla0x2rtLrkWOf/Hp+uUyyemBJbpTr/HrYJIXvW5KyeHnGne1juwnUsJDiubBNnU/V3AitGs+4iuvivqnKtSSiXJ8mFau5OeBD3+HLW/Er8H+uSsUnw1HL8wR3DLfU2smC97w8lUTvtifyJLUyKoYKYcEIr+FEdvvIAJKNylAiDKrrrMoQpPlNfevJoFGW4uIxXfq2emLndIOHEPEkeyExDxj28eWo+fgUf3G76T3zxN7j3+zqRf33w8RRF0rpQ3U/1kVaDGOE1Y6kAQiegw0vvLDY6UNeKT0V+S91XM3HCgjcsGcPzFlq1tML5eSqSY08LX1pavmifTkwslFt3MQFx5GubI7nKuXU/PLiT23pwBX/cq7CckV8usLdvtCPiULOYectlS6fExn3s80Lu0X16wTL0TFYZqfcd1WZb9zXH2RnJOPwNBMmV4MtduVQlI/4dTPPKh+gukBlsiF0uSzn9j4kEL4rIVCdV5QUWcAmcv6QBL9Onok6sDLooSD8sqlSIUNtYQRxl35VaACQkHPn4dC9bxlpxWVs8Re67hORpk/SjO+cSACucUgVcJrIEUJqYe0/7RSfr2djnvLuAuGfHaQv906HSOW4DDzcOutSRMa0aNI4sLHJ0ROg0buNAPY= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2025 11:07:39.3805 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 41857f90-f179-4999-3193-08dd450c2390 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000010.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9410 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen Currently, skb->dev and skb->protocol are set in the switch driver (i.e., 'mlxsw_spectrum'). Previous patches add ports array to bus driver, so we can get netdevice given local port. There is no real reason to not set skb->dev and skb->protocol when SKB is created. Move the relevant code to bus driver. This is needed as a preparation for using xdp_build_skb_from_buff() which takes care of calling eth_type_trans(). eth_type_trans() moves skb->data to point after Ethernet header, so skb->len is decreased accordingly. Add ETH_HLEN when per CPU stats are updated, to save the current behavior which counts also Ethernet header length. eth_type_trans() sets skb->dev, so do not handle this in the driver. Note that for EMADs, local port in CQE is zero, and there is no relevant netdevice, for such packets, do not set skb->dev and skb->protocol. Signed-off-by: Amit Cohen Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 13 ++++++++++--- drivers/net/ethernet/mellanox/mlxsw/spectrum.c | 5 +---- drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c | 6 +----- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index b102be38d29d..b560c21fd3ef 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -494,7 +494,8 @@ mlxsw_pci_sync_for_cpu(const struct mlxsw_pci_queue *q, static struct sk_buff * mlxsw_pci_rdq_build_skb(struct mlxsw_pci_queue *q, - const struct mlxsw_pci_rx_pkt_info *rx_pkt_info) + const struct mlxsw_pci_rx_pkt_info *rx_pkt_info, + struct net_device *netdev) { unsigned int linear_data_size; struct sk_buff *skb; @@ -513,7 +514,7 @@ mlxsw_pci_rdq_build_skb(struct mlxsw_pci_queue *q, skb_put(skb, linear_data_size); if (rx_pkt_info->num_sg_entries == 1) - return skb; + goto out; for (i = 1; i < rx_pkt_info->num_sg_entries; i++) { unsigned int frag_size; @@ -525,6 +526,10 @@ mlxsw_pci_rdq_build_skb(struct mlxsw_pci_queue *q, page, 0, frag_size, PAGE_SIZE); } +out: + if (netdev) + skb->protocol = eth_type_trans(skb, netdev); + return skb; } @@ -814,6 +819,7 @@ static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, struct pci_dev *pdev = mlxsw_pci->pdev; struct mlxsw_pci_queue_elem_info *elem_info; struct mlxsw_rx_info rx_info = {}; + struct mlxsw_pci_port *pci_port; struct sk_buff *skb; u16 byte_count; int err; @@ -851,7 +857,8 @@ static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, if (err) goto out; - skb = mlxsw_pci_rdq_build_skb(q, &rx_pkt_info); + pci_port = &mlxsw_pci->pci_ports[rx_info.local_port]; + skb = mlxsw_pci_rdq_build_skb(q, &rx_pkt_info, pci_port->netdev); if (IS_ERR(skb)) { dev_err_ratelimited(&pdev->dev, "Failed to build skb for RDQ\n"); mlxsw_pci_rdq_pages_recycle(q, rx_pkt_info.pages, diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c index 6b77e087fe47..a7d2e3716283 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c @@ -2340,15 +2340,12 @@ void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb, return; } - skb->dev = mlxsw_sp_port->dev; - pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); u64_stats_update_begin(&pcpu_stats->syncp); pcpu_stats->rx_packets++; - pcpu_stats->rx_bytes += skb->len; + pcpu_stats->rx_bytes += skb->len + ETH_HLEN; u64_stats_update_end(&pcpu_stats->syncp); - skb->protocol = eth_type_trans(skb, skb->dev); napi_gro_receive(mlxsw_skb_cb(skb)->rx_md_info.napi, skb); } diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c index 1f9c1c86839f..2a69f1815e5a 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c @@ -72,16 +72,12 @@ static int mlxsw_sp_rx_listener(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb, return -EINVAL; } - skb->dev = mlxsw_sp_port->dev; - pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); u64_stats_update_begin(&pcpu_stats->syncp); pcpu_stats->rx_packets++; - pcpu_stats->rx_bytes += skb->len; + pcpu_stats->rx_bytes += skb->len + ETH_HLEN; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , CC: Amit Cohen , Ido Schimmel , "Petr Machata" , Alexei Starovoitov , "Daniel Borkmann" , Jesper Dangaard Brouer , John Fastabend , , Subject: [PATCH net-next 12/12] mlxsw: Validate local port from CQE in PCI code Date: Tue, 4 Feb 2025 12:05:07 +0100 Message-ID: <0bd312ed629e85a044725080b9f33403bb51ae41.1738665783.git.petrm@nvidia.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000010:EE_|PH7PR12MB9221:EE_ X-MS-Office365-Filtering-Correlation-Id: efdc2a29-e944-4a7e-60dc-08dd450c27b0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: UEoeQCWdxyeGXHQYPNpm78DnOIYFXEE3WzoEUgNY85U1mWb8nf/wvWDiNvM5L4N+bzCU6eka4qRpsACKub1+pSAAqz0gMFaRWj+oTwwIns6gKjU6GxB5nZ9YhNJpuJJTxBgpf6vGrMX1ZAPPngyHCbyq4IB94YnU3wLPm5GKLvUBe0efXU4gL87L0T2GXDGPvSc66TYPmNL5Sll1sucEPfMGBtvjnq+dzuLiEePeoKk9uNu2Hyxx/GM+9CY3i3GxH8rc72zZ+scNjFOgmCTbjh21IIbp/yX3nf4jJ39QnwqUGQgHddRE4P67S9t7nEmxwQGbfZniwsWlqsanb547hxnumumZeXGJZ4g2KpUV3zOGwLW2lzsx8fdvmmX63y97eP/mVCGbKUlk6s7yF6K1l2BAhn9J2dTg2VhWCncef+jEuQ2AY6kSPDgW7XfwIbX5E6CLbRuIZTxXERMZ5jz2tsQHQu8F37IZrRILyany+6GLCNzi7wgzZ3l4ykuQR83uhYQnRs1ei9zFQImCQGOP30YOY+uib/n0FqN0GTHNBNSY7EBv0XnnrSw96BJusgKxW1aorr8FH5K4HV21Tbbz8rZY+/1l7nhDFxoMtx3yZNEAFgVU7vvDfZyzm7MMmMQnoLdpSyXGxFWBYRJWsop0J1WxPMNGOFrMBgV9wGm1gMTmfmybI8VOr+lNgfiu69yiiFXqbfxtSXmP/PpI7rYDHySiCHAP/Pc9qWo3u3Bh43BEhesu2WK1ziiaZZdy9dar6WAETu9KHdZifQqYLH+0vuXryQvA5ZFa+LZhe7gwNA6WmwDUVCyydAOuDDBAbXpQfnRLEWiznniaBQOypUmfvbJt2QoKE68hK+TdIjSUSNEPSyagFzY52XHknDsImY7Nk4jxPjc+qHcaqrFq3bsmHK0MGsHWeZcblfzqk6ouiv7oJaZFChq/47T4qDMARJmNZpKpmnu4ycgIVUx2/Aw+mcP2SF7iYWE9cpqVk+wFeFf/XoBArewIXYUMeWQEl0RFCxNzXcVtQ/jsQNxJj9mIbxxMNzc1DQfDRldpW0prOAN1B+loyevBG+KKzaHVzzIXO/9aghWc2s7Af1u2GtsWNYHQH9E+XJKbVlaENV21mgmlOky7EYSUAyiofBfKyTeVkXxwedyTT5RrjT0VTj7wFHYwMEGGTu0G152GV4gajGgWMrOSfW7o2Q4wkGrFxJhQTouR6VbtQj1kD5lJkWDOgZBfCM6kmRQyOg8+5XHGdLo+6/BRPyyZjsvCfF4J6Sk5KLubl5X1QD5WZgfE1JckgeaQSbpC0atkLkbsrxKy6YQpVTL3W27SsD8P2GEXcPjD4PlvQdCF62a+gCgx3M+FCHWCraJCkG2ybLlq8iKlNtcrOj7gNiH9X1uQn3j8JBfZeslhbNP5jreTvM4JHu99bjfHwZ9lK5VXCRO1VD6ZG72O1BxpP5uXyL0w5IqBq9jdCO2rFz8MDnPiEVs6XlOYzBXAhWN9jRIWj+wjZar9CKk= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2025 11:07:46.2711 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: efdc2a29-e944-4a7e-60dc-08dd450c27b0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000010.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9221 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen Currently, there is a check in core code to validate that the received local port does not exceed number of ports in the switch. Next patch will have to validate it also in PCI, before accessing the pci_ports array. There is no reason to check it twice, so move this check to PCI code. Note that 'mlxsw_pci->max_ports' and 'mlxsw_core->max_ports' store the same value, which is read from firmware. Signed-off-by: Amit Cohen Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/core.c | 3 +-- drivers/net/ethernet/mellanox/mlxsw/pci.c | 3 +++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.c b/drivers/net/ethernet/mellanox/mlxsw/core.c index 628530e01b19..962283bbfe18 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/core.c +++ b/drivers/net/ethernet/mellanox/mlxsw/core.c @@ -2959,8 +2959,7 @@ void mlxsw_core_skb_receive(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, const struct mlxsw_rx_listener *rxl; bool found = false; - if ((rx_info->trap_id >= MLXSW_TRAP_ID_MAX) || - (rx_info->local_port >= mlxsw_core->max_ports)) + if (rx_info->trap_id >= MLXSW_TRAP_ID_MAX) goto drop; rcu_read_lock(); diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index b560c21fd3ef..778493b21318 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -845,6 +845,9 @@ static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, rx_info.local_port = mlxsw_pci_cqe_system_port_get(cqe); } + if (rx_info.local_port >= mlxsw_pci->max_ports) + goto out; + err = mlxsw_pci_rx_pkt_info_init(q->pci, elem_info, byte_count, &rx_pkt_info); if (err)