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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c122465sm15757919f8f.47.2025.02.04.04.50.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 04:50:12 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v3 1/9] target/arm: Apply correct timer offset when calculating deadlines Date: Tue, 4 Feb 2025 12:50:01 +0000 Message-Id: <20250204125009.2281315-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250204125009.2281315-1-peter.maydell@linaro.org> References: <20250204125009.2281315-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When we are calculating timer deadlines, the correct definition of whether or not to apply an offset to the physical count is described in the Arm ARM DDI4087 rev L.a section D12.2.4.1. This is different from when the offset should be applied for a direct read of the counter sysreg. We got this right for the EL1 physical timer and for the EL1 virtual timer, but got all the rest wrong: they should be using a zero offset always. Factor the offset calculation out into a function that has a comment documenting exactly which offset it is calculating and which gets the HYP, SEC, and HYPVIRT cases right. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1fee8fae127..049362a5500 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2460,6 +2460,32 @@ static uint64_t gt_phys_cnt_offset(CPUARMState *env) return gt_phys_raw_cnt_offset(env); } +static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx) +{ + /* + * Return the timer offset to use for indirect accesses to the timer. + * This is the Offset value as defined in D12.2.4.1 "Operation of the + * CompareValue views of the timers". + * + * The condition here is not always the same as the condition for + * whether to apply an offset register when doing a direct read of + * the counter sysreg; those conditions are described in the + * access pseudocode for each counter register. + */ + switch (timeridx) { + case GTIMER_PHYS: + return gt_phys_raw_cnt_offset(env); + case GTIMER_VIRT: + return env->cp15.cntvoff_el2; + case GTIMER_HYP: + case GTIMER_SEC: + case GTIMER_HYPVIRT: + return 0; + default: + g_assert_not_reached(); + } +} + static void gt_recalc_timer(ARMCPU *cpu, int timeridx) { ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; @@ -2469,8 +2495,7 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) * Timer enabled: calculate and set current ISTATUS, irq, and * reset timer to when ISTATUS next has to change */ - uint64_t offset = timeridx == GTIMER_VIRT ? - cpu->env.cp15.cntvoff_el2 : gt_phys_raw_cnt_offset(&cpu->env); + uint64_t offset = gt_indirect_access_timer_offset(&cpu->env, timeridx); uint64_t count = gt_get_countervalue(&cpu->env); /* Note that this must be unsigned 64 bit arithmetic: */ int istatus = count - offset >= gt->cval; From patchwork Tue Feb 4 12:50:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13959128 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AFB61C02194 for ; Tue, 4 Feb 2025 12:53:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tfIO3-00007x-8V; Tue, 04 Feb 2025 07:50:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfINe-0008JT-S7 for qemu-devel@nongnu.org; Tue, 04 Feb 2025 07:50:19 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tfINc-00029P-7C for qemu-devel@nongnu.org; Tue, 04 Feb 2025 07:50:18 -0500 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-38daf09d37fso267193f8f.1 for ; Tue, 04 Feb 2025 04:50:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738673414; x=1739278214; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TG5YvjSZwhc9TBWdlzGFshXDfcxcwdL+WhbKE+SqJUk=; b=giGXHBhze8BKLoUpD1/nzJaRUPOJRKkjNwAv1KQf/M+UJ0F1XuL6AoZNfQpR9iXTva pGd80DyzQBXgDf3LMvkhr0+NsThqb4uoqcYhpmD37ImyGScTgks5ugdrtYz1Bj5yoKoA Z9cyHeV3Cm0sgSNpATFycj082JN5rJe9U+grZ59pJZgltta8I7ebAkZ4belYEKiPcVSR YQNVDDXCBR8VKcqEUoBukJauFxelCARJVD5a+JSOLhM4oWjJOLbKtyzpdfrxWu7Lh7rt oyTOyHNRB12ZstwoSKTYJpLZNQMPEts08m9ryWfyvJh3Xh/ONCogGK2IkWJFhDw5x+3w 9sGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738673414; x=1739278214; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TG5YvjSZwhc9TBWdlzGFshXDfcxcwdL+WhbKE+SqJUk=; b=TCapBxynE3zIfs21bpyFvhtn/fG8213esJLwwAcbWZOZjkOcPWKPxm4MqKDZ6Zga1P ncv4RT2I0bhjqKwO6/RF4L7I/f8hogmzyNyuyNuhZSIYVmCsQYrhqjb/No5pQ9T3alfz tfxGjojNFGKqI81a7O14Fd7VaA83C0Ae8lgavwo13CBRRSPU03AiCiU81WICSJpWyt5k k5ZqNDopjMPw+XVI0w7z8wlRW/tIx5Bh+AYf9E/xQ1vdSJCS4gSIaUXoiBQjpPpBzINU 5HcZFP1VFvQOkE07Cb39pgj6+z53/gh4aC4wdBfJjZvrx8nGso9h50G8QwfXk99Z1oiJ EvUg== X-Forwarded-Encrypted: i=1; AJvYcCVMkg/ArxUDeLibCflSc0GffmEnE73x43RNm1iWEmq5xuHQBAjxzKKSAkl0Nb/U40t4hKMGrViYhKz8@nongnu.org X-Gm-Message-State: AOJu0YzY1goIP2dwbL4iLC5Hh3/+5iZpPusaN8qk9kl6KO65pMQPnKOt cw7AAIrboRdg2hfSGmC4N5c5DEEbosD0XL23hmMNVjobhnZdbna+jNfVl3LIeG4= X-Gm-Gg: ASbGncv93SvSyljzGD4n2MZnQYt2486BYFDTC4Ey7OxnivNJp78Qmg2CP3Nt899m+Gi NWl3+Fs6/c1yTO4KuZvXdmm575/e2TDizcJzSfmOmqU5MOvCktlGKCCRjIiR5/DqU0//a2f9GFZ fJwZzQuNwLt4OQSBPGazqYycOgazLjJwxCothZlKYYkmuse26oHkoLnJ72CyKdAEJXvKrbTDzLy +YHHXUVZ2Wlqh/zn17IBkfA0SnOZ2Otu6jxOw9lcZyLbzpnhiseMwBuCuOj0gQgG0xrZbshD3LZ Ul743UwvXSFj2YsIbsEp0g== X-Google-Smtp-Source: AGHT+IHgLh+EWaE8oaEYxTNWnzFvvFosBsOIVVYVXWKquQnZ99/Ic74vCOlOuJYBN1p3txo2Tyoxqw== X-Received: by 2002:a05:6000:1884:b0:388:e377:8a1b with SMTP id ffacd0b85a97d-38c51b60c11mr20563034f8f.28.1738673414159; Tue, 04 Feb 2025 04:50:14 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c122465sm15757919f8f.47.2025.02.04.04.50.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 04:50:13 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v3 2/9] target/arm: Don't apply CNTVOFF_EL2 for EL2_VIRT timer Date: Tue, 4 Feb 2025 12:50:02 +0000 Message-Id: <20250204125009.2281315-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250204125009.2281315-1-peter.maydell@linaro.org> References: <20250204125009.2281315-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The CNTVOFF_EL2 offset register should only be applied for accessses to CNTVCT_EL0 and for the EL1 virtual timer (CNTV_*). We were incorrectly applying it for the EL2 virtual timer (CNTHV_*). Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 049362a5500..ac8cb428925 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2604,7 +2604,6 @@ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, switch (timeridx) { case GTIMER_VIRT: - case GTIMER_HYPVIRT: offset = gt_virt_cnt_offset(env); break; case GTIMER_PHYS: @@ -2624,7 +2623,6 @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, switch (timeridx) { case GTIMER_VIRT: - case GTIMER_HYPVIRT: offset = gt_virt_cnt_offset(env); break; case GTIMER_PHYS: From patchwork Tue Feb 4 12:50:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13959127 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CC77FC02194 for ; Tue, 4 Feb 2025 12:53:05 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tfIO5-0000Dv-22; Tue, 04 Feb 2025 07:50:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfINe-0008JR-Qr for qemu-devel@nongnu.org; Tue, 04 Feb 2025 07:50:19 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tfINc-00029m-VE for qemu-devel@nongnu.org; Tue, 04 Feb 2025 07:50:18 -0500 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-3862a921123so3767602f8f.3 for ; Tue, 04 Feb 2025 04:50:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738673415; x=1739278215; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=R869ff5rZccFCzTyQxhPv2mn876SBy48z5OTtaNMV/s=; b=q34Kmo+4kCzQngdTmrf6jomCNA4mYp+pCHJLIKT327pPPTznWDEHNRjByw3wRHiA9E +jEkB/q1gUm7JooctWVDlPiXktO8gnQ5gyVjQ2bdNVwj/9k1ahxtFXfk96SM1vi+IlHS K4idlm7zA55Ds8D2IAP5wa4q7/EvicmcCE/CHLvtK4yo3QJpltbFQ3zhM0E3bmahpHfq WSb5YoQUKYywICTwe6ejr0jt4WeHuzNjVSrjnAvwWeiyJkeFWtWPCJgLkWvMgWw/HOuG ATtSw6fI52Eqos5LX/rlbPfjiFVekaL8zo5y31VfIySYnsgq4CM4MSSUz6dvKaieEtiW p2lQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738673415; x=1739278215; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R869ff5rZccFCzTyQxhPv2mn876SBy48z5OTtaNMV/s=; b=VVposMmmwSUmaCFouarMtHF5HQqE+ug8G300/g0tm0/uOc78RqyKLLWD5azYFY/OjJ eKnNSdhiVSLT2BmsrvXtcsFE6SqtBcY0k+81OaxN/HlbagzMYX4LRUxNSBxcmCZ+U5Sa 6Lm3/5ZTeCjItx5oDDWxIDHccboTWwMNeJAED9HQGAgyeZ7biiwFh+RfhLZHapT2Yl0E t7Rxq79jQ0tV/dPJuHk6o/KPvzjGd16CuXeWS1vGR4WO5CxkQQoMMamwevRo30iQWHyw G+EB01dkla4rFfnAMvw0VU1gZuC5qhSW6bj9a1C75ZsPkYFKv9NOBMvxHrJE90Rb4dnU KWMg== X-Forwarded-Encrypted: i=1; AJvYcCVOpRsx4xg4d2+k+cVjIOzopJ+L4zRo11jyKai9oCkybps6Fvxrn7Nv/v8AIiYoESG3Affvrl2j1yl7@nongnu.org X-Gm-Message-State: AOJu0YzenUg5vYSiT526CwwmmzhS9uz7J/rCedE4Oc2N5DBo/0Y+ZENf 8Z0ch47b7CoE7btLmNolY9/imShe8Oh+7pmzjPk+7/kwTbnZ0cUF+6JH4l0hJvc= X-Gm-Gg: ASbGncu0rxtcledjumEMAXAezDwvccobkHDXWpQ5d7aG3zJ1yUcD8RMrvTnGN1Jin+Q wUrNU9NgXOfu9adnf3CxWL3PeDYc8rDoWaKi8VsX9K7Wn0LJi+8XjTYi9XxKqQQVzHvr4YpiTad ziTY8x9xxJwXmON+ywFiMY5mWVc9SqZ7vK/CnctrXvXlN1UmR1y5QPAbP8c0BoLFhkCsUipQ11/ r4Hnp+B0Zipq4z8HTeqKHPjAEWclOH2frt+/szCD5RBlmb1e63MYu+yh4vIAGhmv+ze3QotzVZr btNIEeIFYwp4UsqjcZ88JA== X-Google-Smtp-Source: AGHT+IFy5V1sEUSCOvK8E5G5DGfVIJFSa43LRtsvOI53ZRMtIr6WvrFHSE5BDrg72O3QKV298X1ncA== X-Received: by 2002:a5d:47c8:0:b0:385:e1a8:e28e with SMTP id ffacd0b85a97d-38c51931ef0mr19713816f8f.10.1738673414994; Tue, 04 Feb 2025 04:50:14 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c122465sm15757919f8f.47.2025.02.04.04.50.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 04:50:14 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v3 3/9] target/arm: Make CNTPS_* UNDEF from Secure EL1 when Secure EL2 is enabled Date: Tue, 4 Feb 2025 12:50:03 +0000 Message-Id: <20250204125009.2281315-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250204125009.2281315-1-peter.maydell@linaro.org> References: <20250204125009.2281315-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When we added Secure EL2 support, we missed that this needs an update to the access code for the EL3 physical timer registers. These are supposed to UNDEF from Secure EL1 when Secure EL2 is enabled. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index ac8cb428925..7ec1e6cfaab 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2387,6 +2387,9 @@ static CPAccessResult gt_stimer_access(CPUARMState *env, if (!arm_is_secure(env)) { return CP_ACCESS_UNDEFINED; } + if (arm_is_el2_enabled(env)) { + return CP_ACCESS_UNDEFINED; + } if (!(env->cp15.scr_el3 & SCR_ST)) { return CP_ACCESS_TRAP_EL3; } From patchwork Tue Feb 4 12:50:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13959119 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 98D6AC02194 for ; Tue, 4 Feb 2025 12:51:11 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tfIO5-0000F3-Jd; Tue, 04 Feb 2025 07:50:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfINj-0008Lw-6e for qemu-devel@nongnu.org; Tue, 04 Feb 2025 07:50:24 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tfINd-0002A9-QT for qemu-devel@nongnu.org; Tue, 04 Feb 2025 07:50:19 -0500 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-38daa53a296so272520f8f.3 for ; Tue, 04 Feb 2025 04:50:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738673416; x=1739278216; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZMomNfTKsnHM/3+WLPMScpmOJgfYrLQIKGo4Qy9Se74=; b=uwI/jWvqv4T8fiRAK0jbroE+uin/zuR/E36HAVbFAC6dJwLWqUBtYukhuKQCTaNdcG 8QnXhdlGL1b6GZaXqq8pGgUGmFg6+9K2Qs87S2Zr80Yb5gDlGF8Otv0Flcc1Pg8t8Yty 145e2dRsoAEXXZddIWZoLrhdJ2Gcy2d7uab9nYaAmlc/WOZaiLHd1e2mGbmE11EM4Cu0 9oqMIm3F7FuXLIM+WNjr8zgmXg0ESCMmwpmsSMpyaPouNRpE+cixU59DDOwewJFYiVSz lYIlMFkstFhcqqCZklY92yriUi59mvMD8SO7MPU0f2JRPnkJLzQdz+U3KwedfKMYhT00 NIRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738673416; x=1739278216; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZMomNfTKsnHM/3+WLPMScpmOJgfYrLQIKGo4Qy9Se74=; b=rU01HtmdNXunzLUvLIGtLiv9vKzXHqhAABZWBnq2lOAsF6l4ncHP1oypgtn5AdENFx 7t7nj40NBDsHZmq/9gQ9ay8hfUQGpCa1g0pObGD3mmphucAyhEhV2K888ocRcFEdR7dB rUf5jik00Ouf9lZ8b2kwXLQd3GMqjpiQxVe3RlNd5d2r8Y33ZVIzg66DrDRFkdbfsddx 6+MdNVrXtymr1OQ/JFvLsfR9mj+XjL0WAFIX79lo6sdYuR4TbGS5353uRdAKWPZFJMdS RHL5ZOg9Fqiy0Dc3nzB6ccw6Bnzyd/ERUg4VN1Nrcxao2hRFOdWo3dfGDjU03gZZF8sw u/bw== X-Forwarded-Encrypted: i=1; AJvYcCXZj3RunoV8oJ8AqcvwmGKhl16c5aPN4G1L9E3NMfxown6c5re2yV6pMQEgGUibKhnr0vpDS7hSTLoK@nongnu.org X-Gm-Message-State: AOJu0YxPsmuy+gGK/af6P0QGS1+xwgOwYvPccprOxWt+Ab4o+GXR9CVz 9khrjBIfVKZdgW4BL/Ek8hegbXR4l5Dlts7qCDri7Kl3E9lBUT3V6HQ+78RiVKpPQjkYSHtaDj7 Y X-Gm-Gg: ASbGnctSGFD2dxTpSTGHM9TH90QR6TwEVBk6ox25Fk7y1MsFBKmIxk6TYSywbokJamm IGypDACqgykbLqPTe4JisDPNpWc9ZcO7Tf73RhoXZ6ghpZMIXk5nBwFERGrUEeR4TaTOD7yy2fa j+c7ekhdjVQtBrlK3h5oCvbGqp6dFQOvljOuHx3yzuhnhA4PP4ZuWHzKNToCaeYjXNTPSw5/aH5 a/aVLupJGUsu02MedZuDD7wIICUYtpWqe171exZjD5M/fpF3PK7bazDK01EkeNIs/8mHP5gTvQG A0QacnrgcslCbn0ayHzGEg== X-Google-Smtp-Source: AGHT+IH41lar320LQzBf74OfHPI1IKm+o2XdQxdLIEafZ8Oerby+u8AdGTr7nEUfM4oIc5bB9MB/fA== X-Received: by 2002:a05:6000:2a3:b0:38d:b099:4546 with SMTP id ffacd0b85a97d-38db099463bmr739289f8f.54.1738673415946; Tue, 04 Feb 2025 04:50:15 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c122465sm15757919f8f.47.2025.02.04.04.50.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 04:50:15 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v3 4/9] target/arm: Always apply CNTVOFF_EL2 for CNTV_TVAL_EL02 accesses Date: Tue, 4 Feb 2025 12:50:04 +0000 Message-Id: <20250204125009.2281315-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250204125009.2281315-1-peter.maydell@linaro.org> References: <20250204125009.2281315-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently we handle CNTV_TVAL_EL02 by calling gt_tval_read() for the EL1 virt timer. This is almost correct, but the underlying CNTV_TVAL_EL0 register behaves slightly differently. CNTV_TVAL_EL02 always applies the CNTVOFF_EL2 offset; CNTV_TVAL_EL0 doesn't do so if we're at EL2 and HCR_EL2.E2H is 1. We were getting this wrong, because we ended up in gt_virt_cnt_offset() and did the E2H check. Factor out the tval read/write calculation from the selection of the offset, so that we can special case gt_virt_tval_read() and gt_virt_tval_write() to unconditionally pass CNTVOFF_EL2. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 36 +++++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7ec1e6cfaab..01ca222903d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2600,6 +2600,12 @@ static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, gt_recalc_timer(env_archcpu(env), timeridx); } +static uint64_t do_tval_read(CPUARMState *env, int timeridx, uint64_t offset) +{ + return (uint32_t)(env->cp15.c14_timer[timeridx].cval - + (gt_get_countervalue(env) - offset)); +} + static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, int timeridx) { @@ -2614,8 +2620,16 @@ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, break; } - return (uint32_t)(env->cp15.c14_timer[timeridx].cval - - (gt_get_countervalue(env) - offset)); + return do_tval_read(env, timeridx, offset); +} + +static void do_tval_write(CPUARMState *env, int timeridx, uint64_t value, + uint64_t offset) +{ + trace_arm_gt_tval_write(timeridx, value); + env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + + sextract64(value, 0, 32); + gt_recalc_timer(env_archcpu(env), timeridx); } static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -2632,11 +2646,7 @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, offset = gt_phys_cnt_offset(env); break; } - - trace_arm_gt_tval_write(timeridx, value); - env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + - sextract64(value, 0, 32); - gt_recalc_timer(env_archcpu(env), timeridx); + do_tval_write(env, timeridx, value, offset); } static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -2768,13 +2778,21 @@ static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) { - return gt_tval_read(env, ri, GTIMER_VIRT); + /* + * This is CNTV_TVAL_EL02; unlike the underlying CNTV_TVAL_EL0 + * we always apply CNTVOFF_EL2. Special case that here rather + * than going into the generic gt_tval_read() and then having + * to re-detect that it's this register. + * Note that the accessfn/perms mean we know we're at EL2 or EL3 here. + */ + return do_tval_read(env, GTIMER_VIRT, env->cp15.cntvoff_el2); } static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - gt_tval_write(env, ri, GTIMER_VIRT, value); + /* Similarly for writes to CNTV_TVAL_EL02 */ + do_tval_write(env, GTIMER_VIRT, value, env->cp15.cntvoff_el2); } static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, From patchwork Tue Feb 4 12:50:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13959120 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7AD76C02194 for ; Tue, 4 Feb 2025 12:52:04 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tfIO9-0000Ox-MF; Tue, 04 Feb 2025 07:50:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfINj-0008Lz-8m for qemu-devel@nongnu.org; Tue, 04 Feb 2025 07:50:24 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tfINf-0002Aw-DD for qemu-devel@nongnu.org; Tue, 04 Feb 2025 07:50:22 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4362bae4d7dso39332375e9.1 for ; Tue, 04 Feb 2025 04:50:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738673417; x=1739278217; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5C04XmL9mrmAcsBNUPKjSrw0Pg8WQ3LqYabnkNL2Gl8=; b=i8GhZJ1kmvc+mfHTJAe4NsUJQKxmLHqfT79ggogPZM9xx261aU+X349hJANXjEJwCX 5Q7DoXsAyClj6Ja4XI9PDpdMS1YmZrDN6UbbTX2IbVivS6kn3fo3Xf7k6CgcZ7vPBKZG ivQ4ryx1MuZ0pEWOX6PvxEFMYQ52d4lF1XE1NVEZayo89VA+IlWeyu5BQAt/efm3adPl 2JF86W/lYMu6RZdV0dNG0pthdusmihDTaLcXdxDjW92D3njPR0qpB2bUiflNgd/JiLrx J4TarOdhLOrzU0K1mpgq7takp3nuLVjuzjq+dJCVUbEiZdNUt+nqLq4JjrL6zyqTiiHy bZbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738673417; x=1739278217; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5C04XmL9mrmAcsBNUPKjSrw0Pg8WQ3LqYabnkNL2Gl8=; b=ndoQwgPC7NycoTZGPVqtcLsJGaARjooyBW9WWT+62e5Qeg5ILuPRD/Eu7w2r42AGHv hLdoCrj4xFPBKh2Xqs3hL4+gIFgB6WjHpWoIqCUSFwIMoDh/BNXy1qljZe/HVdMBVgAs T2oQqz8by7inu1nlwCXZ3pR7D7L9pZswh1mnVU0npxd5mZVRrRj3PCHuKKqTdk+AQqpp fY5bhsfJiF0YAM9Q2zksiCF+3xmuLjMnXxCzso73p/sDcOxnZ7/nmN2he8GqU26gKbfa 7o6wgB/sItwrCWCPqKyFnkLvj6ZIdzT4q8z6fAl+f8tFv65jNsa91OIChYoL4Jy4jvVr BW8g== X-Forwarded-Encrypted: i=1; AJvYcCVjq1QhtD6ZQk2diPjik/LGOXXykqY/F2U+6ZuIu0NAfDTVGZ+zUfFOafUiLMFZ93bkm7B1+9wybICk@nongnu.org X-Gm-Message-State: AOJu0Yx9LGuX00TR2DjiI97NknVHfA9Vuvt8gw3umbLasB32fXyJPeHS RXJ2eEOY3yJ/Cb1BoUTCPbA0GlNs7tek/C/XC/jxqpCOmuiRId+7dEuF0ukOVPY= X-Gm-Gg: ASbGncvPEnHlhV9QSncuxF8bBQHgZVZ0kRfXVPqLszLf+A70u0kYHJ0LN/aVON97ylD X1BkVLIzovic6divZ4fzsW0Rid4MaoV6OVxMg7lgXDF20REV5JCOxL4RSfAbcLIWh4WZMlkbQ54 hJCx3xs1rXOuXjWEnLUOr437PLcs70F4NKjHd3pFwdxoc3mmGF5AouuM+Nc7tjKj0C/Mg7zjcit sIaBNOibbQkU59Sq7sPLWPTm+kPBh6N3dxxSgaZBLV2NEw6AVyyFqONZ6r1G2W5NeNWjfHRybeU CSs1GQ7qVEeO4PywHGZMvg== X-Google-Smtp-Source: AGHT+IFTiu0seO05C8kwhRsYHHQD9uUyjtaNp+TDBCnSSssLSG+GsXUf1yfFb2Zw0XJaLudjMtU2nw== X-Received: by 2002:a5d:5f44:0:b0:385:e411:c894 with SMTP id ffacd0b85a97d-38c520938eemr24335837f8f.43.1738673416878; Tue, 04 Feb 2025 04:50:16 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c122465sm15757919f8f.47.2025.02.04.04.50.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 04:50:16 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v3 5/9] target/arm: Refactor handling of timer offset for direct register accesses Date: Tue, 4 Feb 2025 12:50:05 +0000 Message-Id: <20250204125009.2281315-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250204125009.2281315-1-peter.maydell@linaro.org> References: <20250204125009.2281315-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When reading or writing the timer registers, sometimes we need to apply one of the timer offsets. Specifically, this happens for direct reads of the counter registers CNTPCT_EL0 and CNTVCT_EL0 (and their self-synchronized variants CNTVCTSS_EL0 and CNTPCTSS_EL0). It also applies for direct reads and writes of the CNT*_TVAL_EL* registers that provide the 32-bit downcounting view of each timer. We currently do this with duplicated code in gt_tval_read() and gt_tval_write() and a special-case in gt_virt_cnt_read() and gt_cnt_read(). Refactor this so that we handle it all in a single function gt_direct_access_timer_offset(), to parallel how we handle the offset for indirect accesses. The call in the WFIT helper previously to gt_virt_cnt_offset() is now to gt_direct_access_timer_offset(); this is the correct behaviour, but it's not immediately obvious that it shouldn't be considered an indirect access, so we add an explanatory comment. This commit should make no behavioural changes. (Cc to stable because the following bugfix commit will depend on this one.) Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 5 +- target/arm/helper.c | 103 +++++++++++++++++++------------------ target/arm/tcg/op_helper.c | 8 ++- 3 files changed, 62 insertions(+), 54 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 863a84edf81..b4b3d196191 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1819,9 +1819,10 @@ int delete_hw_watchpoint(target_ulong addr, target_ulong len, int type); uint64_t gt_get_countervalue(CPUARMState *env); /* * Return the currently applicable offset between the system counter - * and CNTVCT_EL0 (this will be either 0 or the value of CNTVOFF_EL2). + * and the counter for the specified timer, as used for direct register + * accesses. */ -uint64_t gt_virt_cnt_offset(CPUARMState *env); +uint64_t gt_direct_access_timer_offset(CPUARMState *env, int timeridx); /* * Return mask of ARMMMUIdxBit values corresponding to an "invalidate diff --git a/target/arm/helper.c b/target/arm/helper.c index 01ca222903d..c021c237b9b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2455,14 +2455,6 @@ static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env) return 0; } -static uint64_t gt_phys_cnt_offset(CPUARMState *env) -{ - if (arm_current_el(env) >= 2) { - return 0; - } - return gt_phys_raw_cnt_offset(env); -} - static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx) { /* @@ -2489,6 +2481,52 @@ static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx) } } +uint64_t gt_direct_access_timer_offset(CPUARMState *env, int timeridx) +{ + /* + * Return the timer offset to use for direct accesses to the + * counter registers CNTPCT and CNTVCT, and for direct accesses + * to the CNT*_TVAL registers. + * + * This isn't exactly the same as the indirect-access offset, + * because here we also care about what EL the register access + * is being made from. + * + * This corresponds to the access pseudocode for the registers. + */ + uint64_t hcr; + + switch (timeridx) { + case GTIMER_PHYS: + if (arm_current_el(env) >= 2) { + return 0; + } + return gt_phys_raw_cnt_offset(env); + case GTIMER_VIRT: + switch (arm_current_el(env)) { + case 2: + hcr = arm_hcr_el2_eff(env); + if (hcr & HCR_E2H) { + return 0; + } + break; + case 0: + hcr = arm_hcr_el2_eff(env); + if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { + return 0; + } + break; + } + return env->cp15.cntvoff_el2; + case GTIMER_HYP: + case GTIMER_SEC: + case GTIMER_HYPVIRT: + return 0; + default: + g_assert_not_reached(); + } +} + static void gt_recalc_timer(ARMCPU *cpu, int timeridx) { ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; @@ -2561,34 +2599,14 @@ static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) { - return gt_get_countervalue(env) - gt_phys_cnt_offset(env); -} - -uint64_t gt_virt_cnt_offset(CPUARMState *env) -{ - uint64_t hcr; - - switch (arm_current_el(env)) { - case 2: - hcr = arm_hcr_el2_eff(env); - if (hcr & HCR_E2H) { - return 0; - } - break; - case 0: - hcr = arm_hcr_el2_eff(env); - if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { - return 0; - } - break; - } - - return env->cp15.cntvoff_el2; + uint64_t offset = gt_direct_access_timer_offset(env, GTIMER_PHYS); + return gt_get_countervalue(env) - offset; } static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) { - return gt_get_countervalue(env) - gt_virt_cnt_offset(env); + uint64_t offset = gt_direct_access_timer_offset(env, GTIMER_VIRT); + return gt_get_countervalue(env) - offset; } static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -2609,16 +2627,7 @@ static uint64_t do_tval_read(CPUARMState *env, int timeridx, uint64_t offset) static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, int timeridx) { - uint64_t offset = 0; - - switch (timeridx) { - case GTIMER_VIRT: - offset = gt_virt_cnt_offset(env); - break; - case GTIMER_PHYS: - offset = gt_phys_cnt_offset(env); - break; - } + uint64_t offset = gt_direct_access_timer_offset(env, timeridx); return do_tval_read(env, timeridx, offset); } @@ -2636,16 +2645,8 @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, int timeridx, uint64_t value) { - uint64_t offset = 0; + uint64_t offset = gt_direct_access_timer_offset(env, timeridx); - switch (timeridx) { - case GTIMER_VIRT: - offset = gt_virt_cnt_offset(env); - break; - case GTIMER_PHYS: - offset = gt_phys_cnt_offset(env); - break; - } do_tval_write(env, timeridx, value, offset); } diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 02c375d196d..30786fd1ff4 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -427,7 +427,13 @@ void HELPER(wfit)(CPUARMState *env, uint64_t timeout) int target_el = check_wfx_trap(env, false, &excp); /* The WFIT should time out when CNTVCT_EL0 >= the specified value. */ uint64_t cntval = gt_get_countervalue(env); - uint64_t offset = gt_virt_cnt_offset(env); + /* + * We want the value that we would get if we read CNTVCT_EL0 from + * the current exception level, so the direct_access offset, not + * the indirect_access one. Compare the pseudocode LocalTimeoutEvent(), + * which calls VirtualCounterTimer(). + */ + uint64_t offset = gt_direct_access_timer_offset(env, GTIMER_VIRT); uint64_t cntvct = cntval - offset; uint64_t nexttick; From patchwork Tue Feb 4 12:50:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13959126 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 883A1C02194 for ; Tue, 4 Feb 2025 12:52:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tfIO8-0000Mn-W0; Tue, 04 Feb 2025 07:50:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfINr-0008PA-4n for qemu-devel@nongnu.org; Tue, 04 Feb 2025 07:50:38 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tfINj-0002B3-UB for qemu-devel@nongnu.org; Tue, 04 Feb 2025 07:50:28 -0500 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-38da72cc47bso499221f8f.2 for ; Tue, 04 Feb 2025 04:50:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738673418; x=1739278218; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tMCLVG75imhon3JRh2v3hSuL1igLHDGnXzv1AZpRurg=; b=pbKyz2MaM1JoCWgVg7uUWJkY6VL02Ot6sO15AitCbL1cRROM+fYNui3BuP2FK4o1l/ fQU/aFKtHuvNq2kL5Sb9c31d+sIAzRb3wZd7/vu/o0lkO7RdCFJPMheC+2KONcTux4wC hjVMSGLdeuzIUZabBeg3Oj4iAm1Tt7uHUFZ7W+d7DAcm6GBrXK+nL25jaPqWW4lrGadc bWIAM/icN2Za89Uugj1AkdKfja9AOY4PlgTY4CoJ1rx3/d1YOlJqP8UrIbxI9fN+Tvtc cWZfLXZI5STTbxEt6UIkKwhWUXSvaKCDtxfITYzD12PbwdCWcrka2kpl5+jNjVuoiq5l COuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738673418; x=1739278218; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tMCLVG75imhon3JRh2v3hSuL1igLHDGnXzv1AZpRurg=; b=mCWxyCIO8BQyYo6hoBOGMI+Axa7uYKGJPiCvEEk+Saw6NfBLmMxg9zufIX1Y9TXSHs P57iQGXBJHJ5L1RzDKokDq/ODz7RZAAcw26qYKQyxjn6Lxijo/BOwkNOhdbOjq8fT8ud cpC5wmcLjvSi2iZcihC8fX8NCX/BVhQyW4mAU6q/rfmZS97O2/SvRO7IgJHHQv1bP5uz 06g2IVRTxOGMzous2F8uMsyR3aadVueUKOKxdP3m0GvOdPWpvbA4xtLS/tFYhEAZTfVH dblzcIrQiL7quuf+4A8Fjxy7WGI6TY4egno91DisOuDtFP0AGhW+33vUXDw9zmYyzFbd 8F9g== X-Forwarded-Encrypted: i=1; AJvYcCVahtv6mWNDbiOa7hrwwupQtLJdHKrQ32hnc6pNIvM4oICWNh8M9ktn5VgqURuFS6lVspaxK+j8dEOi@nongnu.org X-Gm-Message-State: AOJu0Yzc5Wr3BXUHe/6lVqDcamOCDjIJVYgFPoctW6+5egrkMOfR+JYs 68k+JUZTAvV0M2k6x0zCC/zmO1xdOdRzLCqMq/7b2jH7+EOdZSdx9fq/rWcqGKU= X-Gm-Gg: ASbGncux92dobZpsqRXFE+W6Lgwb5bpA63ZEVSk2h/SERRtTzMxNCe+jOVaTlSroHuF gwp0LLxh+4/E/QZMXjv7bws1fkajS61hgp04AmdCdUseVuyqoZDCDhQYOAXYE97Y/YTGxBEfpLX yG1RVjBUBA+gFtFuvnptrvWRAHt541gu6eJ9yMRlLkviE99RAOcoV8c4cXLAcjm7ISxYdQsTRMj B2LCC6gDyngSe+01WaKa+7wyC4GwPLwqlnUnyBFv1WqmK2Lwom88Ssx231a8u62z67kJn/Egx3m Xyp6egMyxh+7LO5K1zTHCQ== X-Google-Smtp-Source: AGHT+IEP4iz2ZMMvy7N7WT7YPobyS75l1byrMXRCtZuqxLR0kt8EHFB2iJpRnHHigF9kRhw9AZqFqg== X-Received: by 2002:adf:ee8b:0:b0:382:3c7b:9ae with SMTP id ffacd0b85a97d-38c51943ddemr18794462f8f.16.1738673417826; Tue, 04 Feb 2025 04:50:17 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c122465sm15757919f8f.47.2025.02.04.04.50.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 04:50:17 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v3 6/9] target/arm: Implement SEL2 physical and virtual timers Date: Tue, 4 Feb 2025 12:50:06 +0000 Message-Id: <20250204125009.2281315-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250204125009.2281315-1-peter.maydell@linaro.org> References: <20250204125009.2281315-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Alex Bennée When FEAT_SEL2 was implemented the SEL2 timers were missed. This shows up when building the latest Hafnium with SPMC_AT_EL=2. The actual implementation utilises the same logic as the rest of the timers so all we need to do is: - define the timers and their access functions - conditionally add the correct system registers - create a new accessfn as the rules are subtly different to the existing secure timer Fixes: e9152ee91c (target/arm: add ARMv8.4-SEL2 system registers) Signed-off-by: Alex Bennée Cc: qemu-stable@nongnu.org Cc: Andrei Homescu Cc: Arve Hjønnevåg Cc: Rémi Denis-Courmont [PMM: CP_ACCESS_TRAP_UNCATEGORIZED -> CP_ACCESS_UNDEFINED; offset logic now in gt_{indirect,direct}_access_timer_offset() ] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/bsa.h | 2 + target/arm/cpu.h | 2 + target/arm/gtimer.h | 4 +- target/arm/cpu.c | 4 ++ target/arm/helper.c | 163 +++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 174 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/bsa.h b/include/hw/arm/bsa.h index 8eaab603c03..13ed2d2ac19 100644 --- a/include/hw/arm/bsa.h +++ b/include/hw/arm/bsa.h @@ -22,6 +22,8 @@ #define QEMU_ARM_BSA_H /* These are architectural INTID values */ +#define ARCH_TIMER_S_EL2_VIRT_IRQ 19 +#define ARCH_TIMER_S_EL2_IRQ 20 #define VIRTUAL_PMU_IRQ 23 #define ARCH_GIC_MAINT_IRQ 25 #define ARCH_TIMER_NS_EL2_IRQ 26 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ae1e8b1c779..3011595b3d0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1148,6 +1148,8 @@ void arm_gt_vtimer_cb(void *opaque); void arm_gt_htimer_cb(void *opaque); void arm_gt_stimer_cb(void *opaque); void arm_gt_hvtimer_cb(void *opaque); +void arm_gt_sel2timer_cb(void *opaque); +void arm_gt_sel2vtimer_cb(void *opaque); unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); diff --git a/target/arm/gtimer.h b/target/arm/gtimer.h index b992941bef1..0e89b8e58d0 100644 --- a/target/arm/gtimer.h +++ b/target/arm/gtimer.h @@ -15,7 +15,9 @@ enum { GTIMER_HYP = 2, GTIMER_SEC = 3, GTIMER_HYPVIRT = 4, -#define NUM_GTIMERS 5 + GTIMER_S_EL2_PHYS = 5, /* CNTHPS_* ; only if FEAT_SEL2 */ + GTIMER_S_EL2_VIRT = 6, /* CNTHVS_* ; only if FEAT_SEL2 */ +#define NUM_GTIMERS 7 }; #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7a83b9ee34f..97acd230298 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2091,6 +2091,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) arm_gt_stimer_cb, cpu); cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, arm_gt_hvtimer_cb, cpu); + cpu->gt_timer[GTIMER_S_EL2_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_sel2timer_cb, cpu); + cpu->gt_timer[GTIMER_S_EL2_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_sel2vtimer_cb, cpu); } #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index c021c237b9b..bc820b0de76 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2404,6 +2404,45 @@ static CPAccessResult gt_stimer_access(CPUARMState *env, } } +static CPAccessResult gt_sel2timer_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* + * The AArch64 register view of the secure EL2 timers are mostly + * accessible from EL3 and EL2 although can also be trapped to EL2 + * from EL1 depending on nested virt config. + */ + switch (arm_current_el(env)) { + case 0: /* UNDEFINED */ + return CP_ACCESS_UNDEFINED; + case 1: + if (!arm_is_secure(env)) { + /* UNDEFINED */ + return CP_ACCESS_UNDEFINED; + } else if (arm_hcr_el2_eff(env) & HCR_NV) { + /* Aarch64.SystemAccessTrap(EL2, 0x18) */ + return CP_ACCESS_TRAP_EL2; + } + /* UNDEFINED */ + return CP_ACCESS_UNDEFINED; + case 2: + if (!arm_is_secure(env)) { + /* UNDEFINED */ + return CP_ACCESS_UNDEFINED; + } + return CP_ACCESS_OK; + case 3: + if (env->cp15.scr_el3 & SCR_EEL2) { + return CP_ACCESS_OK; + } else { + return CP_ACCESS_UNDEFINED; + } + default: + g_assert_not_reached(); + } +} + uint64_t gt_get_countervalue(CPUARMState *env) { ARMCPU *cpu = env_archcpu(env); @@ -2475,6 +2514,8 @@ static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx) case GTIMER_HYP: case GTIMER_SEC: case GTIMER_HYPVIRT: + case GTIMER_S_EL2_PHYS: + case GTIMER_S_EL2_VIRT: return 0; default: g_assert_not_reached(); @@ -2521,6 +2562,8 @@ uint64_t gt_direct_access_timer_offset(CPUARMState *env, int timeridx) case GTIMER_HYP: case GTIMER_SEC: case GTIMER_HYPVIRT: + case GTIMER_S_EL2_PHYS: + case GTIMER_S_EL2_VIRT: return 0; default: g_assert_not_reached(); @@ -2953,6 +2996,62 @@ static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, gt_ctl_write(env, ri, GTIMER_SEC, value); } +static void gt_sec_pel2_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + gt_timer_reset(env, ri, GTIMER_S_EL2_PHYS); +} + +static void gt_sec_pel2_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_cval_write(env, ri, GTIMER_S_EL2_PHYS, value); +} + +static uint64_t gt_sec_pel2_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_tval_read(env, ri, GTIMER_S_EL2_PHYS); +} + +static void gt_sec_pel2_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_tval_write(env, ri, GTIMER_S_EL2_PHYS, value); +} + +static void gt_sec_pel2_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_ctl_write(env, ri, GTIMER_S_EL2_PHYS, value); +} + +static void gt_sec_vel2_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + gt_timer_reset(env, ri, GTIMER_S_EL2_VIRT); +} + +static void gt_sec_vel2_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_cval_write(env, ri, GTIMER_S_EL2_VIRT, value); +} + +static uint64_t gt_sec_vel2_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_tval_read(env, ri, GTIMER_S_EL2_VIRT); +} + +static void gt_sec_vel2_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_tval_write(env, ri, GTIMER_S_EL2_VIRT, value); +} + +static void gt_sec_vel2_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_ctl_write(env, ri, GTIMER_S_EL2_VIRT, value); +} + static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) { gt_timer_reset(env, ri, GTIMER_HYPVIRT); @@ -3009,6 +3108,20 @@ void arm_gt_stimer_cb(void *opaque) gt_recalc_timer(cpu, GTIMER_SEC); } +void arm_gt_sel2timer_cb(void *opaque) +{ + ARMCPU *cpu = opaque; + + gt_recalc_timer(cpu, GTIMER_S_EL2_PHYS); +} + +void arm_gt_sel2vtimer_cb(void *opaque) +{ + ARMCPU *cpu = opaque; + + gt_recalc_timer(cpu, GTIMER_S_EL2_VIRT); +} + void arm_gt_hvtimer_cb(void *opaque) { ARMCPU *cpu = opaque; @@ -5733,6 +5846,56 @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = { .access = PL2_RW, .accessfn = sel2_access, .nv2_redirect_offset = 0x48, .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) }, +#ifndef CONFIG_USER_ONLY + /* Secure EL2 Physical Timer */ + { .name = "CNTHPS_TVAL_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 0, + .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, + .accessfn = gt_sel2timer_access, + .readfn = gt_sec_pel2_tval_read, + .writefn = gt_sec_pel2_tval_write, + .resetfn = gt_sec_pel2_timer_reset, + }, + { .name = "CNTHPS_CTL_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 1, + .type = ARM_CP_IO, .access = PL2_RW, + .accessfn = gt_sel2timer_access, + .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_PHYS].ctl), + .resetvalue = 0, + .writefn = gt_sec_pel2_ctl_write, .raw_writefn = raw_write, + }, + { .name = "CNTHPS_CVAL_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 2, + .type = ARM_CP_IO, .access = PL2_RW, + .accessfn = gt_sel2timer_access, + .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_PHYS].cval), + .writefn = gt_sec_pel2_cval_write, .raw_writefn = raw_write, + }, + /* Secure EL2 Virtual Timer */ + { .name = "CNTHVS_TVAL_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 0, + .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, + .accessfn = gt_sel2timer_access, + .readfn = gt_sec_vel2_tval_read, + .writefn = gt_sec_vel2_tval_write, + .resetfn = gt_sec_vel2_timer_reset, + }, + { .name = "CNTHVS_CTL_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 1, + .type = ARM_CP_IO, .access = PL2_RW, + .accessfn = gt_sel2timer_access, + .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_VIRT].ctl), + .resetvalue = 0, + .writefn = gt_sec_vel2_ctl_write, .raw_writefn = raw_write, + }, + { .name = "CNTHVS_CVAL_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 2, + .type = ARM_CP_IO, .access = PL2_RW, + .accessfn = gt_sel2timer_access, + .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_VIRT].cval), + .writefn = gt_sec_vel2_cval_write, .raw_writefn = raw_write, + }, +#endif }; static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, From patchwork Tue Feb 4 12:50:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13959123 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 73013C02196 for ; Tue, 4 Feb 2025 12:52:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tfIOA-0000Pv-79; Tue, 04 Feb 2025 07:50:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfINo-0008Nv-5M for qemu-devel@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c122465sm15757919f8f.47.2025.02.04.04.50.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 04:50:18 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v3 7/9] target/arm: document the architectural names of our GTIMERs Date: Tue, 4 Feb 2025 12:50:07 +0000 Message-Id: <20250204125009.2281315-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250204125009.2281315-1-peter.maydell@linaro.org> References: <20250204125009.2281315-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Alex Bennée As we are about to add more physical and virtual timers lets make it clear what each timer does. Signed-off-by: Alex Bennée [PMM: Add timer register name prefix to each comment] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/gtimer.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/gtimer.h b/target/arm/gtimer.h index 0e89b8e58d0..d49c63cbf87 100644 --- a/target/arm/gtimer.h +++ b/target/arm/gtimer.h @@ -10,11 +10,11 @@ #define TARGET_ARM_GTIMER_H enum { - GTIMER_PHYS = 0, - GTIMER_VIRT = 1, - GTIMER_HYP = 2, - GTIMER_SEC = 3, - GTIMER_HYPVIRT = 4, + GTIMER_PHYS = 0, /* CNTP_* ; EL1 physical timer */ + GTIMER_VIRT = 1, /* CNTV_* ; EL1 virtual timer */ + GTIMER_HYP = 2, /* CNTHP_* ; EL2 physical timer */ + GTIMER_SEC = 3, /* CNTPS_* ; EL3 physical timer */ + GTIMER_HYPVIRT = 4, /* CNTHV_* ; EL2 virtual timer ; only if FEAT_VHE */ GTIMER_S_EL2_PHYS = 5, /* CNTHPS_* ; only if FEAT_SEL2 */ GTIMER_S_EL2_VIRT = 6, /* CNTHVS_* ; only if FEAT_SEL2 */ #define NUM_GTIMERS 7 From patchwork Tue Feb 4 12:50:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13959121 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0BF20C02194 for ; Tue, 4 Feb 2025 12:52:20 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tfIOB-0000Y9-Ts; Tue, 04 Feb 2025 07:50:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfINv-0008QG-Jk for qemu-devel@nongnu.org; Tue, 04 Feb 2025 07:50:38 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tfINn-0002C4-42 for qemu-devel@nongnu.org; Tue, 04 Feb 2025 07:50:32 -0500 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-38dabb11eaaso312585f8f.0 for ; Tue, 04 Feb 2025 04:50:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738673420; x=1739278220; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=09VHH1K+AfyKzHK84Dwim4tocdMil186/qzqBE0PsZE=; b=qj8mNrKWplZRVo9I525f4UVmQ72nzGqPD+athTuZvv66AFUqXEKIedR0a0io2GxFE7 ZxoFAb2b6vRLv4CXcOjDx0M/ZWtgtH+ImbN0tTSk2YBRa40HDQ0ptvDNJ+eHEcnhcHRx QtRqdhqguRDOoJPnVXo8MLK7ZQjw2gtu/Es3NPGHrtJRzkix/ohdfUpva2nm8Ymlvkyt oguV4a1Dk7xDy7DZ4dGfbzOVi1bxJBRc4r01ZTgM8RpaoRNzMxwoeVHvRsobQwuOZWpV hnBnQ9jOJexGjQgIdCmwmX+ivrHgkqRpzdJi3N8Yr2RD5zpgVdNYqmvIbu8862WM/DUh n6Ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738673420; x=1739278220; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=09VHH1K+AfyKzHK84Dwim4tocdMil186/qzqBE0PsZE=; b=tBBlyXWA3bN9BFtBD80aXUpGjlHqGlxcSRPZrX8gkJedewYhvDKHzUcOmbkyUnYmPN JFzc/5bCD0U5Ykr7rN4uSjD9G33JGiHzcTtgVIgojS9rSH5I9gMqWbRJCvNKKtkzwXQI kvjw/PnsorS8mWdbojBB+PmqCsA4qZkg+HU4/aV+bVy6ojCWoHCX5Hq17a+zhOTuTdRh TiKLNqFURTBziZd1Qo6W2UwtVmK1kpy5Tis23YysJzpKsrQ7XrUL04vCi6Zluax911Qk AoRGygftIxER5zYV1BhxTtKYPaGTY0Quly4s0EgCjkqBQltcBXLXm+PsXEBXRZomxEG5 A2DA== X-Forwarded-Encrypted: i=1; AJvYcCVfb/0mg5/Y59OO4vHf9kcQ+OfaKh30c0XCNu90pcBPLdVFAgOuBQ5/9J03vlxu72Wjiyhx4ck01d5Q@nongnu.org X-Gm-Message-State: AOJu0YyRWTn8Lh1XTb2gNhc/jl3g88w4aZYn4EG4vmOtJjgcp2uTaW1+ tBU+xTv51AunahEUdlRiqieCaZ/D2xgPNtLZjIwjohrRzqxE/iFlWSgljkLQJnOL2NFqWaT5eQL M X-Gm-Gg: ASbGnctO6N6xNcfanh1zRJx8/iE11nl/jBt/k2DrNGlyWW4+N4Velig5PGQ3PQlYe7o 2PpnpBscc8HUVnexhL9Flky7yLJDeaTUbd0i04ialDt1cZYO4DfyjWO0UnSG5q6tLzs6UjMrboX cwTisiBCkRRYTmEBS6FxsIUXiHNyAmLihO0CxxDz8l+VSMKVX1H13EEjSMOgGkvseFsuId4VbXV 6qqdnWpYyCGefNt6XTX22m2vOHgKSjqH1NFR0JoeOWQJJ8ZBd8qNQENQsxHV9RrFEO4pLmuYfdn pSn6o9pW0LJCgu3GanCFlw== X-Google-Smtp-Source: AGHT+IGyz8/6HdawodkAOlH5PK8Zn2lvjzDTYof2mfxaGdU5rwm+uLFeWzG0EqbBJJ3xZ/3JXd2Djg== X-Received: by 2002:a5d:5412:0:b0:38a:9f7d:9339 with SMTP id ffacd0b85a97d-38c51a693c0mr16853944f8f.28.1738673419704; Tue, 04 Feb 2025 04:50:19 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c122465sm15757919f8f.47.2025.02.04.04.50.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 04:50:19 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v3 8/9] hw/arm: enable secure EL2 timers for virt machine Date: Tue, 4 Feb 2025 12:50:08 +0000 Message-Id: <20250204125009.2281315-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250204125009.2281315-1-peter.maydell@linaro.org> References: <20250204125009.2281315-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Alex Bennée Signed-off-by: Alex Bennée Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/virt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 99e0a68b6c5..c00a6e410cd 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -873,6 +873,8 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, + [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ, + [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ, }; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c122465sm15757919f8f.47.2025.02.04.04.50.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 04:50:20 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v3 9/9] hw/arm: enable secure EL2 timers for sbsa machine Date: Tue, 4 Feb 2025 12:50:09 +0000 Message-Id: <20250204125009.2281315-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250204125009.2281315-1-peter.maydell@linaro.org> References: <20250204125009.2281315-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Alex Bennée Signed-off-by: Alex Bennée Reviewed-by: Peter Maydell Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell --- hw/arm/sbsa-ref.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 6183111f2de..d69e7aaa95e 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -484,6 +484,8 @@ static void create_gic(SBSAMachineState *sms, MemoryRegion *mem) [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, + [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ, + [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ, }; for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {