From patchwork Wed Feb 5 10:49:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q3PDs2vDoXMgQmVuY2U=?= X-Patchwork-Id: 13960800 Received: from fw2.prolan.hu (fw2.prolan.hu [193.68.50.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7F6122D4DA; Wed, 5 Feb 2025 10:50:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.68.50.107 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738752607; cv=none; b=QWZ0fX/N1KMAmZ7/IqgHzX3KmesfrKzBa48LXhXYU864o91NkuqhsAEl+fGkXrMNaIJ3eqHXA9i5UuAnIstORim/aJR6KobBZsRdNVn5M+2DUhJfm1Hdv20dRC/1mMgk3pvn8JuX85lp5wRsVy+wJgmxZ+u93kZQg6/iv3GIn98= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738752607; c=relaxed/simple; bh=KQOTWzbhGWsR9+/X0VDEcivnX/oxVCYyQt/frcwp37k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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c=relaxed/relaxed; d=prolan.hu; h=cc :cc:content-transfer-encoding:content-type:content-type:date :from:from:in-reply-to:message-id:mime-version:references :reply-to:subject:subject:to:to; s=mail; bh=spcugB6t6p78x878lmlq UL8jciWNu5Mk1BUINRx7Dfc=; b=YPaTCIhdnLydCfO6rCc/SmKW7gJAUJ3DinjO XLgsi3pfr6P0N+3lnghvktG7yuuu1ESnlf6JPFRhEPTt8BFmTM5E99W0I+s51cPP xScZsc8XRfrKvXkvWtky1+O6eBGkzRwZ73LV8Goj5Wsgi3SMY5JlLS7etHMsU0yV KpCpgGDYwqANtYm4O2QNMvpnyNmcDKlMEH+2MM2UlqbYuXjFK6B2kPHAZDTNq+Tr g5nVBxpuU9hd3cFFy3bVfyytIyMje8YAG5UQDV/IAqV0kTia2kBOvj7HLj7PfoEG G3udsarQqxMIxN/+dSf+4Fjhpl/FDVFTseIgmnwXukSG5KBEhNY4frlSzPBKeGXY h83VIkX/qAPKhQDdIT/1J0iAcBQ8ejQ/5OSXAMrymrmuqH9r5fBoF0vccCIJPBdx lCMKlJMfcgsiiz0tJ3KGgnhzQp0+bCP47IyxTJ0C5O/C5dk+T+UhHvQf+OZcjmiL 2AUDNLo0l4s5CH07GXtqxf0n0MRz8hTKrnzrXq7Wl8LiUs2A//t3xMHsm+SyJjBa TdwQOaAxPekWXnchNPyz5L/CPfg8eWn6MnkIH8unDDeKuG8uPsOknwn6rAUMN5OE UGUitADqQW/PoL3lAze65x7/6D49Rk5egcdbywyMxYBllj7lwTM4RoushY8nbvL1 5Z1hEqo= From: =?utf-8?b?QmVuY2UgQ3PDs2vDoXM=?= To: , , CC: =?utf-8?b?QmVuY2UgQ3PDs2vDoXM=?= , "Kamel Bouhara" , William Breathitt Gray Subject: [PATCH v3 1/2] counter: microchip-tcb-capture: Add IRQ handling Date: Wed, 5 Feb 2025 11:49:53 +0100 Message-ID: <20250205104957.95236-2-csokas.bence@prolan.hu> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250205104957.95236-1-csokas.bence@prolan.hu> References: <20250205104957.95236-1-csokas.bence@prolan.hu> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ESET-AS: R=OK;S=0;OP=CALC;TIME=1738752601;VERSION=7985;MC=1293086803;ID=233956;TRN=0;CRV=0;IPC=;SP=0;SIPS=0;PI=3;F=0 X-ESET-Antispam: OK X-EsetResult: clean, is OK X-EsetId: 37303A29ACD94852667264 Add interrupt servicing to allow userspace to wait for the following events: * Change-of-state caused by external trigger * Capture of timer value into RA/RB * Compare to RC register * Overflow Signed-off-by: Bence Csókás --- Notes: New in v2 Changes in v3: * Add IRQs for Capture events (from next patch) * Add IRQ for RC Compare * Add events as bullet points to commit msg drivers/counter/microchip-tcb-capture.c | 67 +++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/drivers/counter/microchip-tcb-capture.c b/drivers/counter/microchip-tcb-capture.c index 2f096a5b973d..fef4bb69b486 100644 --- a/drivers/counter/microchip-tcb-capture.c +++ b/drivers/counter/microchip-tcb-capture.c @@ -6,10 +6,12 @@ */ #include #include +#include #include #include #include #include +#include #include #include #include @@ -18,6 +20,9 @@ ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_LDBDIS | \ ATMEL_TC_LDBSTOP) +#define ATMEL_TC_DEF_IRQS (ATMEL_TC_ETRGS | ATMEL_TC_COVFS | \ + ATMEL_TC_LDRAS | ATMEL_TC_LDRBS | ATMEL_TC_CPCS) + #define ATMEL_TC_QDEN BIT(8) #define ATMEL_TC_POSEN BIT(9) @@ -27,6 +32,7 @@ struct mchp_tc_data { int qdec_mode; int num_channels; int channel[2]; + int irq; }; static const enum counter_function mchp_tc_count_functions[] = { @@ -294,6 +300,60 @@ static const struct of_device_id atmel_tc_of_match[] = { { /* sentinel */ } }; +static irqreturn_t mchp_tc_isr(int irq, void *dev_id) +{ + struct counter_device *const counter = dev_id; + struct mchp_tc_data *const priv = counter_priv(counter); + u32 sr, mask; + + regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], SR), &sr); + regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], IMR), &mask); + + sr &= mask; + if (!(sr & ATMEL_TC_ALL_IRQ)) + return IRQ_NONE; + + if (sr & ATMEL_TC_ETRGS) + counter_push_event(counter, COUNTER_EVENT_CHANGE_OF_STATE, 0); + if (sr & ATMEL_TC_LDRAS) + counter_push_event(counter, COUNTER_EVENT_CAPTURE, 0); + if (sr & ATMEL_TC_LDRBS) + counter_push_event(counter, COUNTER_EVENT_CAPTURE, 1); + if (sr & ATMEL_TC_CPCS) + counter_push_event(counter, COUNTER_EVENT_THRESHOLD, 2); + if (sr & ATMEL_TC_COVFS) + counter_push_event(counter, COUNTER_EVENT_OVERFLOW, 0); + + return IRQ_HANDLED; +} + +static void mchp_tc_irq_remove(void *ptr) +{ + struct mchp_tc_data *priv = ptr; + + regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], IDR), ATMEL_TC_DEF_IRQS); +} + +static int mchp_tc_irq_enable(struct counter_device *const counter) +{ + struct mchp_tc_data *const priv = counter_priv(counter); + int ret = devm_request_irq(counter->parent, priv->irq, mchp_tc_isr, 0, + dev_name(counter->parent), counter); + + if (ret < 0) + return ret; + + ret = regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], IER), ATMEL_TC_DEF_IRQS); + if (ret < 0) + return ret; + + ret = devm_add_action_or_reset(counter->parent, mchp_tc_irq_remove, priv); + if (ret < 0) + return ret; + + return 0; +} + static void mchp_tc_clk_remove(void *ptr) { clk_disable_unprepare((struct clk *)ptr); @@ -378,6 +438,13 @@ static int mchp_tc_probe(struct platform_device *pdev) counter->num_signals = ARRAY_SIZE(mchp_tc_count_signals); counter->signals = mchp_tc_count_signals; + priv->irq = of_irq_get(np->parent, 0); + if (priv->irq > 0) { + ret = mchp_tc_irq_enable(counter); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "Failed to set up IRQ"); + } + ret = devm_counter_add(&pdev->dev, counter); if (ret < 0) return dev_err_probe(&pdev->dev, ret, "Failed to add counter\n"); From patchwork Wed Feb 5 10:49:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q3PDs2vDoXMgQmVuY2U=?= X-Patchwork-Id: 13960801 Received: from fw2.prolan.hu (fw2.prolan.hu [193.68.50.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B97B22CBF3; Wed, 5 Feb 2025 10:50:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.68.50.107 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738752607; cv=none; b=T4mKCubgLra5ZPqwnJg1k85+1Zucg4bmeeT8QV/pafPuRY37oC9jwm+DPTZWLq77Ynatn0iDPnysJy9nWvv3cx9gPrt6snrQ4gfay/JEwc505617xf85/qQwzWYOUBbg26fARJYZbgk2agqwIgkios9e6u2N7Yq56WlXukNhHzw= ARC-Message-Signature: i=1; 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Wed, 5 Feb 2025 11:50:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=prolan.hu; h=cc :cc:content-transfer-encoding:content-type:content-type:date :from:from:in-reply-to:message-id:mime-version:references :reply-to:subject:subject:to:to; s=mail; bh=SDare0wXthcUSCxt8tJM hXyNRKnHO97BD3ndLeOmDBI=; b=OM7D9kN/qdhvVKfFyRJIY7EmIiYKzs5biVhP SYV12ZKf8A4UtWWnswMGsznVS+CQBPHxIRhewTGcXK8mhHG6OXTKX1/kvkVk+XQc mX5aZd2TQGnB5YFahlKb5/hUevWts/95fdAim5TAiQVHurym71JkR0bE8WvIkWjE 0NUIiBZECxHwT6iCbeXeDb1aMmwY5au9rfSZTHfe6JO5jN0AfZuOpWVL/f1E+71o 656E7X4y06qx9PexxX4e1xR1rjP5q42VM0I+hYMHjuWXb4neA9+QhwL1VDDGLmVF CQkB1aewiXM39KNJyrT250wC7DAln3HGhklq7fwbA1ZdDNNg68byIqtDKTxy1kAL iRTQs/nWds0fATuIJVHJxSepyhSQgrUf/ZnXX1WUoJ/ALNa+hpz+t7TN+Etiiz4/ pAHKQiBG8bvTCkCYbvxbdO3q2p4n5MVRpp3q2yRE4n9cdfg36dEGYieizSgmsoTd hG4hV4XPM1LajeRt4rX5hKfT+Jhigek/NbBofCSkQN9pwNHsm0hEnlJo8B3rkajh MUI+Z4EgwDyOQX1rdQHuaPJkkvNvYvdqFQrKnKyMv2A9E1Uj+OiJ4uJq6fPIbXlW WU3WK5PUa5b5zep4GitPl6jF7sfLcNSz8NwxX0jgXxbYScYtcekYwt381Wn3BY54 yPyfLmI= From: =?utf-8?b?QmVuY2UgQ3PDs2vDoXM=?= To: , , CC: =?utf-8?b?QmVuY2UgQ3PDs2vDoXM=?= , "Kamel Bouhara" , William Breathitt Gray Subject: [PATCH v3 2/2] counter: microchip-tcb-capture: Add capture extensions for registers RA-RC Date: Wed, 5 Feb 2025 11:49:54 +0100 Message-ID: <20250205104957.95236-3-csokas.bence@prolan.hu> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250205104957.95236-1-csokas.bence@prolan.hu> References: <20250205104957.95236-1-csokas.bence@prolan.hu> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ESET-AS: R=OK;S=0;OP=CALC;TIME=1738752602;VERSION=7985;MC=3452472733;ID=233959;TRN=0;CRV=0;IPC=;SP=0;SIPS=0;PI=3;F=0 X-ESET-Antispam: OK X-EsetResult: clean, is OK X-EsetId: 37303A29ACD94852667264 TCB hardware is capable of capturing the timer value to registers RA and RB. On top, it is capable of triggering on compare against a third register, RC. Add these registers as extensions. Signed-off-by: Bence Csókás --- Notes: Changes in v2: * Add IRQs Changes in v3: * Move IRQs to previous patch drivers/counter/microchip-tcb-capture.c | 58 +++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/drivers/counter/microchip-tcb-capture.c b/drivers/counter/microchip-tcb-capture.c index fef4bb69b486..1445ac512c52 100644 --- a/drivers/counter/microchip-tcb-capture.c +++ b/drivers/counter/microchip-tcb-capture.c @@ -253,6 +253,62 @@ static int mchp_tc_count_read(struct counter_device *counter, return 0; } +static int mchp_tc_count_cap_read(struct counter_device *counter, + struct counter_count *count, size_t idx, u64 *val) +{ + struct mchp_tc_data *const priv = counter_priv(counter); + u32 cnt; + + switch (idx) { + case 0: + regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], RA), &cnt); + break; + case 1: + regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], RB), &cnt); + break; + case 2: + regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], RC), &cnt); + break; + default: + return -EINVAL; + } + *val = cnt; + + return 0; +} + +static int mchp_tc_count_cap_write(struct counter_device *counter, + struct counter_count *count, size_t idx, u64 val) +{ + struct mchp_tc_data *const priv = counter_priv(counter); + + if (val > U32_MAX) + return -ERANGE; + + switch (idx) { + case 0: + regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], RA), val); + break; + case 1: + regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], RB), val); + break; + case 2: + regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], RC), val); + break; + default: + return -EINVAL; + } + + return 0; +} + +static DEFINE_COUNTER_ARRAY_CAPTURE(mchp_tc_cnt_cap_array, 3); + +static struct counter_comp mchp_tc_count_ext[] = { + COUNTER_COMP_ARRAY_CAPTURE(mchp_tc_count_cap_read, mchp_tc_count_cap_write, + mchp_tc_cnt_cap_array), +}; + static struct counter_count mchp_tc_counts[] = { { .id = 0, @@ -261,6 +317,8 @@ static struct counter_count mchp_tc_counts[] = { .num_functions = ARRAY_SIZE(mchp_tc_count_functions), .synapses = mchp_tc_count_synapses, .num_synapses = ARRAY_SIZE(mchp_tc_count_synapses), + .ext = mchp_tc_count_ext, + .num_ext = ARRAY_SIZE(mchp_tc_count_ext), }, };