From patchwork Wed Feb 5 13:27:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Russell King (Oracle)" X-Patchwork-Id: 13961060 X-Patchwork-Delegate: kuba@kernel.org Received: from pandora.armlinux.org.uk (pandora.armlinux.org.uk [78.32.30.218]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08F6D39FD9 for ; Wed, 5 Feb 2025 13:27:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=78.32.30.218 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738762079; cv=none; b=EMns7tuNPSC+ajdZzTBuRQnArWtPpNFjsHJZp+kSClVdLfJXDHK6ldsNp56o4xNZ6EMCRnHDS1V9pkW3bYeu1NakqftF4bm9RMsIf4K3lXukpxgdCsyDtlD05FHiVi0rYk56wVqEsz49shUVZKgfAbvernTwFpW4sU5N9DKN4y0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738762079; c=relaxed/simple; bh=TPukQRdEFlVQ0oPmABxaCot4S2cmYCq1h3Vkkpn/UwI=; h=In-Reply-To:References:From:To:Cc:Subject:MIME-Version: Content-Disposition:Content-Type:Message-Id:Date; b=dATGOrcBUqZmPMZ5pon9TN4tFG+dJ7op5QPXw5D+G9oyPstbjg+wCBoh7axlbVmbZS4J5dLKWW9N55u/oIZFgvLRx51kqTnt7N682036RBXpSEWLBqzRimeTOMbWhktGFzUbGpW7D+PUpKzFlJhz+9XE41n4za72Rg5ZwLTGiRQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=armlinux.org.uk; spf=none smtp.mailfrom=armlinux.org.uk; dkim=pass (2048-bit key) header.d=armlinux.org.uk header.i=@armlinux.org.uk header.b=m5hW+ofY; arc=none smtp.client-ip=78.32.30.218 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=armlinux.org.uk Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=armlinux.org.uk Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=armlinux.org.uk header.i=@armlinux.org.uk header.b="m5hW+ofY" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=armlinux.org.uk; s=pandora-2019; h=Date:Sender:Message-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:Subject:Cc:To:From:References: In-Reply-To:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=zhIV5VH9LDN6vTl3HRRd6HkIEuz0uHtIPSi4LyM0640=; b=m5hW+ofYZVHgdu8JXBNreT/rFU k5eH8Qjn9ZkGOUzFiFRXv3u1c7mKWFwRyQiq2KAsMN5QZC0xyuAoom1V29ljk8QwMatvufU7s8gXV gLzR+xX7NgTB53Gy/P3ZpID7lUoHKu4LH+q1MXXmCK2khMd6MEory6vdMHDIxVTU37X6i1f/JnuQB w4rldQcUbWezBbXMNKJV9S2r0aDj3I+3bKMaGB8r0UbMx96nhJRrZYUrpIR1RUsv0NRmo0I/Rg/9o 3kqsMeeSeJwfgKcBt+BiphbWy0Z+VGGG1Va8TmrNpHzIbXQVAQpL1yBzufvISywmCmJjsQ25Z5ztA dOa6NqZQ==; Received: from e0022681537dd.dyn.armlinux.org.uk ([fd8f:7570:feb6:1:222:68ff:fe15:37dd]:50314 helo=rmk-PC.armlinux.org.uk) by pandora.armlinux.org.uk with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1tffRX-00076g-1N; Wed, 05 Feb 2025 13:27:51 +0000 Received: from rmk by rmk-PC.armlinux.org.uk with local (Exim 4.94.2) (envelope-from ) id 1tffRE-003Z5c-0L; Wed, 05 Feb 2025 13:27:32 +0000 In-Reply-To: References: From: "Russell King (Oracle)" To: Tristram.Ha@microchip.com Cc: Vladimir Oltean , UNGLinuxDriver@microchip.com, Woojung Huh , Andrew Lunn , Heiner Kallweit , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , netdev@vger.kernel.org Subject: [PATCH RFC net-next 1/4] net: xpcs: add support for configuring width of 10/100M MII connection Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline Message-Id: Sender: Russell King Date: Wed, 05 Feb 2025 13:27:32 +0000 X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC When in SGMII mode, the hardware can be configured to use either 4-bit or 8-bit MII connection. Currently, we don't change this bit for most implementations with the exception of TXGBE requiring 8-bit. Move this decision to the creation code and act on it when configuring SGMII. Signed-off-by: Russell King (Oracle) --- drivers/net/pcs/pcs-xpcs.c | 19 +++++++++++++++---- drivers/net/pcs/pcs-xpcs.h | 8 ++++++++ 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c index 1faa37f0e7b9..12a3d5a80b45 100644 --- a/drivers/net/pcs/pcs-xpcs.c +++ b/drivers/net/pcs/pcs-xpcs.c @@ -695,9 +695,18 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, DW_VR_MII_PCS_MODE_C37_SGMII); - if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { - mask |= DW_VR_MII_AN_CTRL_8BIT; + switch (xpcs->sgmii_10_100_8bit) { + case DW_XPCS_SGMII_10_100_8BIT: val |= DW_VR_MII_AN_CTRL_8BIT; + fallthrough; + case DW_XPCS_SGMII_10_100_4BIT: + mask |= DW_VR_MII_AN_CTRL_8BIT; + fallthrough; + case DW_XPCS_SGMII_10_100_UNCHANGED: + break; + } + + if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { /* Hardware requires it to be PHY side SGMII */ tx_conf = DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII; } else { @@ -1450,10 +1459,12 @@ static struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev) xpcs_get_interfaces(xpcs, xpcs->pcs.supported_interfaces); - if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) + if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { xpcs->pcs.poll = false; - else + xpcs->sgmii_10_100_8bit = DW_XPCS_SGMII_10_100_8BIT; + } else { xpcs->need_reset = true; + } return xpcs; diff --git a/drivers/net/pcs/pcs-xpcs.h b/drivers/net/pcs/pcs-xpcs.h index adc5a0b3c883..4d53ccf917f3 100644 --- a/drivers/net/pcs/pcs-xpcs.h +++ b/drivers/net/pcs/pcs-xpcs.h @@ -114,6 +114,12 @@ enum dw_xpcs_clock { DW_XPCS_NUM_CLKS, }; +enum dw_xpcs_sgmii_10_100 { + DW_XPCS_SGMII_10_100_UNCHANGED, + DW_XPCS_SGMII_10_100_4BIT, + DW_XPCS_SGMII_10_100_8BIT +}; + struct dw_xpcs { struct dw_xpcs_info info; const struct dw_xpcs_desc *desc; @@ -122,6 +128,8 @@ struct dw_xpcs { struct phylink_pcs pcs; phy_interface_t interface; bool need_reset; + /* Width of the MII MAC/XPCS interface in 100M and 10M modes */ + enum dw_xpcs_sgmii_10_100 sgmii_10_100_8bit; }; int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg); From patchwork Wed Feb 5 13:27:37 2025 Content-Type: text/plain; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , netdev@vger.kernel.org Subject: [PATCH RFC net-next 2/4] net: xpcs: add SGMII mode setting Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline Message-Id: Sender: Russell King Date: Wed, 05 Feb 2025 13:27:37 +0000 X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Add SGMII mode setting which configures whether XPCS immitates the MAC end of the link or the PHY end, and in the latter case, where the data for generating the link's configuration word comes from. This ties up all the register bits necessary to configure this mode into one control. Set this to PHY_HW mode for TXGBE. Signed-off-by: Russell King (Oracle) --- drivers/net/pcs/pcs-xpcs.c | 19 +++++++++++-------- drivers/net/pcs/pcs-xpcs.h | 14 ++++++++++++++ 2 files changed, 25 insertions(+), 8 deletions(-) diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c index 12a3d5a80b45..9d54c04ef6ee 100644 --- a/drivers/net/pcs/pcs-xpcs.c +++ b/drivers/net/pcs/pcs-xpcs.c @@ -706,12 +706,10 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, break; } - if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { - /* Hardware requires it to be PHY side SGMII */ - tx_conf = DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII; - } else { + if (xpcs->sgmii_mode == DW_XPCS_SGMII_MODE_MAC) tx_conf = DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII; - } + else + tx_conf = DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII; val |= FIELD_PREP(DW_VR_MII_TX_CONFIG_MASK, tx_conf); @@ -722,12 +720,16 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, val = 0; mask = DW_VR_MII_DIG_CTRL1_2G5_EN | DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; - if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) - val = DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; + switch (xpcs->sgmii_mode) { + case DW_XPCS_SGMII_MODE_MAC: + if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) + val = DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; + break; - if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { + case DW_XPCS_SGMII_MODE_PHY_HW: mask |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL; val |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL; + break; } ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, mask, val); @@ -1462,6 +1464,7 @@ static struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev) if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { xpcs->pcs.poll = false; xpcs->sgmii_10_100_8bit = DW_XPCS_SGMII_10_100_8BIT; + xpcs->sgmii_mode = DW_XPCS_SGMII_MODE_PHY_HW; } else { xpcs->need_reset = true; } diff --git a/drivers/net/pcs/pcs-xpcs.h b/drivers/net/pcs/pcs-xpcs.h index 4d53ccf917f3..892b85425787 100644 --- a/drivers/net/pcs/pcs-xpcs.h +++ b/drivers/net/pcs/pcs-xpcs.h @@ -120,6 +120,19 @@ enum dw_xpcs_sgmii_10_100 { DW_XPCS_SGMII_10_100_8BIT }; +/* The SGMII mode: + * DW_XPCS_SGMII_MODE_MAC: the XPCS acts as a MAC, reading and acknowledging + * the config word. + * + * DW_XPCS_SGMII_MODE_PHY_HW: the XPCS acts as a PHY, deriving the tx_config + * bits 15 (link), 12 (duplex) and 11:10 (speed) from hardware inputs to the + * XPCS. + */ +enum dw_xpcs_sgmii_mode { + DW_XPCS_SGMII_MODE_MAC, /* XPCS is MAC on SGMII */ + DW_XPCS_SGMII_MODE_PHY_HW, /* XPCS is PHY, tx_config from hw */ +}; + struct dw_xpcs { struct dw_xpcs_info info; const struct dw_xpcs_desc *desc; @@ -130,6 +143,7 @@ struct dw_xpcs { bool need_reset; /* Width of the MII MAC/XPCS interface in 100M and 10M modes */ enum dw_xpcs_sgmii_10_100 sgmii_10_100_8bit; + enum dw_xpcs_sgmii_mode sgmii_mode; }; int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg); From patchwork Wed Feb 5 13:27:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Russell King (Oracle)" X-Patchwork-Id: 13961062 X-Patchwork-Delegate: kuba@kernel.org Received: from pandora.armlinux.org.uk (pandora.armlinux.org.uk [78.32.30.218]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48FCF39FD9 for ; Wed, 5 Feb 2025 13:28:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=78.32.30.218 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Received: from e0022681537dd.dyn.armlinux.org.uk ([fd8f:7570:feb6:1:222:68ff:fe15:37dd]:57970 helo=rmk-PC.armlinux.org.uk) by pandora.armlinux.org.uk with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1tffRh-000777-30; Wed, 05 Feb 2025 13:28:01 +0000 Received: from rmk by rmk-PC.armlinux.org.uk with local (Exim 4.94.2) (envelope-from ) id 1tffRO-003Z5o-8u; Wed, 05 Feb 2025 13:27:42 +0000 In-Reply-To: References: From: "Russell King (Oracle)" To: Tristram.Ha@microchip.com Cc: Vladimir Oltean , UNGLinuxDriver@microchip.com, Woojung Huh , Andrew Lunn , Heiner Kallweit , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , netdev@vger.kernel.org Subject: [PATCH RFC net-next 3/4] net: xpcs: add SGMII MAC manual update mode Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline Message-Id: Sender: Russell King Date: Wed, 05 Feb 2025 13:27:42 +0000 X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Older revisions of the XPCS IP do not support the MAC_AUTO_SW flag and need the BMCR register updated with the speed information from the PHY. Split the DW_XPCS_SGMII_MODE_MAC mode into _AUTO and _MANUAL variants, where _AUTO mode means the update happens in hardware autonomously, whereas the _MANUAL mode means that we need to update the BMCR register when the link comes up. This will be required for the older XPCS IP found in KSZ9477. Signed-off-by: Russell King (Oracle) --- This needs further input from Tristram Ha / Microchip to work out a way to detect KSZ9477 and set DW_XPCS_SGMII_MODE_MAC_MANUAL. On its own, this patch does nothing. --- drivers/net/pcs/pcs-xpcs.c | 19 +++++++++++++------ drivers/net/pcs/pcs-xpcs.h | 11 ++++++++--- 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c index 9d54c04ef6ee..1eba0c583f16 100644 --- a/drivers/net/pcs/pcs-xpcs.c +++ b/drivers/net/pcs/pcs-xpcs.c @@ -706,7 +706,8 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, break; } - if (xpcs->sgmii_mode == DW_XPCS_SGMII_MODE_MAC) + if (xpcs->sgmii_mode == DW_XPCS_SGMII_MODE_MAC_AUTO || + xpcs->sgmii_mode == DW_XPCS_SGMII_MODE_MAC_MANUAL) tx_conf = DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII; else tx_conf = DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII; @@ -721,11 +722,14 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, mask = DW_VR_MII_DIG_CTRL1_2G5_EN | DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; switch (xpcs->sgmii_mode) { - case DW_XPCS_SGMII_MODE_MAC: + case DW_XPCS_SGMII_MODE_MAC_AUTO: if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) val = DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; break; + case DW_XPCS_SGMII_MODE_MAC_MANUAL: + break; + case DW_XPCS_SGMII_MODE_PHY_HW: mask |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL; val |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL; @@ -1151,7 +1155,9 @@ static void xpcs_link_up_sgmii_1000basex(struct dw_xpcs *xpcs, { int ret; - if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) + if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED && + !(interface == PHY_INTERFACE_MODE_SGMII && + xpcs->sgmii_mode == DW_XPCS_SGMII_MODE_MAC_MANUAL)) return; if (interface == PHY_INTERFACE_MODE_1000BASEX) { @@ -1168,10 +1174,11 @@ static void xpcs_link_up_sgmii_1000basex(struct dw_xpcs *xpcs, __func__); } - ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, - mii_bmcr_encode_fixed(speed, duplex)); + ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, + BMCR_SPEED1000 | BMCR_FULLDPLX | BMCR_SPEED100, + mii_bmcr_encode_fixed(speed, duplex)); if (ret) - dev_err(&xpcs->mdiodev->dev, "%s: xpcs_write returned %pe\n", + dev_err(&xpcs->mdiodev->dev, "%s: xpcs_modify returned %pe\n", __func__, ERR_PTR(ret)); } diff --git a/drivers/net/pcs/pcs-xpcs.h b/drivers/net/pcs/pcs-xpcs.h index 892b85425787..96117bd9e2b6 100644 --- a/drivers/net/pcs/pcs-xpcs.h +++ b/drivers/net/pcs/pcs-xpcs.h @@ -121,15 +121,20 @@ enum dw_xpcs_sgmii_10_100 { }; /* The SGMII mode: - * DW_XPCS_SGMII_MODE_MAC: the XPCS acts as a MAC, reading and acknowledging - * the config word. + * DW_XPCS_SGMII_MODE_MAC_AUTO: the XPCS acts as a MAC, accepting the + * parameters from the PHY end of the SGMII link and acknowledging the + * config word. The XPCS autonomously switches speed. + * + * DW_XPCS_SGMII_MODE_MAC_MANUAL: the XPCS acts as a MAC as above, but + * does not autonomously switch speed. * * DW_XPCS_SGMII_MODE_PHY_HW: the XPCS acts as a PHY, deriving the tx_config * bits 15 (link), 12 (duplex) and 11:10 (speed) from hardware inputs to the * XPCS. */ enum dw_xpcs_sgmii_mode { - DW_XPCS_SGMII_MODE_MAC, /* XPCS is MAC on SGMII */ + DW_XPCS_SGMII_MODE_MAC_AUTO, /* XPCS is MAC, auto update */ + DW_XPCS_SGMII_MODE_MAC_MANUAL, /* XPCS is MAC, manual update */ DW_XPCS_SGMII_MODE_PHY_HW, /* XPCS is PHY, tx_config from hw */ }; From patchwork Wed Feb 5 13:27:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Russell King (Oracle)" X-Patchwork-Id: 13961063 X-Patchwork-Delegate: kuba@kernel.org Received: from pandora.armlinux.org.uk (pandora.armlinux.org.uk [78.32.30.218]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8CA7127E18 for ; Wed, 5 Feb 2025 13:28:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=78.32.30.218 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738762096; cv=none; b=pQka0Fxjgj1fkl++Ezd575zeSYw7+76ZLad2aShjmZKRAnRhfwvFdi4FzyIDulrULjH2nEEiJhKRCfWLbwOy0uBEJFls4nJVF+RBYyOTYpaSnnyF4806rIj3k0DYPw9W4qB8sMS6/uc445Adk/E8mAdkacYCG/cKyA+hN7bWh/g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738762096; c=relaxed/simple; bh=s4FRzLkdbDAVdmpko115M+dWhUuMIPAQFvO2jZlQMvI=; h=In-Reply-To:References:From:To:Cc:Subject:MIME-Version: Content-Disposition:Content-Type:Message-Id:Date; b=uz1O5PxydlRuc1gVyHFvpkqgvGYm3WEYOMS8a36fklWt0SKJGTnYzvwlizLZK1H5VTITwncKLDtpBjd34alCS8ql05gdniwYWVPZl8MS3If3AZlILlf+c5uhGa8kfVV/vhxYJFwf6u6qsVx92aeh589Ehh9sDboh8Sd/bfimWak= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=armlinux.org.uk; spf=none smtp.mailfrom=armlinux.org.uk; dkim=pass (2048-bit key) header.d=armlinux.org.uk header.i=@armlinux.org.uk header.b=ZsTVMC6/; arc=none smtp.client-ip=78.32.30.218 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=armlinux.org.uk Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=armlinux.org.uk Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=armlinux.org.uk header.i=@armlinux.org.uk header.b="ZsTVMC6/" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=armlinux.org.uk; s=pandora-2019; h=Date:Sender:Message-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:Subject:Cc:To:From:References: In-Reply-To:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=Js/PGKYXmZWwi4mSKiZuKnNk6qnIeCvWDO0obIBgBwk=; b=ZsTVMC6/Nb9Z7WCEf3+VZJkGer ho/OMg8jbETgc+EFNyrzm9K2XyVb4yik+opRYnFzfS9Vewlm1AFVNiCT4ZMcNxKe7GTUc+h7PaNJR 3eeZZ8CV9f6xvzhuOds4+IKUPQyj0/MF7VJBMbwJSogAoCqLB1Iwl/emOLDFXeioS8HkWz9/6N91S mg1mSK9TGeosY03bqePQ3H7hvOtdsjFDNeAaxZCdkyrzqif/skY8i8VLo1y1muP6vF9LIKp6X0E20 Md05WYFokv7Uou0HzqdV5YUjop/VGBbgzUvLtEqb/DdOo0NFWq/USR3zQlKXrF/Knm/VSQ94DRsvv kIEPlsKg==; Received: from e0022681537dd.dyn.armlinux.org.uk ([fd8f:7570:feb6:1:222:68ff:fe15:37dd]:57974 helo=rmk-PC.armlinux.org.uk) by pandora.armlinux.org.uk with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1tffRn-00077N-0A; Wed, 05 Feb 2025 13:28:07 +0000 Received: from rmk by rmk-PC.armlinux.org.uk with local (Exim 4.94.2) (envelope-from ) id 1tffRT-003Z5u-CY; Wed, 05 Feb 2025 13:27:47 +0000 In-Reply-To: References: From: "Russell King (Oracle)" To: Tristram.Ha@microchip.com Cc: Vladimir Oltean , UNGLinuxDriver@microchip.com, Woojung Huh , Andrew Lunn , Heiner Kallweit , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , netdev@vger.kernel.org Subject: [PATCH RFC net-next 4/4] net: xpcs: allow 1000BASE-X to work with older XPCS IP Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline Message-Id: Sender: Russell King Date: Wed, 05 Feb 2025 13:27:47 +0000 X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Older XPCS IP requires SGMII_LINK and PHY_SIDE_SGMII to be set when operating in 1000BASE-X mode even though the XPCS is not configured for SGMII. An example of a device with older XPCS IP is KSZ9477. We already don't clear these bits if we switch from SGMII to 1000BASE-X on TXGBE - which would result in 1000BASE-X with the PHY_SIDE_SGMII bit left set. It is currently believed to be safe to set both bits on newer IP without side-effects. Signed-off-by: Russell King (Oracle) --- drivers/net/pcs/pcs-xpcs.c | 13 +++++++++++-- drivers/net/pcs/pcs-xpcs.h | 1 + 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c index 1eba0c583f16..d522e4a5a138 100644 --- a/drivers/net/pcs/pcs-xpcs.c +++ b/drivers/net/pcs/pcs-xpcs.c @@ -774,9 +774,18 @@ static int xpcs_config_aneg_c37_1000basex(struct dw_xpcs *xpcs, return ret; } - mask = DW_VR_MII_PCS_MODE_MASK; + /* Older XPCS IP requires PHY_MODE (bit 3) and SGMII_LINK (but 4) to + * be set when operating in 1000BASE-X mode. See page 233 + * https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/KSZ9477S-Data-Sheet-DS00002392C.pdf + * "5.5.9 SGMII AUTO-NEGOTIATION CONTROL REGISTER" + */ + mask = DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_AN_CTRL_SGMII_LINK | + DW_VR_MII_TX_CONFIG_MASK; val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, - DW_VR_MII_PCS_MODE_C37_1000BASEX); + DW_VR_MII_PCS_MODE_C37_1000BASEX) | + FIELD_PREP(DW_VR_MII_TX_CONFIG_MASK, + DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII) | + DW_VR_MII_AN_CTRL_SGMII_LINK; if (!xpcs->pcs.poll) { mask |= DW_VR_MII_AN_INTR_EN; diff --git a/drivers/net/pcs/pcs-xpcs.h b/drivers/net/pcs/pcs-xpcs.h index 96117bd9e2b6..f0ddd93c7a22 100644 --- a/drivers/net/pcs/pcs-xpcs.h +++ b/drivers/net/pcs/pcs-xpcs.h @@ -73,6 +73,7 @@ /* VR_MII_AN_CTRL */ #define DW_VR_MII_AN_CTRL_8BIT BIT(8) +#define DW_VR_MII_AN_CTRL_SGMII_LINK BIT(4) #define DW_VR_MII_TX_CONFIG_MASK BIT(3) #define DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII 0x1 #define DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII 0x0