From patchwork Wed Feb 5 15:32:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steffen Trumtrar X-Patchwork-Id: 13961373 X-Patchwork-Delegate: kuba@kernel.org Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35F7A170A13 for ; Wed, 5 Feb 2025 15:32:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738769575; cv=none; b=SQRH9eLzefJpVOjvuLs7usErOhVyvUFCh0ToOpLD8EwcyBJAuV46hW6wEmzxkp8hakpN23w+VTulrX6rD9aTTcZTaLynYQk5a0t6AV32115DggMWAYYRmqqnCGqS4pnSIs6cacCvloiGPnzTg6y06XYGVItMp65Z9V4nynfZ5Ps= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738769575; c=relaxed/simple; bh=PIjNKPS9QHGFUF7IHhdlZL57aWxOxIWpDcXLIWAma+k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bJt3Hqj8PG0xTS8j/M6gw1WRen2T4WjcRuqKBuHmBKwrIcRT6rE23d1Zn85L81hideF0QlQCclJvMTHb+k1r3Ksy2mHq3rjoJQtgFYoeyyLyas6yq8kmAPYrLAB84X2CcRPBJywNmuCxoIn8kz1hbLQQWNHx0wveryoxWh1n9Xw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from ptz.office.stw.pengutronix.de ([2a0a:edc0:0:900:1d::77] helo=ratatoskr.trumtrar.info) by metis.whiteo.stw.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1tfhOJ-0005Jb-DW; Wed, 05 Feb 2025 16:32:39 +0100 From: Steffen Trumtrar Date: Wed, 05 Feb 2025 16:32:22 +0100 Subject: [PATCH v4 1/6] dt-bindings: socfpga-dwmac: fix typo Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250205-v6-12-topic-socfpga-agilex5-v4-1-ebf070e2075f@pengutronix.de> References: <20250205-v6-12-topic-socfpga-agilex5-v4-0-ebf070e2075f@pengutronix.de> In-Reply-To: <20250205-v6-12-topic-socfpga-agilex5-v4-0-ebf070e2075f@pengutronix.de> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dinh Nguyen Cc: kernel@pengutronix.de, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Steffen Trumtrar X-Mailer: b4 0.14.2 X-SA-Exim-Connect-IP: 2a0a:edc0:0:900:1d::77 X-SA-Exim-Mail-From: s.trumtrar@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The phandle to the SGMII converter must be called "altr,gmii-to-sgmii-converter". This is how the phandle is called in the example and the driver. As there are no upstream users of this binding anyway, this shouldn't break anything. Signed-off-by: Steffen Trumtrar --- Documentation/devicetree/bindings/net/socfpga-dwmac.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt index 612a8e8abc88774619f4fd4e9205a3dd32226a9b..67784463f6f5a3ba7d2e10810810ab2d51715842 100644 --- a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt +++ b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt @@ -24,7 +24,7 @@ Optional properties: altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if DWMAC controller is connected emac splitter. phy-mode: The phy mode the ethernet operates in -altr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter +altr,gmii-to-sgmii-converter: phandle to the TSE SGMII converter This device node has additional phandle dependency, the sgmii converter: From patchwork Wed Feb 5 15:32:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steffen Trumtrar X-Patchwork-Id: 13961377 X-Patchwork-Delegate: kuba@kernel.org Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B211919259A for ; Wed, 5 Feb 2025 15:32:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738769577; cv=none; b=P0hFPIgHMntT6USAPSjmLXOU8kigF65xASk+WruYFvbBSyZSLdF6Ah9gAaAzeiwMRWmF82625Q+j+MJ6LPlbqBm2UUqgiXWemfkFtM4pwmPH1tzsLPH6jxKgXA5IKlXhcLd+tX+kCsuOW85U1f2p64ExzJlHNd/apDSY8mmoGVg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738769577; c=relaxed/simple; bh=dHRUYJ/MnsjiK8Dl07HnCAQq/MHCPjJBp6vjgTdrRCM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=V1MXaxX2t1SkGKhrhD2hOWH1ew3kZezRkVRb7COZy7bAod/JhlLpnucTEVoH2Qx4tUX4WH+81w0wALGVgP4mGaaTfOTJbag8DUDjI08iDI/8POq8P3ULGJKSSyENPTW1TjcBOXasv1WDZIU3RvcthjdXBBE21o5Pb9KIn4l+jMU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from ptz.office.stw.pengutronix.de ([2a0a:edc0:0:900:1d::77] helo=ratatoskr.trumtrar.info) by metis.whiteo.stw.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1tfhOK-0005Jb-6n; Wed, 05 Feb 2025 16:32:40 +0100 From: Steffen Trumtrar Date: Wed, 05 Feb 2025 16:32:23 +0100 Subject: [PATCH v4 2/6] dt-bindings: net: dwmac: Convert socfpga dwmac to DT schema Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250205-v6-12-topic-socfpga-agilex5-v4-2-ebf070e2075f@pengutronix.de> References: <20250205-v6-12-topic-socfpga-agilex5-v4-0-ebf070e2075f@pengutronix.de> In-Reply-To: <20250205-v6-12-topic-socfpga-agilex5-v4-0-ebf070e2075f@pengutronix.de> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dinh Nguyen Cc: kernel@pengutronix.de, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Steffen Trumtrar X-Mailer: b4 0.14.2 X-SA-Exim-Connect-IP: 2a0a:edc0:0:900:1d::77 X-SA-Exim-Mail-From: s.trumtrar@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Changes to the binding while converting: - add "snps,dwmac-3.7{0,2,4}a". They are used, but undocumented. - altr,f2h_ptp_ref_clk is not a required property but optional. Signed-off-by: Steffen Trumtrar --- .../bindings/net/pcs/altr,gmii-to-sgmii.yaml | 47 ++++++++++ .../devicetree/bindings/net/socfpga-dwmac.txt | 57 ------------ .../devicetree/bindings/net/socfpga-dwmac.yaml | 102 +++++++++++++++++++++ 3 files changed, 149 insertions(+), 57 deletions(-) diff --git a/Documentation/devicetree/bindings/net/pcs/altr,gmii-to-sgmii.yaml b/Documentation/devicetree/bindings/net/pcs/altr,gmii-to-sgmii.yaml new file mode 100644 index 0000000000000000000000000000000000000000..1b7b69b2e396a508dfbb2c56399302b1cd1ce658 --- /dev/null +++ b/Documentation/devicetree/bindings/net/pcs/altr,gmii-to-sgmii.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pcs/altr,gmii-to-sgmii.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera SOCFPGA Triple Speed Ethernet GMII-to-SGMII converter + +maintainers: + - Dinh Nguyen + +description: + The Altera Triple Speed Ethernet controller provides a SGMII PCS and some clocks + to the ethernet subsystem to which it is attached. + +properties: + compatible: + const: altr,gmii-to-sgmii-2.0 + + reg: + maxItems: 6 + + reg-names: + const: eth_tse_control_port + + clocks-names: + items: + - const: tse_pcs_ref_clk_clock_connection + - const: tse_rx_cdr_refclk + +required: + - compatible + - reg + - reg-names + +additionalProperties: false + +examples: + - | + gmii_to_sgmii_converter: phy@100000240 { + compatible = "altr,gmii-to-sgmii-2.0"; + reg = <0x00000001 0x00000240 0x00000008>, + <0x00000001 0x00000200 0x00000040>; + reg-names = "eth_tse_control_port"; + clocks = <&sgmii_1_clk_0 &emac1 1 &sgmii_clk_125 &sgmii_clk_125>; + clock-names = "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk"; + }; diff --git a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt deleted file mode 100644 index 67784463f6f5a3ba7d2e10810810ab2d51715842..0000000000000000000000000000000000000000 --- a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt +++ /dev/null @@ -1,57 +0,0 @@ -Altera SOCFPGA SoC DWMAC controller - -This is a variant of the dwmac/stmmac driver an inherits all descriptions -present in Documentation/devicetree/bindings/net/stmmac.txt. - -The device node has additional properties: - -Required properties: - - compatible : For Cyclone5/Arria5 SoCs it should contain - "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs - "altr,socfpga-stmmac-a10-s10". - Along with "snps,dwmac" and any applicable more detailed - designware version numbers documented in stmmac.txt - - altr,sysmgr-syscon : Should be the phandle to the system manager node that - encompasses the glue register, the register offset, and the register shift. - On Cyclone5/Arria5, the register shift represents the PHY mode bits, while - on the Arria10/Stratix10/Agilex platforms, the register shift represents - bit for each emac to enable/disable signals from the FPGA fabric to the - EMAC modules. - - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock - for ptp ref clk. This affects all emacs as the clock is common. - -Optional properties: -altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if - DWMAC controller is connected emac splitter. -phy-mode: The phy mode the ethernet operates in -altr,gmii-to-sgmii-converter: phandle to the TSE SGMII converter - -This device node has additional phandle dependency, the sgmii converter: - -Required properties: - - compatible : Should be altr,gmii-to-sgmii-2.0 - - reg-names : Should be "eth_tse_control_port" - -Example: - -gmii_to_sgmii_converter: phy@100000240 { - compatible = "altr,gmii-to-sgmii-2.0"; - reg = <0x00000001 0x00000240 0x00000008>, - <0x00000001 0x00000200 0x00000040>; - reg-names = "eth_tse_control_port"; - clocks = <&sgmii_1_clk_0 &emac1 1 &sgmii_clk_125 &sgmii_clk_125>; - clock-names = "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk"; -}; - -gmac0: ethernet@ff700000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x60 0>; - reg = <0xff700000 0x2000>; - interrupts = <0 115 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ - clocks = <&emac_0_clk>; - clock-names = "stmmaceth"; - phy-mode = "sgmii"; - altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>; -}; diff --git a/Documentation/devicetree/bindings/net/socfpga-dwmac.yaml b/Documentation/devicetree/bindings/net/socfpga-dwmac.yaml new file mode 100644 index 0000000000000000000000000000000000000000..2568dd90f4555485f18912b5352f191824bb918c --- /dev/null +++ b/Documentation/devicetree/bindings/net/socfpga-dwmac.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/socfpga-dwmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera SOCFPGA SoC DWMAC controller + +maintainers: + - Dinh Nguyen + +description: + This is a variant of the dwmac/stmmac driver an inherits all descriptions + present in Documentation/devicetree/bindings/net/stmmac.txt. + +# We need a select here so we don't match all nodes with 'snps,dwmac' +select: + properties: + compatible: + contains: + enum: + - altr,socfpga-stmmac # For Cyclone5/Arria5 SoCs + - altr,socfpga-stmmac-a10-s10 # For Arria10/Agilex/Stratix10 SoCs + required: + - compatible + +allOf: + - $ref: snps,dwmac.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - altr,socfpga-stmmac + - const: snps,dwmac-3.70a + - const: snps,dwmac + - items: + - enum: + - altr,socfpga-stmmac-a10-s10 + - const: snps,dwmac-3.72a + - const: snps,dwmac + - items: + - enum: + - altr,socfpga-stmmac-a10-s10 + - const: snps,dwmac-3.74a + - const: snps,dwmac + + altr,sysmgr-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the sysmgr node + - description: register offset that controls the PHY mode or FPGA signals + - description: register shift for the PHY mode bits or FPGA signals + description: + Should be the phandle to the system manager node that + encompasses the glue register, the register offset, and the register shift. + On Cyclone5/Arria5, the register shift represents the PHY mode bits, while + on the Arria10/Stratix10/Agilex platforms, the register shift represents + bit for each emac to enable/disable signals from the FPGA fabric to the + EMAC modules. + + altr,f2h_ptp_ref_clk: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Use f2h_ptp_ref_clk instead of default eosc1 clock + for ptp ref clk. This affects all emacs as the clock is common. + + altr,emac-splitter: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Should be the phandle to the emac splitter soft IP node if + DWMAC controller is connected emac splitter. + + altr,gmii-to-sgmii-converter: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the TSE SGMII converter. + +required: + - compatible + - reg + - altr,sysmgr-syscon + +additionalProperties: true + +examples: + - | + //Example 1 + gmac0: ethernet@ff700000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x60 0>; + reg = <0xff700000 0x2000>; + interrupts = <0 115 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ + clocks = <&emac_0_clk>; + clock-names = "stmmaceth"; + phy-mode = "sgmii"; + altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>; + }; From patchwork Wed Feb 5 15:32:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steffen Trumtrar X-Patchwork-Id: 13961374 X-Patchwork-Delegate: kuba@kernel.org Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF7CE1DA31F for ; Wed, 5 Feb 2025 15:32:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738769576; cv=none; b=eh344qxR6180PFrUdQya3mmnRDCTT0+gPhfAsAiCbbCmD6nPVSiH89HJeMnYQOy8mwfUDBnBGK5GuHE5Jlle6etqDFJ+svZ7lACgTVJLt3hU4+HyN8xK7ZsUdHB5ht4Uabth4xH67RSoTnYwwNsftp0MKCR7FTdEdvtBRia4nHw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738769576; c=relaxed/simple; bh=W6EXVDRclBOqT165c+5pG3UXqmPzGOlJeB0NP+pr+eg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ggWSLbCpO7TN/S5+OagpAkC8KybNl+NawneA6TKGpx35/vnmPf1TxBIhkpuzodH5qLe8Cyq/EIZg6VeexllxmfZ5oH5QZjip6C2LtsYm9Rddm9tZK9s8cYZhhSJmX4H+6tCifhRNobE/ZzO6MBEFonwCrCMT6poftQcBXUGRoQM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from ptz.office.stw.pengutronix.de ([2a0a:edc0:0:900:1d::77] helo=ratatoskr.trumtrar.info) by metis.whiteo.stw.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1tfhOK-0005Jb-UX; Wed, 05 Feb 2025 16:32:40 +0100 From: Steffen Trumtrar Date: Wed, 05 Feb 2025 16:32:24 +0100 Subject: [PATCH v4 3/6] dt-bindings: net: dwmac: add compatible for Agilex5 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250205-v6-12-topic-socfpga-agilex5-v4-3-ebf070e2075f@pengutronix.de> References: <20250205-v6-12-topic-socfpga-agilex5-v4-0-ebf070e2075f@pengutronix.de> In-Reply-To: <20250205-v6-12-topic-socfpga-agilex5-v4-0-ebf070e2075f@pengutronix.de> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dinh Nguyen Cc: kernel@pengutronix.de, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Steffen Trumtrar X-Mailer: b4 0.14.2 X-SA-Exim-Connect-IP: 2a0a:edc0:0:900:1d::77 X-SA-Exim-Mail-From: s.trumtrar@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The Agilex5 SoCs have three Synopsys DWXGMAC-compatible ethernet IP-cores. Add a SoC-specific front compatible to the binding. Signed-off-by: Steffen Trumtrar --- Documentation/devicetree/bindings/net/socfpga-dwmac.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/net/socfpga-dwmac.yaml b/Documentation/devicetree/bindings/net/socfpga-dwmac.yaml index 2568dd90f4555485f18912b5352f191824bb918c..31c163bf1b59e14216d1fb4b4b9aaa747e1b19e2 100644 --- a/Documentation/devicetree/bindings/net/socfpga-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/socfpga-dwmac.yaml @@ -21,6 +21,7 @@ select: enum: - altr,socfpga-stmmac # For Cyclone5/Arria5 SoCs - altr,socfpga-stmmac-a10-s10 # For Arria10/Agilex/Stratix10 SoCs + - altr,socfpga-stmmac-agilex5 # For Agilex5 SoCs required: - compatible @@ -45,6 +46,12 @@ properties: - altr,socfpga-stmmac-a10-s10 - const: snps,dwmac-3.74a - const: snps,dwmac + - items: + - enum: + - altr,socfpga-stmmac-agilex5 + - const: altr,socfpga-stmmac-a10-s10 + - const: snps,dwxgmac-2.10 + - const: snps,dwxgmac altr,sysmgr-syscon: $ref: /schemas/types.yaml#/definitions/phandle-array From patchwork Wed Feb 5 15:32:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steffen Trumtrar X-Patchwork-Id: 13961375 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A3F81DA628 for ; Wed, 5 Feb 2025 15:32:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738769576; cv=none; b=DMJqAVyc40rCVBuavqR2IJxayG85MvEGtvhXidXmBRDdHZcygAmtfb0HJs7HaP6T9vPulkneIx1/shBh1g4LUFXtf6uO7P8guHTb97be9fnmwcx9wKHDaWIB7elR5+WlWy4arB54N5VnEJBIC3kveqH/r3x+X2SIfkP7BifBoYU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738769576; c=relaxed/simple; bh=La5zx3Qvv38baoWL9CvoEcR77JLw7HpuWy4xOz2jhoU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cK8KWMQMNiPKPoW/eZKwHRtbtEDLrt2B0GXu37YgUJ7OaQkqDvGGNeW98IpXJh8Azd4cRqeVo5TgqQ0P2CLRtHd1nhGYTJGTWtj5nMr4YVanoyL6rh6VvPijoNTLQEI7mnKHynyA2Z8eGQbXu8vrHuAMxvJHdOFpOCr3UIjfqUk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from ptz.office.stw.pengutronix.de ([2a0a:edc0:0:900:1d::77] helo=ratatoskr.trumtrar.info) by metis.whiteo.stw.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1tfhOL-0005Jb-Mc; Wed, 05 Feb 2025 16:32:41 +0100 From: Steffen Trumtrar Date: Wed, 05 Feb 2025 16:32:25 +0100 Subject: [PATCH v4 4/6] arm64: dts: agilex5: add gmac nodes Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250205-v6-12-topic-socfpga-agilex5-v4-4-ebf070e2075f@pengutronix.de> References: <20250205-v6-12-topic-socfpga-agilex5-v4-0-ebf070e2075f@pengutronix.de> In-Reply-To: <20250205-v6-12-topic-socfpga-agilex5-v4-0-ebf070e2075f@pengutronix.de> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dinh Nguyen Cc: kernel@pengutronix.de, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Steffen Trumtrar X-Mailer: b4 0.14.2 X-SA-Exim-Connect-IP: 2a0a:edc0:0:900:1d::77 X-SA-Exim-Mail-From: s.trumtrar@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: netdev@vger.kernel.org The Agilex5 provides three Synopsys XGMAC ethernet cores, that can be used to transmit and receive data at 10M/100M/1G/2.5G over ethernet connections and enables support for Time Sensitive Networking (TSN) applications. Signed-off-by: Steffen Trumtrar --- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 90 ++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index 51c6e19e40b843adbdb58cfa987878d5b0bbb652..6a9f76cfdf8ea51c4f3498e9f20ef143cb3dae5a 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -141,6 +141,96 @@ soc: soc@0 { device_type = "soc"; interrupt-parent = <&intc>; + gmac0: ethernet@10810000 { + compatible = "altr,socfpga-stmmac-agilex5", + "altr,socfpga-stmmac-a10-s10", + "snps,dwxgmac-2.10", + "snps,dwxgmac"; + reg = <0x10810000 0x3500>; + interrupt-parent = <&intc>; + interrupts = ; + interrupt-names = "macirq"; + max-frame-size = <3800>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <64>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <32768>; + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; + reset-names = "stmmaceth", "ahb"; + clocks = <&clkmgr AGILEX5_EMAC0_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + snps,axi-config = <&stmmac_axi_emac0_setup>; + altr,sysmgr-syscon = <&sysmgr 0x44 0>; + status = "disabled"; + + stmmac_axi_emac0_setup: stmmac-axi-config { + snps,wr_osr_lmt = <31>; + snps,rd_osr_lmt = <31>; + snps,blen = <0 0 0 32 16 8 4>; + }; + }; + + gmac1: ethernet@10820000 { + compatible = "altr,socfpga-stmmac-agilex5", + "altr,socfpga-stmmac-a10-s10", + "snps,dwxgmac-2.10", + "snps,dwxgmac"; + reg = <0x10820000 0x3500>; + interrupt-parent = <&intc>; + interrupts = ; + interrupt-names = "macirq"; + max-frame-size = <3800>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <64>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <32768>; + resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; + reset-names = "stmmaceth", "ahb"; + clocks = <&clkmgr AGILEX5_EMAC1_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + snps,axi-config = <&stmmac_axi_emac1_setup>; + altr,sysmgr-syscon = <&sysmgr 0x48 0>; + status = "disabled"; + + stmmac_axi_emac1_setup: stmmac-axi-config { + snps,wr_osr_lmt = <31>; + snps,rd_osr_lmt = <31>; + snps,blen = <0 0 0 32 16 8 4>; + }; + }; + + gmac2: ethernet@10830000 { + compatible = "altr,socfpga-stmmac-agilex5", + "altr,socfpga-stmmac-a10-s10", + "snps,dwxgmac-2.10", + "snps,dwxgmac"; + reg = <0x10830000 0x3500>; + interrupt-parent = <&intc>; + interrupts = ; + interrupt-names = "macirq"; + max-frame-size = <3800>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <64>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <32768>; + resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; + reset-names = "stmmaceth", "ahb"; + clocks = <&clkmgr AGILEX5_EMAC2_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + snps,axi-config = <&stmmac_axi_emac2_setup>; + altr,sysmgr-syscon = <&sysmgr 0x4c 0>; + status = "disabled"; + + stmmac_axi_emac2_setup: stmmac-axi-config { + snps,wr_osr_lmt = <31>; + snps,rd_osr_lmt = <31>; + snps,blen = <0 0 0 32 16 8 4>; + }; + }; + clkmgr: clock-controller@10d10000 { compatible = "intel,agilex5-clkmgr"; reg = <0x10d10000 0x1000>; From patchwork Wed Feb 5 15:32:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steffen Trumtrar X-Patchwork-Id: 13961378 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B25DD1DB92A for ; Wed, 5 Feb 2025 15:32:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738769578; cv=none; b=gL1DDKOmG0+QTNInGtVZbsBADO2Rd+uHzoEG0Q/HcWhTfcgblJitrde50ipc7BFZR2e7OVGjyyo1JGv7IasjEpPKnsO+Mv2PVGo0khPyHwuZ8Z3gj0mxDs6i/pwLcIKtu3mZgihfpeVY5IoacsrCVYGUsLucWfN0FVZswSjbJg8= ARC-Message-Signature: i=1; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dinh Nguyen Cc: kernel@pengutronix.de, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Steffen Trumtrar , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-SA-Exim-Connect-IP: 2a0a:edc0:0:900:1d::77 X-SA-Exim-Mail-From: s.trumtrar@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: netdev@vger.kernel.org Add binding for the Arrow Agilex5-based AXE5-Eagle board. Signed-off-by: Steffen Trumtrar Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml index 2ee0c740eb56d63cff7767167ee3c640beba0803..03de49222d465584f24cc6c7dfff6ccfe304db46 100644 --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml @@ -24,6 +24,7 @@ properties: - description: Agilex5 boards items: - enum: + - arrow,socfpga-agilex5-axe5-eagle - intel,socfpga-agilex5-socdk - const: intel,socfpga-agilex5 From patchwork Wed Feb 5 15:32:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steffen Trumtrar X-Patchwork-Id: 13961379 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20D2518950A for ; Wed, 5 Feb 2025 15:32:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738769578; cv=none; b=kyqpKHIAMv6RByepxclGXwGL0Ssim3SxRg9lB9lHpw6Zn3tIzCVtKuJm3WzVB4BxE7AYkWvqA0opPu7+BMDy4SG3IvOu04chZoQAqNbm4N2aA/VUC/H7KjWSr0PXI2mumV8WwYnyuBVZWRHxEhEq6IPP1dbcx7deG1Bdkr/5J1w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738769578; c=relaxed/simple; bh=tSu8YXFQbJwcQqiIoKaZChI++VggDiWGOByDugkawos=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ew+uSy/o0Ay0446WgVNqEYRa/ewhZRXVRIHQ+SGLj8lXLZ9sBo24lcuvhjInkKmM9IUpMSJe1G3IkArTMzfzFnUZvOHe8+Tg93wzbnNkA0LJ+G2ZxzH8CAkJAoj0p+xR21vs1YNv+BtrfEs+4ddhe48c6O358k9Lta1jz17ao8E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from ptz.office.stw.pengutronix.de ([2a0a:edc0:0:900:1d::77] helo=ratatoskr.trumtrar.info) by metis.whiteo.stw.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1tfhON-0005Jb-8h; Wed, 05 Feb 2025 16:32:43 +0100 From: Steffen Trumtrar Date: Wed, 05 Feb 2025 16:32:27 +0100 Subject: [PATCH v4 6/6] arm64: dts: agilex5: initial support for Arrow AXE5-Eagle Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250205-v6-12-topic-socfpga-agilex5-v4-6-ebf070e2075f@pengutronix.de> References: <20250205-v6-12-topic-socfpga-agilex5-v4-0-ebf070e2075f@pengutronix.de> In-Reply-To: <20250205-v6-12-topic-socfpga-agilex5-v4-0-ebf070e2075f@pengutronix.de> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dinh Nguyen Cc: kernel@pengutronix.de, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Steffen Trumtrar , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-SA-Exim-Connect-IP: 2a0a:edc0:0:900:1d::77 X-SA-Exim-Mail-From: s.trumtrar@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: netdev@vger.kernel.org The Arrow AXE5-Eagle is an Intel Agilex5 SoCFPGA based board with: - 1x PCIe Gen4.0 edge connector - 4-port USB HUB - 2x 1Gb Ethernet - microSD - HDMI output - 2x 10Gb SFP+ cages As most devices aren't supported mainline yet, this is only the initial support for the board: leds, gpios, gmac2, i2c, uart and qspi. Although gmac1 is equipped on the board, it doesn't work yet as it needs additional pinctrl settings in the bootloader to work. Signed-off-by: Steffen Trumtrar Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/intel/Makefile | 1 + .../boot/dts/intel/socfpga_agilex5_axe5_eagle.dts | 140 +++++++++++++++++++++ 2 files changed, 141 insertions(+) diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index d39cfb723f5b6674a821dfdafb21b12668bb1e0e..3e87d548c532b1a9e38f4489c037c5c4db3a50b8 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -3,5 +3,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ socfpga_agilex_socdk.dtb \ socfpga_agilex_socdk_nand.dtb \ socfpga_agilex5_socdk.dtb \ + socfpga_agilex5_axe5_eagle.dtb \ socfpga_n5x_socdk.dtb dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dts new file mode 100644 index 0000000000000000000000000000000000000000..c0f6870e7b40a53ca0d685b4109ff24e1409bb0e --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dts @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024, Arrow Electronics, Inc. + */ +#include "socfpga_agilex5.dtsi" + +/ { + model = "SoCFPGA Agilex5 Arrow AXE5-Eagle"; + compatible = "arrow,socfpga-agilex5-axe5-eagle", "intel,socfpga-agilex5"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "hps_led0"; + gpios = <&porta 6 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + label = "hps_led1"; + gpios = <&porta 7 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-0 { + label = "hps_sw0"; + gpios = <&porta 10 0>; + linux,input-type = <5>; /* EV_SW */ + linux,code = <0x0>; + }; + + key-1 { + label = "hps_sw1"; + gpios = <&porta 1 0>; + linux,input-type = <5>; /* EV_SW */ + linux,code = <0x0>; + }; + + key-2 { + label = "hps_pb0"; + gpios = <&porta 8 1>; + linux,code = <187>; /* KEY_F17 */ + }; + + key-3 { + label = "hps_pb1"; + gpios = <&porta 9 1>; + linux,code = <188>; /* KEY_F18 */ + }; + }; + + vdd: regulator-vdd { + compatible = "regulator-fixed"; + regulator-name = "fixed-supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_3_3: regulator-vdd { + compatible = "regulator-fixed"; + regulator-name = "fixed-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&emac2_phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + emac2_phy0: ethernet-phy@1 { + reg = <0x1>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + status = "okay"; + }; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&qspi { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt25qu02g", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,read-delay = <2>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + }; +}; + +&uart0 { + status = "okay"; +};