From patchwork Wed Feb 5 22:22:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Denzeel Oliva X-Patchwork-Id: 13961967 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BB30AC02192 for ; Wed, 5 Feb 2025 22:27:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=gJTKfLilyHPLx3eObPNpy3DS6ZtIlktsSD9MZI8c8bs=; b=r0M2cGJEYGtgCIrTwZYv8NQlmJ yT0mWulhOSINwes4EdSmWlciK/tS5KBZ1L6Zj9nk+bk5APTPea2HU02YiNRhZY8oOH+KRWE4JhfZN HtSyY+f3Mp75IEv19MJQdZw/FPR+u/vOFNSD/THTCSGDiFwN1nUUk8Z1OpPZ1SZF5pMfP0cX2fIj0 0y+okQ8oheF2vn5O5I7d+z2ErIT9ENjbrfMFv2YXZNAEBGtkvO4L4w8I5DB4li8qD0mGXTG693dGe t0pkX0c0kZjXSur1Uff6kPZ1+B97YOzjtnxl3tZCex9IbTHWD69t+caNzzb9sOQMRFOwJ3Ho1XtxX NW+u0DMw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfns2-00000004jYE-3FEQ; Wed, 05 Feb 2025 22:27:46 +0000 Received: from mail-ua1-x935.google.com ([2607:f8b0:4864:20::935]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfnph-00000004j1q-39hJ for linux-arm-kernel@lists.infradead.org; Wed, 05 Feb 2025 22:25:22 +0000 Received: by mail-ua1-x935.google.com with SMTP id a1e0cc1a2514c-866e57ec274so101981241.2 for ; Wed, 05 Feb 2025 14:25:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738794320; x=1739399120; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gJTKfLilyHPLx3eObPNpy3DS6ZtIlktsSD9MZI8c8bs=; b=S73NTudRnlABpRObwp0wtYXWyihqHSkBiV1cTr+lhycdZbs2kzb55doM9NfoD2Zkvx +4eymz5t/K2aVHHj2hHMH7IBYZoPncZIaQcZS/EynRjm1LKdfwozLWcXnz1S/t654tFy S5miL9K2jzg3fisV3o9hoFwlOxz3g7jZm/eh3MPJ+pZV0vqxeS2LQoWMNWz3E9fiSv7+ VpYCqlZ7a7wNijBksiUomLFc/MPeO5PvjlOCQ5befY7RJ1c9EqFe3YplDFOjMP9VZXt3 +BDV4Qg3lGk06HXm5dETaaLX8YS2bOjoI3KpFx7OtYgE+qgiq3yBkeT3qIsXMCI8TCi6 g5xQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738794320; x=1739399120; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gJTKfLilyHPLx3eObPNpy3DS6ZtIlktsSD9MZI8c8bs=; b=jOHTHszC2y6m7cQ3EWA7Yd3LPLZtOd0ACE7+RBiv2kAfWdnj4WtRgP43/TQx8WkFmL WWv2HfwDvae/pGoYq0Xs8duesiyEqoaaWKahN209WX8+u1nugImgX2zVLeKrczxnsMqA ZCNHepsmeefHYmbBIp5FkcCsH5ke6Desp4wLe3Dw8o2eZ5IAnM6qrJA7i8WMvoU3p0FX /FDLIjKvzTxVmezsWjavAeUFLrnoQAO6PVvCI9Ou1/bzrJvMNmaokqk3ryMVnZChoabY oq9Y5n7jrsDnJA9TydgSxPfggPbwI/YYLC9nGH8GJbWELfw0kPK5eIh3nLvvbnH+mfiR +eEg== X-Forwarded-Encrypted: i=1; AJvYcCURSRxK04FR34BeVBGXA2DUV1aKSmEvDb3T7/6PpMF+9jotGJ1KrSRXbsHC22duOMs7xQilu2rr46zosmfLL6fP@lists.infradead.org X-Gm-Message-State: AOJu0Yzx7/Xe4EQCSrRCdtcUOYyAnh7Ueu5Qa6/oZoCeboEAxglVXBaZ kOFvN3gEhWJMWZVOn1wbWUVHah2TmfKDY0ir48sVCeSR6VCSeMJiKxm0I1xv X-Gm-Gg: ASbGncvN7NBVF6ztb0IhqpqXFfvKe30XlHoOIrMTtnYnhVP2hZsbfgBfnn1eB+Rv8JJ AuUH34FHeu81LcKGLe/nEVIIdGZ4terv2tjM+Orm9VF/LwUMyHfiA+kG5f5kkTADhis6wiYTHLF 89qtZurCiHPL4z4fCOg3cRFekS+CINl/ciVXUlDHnmaeyu2T+4xfO4TXQpq+cU952n7s65xbBQU +dtTiFS92N8IzRpOxHUakz+uQbjdO5ih/4l4U2B74i5SW2de5VYRL9CNE2IGsmM80oabKD+B4fA g/7a4REECi0wlS37bHJVWpEkKW0fVPm60xJlQzyWl7KpU7CucnP7Q9mWMYWFCHBJs6tgrE/UgnC 5Gw== X-Google-Smtp-Source: AGHT+IETBHJFgsxv08BokD07Ze3sD9qMnzxrSwYE0FIosYhyygsNEboJYxXQI1epDJdsv5iLBBxyfA== X-Received: by 2002:a05:6102:5e89:b0:4b6:d108:cac0 with SMTP id ada2fe7eead31-4ba478b11d3mr3790967137.3.1738794320247; Wed, 05 Feb 2025 14:25:20 -0800 (PST) Received: from localhost.localdomain ([38.44.237.182]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-866941edbefsm2475354241.28.2025.02.05.14.25.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 14:25:19 -0800 (PST) From: Denzeel Oliva To: krzk@kernel.org, alim.akhtar@samsung.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Denzeel Oliva Subject: [PATCH v1 1/9] dt-bindings: clock: samsung,exynos990-clock: add PERIC0/1 clock management unit Date: Wed, 5 Feb 2025 22:22:15 +0000 Message-Id: <20250205222223.613-2-wachiturroxd150@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250205222223.613-1-wachiturroxd150@gmail.com> References: <20250205222223.613-1-wachiturroxd150@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_142521_790271_D682E1E2 X-CRM114-Status: GOOD ( 11.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add dt-schema documentation for the Connectivity Peripheral 0 / 1 (PERIC0/1) clock management unit. Signed-off-by: Denzeel Oliva --- .../clock/samsung,exynos990-clock.yaml | 24 +++ include/dt-bindings/clock/samsung,exynos990.h | 178 +++++++++++++++++- 2 files changed, 201 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml index 9e7944b5f..6b053d1bc 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml @@ -30,6 +30,8 @@ description: | properties: compatible: enum: + - samsung,exynos990-cmu-peric1 + - samsung,exynos990-cmu-peric0 - samsung,exynos990-cmu-hsi0 - samsung,exynos990-cmu-top @@ -55,6 +57,28 @@ required: - reg allOf: + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos990-cmu-peric1 + - samsung,exynos990-cmu-peric0 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP) + - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - const: ip + - if: properties: compatible: diff --git a/include/dt-bindings/clock/samsung,exynos990.h b/include/dt-bindings/clock/samsung,exynos990.h index 307215a3f..97cb5e8d2 100644 --- a/include/dt-bindings/clock/samsung,exynos990.h +++ b/include/dt-bindings/clock/samsung,exynos990.h @@ -233,4 +233,180 @@ #define CLK_GOUT_HSI0_CMU_HSI0_PCLK 21 #define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK 22 -#endif +/* CMU_PERIC0 */ +#define CLK_MOUT_PERIC0_BUS_USER 1 +#define CLK_MOUT_PERIC0_USI00_USI_USER 2 +#define CLK_MOUT_PERIC0_USI01_USI_USER 3 +#define CLK_MOUT_PERIC0_USI02_USI_USER 4 +#define CLK_MOUT_PERIC0_USI03_USI_USER 5 +#define CLK_MOUT_PERIC0_USI04_USI_USER 6 +#define CLK_MOUT_PERIC0_USI05_USI_USER 7 +#define CLK_MOUT_PERIC0_USI_I2C_USER 8 +#define CLK_MOUT_PERIC0_UART_DBG 9 +#define CLK_MOUT_PERIC0_USI13_USI_USER 10 +#define CLK_MOUT_PERIC0_USI14_USI_USER 11 +#define CLK_MOUT_PERIC0_USI15_USI_USER 12 +#define CLK_DOUT_PERIC0_USI00_USI 13 +#define CLK_DOUT_PERIC0_USI01_USI 14 +#define CLK_DOUT_PERIC0_USI02_USI 15 +#define CLK_DOUT_PERIC0_USI03_USI 16 +#define CLK_DOUT_PERIC0_USI04_USI 17 +#define CLK_DOUT_PERIC0_USI05_USI 18 +#define CLK_DOUT_PERIC0_USI_I2C 19 +#define CLK_DOUT_PERIC0_UART_DBG 20 +#define CLK_DOUT_PERIC0_USI13_USI 21 +#define CLK_DOUT_PERIC0_USI14_USI 22 +#define CLK_DOUT_PERIC0_USI15_USI 23 +#define CLK_GOUT_PERIC0_GPIO_PCLK 24 +#define CLK_GOUT_PERIC0_SYSREG_PCLK 25 +#define CLK_GOUT_PERIC0_CMU_PCLK 26 +#define CLK_GOUT_PERIC0_BUSP_CLK 27 +#define CLK_GOUT_PERIC0_OSCCLK_CLK 28 +#define CLK_GOUT_PERIC0_USI00_USI_CLK 29 +#define CLK_GOUT_PERIC0_USI_I2C_CLK 30 +#define CLK_GOUT_PERIC0_USI01_USI_CLK 31 +#define CLK_GOUT_PERIC0_USI02_USI_CLK 32 +#define CLK_GOUT_PERIC0_USI03_USI_CLK 33 +#define CLK_GOUT_PERIC0_USI04_USI_CLK 34 +#define CLK_GOUT_PERIC0_USI05_USI_CLK 35 +#define CLK_GOUT_PERIC0_UART_DBG_CLK 36 +#define CLK_GOUT_PERIC0_LHM_AXI_P_CLK 37 +#define CLK_GOUT_PERIC0_USI13_USI_CLK 38 +#define CLK_GOUT_PERIC0_USI14_USI_CLK 39 +#define CLK_GOUT_PERIC0_D_TZPC_PCLK 40 +#define CLK_GOUT_PERIC0_USI15_USI_CLK 41 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_4 42 +#define CLK_GOUT_PERIC0_TOP0_PCLK_4 43 +#define CLK_GOUT_PERIC0_TOP0_PCLK_5 44 +#define CLK_GOUT_PERIC0_TOP0_PCLK_6 45 +#define CLK_GOUT_PERIC0_TOP0_PCLK_7 46 +#define CLK_GOUT_PERIC0_TOP0_PCLK_8 47 +#define CLK_GOUT_PERIC0_TOP0_PCLK_9 48 +#define CLK_GOUT_PERIC0_TOP0_PCLK_10 49 +#define CLK_GOUT_PERIC0_TOP0_PCLK_11 50 +#define CLK_GOUT_PERIC0_TOP0_PCLK_12 51 +#define CLK_GOUT_PERIC0_TOP0_PCLK_13 52 +#define CLK_GOUT_PERIC0_TOP0_PCLK_14 53 +#define CLK_GOUT_PERIC0_TOP0_PCLK_15 54 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_5 55 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_6 56 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_7 57 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_8 58 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_9 59 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_10 60 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_11 61 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_12 62 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_13 63 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_14 64 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_15 65 +#define CLK_GOUT_PERIC0_TOP1_PCLK_0 66 +#define CLK_GOUT_PERIC0_TOP1_PCLK_3 67 +#define CLK_GOUT_PERIC0_TOP1_PCLK_4 68 +#define CLK_GOUT_PERIC0_TOP1_PCLK_5 69 +#define CLK_GOUT_PERIC0_TOP1_PCLK_6 70 +#define CLK_GOUT_PERIC0_TOP1_PCLK_7 71 +#define CLK_GOUT_PERIC0_TOP1_PCLK_8 72 +#define CLK_GOUT_PERIC0_TOP1_PCLK_15 73 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_0 74 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_3 75 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_4 76 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_5 77 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_6 78 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_7 79 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_8 80 + +/* CMU_PERIC1 */ +#define CLK_MOUT_PERIC1_BUS_USER 1 +#define CLK_MOUT_PERIC1_UART_BT_USER 2 +#define CLK_MOUT_PERIC1_USI_I2C_USER 3 +#define CLK_MOUT_PERIC1_USI06_USI_USER 4 +#define CLK_MOUT_PERIC1_USI07_USI_USER 5 +#define CLK_MOUT_PERIC1_USI08_USI_USER 6 +#define CLK_MOUT_PERIC1_USI09_USI_USER 7 +#define CLK_MOUT_PERIC1_USI10_USI_USER 8 +#define CLK_MOUT_PERIC1_USI11_USI_USER 9 +#define CLK_MOUT_PERIC1_USI12_USI_USER 10 +#define CLK_MOUT_PERIC1_USI18_USI_USER 11 +#define CLK_MOUT_PERIC1_USI16_USI_USER 12 +#define CLK_MOUT_PERIC1_USI17_USI_USER 13 +#define CLK_DOUT_PERIC1_UART_BT 14 +#define CLK_DOUT_PERIC1_USI_I2C 15 +#define CLK_DOUT_PERIC1_USI06_USI 16 +#define CLK_DOUT_PERIC1_USI07_USI 17 +#define CLK_DOUT_PERIC1_USI08_USI 18 +#define CLK_DOUT_PERIC1_USI18_USI 19 +#define CLK_DOUT_PERIC1_USI12_USI 20 +#define CLK_DOUT_PERIC1_USI09_USI 21 +#define CLK_DOUT_PERIC1_USI10_USI 22 +#define CLK_DOUT_PERIC1_USI11_USI 23 +#define CLK_DOUT_PERIC1_USI16_USI 24 +#define CLK_DOUT_PERIC1_USI17_USI 25 +#define CLK_GOUT_PERIC1_GPIO_PCLK 26 +#define CLK_GOUT_PERIC1_SYSREG_PCLK 27 +#define CLK_GOUT_PERIC1_CMU_PCLK 28 +#define CLK_GOUT_PERIC1_BUSP_CLK 29 +#define CLK_GOUT_PERIC1_USI06_USI_CLK 30 +#define CLK_GOUT_PERIC1_USI07_USI_CLK 31 +#define CLK_GOUT_PERIC1_USI08_USI_CLK 32 +#define CLK_GOUT_PERIC1_USI09_USI_CLK 33 +#define CLK_GOUT_PERIC1_USI10_USI_CLK 34 +#define CLK_GOUT_PERIC1_USI_I2C_CLK 35 +#define CLK_GOUT_PERIC1_UART_BT_CLK 36 +#define CLK_GOUT_PERIC1_USI12_USI_CLK 37 +#define CLK_GOUT_PERIC1_USI18_USI_CLK 38 +#define CLK_GOUT_PERIC1_LHM_AXI_P_CLK 39 +#define CLK_GOUT_PERIC1_USI11_USI_CLK 40 +#define CLK_GOUT_PERIC1_D_TZPC_PCLK 41 +#define CLK_GOUT_PERIC1_USI16_USI_CLK 42 +#define CLK_GOUT_PERIC1_USI17_USI_CLK 43 +#define CLK_GOUT_PERIC1_TOP0_PCLK_4 44 +#define CLK_GOUT_PERIC1_TOP0_PCLK_10 45 +#define CLK_GOUT_PERIC1_TOP0_PCLK_11 46 +#define CLK_GOUT_PERIC1_TOP0_PCLK_12 47 +#define CLK_GOUT_PERIC1_TOP0_PCLK_13 48 +#define CLK_GOUT_PERIC1_TOP0_PCLK_14 49 +#define CLK_GOUT_PERIC1_TOP0_PCLK_15 50 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_4 51 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_10 52 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_11 53 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_12 54 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_13 55 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_14 56 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_15 57 +#define CLK_GOUT_PERIC1_TOP1_PCLK_1 58 +#define CLK_GOUT_PERIC1_TOP1_PCLK_0 59 +#define CLK_GOUT_PERIC1_TOP1_PCLK_2 60 +#define CLK_GOUT_PERIC1_TOP1_PCLK_3 61 +#define CLK_GOUT_PERIC1_TOP1_PCLK_4 62 +#define CLK_GOUT_PERIC1_TOP1_PCLK_5 63 +#define CLK_GOUT_PERIC1_TOP1_PCLK_6 64 +#define CLK_GOUT_PERIC1_TOP1_PCLK_7 65 +#define CLK_GOUT_PERIC1_TOP1_PCLK_9 66 +#define CLK_GOUT_PERIC1_TOP1_PCLK_10 67 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_0 68 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_1 69 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_2 70 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_3 71 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_4 72 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_5 73 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_6 74 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_7 75 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_9 76 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_10 77 +#define CLK_GOUT_PERIC1_OSCCLK_CLK 78 +#define CLK_GOUT_PERIC1_LHM_AXI_P_CSIS_CLK 79 +#define CLK_GOUT_PERIC1_XIU_P_ACLK 80 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_12 81 +#define CLK_GOUT_PERIC1_TOP1_PCLK_12 82 +#define CLK_GOUT_PERIC1_TOP1_PCLK_13 83 +#define CLK_GOUT_PERIC1_TOP1_PCLK_14 84 +#define CLK_GOUT_PERIC1_TOP1_PCLK_15 85 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_13 86 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_14 87 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_15 88 +#define CLK_GOUT_PERIC1_USI16_I3C_PCLK 89 +#define CLK_GOUT_PERIC1_USI16_I3C_SCLK 90 +#define CLK_GOUT_PERIC1_USI17_I3C_SCLK 91 +#define CLK_GOUT_PERIC1_USI17_I3C_PCLK 92 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS990_H */ From patchwork Wed Feb 5 22:22:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Denzeel Oliva X-Patchwork-Id: 13961968 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E1B8CC02192 for ; Wed, 5 Feb 2025 22:29:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=lLGSgDdl5g9MmO62+ZaKTd5URN0HQgATTN7adUAMeJ4=; b=zgwhulu5LxnQfYGuE/oWz65Hrz ac93VNX74V7eo93gThmyXaZ4Weq1QVpdgg3sqBbqm5dGVU2/ad/xww0Wsl37m/RTE86RSd+osOZ5I 0gxU629DEGH8wpidoT1+IequG7qIf0S7gxTEUep9RKRXfFVuLDNHwWQOGZjKrlAoYEmU1G6QXEjRX fDqPkWkCAd1MtYPgV4QHIDJUU17FTl29oyZnTaA8l2rl+NlRvgr31arHzAmimtO0gw2XhsU9LCzFi w5boOAq3s9LjelEBlJPiMXKQXonHO7VjddE57rdCj7oL+qkFdSoYOuQ/YYUeXxJZKub+miJGIaA8A yi4oqVzA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfntN-00000004jjk-1sWI; Wed, 05 Feb 2025 22:29:09 +0000 Received: from mail-vs1-xe34.google.com ([2607:f8b0:4864:20::e34]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfnpj-00000004j2I-3P4B for linux-arm-kernel@lists.infradead.org; Wed, 05 Feb 2025 22:25:24 +0000 Received: by mail-vs1-xe34.google.com with SMTP id ada2fe7eead31-4aff1c57377so165029137.0 for ; Wed, 05 Feb 2025 14:25:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738794322; x=1739399122; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lLGSgDdl5g9MmO62+ZaKTd5URN0HQgATTN7adUAMeJ4=; b=apS5mKjUfBGyohmmdLOytL+KUoFun6SvdA+eNSOY6lSLtrTl7OdTmgjyaMZ7Fanuqs Cib2J9Lk8MARkglzWlCmv+YXhPlVqEgsLxVbFvDtBtD34wmJWHoiOwgD0ZryutifUbs+ f5zWNQETbiFbKOg9NhDFNCvVcxrjJZCRXSGkTkcJlqprNq1KbezTewLOaPt5jhS5dV4j 769yp0dG9IxRAy9Fg/Mlxu+suhWN44xRFeS1a+81NxWqN65YvfnBx9L+U8lOCmIXg9mJ jWzlmNO0V2VChWiX4lXy5sArlHOmSs05fEjO8VtEvKp7ulrkIVTGJ70vts998kw7KBl2 q71Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738794322; x=1739399122; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lLGSgDdl5g9MmO62+ZaKTd5URN0HQgATTN7adUAMeJ4=; b=lbLOhBf76Avzxu9A9G+ISJwRmvEdKc08uDkMNF3Tkkty9ZkQRQXHJJaWGy0nRq1U/D IUKpqxjXqH2b04kI3oVIEVVnRxkEmaSwr4oe9JFX0YzbOmc39PlxyPYTlEub99mb9vnN UsIeBCZHlEdbt+DkVRRmVU29RFY2KB+MR3ZKa9ASrkBVM3Adv+Ll0zOK1UDZGlj6bIwD ZSmMo5oSu0i0HuWbVyyy5DRn/qITv6PbDpwEKlmmLwE/yt9iG1QRI9GwyJuQsa6ySLnW nN9iUE5wjje3IWOBehuPolVsoiefsaXd40yCo7R3dGlM5Lm2GZQIMtEb3R44OGIOd/tN vRRQ== X-Forwarded-Encrypted: i=1; AJvYcCUhOh9uTYEjnhGDI5gSYc98lZXmL1YXLYj35QoOOLyOdwp9057oa8hqE1i26jS+o/UZDkx3IVPdb7kHOdd+K6V1@lists.infradead.org X-Gm-Message-State: AOJu0YyCntN2sNIvmXMt8ePg6XDYRu6aZXk+BRypaOl4Y6ukVVD4dbFU Yr9oB6+39tE+H6PWKdykwvDm2Jva1KaHCI7B60q9ESUOtfk3Rof1 X-Gm-Gg: ASbGncsby4P8g7aL/rNrPkvCsR8YuKoVI9NeSkmtLTk4Tci7cp7Y9u+/3S5njcTb5Wl aFE5/9MCyoFLEzOpTimaoKIs1slly0ZZushPKBz96XwndLEpwRP6no8eL2Ce82bs64jyk/bF9rh Sqyh8G+jbDWek1IxWQEIrLtHTn3X25TEQkXj6PtQKHJwWM4tFpHTDPcUbhaDVz20CASNQBTt8Rm QnW94jUZGOum0junk4cQRVkaK07unGjlfQIjdj7nqq87iEeY8JmeXWu5Rzlu0UHKGc11KH+tv6I GKj1l87phtbi3pADUbODlccKJOMjTboMIbvb1MOZNTHNQOy7Hr0w5ybHakeKZDoqZtKm82rmODa +aQ== X-Google-Smtp-Source: AGHT+IE0tEZegMQHIWkk0mn6LCcU2W7qerUiRb0uNn6UQq7E/4NmKo29oH1zA0GoKMQe8I67Cz1aug== X-Received: by 2002:a05:6102:82d2:b0:4b5:c302:37b3 with SMTP id ada2fe7eead31-4ba71f8cffcmr740160137.5.1738794322551; Wed, 05 Feb 2025 14:25:22 -0800 (PST) Received: from localhost.localdomain ([38.44.237.182]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-866941edbefsm2475354241.28.2025.02.05.14.25.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 14:25:22 -0800 (PST) From: Denzeel Oliva To: krzk@kernel.org, alim.akhtar@samsung.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Denzeel Oliva Subject: [PATCH v1 2/9] dt-bindings: i2c: exynos5: add samsung,exynos990-hsi2c compatible Date: Wed, 5 Feb 2025 22:22:16 +0000 Message-Id: <20250205222223.613-3-wachiturroxd150@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250205222223.613-1-wachiturroxd150@gmail.com> References: <20250205222223.613-1-wachiturroxd150@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_142523_846834_010B9E69 X-CRM114-Status: UNSURE ( 8.91 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add samsung,exynos990-hsi2c dedicated compatible for representing I2C of Exynos990 SoC. Signed-off-by: Denzeel Oliva --- Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml index 70cc2ee9e..b05d1e9e2 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml @@ -36,6 +36,7 @@ properties: - enum: - google,gs101-hsi2c - samsung,exynos850-hsi2c + - samsung,exynos990-hsi2c - const: samsung,exynosautov9-hsi2c - const: samsung,exynos5-hsi2c # Exynos5250 and Exynos5420 deprecated: true From patchwork Wed Feb 5 22:22:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Denzeel Oliva X-Patchwork-Id: 13961980 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2F30BC02192 for ; Wed, 5 Feb 2025 22:30:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=mnz2IMViKhDM4Hj0WSKlwwRNtgDGeYFPFQd7FGQc5WM=; b=ZAnK/4t76RqAFom7kcBv0rBrrA fOYeBp/18qggkfCdHCenR88pze2/2nK2lOcjcBLUPNJpikARi3m748tVN/WheIH2i6YuCuGqnFk+U QP/H+84aTxVgrrp9T/H0xnJX8BXwJeP2UH9GMQbQfGJx+K1QTX/EHfuXl3ttW0NugWPQFtPGX9kWm j1RTqUmORNgLIG1jdbkKBSpmc9hhcLDdVSqyPHWE5hrMUnbCIOxAf6Tok7qiIFXfWhqx5NtbaWO2d r/hAVhoLzHHTSL9Wcac/CMF4ui82A0igXiivTfffrIa9QYUIW5tvsLqs9/4gnPtypqSFhTSoQZ1iO 82VvBdhA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfnui-00000004ju0-0NNV; Wed, 05 Feb 2025 22:30:32 +0000 Received: from mail-ua1-x929.google.com ([2607:f8b0:4864:20::929]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfnpm-00000004j2x-1HdQ for linux-arm-kernel@lists.infradead.org; Wed, 05 Feb 2025 22:25:27 +0000 Received: by mail-ua1-x929.google.com with SMTP id a1e0cc1a2514c-866f01c2f2aso76332241.0 for ; Wed, 05 Feb 2025 14:25:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738794325; x=1739399125; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mnz2IMViKhDM4Hj0WSKlwwRNtgDGeYFPFQd7FGQc5WM=; b=jbE5UbDtzMHKnxEYEL0pAPLAJ0wsyQm3yct4m8ovtClgXB5B8FERgu3x9jg3Vhtejm 2yoUcEJwxACYRaeeFT2OUk6/CltIv/OUpoLHC/hcVbJTEORrghqicH0IskDML8HSni9B 2Zhck8ihaTTVqY8WfN2jEpigoG/H22ksB+fvcMCvD1JdSeXMQo4fcR2e/GxK/lmQZVau 9EvlM9g4TbTR5uFjslrTRj1owMqVQeVdsL7z9G5+V5mqTk/+lLtPUCm/5wMdVUW5KH/c rzSpvw+8ONNGn5GaDfJ2wnsswtQBOE1T2gB58YkP4XDz21j/yIs8BSFjmJXJYAVl/jmC QK2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738794325; x=1739399125; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mnz2IMViKhDM4Hj0WSKlwwRNtgDGeYFPFQd7FGQc5WM=; b=JsOPTZV/NyJYJPGQI6vUh5H3QHG/07KvLVOWT0/7rDkhM1q/DB03lSASfMxbCM3ZL4 q0lhuHIQNp9WgTqBV4ayx0KMtdW+AGk1j4MQOG6Gxhu5WUOoSoObiU9zihvS9kJ/CtK5 WYT0AwMl0nKLshG/AKZsGBvAmZ3UZuaS1EW9tqN30j0HumyG5ZHeNnUproCxnbDskRRa RMDJ7lT2L0wvj77slwDkKofrKMQKA53Nma061ly7Z0N6a6/v0UDOJUtxiSf8EMm4BPKR BCQKhJZiJeLAyEvBLOHnD2YN81eqHDprIBycuXkGr/CA5kOeYL7rfyMjQa91tV75+n9z 9fxA== X-Forwarded-Encrypted: i=1; AJvYcCVWRTGPgPbod5g+nVtV8IrkG8FYX7X6eWLNsYAA4yuJAsV/7U1v5GVu97MK2E0JWCvnaHS9IMPzSKUWrFO37BCD@lists.infradead.org X-Gm-Message-State: AOJu0YxWLWuNTVwo0XoZailZ7ULMXieke4RjhvH7wH2p1c7OToWhWUO0 M4erDUbDkxMnD0dBW53c0qbCGp8BIn3ahFYM9npe78uIfxLxd7lBPT+kV8hu X-Gm-Gg: ASbGnctuPUB8APGRqPGk5IA8ECJHehDp8tmASAmaWlR6+RvKHy1T0OIxyUtMKjhSNmI i7gghYsp1Uv5WwHCCV7wIa6ubSTupza/7IATd8bbLUum4/mzt06ybDQOaf8+9iLBXkTb1tR6bRf HQoLOURMmBL/Hy3cYqSFB8dNjUU9L6sxy+UdDEsNvQqzMnisMDiQ3M4kaP51jURmIiECnUwkuKT Yx68+FmSihV+QadT6G0SzlzDPj27MYS4Ritc/1NuylAWsjm9BoeU8WT00mg94/4/qbaPZOnr0dN YvA7c5qS/Tyq09B3HDhWCfDJiXg21Z4V97JwNtstgi6xTTK+PCiYBYiO040bQHhC7UpXOSmmFQ/ gCw== X-Google-Smtp-Source: AGHT+IGjopzGNcqEb/rWZdE5VUOc6SG26nGBuvHP2iF+xN8ZgN2V7SZQt93KOh1MxhdKUcdYZH1nZQ== X-Received: by 2002:a05:6102:1492:b0:4b2:5c4b:5186 with SMTP id ada2fe7eead31-4ba47abc62fmr3535589137.23.1738794325018; Wed, 05 Feb 2025 14:25:25 -0800 (PST) Received: from localhost.localdomain ([38.44.237.182]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-866941edbefsm2475354241.28.2025.02.05.14.25.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 14:25:24 -0800 (PST) From: Denzeel Oliva To: krzk@kernel.org, alim.akhtar@samsung.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Denzeel Oliva Subject: [PATCH v1 3/9] dt-bindings: serial: samsung: add Exynos990 compatible Date: Wed, 5 Feb 2025 22:22:17 +0000 Message-Id: <20250205222223.613-4-wachiturroxd150@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250205222223.613-1-wachiturroxd150@gmail.com> References: <20250205222223.613-1-wachiturroxd150@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_142526_343546_8C73717C X-CRM114-Status: UNSURE ( 8.88 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add samsung,exynos990-uart compatible. It falls back to samsung,exynos8895-uart since FIFO size is defined in DT. Signed-off-by: Denzeel Oliva --- Documentation/devicetree/bindings/serial/samsung_uart.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml index 070eba9f1..f38be8e95 100644 --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -28,6 +28,7 @@ properties: - samsung,exynos5433-uart - samsung,exynos850-uart - samsung,exynos8895-uart + - samsung,exynos990-uart - items: - enum: - samsung,exynos7-uart @@ -42,6 +43,10 @@ properties: - samsung,exynosautov9-uart - samsung,exynosautov920-uart - const: samsung,exynos850-uart + - items: + - enum: + - samsung,exynos990-uart + - const: samsung,exynos8895-uart reg: maxItems: 1 @@ -162,6 +167,7 @@ allOf: enum: - google,gs101-uart - samsung,exynos8895-uart + - samsung,exynos990-uart then: required: - samsung,uart-fifosize From patchwork Wed Feb 5 22:22:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Denzeel Oliva X-Patchwork-Id: 13961981 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AF902C02192 for ; Wed, 5 Feb 2025 22:32:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=beA6gjGZdB5oydWLbpWxW9pYKOlWwgtrMIKBgVMVP0I=; b=O6Z0bklRoqEcTCrFNx1f8OSPwH 4e34FGzuTCl8WE+VDw0VphxkuA97901SoAONXdMA8QZTxwkOB41PlH6e8X3uSBFZ4UrT5UrZaOipZ 3L/LVCwpNWtbnwAI4EVj3k8++bV7BchhDHj0Y6i+uVHgJ/8lZBG5LY2c5gV+do6DjxM2QHnU/cAfp 30232FqeDKbzA9IOOpxntmlZQlg+psyNKeyb0Zi8fqzO/QwnbTskm8o+xz2P4gbesut4jx7n8KHCg B0K4ltyacf8tR5hGm2kxFS1A7aO/Z73ellCnrSw6LM7zGyQmISyET405nNUE+D/mSr8wWifllC6n+ npbT1VPQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfnw2-00000004k5O-3RrN; Wed, 05 Feb 2025 22:31:54 +0000 Received: from mail-vs1-xe29.google.com ([2607:f8b0:4864:20::e29]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfnpo-00000004j3J-2NRb for linux-arm-kernel@lists.infradead.org; Wed, 05 Feb 2025 22:25:29 +0000 Received: by mail-vs1-xe29.google.com with SMTP id ada2fe7eead31-4afdf300d07so122761137.3 for ; Wed, 05 Feb 2025 14:25:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738794327; x=1739399127; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=beA6gjGZdB5oydWLbpWxW9pYKOlWwgtrMIKBgVMVP0I=; b=T3eLvSChZaxigSkM9+64kB8D98WO2M5xUb/3jot2LxnvkM8RFpF7S84Ylvpl3O5Mit r6G5QSkFQX64Cc1U43tVEtJIkbRNujRO0t4tdORlVOXqHNXagV8i/NuuoZAjv/qJ/wl6 ci2BKyLjCj2bocLvnEdmbbI8ITMk436CZtfIECstA6VYbriuAII5WFy1xYUOWk2sm/+i Af71QElZcuiUEz830oF6dajFhCY+N0z6MQPf32Bs6E/kB96rzeLuPdbLF3aC14TWQGIv 2Bhf1gHjXfrna9UPbCH/JUJ2lKv9u+ABMgW94xkkWJ67T9fYxaXMhOSP5w5PQxvI9+LX 9ybA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738794327; x=1739399127; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=beA6gjGZdB5oydWLbpWxW9pYKOlWwgtrMIKBgVMVP0I=; b=P3P3kDiRJTe55lg/J4F+QHNw9lXwmdemwm4WDadtntlfDo9p9VG/jhAARDErtg8cwM EG6dyPs4cT+uk1wuU4ZwNEUzQLKEa9oDZUJIvG7vpNztnumREwx+C2Lb2VH2M7xT1ZiL +2AleW1TWeWs5W4bHlgP3A30He9roRP3GxhdKWwFCPhKqrtlFkWuC+j7ErYSJziVceQ7 9FB+OY30S4NLssk7HEbvitKqaAxmrjCC6idNRu6zOKw3t/fDLdUyDKyggTKt1ICZmx8C PYR5io33NHtfGu5fN2lcdIe+LK5/Bq/piUEzUIBgro4YpqGDJdUD/5T1ttMoBY2xtudF o6jg== X-Forwarded-Encrypted: i=1; AJvYcCUMNQT154F87LR4JyOWqEWgM3hjHKttdG07F4l1c4LhDV1U10QRk+OKYFfcDzZDlT3moPpYRMYFSAo8uZfZWeCP@lists.infradead.org X-Gm-Message-State: AOJu0Yz9Pv1FfIl22kShwSTLPsp/fIMkvNZkj01ROmMfiiruRnumqMyR RLpbXFkpK9tln1bXZ2lC6SBvKcLwXyre8m9l7XkaeV8PCgbeFaHv X-Gm-Gg: ASbGncvAVU9m4T3KLylyWnAiFnTWPW17xqYGCGtcyv/7nYOmmLj/SVjdyTmprToFFc/ gZpcJf+8kzp/z5sPjB7Dy0YsRyDfO8lI5sFsl5TUArBzjkCmluRorXfJS297MMLRMstN5vGuu/p g4LITz7Wb47GGNIGqywprmVyebaFiSggw7KdUeC11EdNT6MyVcCp6BiCN7ez//mDwFTDAB+FGPI YkZwSUDuNbqeEiWqh1z6yeEKlhd59BVCua+LZlMPkvHpfW8QfRO4pGZWqX54CQo1fERThF13TLj sGmOgjNJzFTMUmSQr/x8CbKwENrv3wFN0smpj/FLOAL1D+NDltsTXzWSn2EJkL9mpAnkjTFqgI9 a8Q== X-Google-Smtp-Source: AGHT+IE3nI+T7UN/svC5dEEyiI49AVWPcqQVx+uU5ZAnx1goXIkB2M6UC2RNJ+9BdlxIm9Bylg54jg== X-Received: by 2002:a05:6102:8086:b0:4b6:4502:4a84 with SMTP id ada2fe7eead31-4ba478b3533mr3842089137.2.1738794327322; Wed, 05 Feb 2025 14:25:27 -0800 (PST) Received: from localhost.localdomain ([38.44.237.182]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-866941edbefsm2475354241.28.2025.02.05.14.25.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 14:25:27 -0800 (PST) From: Denzeel Oliva To: krzk@kernel.org, alim.akhtar@samsung.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Denzeel Oliva Subject: [PATCH v1 4/9] dt-bindings: samsung: usi: add exynos990-usi compatible Date: Wed, 5 Feb 2025 22:22:18 +0000 Message-Id: <20250205222223.613-5-wachiturroxd150@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250205222223.613-1-wachiturroxd150@gmail.com> References: <20250205222223.613-1-wachiturroxd150@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_142528_607109_30F20548 X-CRM114-Status: UNSURE ( 9.18 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add samsung,exynos990-usi dedicated compatible for representing USI of Exynos990. Signed-off-by: Denzeel Oliva --- Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml index 5b046932f..4283d35f5 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml @@ -26,6 +26,7 @@ properties: - items: - enum: - google,gs101-usi + - samsung,exynos990-usi - samsung,exynosautov9-usi - samsung,exynosautov920-usi - const: samsung,exynos850-usi From patchwork Wed Feb 5 22:22:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Denzeel Oliva X-Patchwork-Id: 13961982 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 27461C02192 for ; Wed, 5 Feb 2025 22:33:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=fudfumjX9RZBH6qmvyzpFv6ekbh13Mvx8da8aLOM2hY=; b=EF7elvrqSIrVEN8WWiJiRkC5HC hEfPXDw9GfowuK0Mc1vooSdCkoY5xrfujC3SLNikeOVVWyUsous23xy2bGmgfk52rGopvfYBcNuXT zsxiQkNNJxhisa0X7zM6BOFcCumWnml30DC0z2DuFut6yj1amsHGfPxCBM55ePDkjevJiwZFF1y6i Mroizvicyhda4uYnzZE6FpW6t6hnT4FYBzr0CFfuiOulRRz3/9nAsGmNS+rB2QDcb6FhFjijRHelJ Ji7gs1pkxiRJ4gEKsIekyCVvXx/ZQFnfQB79M486ZBFqQnOqflSosuvvTRO/3FZm3En0+PYnXYNyJ nyRCDu0A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfnxN-00000004kJC-25wH; Wed, 05 Feb 2025 22:33:17 +0000 Received: from mail-vs1-xe36.google.com ([2607:f8b0:4864:20::e36]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfnpq-00000004j3j-3cV7 for linux-arm-kernel@lists.infradead.org; Wed, 05 Feb 2025 22:25:31 +0000 Received: by mail-vs1-xe36.google.com with SMTP id ada2fe7eead31-4aff5b3845eso81210137.2 for ; Wed, 05 Feb 2025 14:25:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738794330; x=1739399130; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fudfumjX9RZBH6qmvyzpFv6ekbh13Mvx8da8aLOM2hY=; b=GPhzRmE+0URTRvVwGRb6wgl+vNFJBDPY/MLCpI+hpL+oez0iocNGzxEc7TfTwbcdr1 BC/IsJzkTrZrBOt9Wt33jvLAzDqGDzioY+K45O/or+smc3+Q2ODWS64EoLjl24KYEL55 K5BA2FL5Dzknw+oIIc0y8PLbAQNSkLr7tATNhAVTyK/Gk9mLLn9AOKjXrsMFKeqXmkbw RMH4sBeViXs1m7uRNdH45dtvtKtld6RMlJQreBFzsrfBbIcYXncXZNv+FjvcsaqPkWnI MOe1UPV8fyMwJR0QWDT8SM8cql/WQq3UjnfkDuYQpqdRmbNSaMMc8c0G/Qazy51f08Zj TfYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738794330; x=1739399130; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fudfumjX9RZBH6qmvyzpFv6ekbh13Mvx8da8aLOM2hY=; b=p2q1pKTSYHeY77iPNVxDZ1dp9naJ0AW1MGdRCkr7l8dQoHPlS6Qq4g8dV9EF08+7Ga r95ECJnFiKlntPTLpS6jbENjYansG6/GzcsE4B4FcL+H0fB2CKaBdi+Tmk4+GbNgQwyz m1BrhTNcHqqru1GmlO603DzGQfZwIXeHgdF+Mh8CX0zD4rxVxKvbTngSy+igDFVugmX+ wF/mVPJrqcVrNH9r2yo6uHFG2mck31C150R0U04ikH28yvzjUUlWcRt5mQ7zjtznVdb+ ocNjIaQH2oaoryN97DocsvrJ5gElpagq2j6yZnDlB7vAlYbDksXXyJtusXUZMEiVbEhi DWkQ== X-Forwarded-Encrypted: i=1; AJvYcCU7hnHU/5NspDLgXykN4J4Qi+XF4hqALb7Of4ja+Cw4N6PZuy5M+MQCmLWU6ClT/l/MKttn+nJ+MI4ak114cqne@lists.infradead.org X-Gm-Message-State: AOJu0YwFo+/6ypjOqWYQtD56ckLMRfiXLgQrGSgJtJv7qBcgBSW5BuBi Psha9QhMwrYaxnTdfq895dULSde+Wx01vcPLhPOzBwsFOKjyT113 X-Gm-Gg: ASbGncssT6Pk6BUszEERBoFbHpHN9JULPYRooOEjxN4Df9deOL0yOV4gDHoM0grhFh3 GgwVSzlnIaNuYhLSZNThXjHWbEaI65A+FvamHRCO6yYzMnSd5jxbUmxX4oq34zA2rzddtvaj2Gh sM02qKSu9WX2LgIO/fpDX47g/37A6IofPMU5rZoWRyCwuSJbzY49XYVhjrxqcOeD+UeAPVx5At0 rhqzu19w48n3EM4l3njozSb2y8AsGN79FnSa59VFZmIioOKdkAkgkdcP+OMlRTn9d2xEEEDHA0i 07iUMgMa1Fo6Q99g8vVOjp27pAqZC72auX1L4YBbj58hrpT3uHOrVc8pRfONq6hvUh+DxxOaV4P lvA== X-Google-Smtp-Source: AGHT+IEdJ0L14y+yqJvu1qivXHC8OglVARnsngubthm0PnC7P3RsJxZ/FSG6acgtAR+YQSQh8g2aNg== X-Received: by 2002:a05:6102:3f05:b0:4b2:cc94:1879 with SMTP id ada2fe7eead31-4ba47ae894emr3528199137.22.1738794329685; Wed, 05 Feb 2025 14:25:29 -0800 (PST) Received: from localhost.localdomain ([38.44.237.182]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-866941edbefsm2475354241.28.2025.02.05.14.25.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 14:25:29 -0800 (PST) From: Denzeel Oliva To: krzk@kernel.org, alim.akhtar@samsung.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Denzeel Oliva Subject: [PATCH v1 5/9] spi: dt-bindings: samsung: add samsung,exynos990-spi compatible Date: Wed, 5 Feb 2025 22:22:19 +0000 Message-Id: <20250205222223.613-6-wachiturroxd150@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250205222223.613-1-wachiturroxd150@gmail.com> References: <20250205222223.613-1-wachiturroxd150@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_142530_898906_815DDF7F X-CRM114-Status: UNSURE ( 9.74 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org According to the Exynos 990 downstream kernel, almost all of them do not use the same 64 bytes depth. Some SPI nodes using a depth of 256 bytes (SPI 9/8/10). But in the end these nodes work. Signed-off-by: Denzeel Oliva --- Documentation/devicetree/bindings/spi/samsung,spi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/samsung,spi.yaml b/Documentation/devicetree/bindings/spi/samsung,spi.yaml index 3c206a64d..1d3c95bd2 100644 --- a/Documentation/devicetree/bindings/spi/samsung,spi.yaml +++ b/Documentation/devicetree/bindings/spi/samsung,spi.yaml @@ -24,6 +24,7 @@ properties: - samsung,exynos4210-spi - samsung,exynos5433-spi - samsung,exynos850-spi + - samsung,exynos990-spi - samsung,exynosautov9-spi - tesla,fsd-spi - items: From patchwork Wed Feb 5 22:22:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Denzeel Oliva X-Patchwork-Id: 13961983 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3A182C02192 for ; Wed, 5 Feb 2025 22:34:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=62TGT2cJ8N53D9ZE5FWVLQuLK0YScVrC8nxALy7btwM=; b=lh6z1g3gQ+A14l90meCNpgI0X/ UFphRNaZXj4iGg6jnUa0PSljHERD/ZKcUrgaUzlXW7e1X/aVfBoxSMSdgjVZj20FTyJlQbRgT650k Ncydf0L9ai7onnQ517SahBE5WDORh94O96F7T1+FgpoHL6oU/zNYWiDOrV+aobh66uNaJxM5x9qpg uC48oXARUYr1kPmw5xrrQT8tKJScH06CFTcwoC539cSGgmd95p1HDYVM9U1aZM6I+/fME0n62yUbG 9bIkfUMPGjYYWMy7XL2ev2THxOZM9lhTP/xjFeib8VTH28931O4FDcXQvYgGiL+0wxCSfGGby0NJ+ UzWMsyOQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfnyj-00000004kXP-0eoo; Wed, 05 Feb 2025 22:34:41 +0000 Received: from mail-vs1-xe34.google.com ([2607:f8b0:4864:20::e34]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfnps-00000004j4L-3W7h for linux-arm-kernel@lists.infradead.org; Wed, 05 Feb 2025 22:25:33 +0000 Received: by mail-vs1-xe34.google.com with SMTP id ada2fe7eead31-4affab62589so75032137.1 for ; Wed, 05 Feb 2025 14:25:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738794332; x=1739399132; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=62TGT2cJ8N53D9ZE5FWVLQuLK0YScVrC8nxALy7btwM=; b=nRIGfPLNAJx8cXBOSMO4Qt0g82g0iy2T/Qv5SnvbBW/IFuGeD8G2++w4igMlqXFXJU LOaXsq9Bav48eaQZ4adCwfjt/3ZzkV0WySup6m5Yr8sKqRv7+jlBBn8v2FKos63r9lTa IQhd5NgmpzcnYmlBvyYEqdbAZ8U/6HWOXdnMgAc3V2dAd7VbaHhRLN5oqAxEI1VEkMN1 RWgIq2a1Z0ZgKtCZ/oPMfUldh8X4+Atjeh94AoRZ5fm29DJX2QTJ5PFjY7RX3/Jf7ri4 3vLDffZTlrK1M3ZXMyyx2l1NRxYiFW1MpPVVf86ARna5OGN42GmVTPBIyojZVwRv3fsA DxIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738794332; x=1739399132; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=62TGT2cJ8N53D9ZE5FWVLQuLK0YScVrC8nxALy7btwM=; b=X8+wq8cqa17i3iCcFKXtAw5GTlHaZg2VuroT1OuF58c1HlcNkyuOxkB5QOh70WZeKO zn/RMGiKaLkKhfncLMihUCe7QQtECP8hjRZLoVoGg8NhaAXmT/yvZO3QGtoPc/uBOthT tOlNzx9fy92HC1gO36A5xV7LFJ8YFzNYa9+UiJLHeEiWS+yiVwwxSCl+GO0XMbcEE4Y+ d2TCxvftiixfmlHQMrcaD0I9Y4+VBrRJNpieMv1sOMG/KJWlTN6mSOA+pGDqVbO7Qbqz 9iTAz+QqEnlQ92c/EZBOPkM52AZ7vtDMWBEaWa2DjSH/Laz5ycALHGc18LpfhqKzaBo/ aI3Q== X-Forwarded-Encrypted: i=1; AJvYcCXnElO32v3YNN3rnVSu01o0mk0ZLm6DPS0XRr8Tki3w5O93mimfEk0fzBfArNu4O2N2/gxixnINzrWqAxcM+eM5@lists.infradead.org X-Gm-Message-State: AOJu0Yznz6hcjq0LULOeHvLcwEde+KMX4na8Iy0KuFsvlnFbI24xzFW6 wkBUsy80wSUh0HfbKXwfDFF0qJoFAjznpU5DxGNTHzIWq+eCIaWz X-Gm-Gg: ASbGncuANuQNonMqD04K7XGtdkPm3Hvv6RMCfQOBAM+42hz0PMPw51FrYS0k5VMGA8s Ggda9wrrSR3mT2WQkfqvMJrla7dK28bYmqBra1UI2RyPkPuH9pQu1S1t3XkEtdad3uj/DiOxb0K xYoXC9a729cfNr+sxGzBIpKklo1uu0MtFFnTNs+DRK0mva/ul/fB8Cf8B+b+uZoPgkN7OneknQy Fk/dKOWQ2J8Xkx1XIGvDsNqpoTnreibfxFpTjS9if5vTLwwZBxD2QE9ZurjSxeK8mulT63sP4Aa 88bvKmRCh42Mv/KpGfYlGGlfUdNTSihFK6m76eXrWco3gk3VjWiNcrAXJqOl4yRxkMhkXneUUT9 /Kg== X-Google-Smtp-Source: AGHT+IGvdgPJQLNk8VYsJILY0GbhobojYDagFzi9U9GlfgWpk9agg+4Z4umGvcSaLY4EEXsdXUXAcQ== X-Received: by 2002:a05:6102:5121:b0:4b2:cca7:7d51 with SMTP id ada2fe7eead31-4ba47a68d02mr2571561137.19.1738794332017; Wed, 05 Feb 2025 14:25:32 -0800 (PST) Received: from localhost.localdomain ([38.44.237.182]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-866941edbefsm2475354241.28.2025.02.05.14.25.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 14:25:31 -0800 (PST) From: Denzeel Oliva To: krzk@kernel.org, alim.akhtar@samsung.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Denzeel Oliva Subject: [PATCH v1 6/9] dt-bindings: soc: samsung: exynos-sysreg: add compatibles peric0/1 sysreg for Exynos990 Date: Wed, 5 Feb 2025 22:22:20 +0000 Message-Id: <20250205222223.613-7-wachiturroxd150@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250205222223.613-1-wachiturroxd150@gmail.com> References: <20250205222223.613-1-wachiturroxd150@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_142532_881125_31D62EA5 X-CRM114-Status: UNSURE ( 9.92 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Downstream from the Exynos990 kernel source it has more sysreg in flexpmu, but for now only those two will be added Signed-off-by: Denzeel Oliva --- .../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml index a75aef240..6ca3862b1 100644 --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml @@ -25,6 +25,8 @@ properties: - samsung,exynos8895-fsys1-sysreg - samsung,exynos8895-peric0-sysreg - samsung,exynos8895-peric1-sysreg + - samsung,exynos990-peric0-sysreg + - samsung,exynos990-peric1-sysreg - samsung,exynosautov920-peric0-sysreg - samsung,exynosautov920-peric1-sysreg - tesla,fsd-cam-sysreg From patchwork Wed Feb 5 22:22:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Denzeel Oliva X-Patchwork-Id: 13961984 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 97C53C02192 for ; Wed, 5 Feb 2025 22:36:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=uzHXPjnnQeZMi9cL52smC0ygDtHtZgnTWZYMMKv/xU0=; b=Kx9++88ypGvbQ9VWWP4klbQWTz 43oL1DOSNZpIHYKpT/g4Dp6Ln1yRqK+xXx1ZZR3vKvlQiYaHOzX4nlDOMyhxppGYaWULfsb6VK7dS UaxkCdAlLGd41R+tOy16wqf1avJUyinMONZM3KIFGfr/YC4khAgGQaYs4Tdpfisd6p3nCipHCG8sn pQtgpbOocLiCno6wf2NMvGvzVvZEG6Ru08Idz4kLTjh/dOiie/5in2f+RRFvEC1YhS2NJcmV3Flu3 TFPj9dZgA8i5dT6guBN545AuZuLj7fj/A4B25+dL9fk5AFD7JTmdEMNjoVks5dtQSs0zvUNrg4M+M U4AGr+/g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfo02-00000004ke1-3H9G; Wed, 05 Feb 2025 22:36:02 +0000 Received: from mail-vs1-xe2a.google.com ([2607:f8b0:4864:20::e2a]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfnpw-00000004j4z-0T1L for linux-arm-kernel@lists.infradead.org; Wed, 05 Feb 2025 22:25:38 +0000 Received: by mail-vs1-xe2a.google.com with SMTP id ada2fe7eead31-4affbc4dc74so173504137.0 for ; Wed, 05 Feb 2025 14:25:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738794335; x=1739399135; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uzHXPjnnQeZMi9cL52smC0ygDtHtZgnTWZYMMKv/xU0=; b=bWmTLxqoVjkqx+J7/Se4UuRoctg7sAqNb07GrqC1AyRwEP7NBrYb/h2TQ0s1swqKDT jtUdIylfffLxLzslpcAg9wBOfDosZZc7EU1VbCtl1on3GFcC23+vBilrZVxnVshKfUe9 342g3cJrgDoUMxU0ggwhwpK3HGBjuiYHZ00OghxhDBIRTYnFKoyUdy4gPPbc3ob/6dWD Yk06saX7iuXrZxgt0U78xICEz2ts12ODUELUxa2rc5Kmd0y2kfTwhhrZr5RHwGWRYLEP UfwoD4H4IUk9g4qMJqJBPRNFumont8/8CSguaiYFcyTW+fVxTnPbzMiZDzg7R1FIDWZm uGcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738794335; x=1739399135; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uzHXPjnnQeZMi9cL52smC0ygDtHtZgnTWZYMMKv/xU0=; b=ukNvIVvXvOe2UYCaz4EqavozpJmp0XdeK8WDCWL7To52JTRl84IOKy3CVG3GQal4nI i/7JHP+ouL7GZuWv+xan49rtNoSOpPp7J+lXREf+0JO0MBHjQjomQuXZze9/pipS6ZON Ie8gChDqxtoNP1Rx1Wr91gUh1BGSKqYd21T+AiLygmynVu6YtLuGiQFHj3/QkmV/uoI7 PisPGgKH4i5DaFcNZeDkD687raEPotWUwiHD34FwY8EQiQW4/lLv9mF12UxQV/vCAnn/ EnB41zb1EtrAbhu3gC8ycrbWufJYaDPQBIod+kNu3T5Kx61DWFS3QlpZwSWOaoHVnkyn d/iw== X-Forwarded-Encrypted: i=1; AJvYcCVlhkdOJbhMTM56/Kkd7kdq1uyuil5+pVFqrm6qQJRrsgQz49+nGDsahjK8eQYUiazxVf084nx4Z27ZeDZPwn4G@lists.infradead.org X-Gm-Message-State: AOJu0YzhezCr0uySTTQrdSUF24YE4Fk8qeAvPTldUAx7opCufYUGueH/ vEKBi0sLs8NDEnHZp/2utiAfZfFa55isrXkun4bZxuhWKLy9yIyHMYiPY+HQ X-Gm-Gg: ASbGncsmx8EIn0rmlj//UhKZq670WoEXQQBVsYvk6JwqpdoMaX64EIPeRbG0n7hKmT2 UVwa53YAmE48rRdLWT5fIAK+WKdA1ZFbd1xLNliFDzwxbQdpARsvVox+Bhgl3u6hdZBfEbJ3Jw8 oiCtgW1jgmzCCVeablr/H33vntAnPHFrB426VLFjnUay3GKJ3z6KQ7pkzxD+OyKHdLmKlD3f58p B/Yi9+A9jHDuFHcVObmqSG1Pj5T9+MreIRXVjEOoyKJlxTyUF7saXodK6N8/EQ2mmdFxXhUcnus 2NJmdb5kUjvLj67DNA8U8NNCECMOJ4i7tZFWvrcJ8U6CU7hgSFeZoHTU5BACbqYuKt8MwQxXWnT 90A== X-Google-Smtp-Source: AGHT+IEk9t6iHqM9zzo5cq76ILwFDWUhzF27u0ipR8iiY+utpNoGDIMrxrnvywNjcWlJi/RTnBmtNg== X-Received: by 2002:a05:6102:5122:b0:4b9:b499:890 with SMTP id ada2fe7eead31-4ba47b0614cmr3362072137.23.1738794334674; Wed, 05 Feb 2025 14:25:34 -0800 (PST) Received: from localhost.localdomain ([38.44.237.182]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-866941edbefsm2475354241.28.2025.02.05.14.25.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 14:25:34 -0800 (PST) From: Denzeel Oliva To: krzk@kernel.org, alim.akhtar@samsung.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Denzeel Oliva Subject: [PATCH v1 7/9] clk: samsung: exynos990: add support for CMU_PERIC0/1 Date: Wed, 5 Feb 2025 22:22:21 +0000 Message-Id: <20250205222223.613-8-wachiturroxd150@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250205222223.613-1-wachiturroxd150@gmail.com> References: <20250205222223.613-1-wachiturroxd150@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_142536_231295_014E85D3 X-CRM114-Status: GOOD ( 13.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org CMU_PERIC0/1 is the clock management unit used for the peric0/1 block which is used for USI and I2C. Add support for all cmu_peric0 clocks but CLK_GOUT_PERIC0|1_IP (not enough info in the datasheet). None of the clocks are marked as critical. Signed-off-by: Denzeel Oliva --- drivers/clk/samsung/clk-exynos990.c | 1079 +++++++++++++++++++++++++++ 1 file changed, 1079 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-exynos990.c index 8e2a2e8ec..9ba17f360 100644 --- a/drivers/clk/samsung/clk-exynos990.c +++ b/drivers/clk/samsung/clk-exynos990.c @@ -19,6 +19,8 @@ /* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR_TOP (CLK_GOUT_CMU_VRA_BUS + 1) #define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_D_HSI0_ACLK + 1) +#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_TOP1_IPCLK_8 + 1) +#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_USI17_I3C_PCLK + 1) /* ---- CMU_TOP ------------------------------------------------------------- */ @@ -1305,6 +1307,1077 @@ static const struct samsung_cmu_info hsi0_cmu_info __initconst = { .clk_name = "bus", }; +/* ---- CMU_PERIC0 --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_PERIC0 (0x10400000) */ +#define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600 +#define PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER 0x0604 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USI_USER 0x0620 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI00_USI_USER 0x0624 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USI_USER 0x0630 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI01_USI_USER 0x0634 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USI_USER 0x0640 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI02_USI_USER 0x0644 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USI_USER 0x0650 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI03_USI_USER 0x0654 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI04_USI_USER 0x0660 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI04_USI_USER 0x0664 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI05_USI_USER 0x0670 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI05_USI_USER 0x0674 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI_I2C_USER 0x06b0 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI_I2C_USER 0x06b4 +#define PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG 0x0610 +#define PLL_CON1_MUX_CLKCMU_PERIC0_UART_DBG 0x0614 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI13_USI_USER 0x0680 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI13_USI_USER 0x0684 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0690 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0694 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI15_USI_USER 0x06a0 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI15_USI_USER 0x06a4 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI 0x1804 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI 0x1808 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI 0x180c +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI 0x1810 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI 0x1814 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI 0x1818 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C 0x1828 +#define CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG 0x1800 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI 0x181c +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI 0x1820 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI 0x1824 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2010 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x20e4 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK 0x2004 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK 0x20b4 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK 0x2008 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK 0x20bc +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK 0x20e0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK 0x20c0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK 0x20c4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK 0x20c8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK 0x20cc +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK 0x20d0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK 0x20b8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK 0x2014 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK 0x20d4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK 0x20d8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK 0x200c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK 0x20dc +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x2030 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2060 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2064 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x2068 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x206c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2070 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2074 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x2048 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x204c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12 0x2050 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13 0x2054 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14 0x2058 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15 0x205c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2034 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x2038 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x203c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x2040 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2044 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x2018 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x201c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12 0x2020 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13 0x2024 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14 0x2028 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15 0x202c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0 0x2094 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3 0x209c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4 0x20a0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5 0x20a4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6 0x20a8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7 0x20ac +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8 0x20b0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15 0x2098 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0 0x2078 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3 0x207c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4 0x2080 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5 0x2084 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6 0x2088 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7 0x208c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8 0x2090 + +static const unsigned long peric0_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI00_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI01_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI02_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI03_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI04_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI04_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI05_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI05_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI_I2C_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI_I2C_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG, + PLL_CON1_MUX_CLKCMU_PERIC0_UART_DBG, + PLL_CON0_MUX_CLKCMU_PERIC0_USI13_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI13_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI15_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI15_USI_USER, + CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, + CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG, + CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8, +}; + +PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_cmu_peric0_bus" }; +PNAME(mout_peric0_usi00_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi01_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi02_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi03_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi04_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi05_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi_i2c_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_uart_dbg_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi13_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi14_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi15_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; + +static const struct samsung_mux_clock peric0_mux_clks[] __initconst = { + MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user", + mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI00_USI_USER, "mout_peric0_usi00_usi_user", + mout_peric0_usi00_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI01_USI_USER, "mout_peric0_usi01_usi_user", + mout_peric0_usi01_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI02_USI_USER, "mout_peric0_usi02_usi_user", + mout_peric0_usi02_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI03_USI_USER, "mout_peric0_usi03_usi_user", + mout_peric0_usi03_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI04_USI_USER, "mout_peric0_usi04_usi_user", + mout_peric0_usi04_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI04_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI05_USI_USER, "mout_peric0_usi05_usi_user", + mout_peric0_usi05_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI05_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI_I2C_USER, "mout_peric0_usi_i2c_user", + mout_peric0_usi_i2c_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI_I2C_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_UART_DBG, "mout_peric0_uart_dbg", + mout_peric0_uart_dbg_p, PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG, 4, 1), + MUX(CLK_MOUT_PERIC0_USI13_USI_USER, "mout_peric0_usi13_usi_user", + mout_peric0_usi13_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI13_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI14_USI_USER, "mout_peric0_usi14_usi_user", + mout_peric0_usi14_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI15_USI_USER, "mout_peric0_usi15_usi_user", + mout_peric0_usi15_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI15_USI_USER, 4, 1), +}; + +static const struct samsung_div_clock peric0_div_clks[] __initconst = { + DIV(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi", "mout_peric0_usi00_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi", "mout_peric0_usi01_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi", "mout_peric0_usi02_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi", "mout_peric0_usi03_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi", "mout_peric0_usi04_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi", "mout_peric0_usi05_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI_I2C, "dout_peric0_usi_i2c", "mout_peric0_usi_i2c_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0, 4), + DIV(CLK_DOUT_PERIC0_UART_DBG, "dout_peric0_uart_dbg", "mout_peric0_uart_dbg", + CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG, 0, 4), + DIV(CLK_DOUT_PERIC0_USI13_USI, "dout_peric0_usi13_usi", "mout_peric0_usi13_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI14_USI, "dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI15_USI, "dout_peric0_usi15_usi", "mout_peric0_usi15_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI, 0, 4), +}; + +static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { + GATE(CLK_GOUT_PERIC0_GPIO_PCLK, "gout_peric0_gpio_pclk", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_SYSREG_PCLK, "gout_peric0_sysreg_pclk", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CMU_PCLK, "gout_peric0_cmu_pclk", + "mout_peric0_bus_user", + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_BUSP_CLK, "gout_peric0_busp_pclk", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_OSCCLK_CLK, "gout_peric0_oscclk_pclk", + "oscclk", + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI00_USI_CLK, "gout_peric0_usi00_usi_clk", + "dout_peric0_usi00_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI_I2C_CLK, "gout_peric0_usi_i2c_clk", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI01_USI_CLK, "gout_peric0_usi01_usi_clk", + "dout_peric0_usi01_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI02_USI_CLK, "gout_peric0_usi02_usi_clk", + "dout_peric0_usi02_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI03_USI_CLK, "gout_peric0_usi03_usi_clk", + "dout_peric0_usi03_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI04_USI_CLK, "gout_peric0_usi04_usi_clk", + "dout_peric0_usi04_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI05_USI_CLK, "gout_peric0_usi05_usi_clk", + "dout_peric0_usi05_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_UART_DBG_CLK, "gout_peric0_uart_dbg_clk", + "dout_peric0_uart_dbg", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_LHM_AXI_P_CLK, "gout_peric0_lhm_axi_p_clk", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI13_USI_CLK, "gout_peric0_usi13_usi_clk", + "dout_peric0_usi13_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI14_USI_CLK, "gout_peric0_usi14_usi_clk", + "dout_peric0_usi14_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_D_TZPC_PCLK, "gout_peric0_d_tpzc_pclk", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_USI15_USI_CLK, "gout_peric0_usi15_usi_clk", + "dout_peric0_usi15_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_4, "gout_peric0_top0_ipclk_4", + "dout_peric0_uart_dbg", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_4, "gout_peric0_top0_pclk_4", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_5, "gout_peric0_top0_pclk_5", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_6, "gout_peric0_top0_pclk_6", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_7, "gout_peric0_top0_pclk_7", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_8, "gout_peric0_top0_pclk_8", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_9, "gout_peric0_top0_pclk_9", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_10, "gout_peric0_top0_pclk_10", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_11, "gout_peric0_top0_pclk_11", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_12, "gout_peric0_top0_pclk_12", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_13, "gout_peric0_top0_pclk_13", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_14, "gout_peric0_top0_pclk_14", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_PCLK_15, "gout_peric0_top0_pclk_15", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_5, "gout_peric0_top0_ipclk_5", + "dout_peric0_usi00_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_6, "gout_peric0_top0_ipclk_6", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_7, "gout_peric0_top0_ipclk_7", + "dout_peric0_usi01_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_8, "gout_peric0_top0_ipclk_8", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_9, "gout_peric0_top0_ipclk_9", + "dout_peric0_usi02_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_10, "gout_peric0_top0_ipclk_10", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_11, "gout_peric0_top0_ipclk_11", + "dout_peric0_usi03_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_12, "gout_peric0_top0_ipclk_12", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_13, "gout_peric0_top0_ipclk_13", + "dout_peric0_usi04_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_14, "gout_peric0_top0_ipclk_14", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_15, "gout_peric0_top0_ipclk_15", + "dout_peric0_usi05_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_0, "gout_peric0_top1_pclk_0", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_3, "gout_peric0_top1_pclk_3", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_4, "gout_peric0_top1_pclk_4", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_5, "gout_peric0_top1_pclk_5", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_6, "gout_peric0_top1_pclk_6", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_7, "gout_peric0_top1_pclk_7", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_8, "gout_peric0_top1_pclk_8", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_PCLK_15, "gout_peric0_top1_pclk_15", + "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_0, "gout_peric0_top1_ipclk_0", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_3, "gout_peric0_top1_ipclk_3", + "dout_peric0_usi13_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_4, "gout_peric0_top1_ipclk_4", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_5, "gout_peric0_top1_ipclk_5", + "dout_peric0_usi14_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_6, "gout_peric0_top1_ipclk_6", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_7, "gout_peric0_top1_ipclk_7", + "dout_peric0_usi15_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_8, "gout_peric0_top1_ipclk_8", + "dout_peric0_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8, + 21, 0, 0), +}; + +static const struct samsung_cmu_info peric0_cmu_info __initconst = { + .mux_clks = peric0_mux_clks, + .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), + .div_clks = peric0_div_clks, + .nr_div_clks = ARRAY_SIZE(peric0_div_clks), + .gate_clks = peric0_gate_clks, + .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), + .nr_clk_ids = CLKS_NR_PERIC0, + .clk_regs = peric0_clk_regs, + .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), + .clk_name = "bus", +}; + +/* ---- CMU_PERIC1 --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_PERIC1 (0x10700000) */ +#define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600 +#define PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER 0x0604 +#define PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER 0x0610 +#define PLL_CON1_MUX_CLKCMU_PERIC1_UART_BT_USER 0x0614 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI_I2C_USER 0x06c0 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI_I2C_USER 0x06c4 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USI_USER 0x0620 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI06_USI_USER 0x0624 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USI_USER 0x0630 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI07_USI_USER 0x0634 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USI_USER 0x0640 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI08_USI_USER 0x0644 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USI_USER 0x0650 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI09_USI_USER 0x0654 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0660 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0664 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0670 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0674 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0680 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0684 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI18_USI_USER 0x06b0 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI18_USI_USER 0x06b4 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER 0x0690 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI16_USI_USER 0x0694 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI17_USI_USER 0x06a0 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI17_USI_USER 0x06a4 +#define CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT 0x1800 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x182c +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI 0x1804 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI 0x1808 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI 0x180c +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI 0x1828 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x181c +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x1810 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1814 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x1818 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI 0x1820 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI 0x1824 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK 0x2018 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK 0x2108 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK 0x2004 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK 0x20dc +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK 0x20e4 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK 0x20e8 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK 0x20ec +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK 0x20f0 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK 0x20f4 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK 0x2104 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK 0x2008 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK 0x200c +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK 0x2010 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK 0x2020 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK 0x20f8 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK 0x2014 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK 0x20fc +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK 0x2100 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x2058 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10 0x2040 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11 0x2044 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_12 0x2048 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_13 0x204c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_14 0x2050 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15 0x2054 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x203c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10 0x2024 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11 0x2028 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_12 0x202c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_13 0x2030 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_14 0x2034 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_15 0x2038 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_1 0x20a0 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_0 0x209c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_2 0x20bc +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_3 0x20c0 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4 0x20c4 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5 0x20c8 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6 0x20cc +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7 0x20d0 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9 0x20d8 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10 0x20a4 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_0 0x205c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_1 0x2060 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_2 0x207c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_3 0x2080 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4 0x2084 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5 0x2088 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6 0x208c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7 0x2090 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9 0x2098 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10 0x2064 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK 0x20e0 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK 0x201c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK 0x211c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12 0x206c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12 0x20ac +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13 0x20b0 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14 0x20b4 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15 0x20b8 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13 0x2070 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14 0x2074 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15 0x2078 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK 0x210c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK 0x2110 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK 0x2118 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK 0x2114 + +static const unsigned long peric1_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_UART_BT_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI_I2C_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI_I2C_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI06_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI07_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI08_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI09_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI18_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI18_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI16_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI17_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI17_USI_USER, + CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT, + CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, + CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_1, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_1, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK, +}; + +PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_cmu_peric1_bus" }; +PNAME(mout_peric1_uart_bt_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi_i2c_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi06_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi07_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi08_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi09_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi10_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi11_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi12_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi18_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi16_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; +PNAME(mout_peric1_usi17_user_p) = { "oscclk", "dout_cmu_peric1_ip" }; + +static const struct samsung_mux_clock peric1_mux_clks[] __initconst = { + MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user", + mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_UART_BT_USER, "mout_peric1_uart_bt_user", + mout_peric1_uart_bt_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI_I2C_USER, "mout_peric1_usi_i2c_user", + mout_peric1_usi_i2c_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI_I2C_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI06_USI_USER, "mout_peric1_usi06_usi_user", + mout_peric1_usi06_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI07_USI_USER, "mout_peric1_usi07_usi_user", + mout_peric1_usi07_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI08_USI_USER, "mout_peric1_usi08_usi_user", + mout_peric1_usi08_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI09_USI_USER, "mout_peric1_usi09_usi_user", + mout_peric1_usi09_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI10_USI_USER, "mout_peric1_usi10_usi_user", + mout_peric1_usi10_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI11_USI_USER, "mout_peric1_usi11_usi_user", + mout_peric1_usi11_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI12_USI_USER, "mout_peric1_usi12_usi_user", + mout_peric1_usi12_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI18_USI_USER, "mout_peric1_usi18_usi_user", + mout_peric1_usi18_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI18_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI16_USI_USER, "mout_peric1_usi16_usi_user", + mout_peric1_usi16_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI17_USI_USER, "mout_peric1_usi17_usi_user", + mout_peric1_usi17_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI17_USI_USER, 4, 1), +}; + +static const struct samsung_div_clock peric1_div_clks[] __initconst = { + DIV(CLK_DOUT_PERIC1_UART_BT, "dout_peric1_uart_bt", "mout_peric1_uart_bt_user", + CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT, 0, 4), + DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c", "mout_peric1_usi_i2c_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4), + DIV(CLK_DOUT_PERIC1_USI06_USI, "dout_peric1_usi06_usi", "mout_peric1_usi06_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI07_USI, "dout_peric1_usi07_usi", "mout_peric1_usi07_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI08_USI, "dout_peric1_usi08_usi", "mout_peric1_usi08_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI18_USI, "dout_peric1_usi18_usi", "mout_peric1_usi18_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI12_USI, "dout_peric1_usi12_usi", "mout_peric1_usi12_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi", "mout_peric1_usi09_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi", "mout_peric1_usi10_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi", "mout_peric1_usi11_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI16_USI, "dout_peric1_usi16_usi", "mout_peric1_usi16_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI17_USI, "dout_peric1_usi17_usi", "mout_peric1_usi17_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI, 0, 4), +}; + +static const struct samsung_gate_clock peric1_gate_clks[] __initconst = { + GATE(CLK_GOUT_PERIC1_GPIO_PCLK, "gout_peric1_gpio_pclk", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_SYSREG_PCLK, "gout_peric1_sysreq_pclk", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_CMU_PCLK, "gout_peric1_cmu_pclk", + "mout_peric1_bus_user", + CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_BUSP_CLK, "gout_peric1_busp_clk", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI06_USI_CLK, "gout_peric1_usi06_usi_clk", + "dout_peric1_usi06_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI07_USI_CLK, "gout_peric1_usi07_usi_clk", + "dout_peric1_usi07_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI08_USI_CLK, "gout_peric1_usi08_usi_clk", + "dout_peric1_usi08_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI09_USI_CLK, "gout_peric1_usi09_usi_clk", + "dout_peric1_usi09_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI10_USI_CLK, "gout_peric1_usi10_usi_clk", + "dout_peric1_usi10_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI_I2C_CLK, "gout_peric1_usi_i2c_clk", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_UART_BT_CLK, "gout_peric1_uart_bt_clk", + "dout_peric1_uart_bt", + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI12_USI_CLK, "gout_peric1_usi12_usi_clk", + "dout_peric1_usi12_usi", + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI18_USI_CLK, "gout_peric1_usi18_usi_clk", + "dout_peric1_usi18_usi", + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_LHM_AXI_P_CLK, "gout_peric1_lhm_axi_p_clk", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI11_USI_CLK, "gout_peric1_usi11_usi_clk", + "dout_peric1_usi11_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_D_TZPC_PCLK, "gout_peric1_d_tzpc_pclk", + "dout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI16_USI_CLK, "gout_peric1_usi16_usi_clk", + "dout_peric1_usi16_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI17_USI_CLK, "gout_peric1_usi17_usi_clk", + "dout_peric1_usi17_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_PCLK_4, "gout_peric1_top0_pclk_4", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_PCLK_10, "gout_peric1_top0_pclk_10", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_PCLK_11, "gout_peric1_top0_pclk_11", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_PCLK_12, "gout_peric1_top0_pclk_12", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_PCLK_13, "gout_peric1_top0_pclk_13", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_PCLK_14, "gout_peric1_top0_pclk_14", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_PCLK_15, "gout_peric1_top0_pclk_15", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_4, "gout_peric1_top0_ipclk_4", + "dout_peric1_uart_bt", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_10, "gout_peric1_top0_ipclk_10", + "dout_peric1_usi06_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_11, "gout_peric1_top0_ipclk_11", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_12, "gout_peric1_top0_ipclk_12", + "dout_peric1_usi07_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_13, "gout_peric1_top0_ipclk_13", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_14, "gout_peric1_top0_ipclk_14", + "dout_peric1_usi08_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_15, "gout_peric1_top0_ipclk_15", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_1, "gout_peric1_top1_pclk_1", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_1, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_0, "gout_peric1_top1_pclk_0", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_0, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_2, "gout_peric1_top1_pclk_2", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_2, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_3, "gout_peric1_top1_pclk_3", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_4, "gout_peric1_top1_pclk_4", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_5, "gout_peric1_top1_pclk_5", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_6, "gout_peric1_top1_pclk_6", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_7, "gout_peric1_top1_pclk_7", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_9, "gout_peric1_top1_pclk_9", + "dout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_10, "gout_peric1_top1_pclk_10", + "dout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_0, "gout_peric1_top1_ipclk_0", + "dout_peric1_usi09_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_0, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_1, "gout_peric1_top1_ipclk_1", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_1, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_2, "gout_peric1_top1_ipclk_2", + "dout_peric1_usi10_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_2, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_3, "gout_peric1_top1_ipclk_3", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_4, "gout_peric1_top1_ipclk_4", + "dout_peric1_usi11_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_5, "gout_peric1_top1_ipclk_5", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_6, "gout_peric1_top1_ipclk_6", + "dout_peric1_usi16_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_7, "gout_peric1_top1_ipclk_7", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_9, "gout_peric1_top1_ipclk_9", + "dout_peric1_usi17_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_10, "gout_peric1_top1_ipclk_10", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_OSCCLK_CLK, "gout_peric1_oscclk_clk", + "oscclk", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_LHM_AXI_P_CSIS_CLK, "gout_peric1_lhm_axi_p_csis_clk", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_XIU_P_ACLK, "gout_peric1_xiu_p_aclk", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_12, "gout_peric1_top1_ipclk_12", + "dout_peric1_usi12_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_12, "gout_peric1_top1_pclk_12", + "dout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_13, "gout_peric1_top1_pclk_13", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_14, "gout_peric1_top1_pclk_14", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_PCLK_15, "gout_peric1_top1_pclk_15", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_13, "gout_peric1_top1_ipclk_13", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_14, "gout_peric1_top1_ipclk_14", + "dout_peric1_usi18_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_15, "gout_peric1_top1_ipclk_15", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI16_I3C_PCLK, "gout_peric1_usi16_i3c_pclk", + "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI16_I3C_SCLK, "gout_peric1_usi16_i3c_sclk", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI17_I3C_SCLK, "gout_peric1_usi17_i3c_sclk", + "dout_peric1_usi_i2c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_USI17_I3C_PCLK, "gout_peric1_usi17_i3c_pclk", + "dout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK, + 21, 0, 0), +}; + +static const struct samsung_cmu_info peric1_cmu_info __initconst = { + .mux_clks = peric1_mux_clks, + .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), + .div_clks = peric1_div_clks, + .nr_div_clks = ARRAY_SIZE(peric1_div_clks), + .gate_clks = peric1_gate_clks, + .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), + .nr_clk_ids = CLKS_NR_PERIC1, + .clk_regs = peric1_clk_regs, + .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), + .clk_name = "bus", +}; + /* ----- platform_driver ----- */ static int __init exynos990_cmu_probe(struct platform_device *pdev) @@ -1322,6 +2395,12 @@ static const struct of_device_id exynos990_cmu_of_match[] = { { .compatible = "samsung,exynos990-cmu-hsi0", .data = &hsi0_cmu_info, + }, { + .compatible = "samsung,exynos990-cmu-peric0", + .data = &peric0_cmu_info, + }, { + .compatible = "samsung,exynos990-cmu-peric1", + .data = &peric1_cmu_info, }, { }, }; From patchwork Wed Feb 5 22:22:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Denzeel Oliva X-Patchwork-Id: 13961985 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 946BEC02192 for ; Wed, 5 Feb 2025 22:37:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=u5xkd5rT9wUgRW3DUsokQnKDvE7TCE8CtMzGLaY1JBw=; b=rOb939YRbQVQPN1TXOCbYnWkVh Jxx79Rf14thN9q+g2ZD9H18lkWe5G6NiZYJRKpOyTOcqQi5Xu91Vl5uWQzR50o32dLevVkOhUz0RN +RyswRuuCZQFtUQTEt0E+2PF9CRLSPh4gz7eq3QJUNplY3SsoP3BpJXHl4kXvZck17eRf0xgAVFPq lcl0QJZ9HMteQ5qJUzWXxrFYjFxnZ9PXqQh4HgBg31ik9P9ufWT9NVJiN2H+m/QWt/U/sb8tXs8+n uCLtP4Rlr/dlVyvOwJxCPX8MIDvuecx4mOH+EO4bqIn4EI87DwiQ+hJKR7lGuWN/SmM4rdNP6AaDL 10xx9Jbw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfo1O-00000004klA-2ej5; Wed, 05 Feb 2025 22:37:26 +0000 Received: from mail-vs1-xe2c.google.com ([2607:f8b0:4864:20::e2c]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfnpy-00000004j6B-0QbJ for linux-arm-kernel@lists.infradead.org; Wed, 05 Feb 2025 22:25:39 +0000 Received: by mail-vs1-xe2c.google.com with SMTP id ada2fe7eead31-4afe4f1ce18so85842137.3 for ; Wed, 05 Feb 2025 14:25:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738794337; x=1739399137; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u5xkd5rT9wUgRW3DUsokQnKDvE7TCE8CtMzGLaY1JBw=; b=irdHHkNOAnfwY0YXpIB7il0MwDOJd/XvtveoinhxenaCMQab2o7OkJbztg5NCIe9Fu Q/myS0Bhqa9ywKW15rcBsw/NpPRA2Yh27R44JL9yfxOp6qMbCOykYTcPzgKhYvgv64Y8 SMG2jcuJ/A1aD/iKGctttY5QbKyStV8JY2EkbsxBfinGb9LDBbyMznqI9RQ9QtA3kYqY 3ss2vM+nRzRjuhPwDAlIdpvAN4Tkk0o4QoYqL+Kn5YdjLNrK6n6SkFmUA+NlpPozQrb7 iVVjkjkoRtOpgEozgnkbe6AV4zSspzBSWrthGoXHs++Gqij2tHgnRL8LrAUtBoDW9zTq Vxow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738794337; x=1739399137; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u5xkd5rT9wUgRW3DUsokQnKDvE7TCE8CtMzGLaY1JBw=; b=X2zJ59TIgODHtZ0Sqr8xvvvYeXMRpzHCofarrLOAIFA4JIrNTwMvTpXrP/hzZI6JLt bSc9Yp1r+hOGXAOmceYRMn66v3Cj2rlRqU+OvUj7yyOV9iuzf7pJGQNp09MO1t2Bgoow Le14jwrHLasUsmbFeoZE7qaVNMUQsj0PgDiXRjcbFHaNs4wXUj+LZC5tP0P00hYskeXX +GxmL7Lz02ENbGF/Wmt3syn7jKgiLF2z0LG8O2ADqlw7PmmBRXZQQk8M+r202WRduJ+w r7jTTtoCfXEJhUN2NI9gpFmrFL4gTn0tbZpH9Keh1HMT6aWEcQQOR7dnntFffT6TzIhP cxqw== X-Forwarded-Encrypted: i=1; AJvYcCWg+WU3yBopjsH63oP3uDwtSg9iMOQv9sLfmWi28JUEgprzyuy/QnrigDua+lj3ysDbcBzj44SRaZVKYoHFB2s3@lists.infradead.org X-Gm-Message-State: AOJu0YzedJu4DUbRoWArCTlcs2WerMiaQR3g0Ft8hOqvhlWAnWo569Fu DpkBZo4X4Dn+3m1oZefyBzzvhuhaDw68WMDgzYQzY2Grsku6UEVc X-Gm-Gg: ASbGnctSeylYppl1fQC4RfCAyNLRloTZwWVthKMRsQidA/Reg4USm8otMdQSKuSTkPE x9LHKp6StX1OU4ZTag2aVX4OnkGV524L4kTbqjcXve9SkcQNPkabnXpXKu/E90N8ugzUmWvznIC YolmMyXYve6X0GTLHB3+1IrXk0SZcNRapQbtGH7UnMaynfSyo+SEK4q+pM8R7uHxBCgd5cbwPhG NecxDVCX8pYyy3hiTfei7LrqlzMPrnm5e0NFkpMtBxb6FMguwHRUcYu3RFJ6LzfZplAJdXacwor Z0LmGH9hJa7HdBksCT+Zxjkw6AtWItq23jnWoya47RksqaEgGHS1OBo0ZdxTJ4CNz6B/G8qJLbV DUw== X-Google-Smtp-Source: AGHT+IGX27jCqcI1MnR7gOhw8BskvTBlBSzOqYsxe/kPSS2u9T2tZ7z6U3M/YmSUWd09bAr2G7LKUA== X-Received: by 2002:a05:6102:418d:b0:4b2:7996:6ba4 with SMTP id ada2fe7eead31-4ba47ae4d3amr3246093137.25.1738794336852; Wed, 05 Feb 2025 14:25:36 -0800 (PST) Received: from localhost.localdomain ([38.44.237.182]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-866941edbefsm2475354241.28.2025.02.05.14.25.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 14:25:36 -0800 (PST) From: Denzeel Oliva To: krzk@kernel.org, alim.akhtar@samsung.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Denzeel Oliva Subject: [PATCH v1 8/9] spi: s3c64xx: add support exynos990-spi to new port config data Date: Wed, 5 Feb 2025 22:22:22 +0000 Message-Id: <20250205222223.613-9-wachiturroxd150@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250205222223.613-1-wachiturroxd150@gmail.com> References: <20250205222223.613-1-wachiturroxd150@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_142538_142991_FB5C9776 X-CRM114-Status: GOOD ( 13.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Exynos990 has the same version of USI SPI (v2.1) as GS101. Drop the fifo_lvl_mask and rx_lvl_offset and switch to the new port config data. Exynoos990 data for SPI: - the FIFO depth is always the same size for exynos990 (64 bytes and 256 bytes), sizes of 256 bytes will be put in DT. - Exynos990 allows only accesses to 32-bit registers; otherwise, An error interrupt is generated. Perform write register accesses in 32 bits. Signed-off-by: Denzeel Oliva --- drivers/spi/spi-s3c64xx.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 389275dbc..d4cbbaa9a 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1586,6 +1586,19 @@ static const struct s3c64xx_spi_port_config exynos850_spi_port_config = { .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, }; +static const struct s3c64xx_spi_port_config exynos990_spi_port_config = { + .fifo_depth = 64, + .rx_fifomask = S3C64XX_SPI_ST_RX_FIFO_RDY_V2, + .tx_fifomask = S3C64XX_SPI_ST_TX_FIFO_RDY_V2, + .tx_st_done = 25, + .clk_div = 4, + .high_speed = true, + .clk_from_cmu = true, + .has_loopback = true, + .use_32bit_io = true, + .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, +}; + static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = { /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f, @@ -1664,6 +1677,9 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = { { .compatible = "samsung,exynos850-spi", .data = &exynos850_spi_port_config, }, + { .compatible = "samsung,exynos990-spi", + .data = &exynos990_spi_port_config, + }, { .compatible = "samsung,exynosautov9-spi", .data = &exynosautov9_spi_port_config, }, From patchwork Wed Feb 5 22:22:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Denzeel Oliva X-Patchwork-Id: 13961986 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F334C02192 for ; Wed, 5 Feb 2025 22:39:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=f5vxVshxL+QJcnnvml+ele3UhXfF2Cm1K2Nc5CJEARA=; b=ClNDqIesR5EKfmo4srsMkArr3k MMXjRUV9ZuHIsfK0CjpZrfSK4P8ihYkovsQAGwIpLxYQK4hCPfGN6JrxUHvYxyDD6e0t8y1vqXe0c XUMnplewFZdF5vv8WoSH4DKi2XIggRo03RUVWhXfDiuF2OD+kJ6jzav6k1a6gTIl+duYMaw+IR7Mi 6RKZ93v9doBPzrcSEZWTE6gcAUM64OagbI7y/wC4hmGfzRLNJcD1TC2oxh1BUcxXUD93kIBD60UJ+ TKbaIyLcpyTC+5oWusQqxCcuyqDTpmSr/oYENRJuttyfF+pKU7S4ifmF6cvjU4PqHwiQ1xiDny1gR T5xVdh1Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfo2j-00000004ksc-0zfV; Wed, 05 Feb 2025 22:38:49 +0000 Received: from mail-ua1-x92c.google.com ([2607:f8b0:4864:20::92c]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfnq0-00000004j8B-3urI for linux-arm-kernel@lists.infradead.org; Wed, 05 Feb 2025 22:25:43 +0000 Received: by mail-ua1-x92c.google.com with SMTP id a1e0cc1a2514c-866e8a51fa9so159494241.1 for ; Wed, 05 Feb 2025 14:25:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738794340; x=1739399140; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f5vxVshxL+QJcnnvml+ele3UhXfF2Cm1K2Nc5CJEARA=; b=GJYLbIDRzKhxnr5UKVFtZvMnkAZW46N56k5xpMLHVRk3Cz2Ng1poRy74D9JPlOFO6X oqQ694+cczI1e1nh6rhux1g4xRIWxEBrmm9vyP1DOPI+Qklyk3FfBHoeFPTh3fhO4My3 wuch5vh+FgnVzHsuQGnvxc+rCdyDrNdaRjITCDrfJ3S288hN89W//u1XoSB+rtwDjIOk ygxgkDHXb+1RtxlIM7qtSO1c+sDYyRrx3bym0EXKK8YbMSZjRDsoOCwZ/3r+MVtJDwrM Z1n/7JGlyJkcUtOu+7sjJ4nxMgoUSgAcbNIoMg6iI79CYYmAcgCy+eeXr2Ul8hfQTPaP WbUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738794340; x=1739399140; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f5vxVshxL+QJcnnvml+ele3UhXfF2Cm1K2Nc5CJEARA=; b=h6xgMPNSt+ryeFkb/tuEpi0BqHsbkavf+zziBmQfPaeJhgN1+burOXv57S7KzXHFB3 DIgMuz17fK6yFtgvIgSQmdn51lO6fOyPXjyvcmSpzHd4HhWZPclkN4f2SM+gIcIf/pJF FmZLVbUunp2c5y2o4nKijk5mg0m9r2MzWCs3PlWqBy8P222BgmlY4aS/TdQk3XXE2wxl D5xy2zUq5p8sd6kI4aHPiCq6RqyFZXw21Ei5/AlOqJpizghRjEYX2G9yRoiJtne96DZg KgcKGcs0kwB1meJobyXPdnQx9fM1VaJH0434b7nlMkTRNzH1yLAqtlQR0qVuqssXMlPx njBg== X-Forwarded-Encrypted: i=1; AJvYcCX7SKkTgUKiO5Vdn9wYwHJ/fy8q4VAuZ77hd+dPxNtxDOM2pGYcgnlTSI9Z4oqSniofLXENC5WzwsLknCN14c9a@lists.infradead.org X-Gm-Message-State: AOJu0YylxQqhXiwf6YWyQppO7uGjRPJ7EAZsalwuWQ87ZtL4uF8LL6cH vghyy+ItCAdQmZaVtyac6NbVpOaZ+fa/FUOkxOeFgDQ0kvkPq6OP X-Gm-Gg: ASbGncsjdURbu0chyZRGR3zfNOXUw6m4nIsOBk4nqvYxpp/tKBSkH/S+BkRx0Lqvb2Z 81SVsXHqoiCshi3f/eEeeADkVPI+xJA2l7wCQA/luWj+vrVvUZPG3Z+VAxxG1F/UA89ZNE+sVCH xB+vcFoqv9PFbSDMDzvKnp6JnZq7XL3iED/31lyk4hRw/hQwPGSUKhuAvS76C77vQu+Bece71nM ataxDxhABHgmzpL22P4/szhIyeuaMBb4DwG7o5jUtKiGqlWEoShcq3yrFkGT4BtoKMsXSiDFRTw 871mdQLtPbIhjVOz13/wMs6e8Y8XwZ8xy+6w3K8igbSL4+14Ii1fpnYTRfKMTRD4oJ03Isq32P6 Rxw== X-Google-Smtp-Source: AGHT+IFtH9HOARxnQefzm3RIupJ46GdZJabCLs7VgyFJPLtIb0Q+JDpiUpXQXiwr78wowR5ccujb5w== X-Received: by 2002:a67:f847:0:b0:4b6:8bd1:6b5d with SMTP id ada2fe7eead31-4ba71f5968bmr657088137.1.1738794339372; Wed, 05 Feb 2025 14:25:39 -0800 (PST) Received: from localhost.localdomain ([38.44.237.182]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-866941edbefsm2475354241.28.2025.02.05.14.25.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 14:25:38 -0800 (PST) From: Denzeel Oliva To: krzk@kernel.org, alim.akhtar@samsung.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Denzeel Oliva Subject: [PATCH v1 9/9] arm64: dts: exynos990: define all PERIC USI nodes Date: Wed, 5 Feb 2025 22:22:23 +0000 Message-Id: <20250205222223.613-10-wachiturroxd150@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250205222223.613-1-wachiturroxd150@gmail.com> References: <20250205222223.613-1-wachiturroxd150@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_142540_987708_1EC906C1 X-CRM114-Status: GOOD ( 10.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Universal Serial Interface (USI) supports three types of serial interface such as Universal Asynchronous Receiver and Transmitter (UART), Serial Peripheral Interface (SPI), and Inter-Integrated Circuit (I2C). Each protocols can be working independently and configured as one of those using external configuration inputs. Exynos990 SoC defines 18 USI nodes in PERIC0/1 blocks. Nodes have different depths from 64-256 bytes. Signed-off-by: Denzeel Oliva --- arch/arm64/boot/dts/exynos/exynos990.dtsi | 1711 +++++++++++++++++++++ 1 file changed, 1711 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos990.dtsi b/arch/arm64/boot/dts/exynos/exynos990.dtsi index 9d017dbed..adecad582 100644 --- a/arch/arm64/boot/dts/exynos/exynos990.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos990.dtsi @@ -201,12 +201,1723 @@ pinctrl_peric0: pinctrl@10430000 { interrupts = ; }; + cmu_peric0: clock-controller@10400000 { + compatible = "samsung,exynos990-cmu-peric0"; + reg = <0x10400000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; + clock-names = "oscclk", "bus", "ip"; + }; + + sysreg_peric0: syscon@10420000 { + compatible = "samsung,exynos990-peric0-sysreg", "syscon"; + reg = <0x10420000 0x10000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PCLK>; + }; + + usi_uart: usi@105400c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105400c0 0x20>; + samsung,sysreg = <&sysreg_peric0 0x1000>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_4>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_4>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + serial_0: serial@10540000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10540000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_4>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_4>; + clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + }; + + usi0: usi@105500c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105500c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_5>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1004>; + status = "disabled"; + + hsi2c_0: i2c@10550000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10550000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_5>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c0_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_0: spi@10550000 { + compatible = "samsung,exynos990-spi"; + reg = <0x10550000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_5>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_2: serial@10550000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10550000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_5>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart2_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_0: usi@105600c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105600c0 0x20>; + samsung,sysreg = <&sysreg_peric0 0x1008>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_6>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_6>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_1: i2c@10560000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10560000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c1_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_6>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_6>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi1: usi@105700c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105700c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_7>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x100c>; + status = "disabled"; + + hsi2c_2: i2c@10570000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10570000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_7>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c2_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_1: spi@10570000 { + compatible = "samsung,exynos990-spi"; + reg = <0x10570000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_7>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_3: serial@10570000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10570000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_7>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart3_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_1: usi@105800c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105800c0 0x20>; + samsung,sysreg = <&sysreg_peric0 0x1010>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_8>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_8>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_3: i2c@10580000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10580000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c3_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_8>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_8>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi2: usi@105900c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105900c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_9>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_9>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1014>; + status = "disabled"; + + hsi2c_4: i2c@10590000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10590000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_9>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_9>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c4_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_2: spi@10590000 { + compatible = "samsung,exynos990-spi"; + reg = <0x10590000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_9>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_9>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_4: serial@10590000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10590000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_9>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_9>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart4_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_2: usi@105a00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105a00c0 0x20>; + samsung,sysreg = <&sysreg_peric0 0x1018>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_10>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_10>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_5: i2c@105a0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x105a0000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c5_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_10>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_10>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi3: usi@105b00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105b00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_11>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_11>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x101c>; + status = "disabled"; + + hsi2c_6: i2c@105b0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x105b0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_11>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_11>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c6_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_3: spi@105b0000 { + compatible = "samsung,exynos990-spi"; + reg = <0x105b0000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_11>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_11>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_5: serial@105b0000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x105b0000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_11>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_11>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart5_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_3: usi@105c00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105c00c0 0x20>; + samsung,sysreg = <&sysreg_peric0 0x1020>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_12>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_12>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_7: i2c@105c0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x105c0000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c7_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_12>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_12>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi4: usi@105d00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105d00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_13>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_13>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1024>; + status = "disabled"; + + hsi2c_8: i2c@105d0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x105d0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_13>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_13>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c8_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_4: spi@105d0000 { + compatible = "samsung,exynos990-spi"; + reg = <0x105d0000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi4_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_13>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_13>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_6: serial@105d0000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x105d0000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_13>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_13>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart6_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_4: usi@105e00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105e00c0 0x20>; + samsung,sysreg = <&sysreg_peric0 0x1028>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_14>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_14>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_9: i2c@105e0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x105e0000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c9_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_14>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_14>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi5: usi@105f00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x105f00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_15>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_15>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x102c>; + status = "disabled"; + + hsi2c_10: i2c@105f0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x105f0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_15>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_15>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c10_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_5: spi@105f0000 { + compatible = "samsung,exynos990-spi"; + reg = <0x105f0000 0x30>; + interrupts = ; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi5_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_15>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_15>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_7: serial@105f0000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x105f0000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_PCLK_15>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP0_IPCLK_15>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart7_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_5: usi@106000c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x106000c0 0x20>; + samsung,sysreg = <&sysreg_peric0 0x1030>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_0>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_11: i2c@10600000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10600000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c11_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_0>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi13: usi@106300c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x106300c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_3>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_3>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x103c>; + status = "disabled"; + + hsi2c_26: i2c@10630000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10630000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_3>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_3>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c26_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_13: spi@10630000 { + compatible = "samsung,exynos990-spi"; + reg = <0x10630000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi13_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_3>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_3>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_15: serial@10630000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10630000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_3>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_3>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart15_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_13: usi@106400c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x106400c0 0x20>; + samsung,sysreg = <&sysreg_peric0 0x1040>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_4>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_4>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_27: i2c@10640000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10640000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c27_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_4>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_4>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi14: usi@106500c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x106500c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_5>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1044>; + status = "disabled"; + + hsi2c_28: i2c@10650000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10650000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_5>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c28_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_14: spi@10650000 { + compatible = "samsung,exynos990-spi"; + reg = <0x10650000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi14_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_5>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_16: serial@10650000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10650000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_5>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart16_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_14: usi@106600c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x106600c0 0x20>; + samsung,sysreg = <&sysreg_peric0 0x1048>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_0>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_29: i2c@10660000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10660000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c29_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_6>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_6>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi15: usi@106700c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x106700c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_7>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x104c>; + status = "disabled"; + + hsi2c_30: i2c@10670000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10670000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_7>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c30_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_15: spi@10650000 { + compatible = "samsung,exynos990-spi"; + reg = <0x10670000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi15_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_7>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_17: serial@10670000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10670000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_7>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart17_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_15: usi@106800c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x106800c0 0x20>; + samsung,sysreg = <&sysreg_peric0 0x1050>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_8>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_8>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_31: i2c@10680000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10680000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c31_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_IPCLK_8>, + <&cmu_peric0 CLK_GOUT_PERIC0_TOP1_PCLK_8>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + pinctrl_peric1: pinctrl@10730000 { compatible = "samsung,exynos990-pinctrl"; reg = <0x10730000 0x1000>; interrupts = ; }; + cmu_peric1: clock-controller@10700000 { + compatible = "samsung,exynos990-cmu-peric1"; + reg = <0x10700000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; + clock-names = "oscclk", "bus", "ip"; + }; + + sysreg_peric1: syscon@10720000 { + compatible = "samsung,exynos990-peric1-sysreg", "syscon"; + reg = <0x10720000 0x10000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PCLK>; + }; + + usi_bt_uart: usi@108400c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x108400c0 0x20>; + samsung,sysreg = <&sysreg_peric1 0x1000>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_4>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + serial_1: serial@10840000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10840000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_bus_single>; + pinctrl-1 = <&uart1_bus_rts &uart1_bus_tx_con>; + pinctrl-2 = <&uart1_bus_tx_dat>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC0_TOP0_PCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC0_TOP0_IPCLK_4>; + clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + }; + + usi6: usi@108a00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x108a00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_10>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_10>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1018>; + status = "disabled"; + + hsi2c_12: i2c@108a0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x108a0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_10>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_10>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c12_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_6: spi@108a0000 { + compatible = "samsung,exynos990-spi"; + reg = <0x108a0000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi6_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_10>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_10>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_8: serial@108a0000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x108a0000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_10>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_10>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart8_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_6: usi@108b00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x108b00c0 0x20>; + samsung,sysreg = <&sysreg_peric1 0x101c>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_11>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_11>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_13: i2c@108b0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x108b0000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c13_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_11>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_11>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi7: usi@108c00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x108c00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_12>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_12>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1020>; + status = "disabled"; + + hsi2c_14: i2c@108c0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x108c0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_12>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_12>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c14_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_7: spi@108c0000 { + compatible = "samsung,exynos990-spi"; + reg = <0x108c0000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi7_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_12>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_12>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_9: serial@108c0000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x108c0000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_12>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_12>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart9_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_7: usi@108d00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x108d00c0 0x20>; + samsung,sysreg = <&sysreg_peric1 0x1024>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_13>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_13>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_15: i2c@108d0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x108d0000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c15_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_13>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_13>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi8: usi@108e00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x108e00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_14>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_14>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1028>; + status = "disabled"; + + hsi2c_16: i2c@108e0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x108e0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_14>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_14>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c16_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_8: spi@108e0000 { + compatible = "samsung,exynos990-spi"; + reg = <0x108e0000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi8_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_14>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_14>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + fifo-depth = <256> + status = "disabled"; + }; + + serial_10: serial@108e0000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x108e0000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_14>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_14>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart10_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + }; + + usi_i2c_8: usi@108f00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x108f00c0 0x20>; + samsung,sysreg = <&sysreg_peric1 0x102c>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_15>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_15>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_17: i2c@108f0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x108f0000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c17_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_IPCLK_15>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP0_PCLK_15>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi9: usi@109000c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109000c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_0>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_0>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1030>; + status = "disabled"; + + hsi2c_18: i2c@10900000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10900000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_0>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_0>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c18_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_9: spi@10900000 { + compatible = "samsung,exynos990-spi"; + reg = <0x10900000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi9_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_0>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_0>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + fifo-depth = <256> + status = "disabled"; + }; + + serial_11: serial@10900000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10900000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_0>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_0>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart11_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + }; + + usi_i2c_9: usi@109100c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109100c0 0x20>; + samsung,sysreg = <&sysreg_peric1 0x1034>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_1>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_1>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_19: i2c@10910000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10910000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c19_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_1>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_1>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi10: usi@109200c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109200c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_2>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_2>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1038>; + status = "disabled"; + + hsi2c_20: i2c@10920000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10920000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_2>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_2>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c20_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_10: spi@10920000 { + compatible = "samsung,exynos990-spi"; + reg = <0x10920000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi10_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_2>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_2>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + fifo-depth = <256> + status = "disabled"; + }; + + serial_12: serial@10920000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10920000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_2>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_2>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart12_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + }; + + usi_i2c_10: usi@109300c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109300c0 0x20>; + samsung,sysreg = <&sysreg_peric1 0x103c>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_3>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_3>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_21: i2c@10930000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10930000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c21_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_3>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_3>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi11: usi@109400c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109400c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_4>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1040>; + status = "disabled"; + + hsi2c_22: i2c@10940000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10940000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_4>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c22_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_11: spi@10940000 { + compatible = "samsung,exynos990-spi"; + reg = <0x10940000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi11_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_4>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_13: serial@10940000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10940000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_4>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart13_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_11: usi@109500c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109500c0 0x20>; + samsung,sysreg = <&sysreg_peric1 0x1044>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_5>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_5>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_23: i2c@10950000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10950000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c23_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_5>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_5>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi12: usi@109c00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109c00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_12>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_12>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x2000>; + status = "disabled"; + + hsi2c_24: i2c@109c0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x109c0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_12>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_12>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c24_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_12: spi@109c0000 { + compatible = "samsung,exynos990-spi"; + reg = <0x109c0000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi12_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_12>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_12>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_14: serial@109c0000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x109c0000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_12>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_12>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart14_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_12: usi@109d00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109d00c0 0x20>; + samsung,sysreg = <&sysreg_peric1 0x2004>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_13>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_13>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_25: i2c@109d0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x109d0000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c25_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_13>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_13>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi16: usi@109600c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109600c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_6>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_6>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1048>; + status = "disabled"; + + hsi2c_32: i2c@10960000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10960000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_6>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_6>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c32_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_16: spi@10960000 { + compatible = "samsung,exynos990-spi"; + reg = <0x10960000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi16_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_6>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_6>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_18: serial@10960000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10960000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_6>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_6>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart18_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_16: usi@109700c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109700c0 0x20>; + samsung,sysreg = <&sysreg_peric1 0x104c>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_7>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_7>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_33: i2c@10970000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10970000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c33_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_7>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_7>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi17: usi@109900c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109900c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_9>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_9>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1050>; + status = "disabled"; + + hsi2c_34: i2c@10990000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10990000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_9>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_9>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c34_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_17: spi@10990000 { + compatible = "samsung,exynos990-spi"; + reg = <0x10990000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi17_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_9>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_9>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_19: serial@10990000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x10990000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_9>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_9>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart19_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_17: usi@109a00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109a00c0 0x20>; + samsung,sysreg = <&sysreg_peric1 0x1054>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_10>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_10>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_35: i2c@10990000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10990000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c35_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_10>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_10>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi18: usi@109e00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109e00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_14>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_14>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x2008>; + status = "disabled"; + + hsi2c_36: i2c@109e0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x109e0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_14>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_14>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c36_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_18: spi@109e0000 { + compatible = "samsung,exynos990-spi"; + reg = <0x109e0000 0x30>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi18_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_14>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_14>; + clock-names = "spi", "spi_busclk0"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + serial_20: serial@109e0000 { + compatible = "samsung,exynos990-uart", + "samsung,exynos8895-uart"; + reg = <0x109e0000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_14>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_14>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart20_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_18: usi@109f00c0 { + compatible = "samsung,exynos990-usi", "samsung,exynos850-usi"; + reg = <0x109f00c0 0x20>; + samsung,sysreg = <&sysreg_peric1 0x200c>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_15>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_15>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_37: i2c@109f0000 { + compatible = "samsung,exynos990-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x109f0000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c37_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_IPCLK_15>, + <&cmu_peric1 CLK_GOUT_PERIC1_TOP1_PCLK_15>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + cmu_hsi0: clock-controller@10a00000 { compatible = "samsung,exynos990-cmu-hsi0"; reg = <0x10a00000 0x8000>;