From patchwork Thu Feb 6 07:23:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13962491 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D36B1C0219B for ; Thu, 6 Feb 2025 07:24:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=EbR53QpGwNFFyig0xbPX9PJgJC4UNH9Ua/LqoKfcq5I=; b=QRgyLMlCcsRTQM GnbY2OyVqHAIlq4+CaO/1309MgLd3PmGN6ipUvwIhcLTk9JSY7fRReB3Qr3NuDJBXvnsKopD1JEJY 99CrqhGRAa/IvQX0yTjeebLf+tXtqTcamLXMnkvz9HnVQvCaygAPaDyd0KQRkhLonggcNuz1ttm3G khcX3pbITMoOovNsX8FEy1akERVPTofxwuWjy1nugiWQ9f7QGNYpghN/Q7qMmmRLANOXMiQnrnI2r ShzMtPBSQkiBmMGtUzykU9kZZxpfmzYlsszvOu7TTAzvOqxmw6NIB7J+2XjsW7wcbn8X3w3c3jX0b 0boE0b669oQ6Kx6pgAVQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfwFj-00000005Yhj-16P0; Thu, 06 Feb 2025 07:24:47 +0000 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfwEI-00000005XsZ-1Dbg for linux-riscv@lists.infradead.org; Thu, 06 Feb 2025 07:23:23 +0000 Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-2f43d17b0e3so988066a91.0 for ; Wed, 05 Feb 2025 23:23:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1738826597; x=1739431397; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=NxybKo6wKHKxESvcOW2nXeuq/jFAsxN4ho9kLcK6bSI=; b=QMSknWt/fI8vzNvBcrArlqnFPLcDaXdCAgZdDCGTGqP9DsM2in/HCmwGXGjeAdNE0Z 6MFdjeeLSUGkqcUgMCBgNJulexFrqfzwYTJ/b+mDi4vXnppey7H52d29X+HArjri9tRN x4mq7Aojgpmd5mVtyQUep1RZMQOWZud8Pgseq9fnAMWwY7YGCPC8i0VBxfMK8k/ndwZF bMN8WNqBIUeYzqvDVIaAqVTqmhgpDDVekm7qFRo2HKO5bGIOxTkt6l90xK1BLjmzA8pl 5JeifA/zOgb4wvHHxD6xD1C8yXe260JUTkoNs1gA3shAHTby30zy6PcMbrOi1H3uT1/d MR3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738826597; x=1739431397; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NxybKo6wKHKxESvcOW2nXeuq/jFAsxN4ho9kLcK6bSI=; b=UFWTfVhx9LCduBfSQWjKbKda3A+magxMNtaFzpJSVfGREnVgUGkrZ4OF7gzn0kSZ8N tIxp1HPWgvkACyd6ZU+eG6mH3Ow6v4Rys/0oVyoPp3rcr5R+8S/2uqgbFDcvAo3vKrXv g9ECinZOJDu3EQnqm5wIYeoh7llGEP2Y/V+sYf3N+886CmHe8TRhw0x9koAdLx54Vucc M8vekJ4goLHc3+HVZBN6XM0pWT40j09ViEbHLHEuQOF6HWgpiJcD3VhhA8LuFts2s1GS CYQqtNiadcgJd9TPyGYVCKA1/LtM7+OFns9ux+YmLqd2HUw6R8hObyPIO5+ImK3RwB9p /RJA== X-Gm-Message-State: AOJu0YyZZiR7zGlx/kP7W7NK5mqN+MjrQW1BED5ngkHuB3CJsMkwUnl3 0Be0I4GeUVhHFGQw6ScLFeFxI+rN3YhSjvuIqZMEXcNT9e1xBH4AAXDlFmZsUQg= X-Gm-Gg: ASbGnctb6Xo5G1mqXnMgoVCVKXXATuCC1sRwtRNWEcbSe9jtUaPdroD4yhwfpA/Hf3O 2hoFjfzagSx/6b13X+nh+Xx5ON/LGUahU59Omg9Ip2FeqOyL59U0N8tzlSNSjikUtDvfUlGQtv1 JEmxYt6/WxmdtUz9Ly+qmFtWT75lToGEFoaOWuKBWeuBiHtQqlX6qPAaMrcgfLkPrIcU85TtZ3m S5Hhnx91J9qlGHTh7MYrV7J3AeDadcV+hdhU8vzHONhgCF1ogLUpctx5jl2xCO5PU/9doUUs8Py LvyGeTxzrZ1/5GdH8h6vfLhiJO0S X-Google-Smtp-Source: AGHT+IFT6mwcX1AF4g8ZydopueptdAl80WdzAm6cTfrKu9FnLeLwiOd9eXRT7KCT16vslg88b4iYTQ== X-Received: by 2002:a17:90b:4cc2:b0:2f5:63a:44f9 with SMTP id 98e67ed59e1d1-2f9e0811e4bmr7386320a91.23.1738826597037; Wed, 05 Feb 2025 23:23:17 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a72292sm630883a91.27.2025.02.05.23.23.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 23:23:16 -0800 (PST) From: Atish Patra Date: Wed, 05 Feb 2025 23:23:06 -0800 Subject: [PATCH v4 01/21] perf pmu-events: Add functions in jevent.py to parse counter and event info for hardware aware grouping MIME-Version: 1.0 Message-Id: <20250205-counter_delegation-v4-1-835cfa88e3b1@rivosinc.com> References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> In-Reply-To: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_232318_395399_0F36062D X-CRM114-Status: GOOD ( 12.64 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Weilin Wang These functions are added to parse event counter restrictions and counter availability info from json files so that the metric grouping method could do grouping based on the counter restriction of events and the counters that are available on the system. Signed-off-by: Weilin Wang --- tools/perf/pmu-events/empty-pmu-events.c | 299 ++++++++++++++++++++----------- tools/perf/pmu-events/jevents.py | 205 ++++++++++++++++++++- tools/perf/pmu-events/pmu-events.h | 32 +++- 3 files changed, 419 insertions(+), 117 deletions(-) diff --git a/tools/perf/pmu-events/empty-pmu-events.c b/tools/perf/pmu-events/empty-pmu-events.c index 1c7a2cfa321f..3a7ec31576f5 100644 --- a/tools/perf/pmu-events/empty-pmu-events.c +++ b/tools/perf/pmu-events/empty-pmu-events.c @@ -20,73 +20,73 @@ struct pmu_table_entry { static const char *const big_c_string = /* offset=0 */ "tool\000" -/* offset=5 */ "duration_time\000tool\000Wall clock interval time in nanoseconds\000config=1\000\00000\000\000" -/* offset=78 */ "user_time\000tool\000User (non-kernel) time in nanoseconds\000config=2\000\00000\000\000" -/* offset=145 */ "system_time\000tool\000System/kernel time in nanoseconds\000config=3\000\00000\000\000" -/* offset=210 */ "has_pmem\000tool\0001 if persistent memory installed otherwise 0\000config=4\000\00000\000\000" -/* offset=283 */ "num_cores\000tool\000Number of cores. A core consists of 1 or more thread, with each thread being associated with a logical Linux CPU\000config=5\000\00000\000\000" -/* offset=425 */ "num_cpus\000tool\000Number of logical Linux CPUs. There may be multiple such CPUs on a core\000config=6\000\00000\000\000" -/* offset=525 */ "num_cpus_online\000tool\000Number of online logical Linux CPUs. There may be multiple such CPUs on a core\000config=7\000\00000\000\000" -/* offset=639 */ "num_dies\000tool\000Number of dies. Each die has 1 or more cores\000config=8\000\00000\000\000" -/* offset=712 */ "num_packages\000tool\000Number of packages. Each package has 1 or more die\000config=9\000\00000\000\000" -/* offset=795 */ "slots\000tool\000Number of functional units that in parallel can execute parts of an instruction\000config=0xa\000\00000\000\000" -/* offset=902 */ "smt_on\000tool\0001 if simultaneous multithreading (aka hyperthreading) is enable otherwise 0\000config=0xb\000\00000\000\000" -/* offset=1006 */ "system_tsc_freq\000tool\000The amount a Time Stamp Counter (TSC) increases per second\000config=0xc\000\00000\000\000" -/* offset=1102 */ "default_core\000" -/* offset=1115 */ "bp_l1_btb_correct\000branch\000L1 BTB Correction\000event=0x8a\000\00000\000\000" -/* offset=1174 */ "bp_l2_btb_correct\000branch\000L2 BTB Correction\000event=0x8b\000\00000\000\000" -/* offset=1233 */ "l3_cache_rd\000cache\000L3 cache access, read\000event=0x40\000\00000\000Attributable Level 3 cache access, read\000" -/* offset=1328 */ "segment_reg_loads.any\000other\000Number of segment register loads\000event=6,period=200000,umask=0x80\000\00000\000\000" -/* offset=1427 */ "dispatch_blocked.any\000other\000Memory cluster signals to block micro-op dispatch for any reason\000event=9,period=200000,umask=0x20\000\00000\000\000" -/* offset=1557 */ "eist_trans\000other\000Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions\000event=0x3a,period=200000\000\00000\000\000" -/* offset=1672 */ "hisi_sccl,ddrc\000" -/* offset=1687 */ "uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\000event=2\000\00000\000DDRC write commands\000" -/* offset=1773 */ "uncore_cbox\000" -/* offset=1785 */ "unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\000event=0x22,umask=0x81\000\00000\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\000" -/* offset=2016 */ "event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=0xe0\000\00000\000UNC_CBO_HYPHEN\000" -/* offset=2081 */ "event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=0xc0\000\00000\000UNC_CBO_TWO_HYPH\000" -/* offset=2152 */ "hisi_sccl,l3c\000" -/* offset=2166 */ "uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000event=7\000\00000\000Total read hits\000" -/* offset=2246 */ "uncore_imc_free_running\000" -/* offset=2270 */ "uncore_imc_free_running.cache_miss\000uncore\000Total cache misses\000event=0x12\000\00000\000Total cache misses\000" -/* offset=2365 */ "uncore_imc\000" -/* offset=2376 */ "uncore_imc.cache_hits\000uncore\000Total cache hits\000event=0x34\000\00000\000Total cache hits\000" -/* offset=2454 */ "uncore_sys_ddr_pmu\000" -/* offset=2473 */ "sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\000event=0x2b\000v8\00000\000\000" -/* offset=2546 */ "uncore_sys_ccn_pmu\000" -/* offset=2565 */ "sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\000config=0x2c\0000x01\00000\000\000" -/* offset=2639 */ "uncore_sys_cmn_pmu\000" -/* offset=2658 */ "sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache misses in first lookup result (high priority)\000eventid=1,type=5\000(434|436|43c|43a).*\00000\000\000" -/* offset=2798 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000" -/* offset=2820 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\000\000\000\000\000\000\000\00000" -/* offset=2883 */ "Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000" -/* offset=3049 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000" -/* offset=3113 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000" -/* offset=3180 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_cycles\000\000\000\000\000\000\000\00000" -/* offset=3251 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000" -/* offset=3345 */ "DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000\000\000\000\000\000\000\00000" -/* offset=3479 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\000\000\000\000\000\000\000\00000" -/* offset=3543 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_All)\000\000\000\000\000\000\000\00000" -/* offset=3611 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2_All)\000\000\000\000\000\000\000\00000" -/* offset=3681 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\00000" -/* offset=3703 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\00000" -/* offset=3725 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\00000" -/* offset=3745 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duration_time\000\000\000\000\000\000\000\00000" +/* offset=5 */ "duration_time\000tool\000Wall clock interval time in nanoseconds\000config=1\000\00000\000\000\000" +/* offset=79 */ "user_time\000tool\000User (non-kernel) time in nanoseconds\000config=2\000\00000\000\000\000" +/* offset=147 */ "system_time\000tool\000System/kernel time in nanoseconds\000config=3\000\00000\000\000\000" +/* offset=213 */ "has_pmem\000tool\0001 if persistent memory installed otherwise 0\000config=4\000\00000\000\000\000" +/* offset=287 */ "num_cores\000tool\000Number of cores. A core consists of 1 or more thread, with each thread being associated with a logical Linux CPU\000config=5\000\00000\000\000\000" +/* offset=430 */ "num_cpus\000tool\000Number of logical Linux CPUs. There may be multiple such CPUs on a core\000config=6\000\00000\000\000\000" +/* offset=531 */ "num_cpus_online\000tool\000Number of online logical Linux CPUs. There may be multiple such CPUs on a core\000config=7\000\00000\000\000\000" +/* offset=646 */ "num_dies\000tool\000Number of dies. Each die has 1 or more cores\000config=8\000\00000\000\000\000" +/* offset=720 */ "num_packages\000tool\000Number of packages. Each package has 1 or more die\000config=9\000\00000\000\000\000" +/* offset=804 */ "slots\000tool\000Number of functional units that in parallel can execute parts of an instruction\000config=0xa\000\00000\000\000\000" +/* offset=912 */ "smt_on\000tool\0001 if simultaneous multithreading (aka hyperthreading) is enable otherwise 0\000config=0xb\000\00000\000\000\000" +/* offset=1017 */ "system_tsc_freq\000tool\000The amount a Time Stamp Counter (TSC) increases per second\000config=0xc\000\00000\000\000\000" +/* offset=1114 */ "default_core\000" +/* offset=1127 */ "bp_l1_btb_correct\000branch\000L1 BTB Correction\000event=0x8a\000\00000\000\000\000" +/* offset=1187 */ "bp_l2_btb_correct\000branch\000L2 BTB Correction\000event=0x8b\000\00000\000\000\000" +/* offset=1247 */ "l3_cache_rd\000cache\000L3 cache access, read\000event=0x40\000\00000\000Attributable Level 3 cache access, read\000\000" +/* offset=1343 */ "segment_reg_loads.any\000other\000Number of segment register loads\000event=6,period=200000,umask=0x80\000\00000\000\0000,1\000" +/* offset=1446 */ "dispatch_blocked.any\000other\000Memory cluster signals to block micro-op dispatch for any reason\000event=9,period=200000,umask=0x20\000\00000\000\0000,1\000" +/* offset=1580 */ "eist_trans\000other\000Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions\000event=0x3a,period=200000\000\00000\000\0000,1\000" +/* offset=1699 */ "hisi_sccl,ddrc\000" +/* offset=1714 */ "uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\000event=2\000\00000\000DDRC write commands\000\000" +/* offset=1801 */ "uncore_cbox\000" +/* offset=1813 */ "unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\000event=0x22,umask=0x81\000\00000\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\0000,1\000" +/* offset=2048 */ "event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=0xe0\000\00000\000UNC_CBO_HYPHEN\000\000" +/* offset=2114 */ "event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=0xc0\000\00000\000UNC_CBO_TWO_HYPH\000\000" +/* offset=2186 */ "hisi_sccl,l3c\000" +/* offset=2200 */ "uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000event=7\000\00000\000Total read hits\000\000" +/* offset=2281 */ "uncore_imc_free_running\000" +/* offset=2305 */ "uncore_imc_free_running.cache_miss\000uncore\000Total cache misses\000event=0x12\000\00000\000Total cache misses\000\000" +/* offset=2401 */ "uncore_imc\000" +/* offset=2412 */ "uncore_imc.cache_hits\000uncore\000Total cache hits\000event=0x34\000\00000\000Total cache hits\000\000" +/* offset=2491 */ "uncore_sys_ddr_pmu\000" +/* offset=2510 */ "sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\000event=0x2b\000v8\00000\000\000\000" +/* offset=2584 */ "uncore_sys_ccn_pmu\000" +/* offset=2603 */ "sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\000config=0x2c\0000x01\00000\000\000\000" +/* offset=2678 */ "uncore_sys_cmn_pmu\000" +/* offset=2697 */ "sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache misses in first lookup result (high priority)\000eventid=1,type=5\000(434|436|43c|43a).*\00000\000\000\000" +/* offset=2838 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000" +/* offset=2860 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\000\000\000\000\000\000\000\00000" +/* offset=2923 */ "Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000" +/* offset=3089 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000" +/* offset=3153 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000" +/* offset=3220 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_cycles\000\000\000\000\000\000\000\00000" +/* offset=3291 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000" +/* offset=3385 */ "DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000\000\000\000\000\000\000\00000" +/* offset=3519 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\000\000\000\000\000\000\000\00000" +/* offset=3583 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_All)\000\000\000\000\000\000\000\00000" +/* offset=3651 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2_All)\000\000\000\000\000\000\000\00000" +/* offset=3721 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\00000" +/* offset=3743 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\00000" +/* offset=3765 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\00000" +/* offset=3785 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duration_time\000\000\000\000\000\000\000\00000" ; static const struct compact_pmu_event pmu_events__common_tool[] = { -{ 5 }, /* duration_time\000tool\000Wall clock interval time in nanoseconds\000config=1\000\00000\000\000 */ -{ 210 }, /* has_pmem\000tool\0001 if persistent memory installed otherwise 0\000config=4\000\00000\000\000 */ -{ 283 }, /* num_cores\000tool\000Number of cores. A core consists of 1 or more thread, with each thread being associated with a logical Linux CPU\000config=5\000\00000\000\000 */ -{ 425 }, /* num_cpus\000tool\000Number of logical Linux CPUs. There may be multiple such CPUs on a core\000config=6\000\00000\000\000 */ -{ 525 }, /* num_cpus_online\000tool\000Number of online logical Linux CPUs. There may be multiple such CPUs on a core\000config=7\000\00000\000\000 */ -{ 639 }, /* num_dies\000tool\000Number of dies. Each die has 1 or more cores\000config=8\000\00000\000\000 */ -{ 712 }, /* num_packages\000tool\000Number of packages. Each package has 1 or more die\000config=9\000\00000\000\000 */ -{ 795 }, /* slots\000tool\000Number of functional units that in parallel can execute parts of an instruction\000config=0xa\000\00000\000\000 */ -{ 902 }, /* smt_on\000tool\0001 if simultaneous multithreading (aka hyperthreading) is enable otherwise 0\000config=0xb\000\00000\000\000 */ -{ 145 }, /* system_time\000tool\000System/kernel time in nanoseconds\000config=3\000\00000\000\000 */ -{ 1006 }, /* system_tsc_freq\000tool\000The amount a Time Stamp Counter (TSC) increases per second\000config=0xc\000\00000\000\000 */ -{ 78 }, /* user_time\000tool\000User (non-kernel) time in nanoseconds\000config=2\000\00000\000\000 */ +{ 5 }, /* duration_time\000tool\000Wall clock interval time in nanoseconds\000config=1\000\00000\000\000\000 */ +{ 213 }, /* has_pmem\000tool\0001 if persistent memory installed otherwise 0\000config=4\000\00000\000\000\000 */ +{ 287 }, /* num_cores\000tool\000Number of cores. A core consists of 1 or more thread, with each thread being associated with a logical Linux CPU\000config=5\000\00000\000\000\000 */ +{ 430 }, /* num_cpus\000tool\000Number of logical Linux CPUs. There may be multiple such CPUs on a core\000config=6\000\00000\000\000\000 */ +{ 531 }, /* num_cpus_online\000tool\000Number of online logical Linux CPUs. There may be multiple such CPUs on a core\000config=7\000\00000\000\000\000 */ +{ 646 }, /* num_dies\000tool\000Number of dies. Each die has 1 or more cores\000config=8\000\00000\000\000\000 */ +{ 720 }, /* num_packages\000tool\000Number of packages. Each package has 1 or more die\000config=9\000\00000\000\000\000 */ +{ 804 }, /* slots\000tool\000Number of functional units that in parallel can execute parts of an instruction\000config=0xa\000\00000\000\000\000 */ +{ 912 }, /* smt_on\000tool\0001 if simultaneous multithreading (aka hyperthreading) is enable otherwise 0\000config=0xb\000\00000\000\000\000 */ +{ 147 }, /* system_time\000tool\000System/kernel time in nanoseconds\000config=3\000\00000\000\000\000 */ +{ 1017 }, /* system_tsc_freq\000tool\000The amount a Time Stamp Counter (TSC) increases per second\000config=0xc\000\00000\000\000\000 */ +{ 79 }, /* user_time\000tool\000User (non-kernel) time in nanoseconds\000config=2\000\00000\000\000\000 */ }; @@ -99,29 +99,29 @@ const struct pmu_table_entry pmu_events__common[] = { }; static const struct compact_pmu_event pmu_events__test_soc_cpu_default_core[] = { -{ 1115 }, /* bp_l1_btb_correct\000branch\000L1 BTB Correction\000event=0x8a\000\00000\000\000 */ -{ 1174 }, /* bp_l2_btb_correct\000branch\000L2 BTB Correction\000event=0x8b\000\00000\000\000 */ -{ 1427 }, /* dispatch_blocked.any\000other\000Memory cluster signals to block micro-op dispatch for any reason\000event=9,period=200000,umask=0x20\000\00000\000\000 */ -{ 1557 }, /* eist_trans\000other\000Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions\000event=0x3a,period=200000\000\00000\000\000 */ -{ 1233 }, /* l3_cache_rd\000cache\000L3 cache access, read\000event=0x40\000\00000\000Attributable Level 3 cache access, read\000 */ -{ 1328 }, /* segment_reg_loads.any\000other\000Number of segment register loads\000event=6,period=200000,umask=0x80\000\00000\000\000 */ +{ 1127 }, /* bp_l1_btb_correct\000branch\000L1 BTB Correction\000event=0x8a\000\00000\000\000\000 */ +{ 1187 }, /* bp_l2_btb_correct\000branch\000L2 BTB Correction\000event=0x8b\000\00000\000\000\000 */ +{ 1446 }, /* dispatch_blocked.any\000other\000Memory cluster signals to block micro-op dispatch for any reason\000event=9,period=200000,umask=0x20\000\00000\000\0000,1\000 */ +{ 1580 }, /* eist_trans\000other\000Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions\000event=0x3a,period=200000\000\00000\000\0000,1\000 */ +{ 1247 }, /* l3_cache_rd\000cache\000L3 cache access, read\000event=0x40\000\00000\000Attributable Level 3 cache access, read\000\000 */ +{ 1343 }, /* segment_reg_loads.any\000other\000Number of segment register loads\000event=6,period=200000,umask=0x80\000\00000\000\0000,1\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_hisi_sccl_ddrc[] = { -{ 1687 }, /* uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\000event=2\000\00000\000DDRC write commands\000 */ +{ 1714 }, /* uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\000event=2\000\00000\000DDRC write commands\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_hisi_sccl_l3c[] = { -{ 2166 }, /* uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000event=7\000\00000\000Total read hits\000 */ +{ 2200 }, /* uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000event=7\000\00000\000Total read hits\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_cbox[] = { -{ 2016 }, /* event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=0xe0\000\00000\000UNC_CBO_HYPHEN\000 */ -{ 2081 }, /* event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=0xc0\000\00000\000UNC_CBO_TWO_HYPH\000 */ -{ 1785 }, /* unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\000event=0x22,umask=0x81\000\00000\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\000 */ +{ 2048 }, /* event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=0xe0\000\00000\000UNC_CBO_HYPHEN\000\000 */ +{ 2114 }, /* event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=0xc0\000\00000\000UNC_CBO_TWO_HYPH\000\000 */ +{ 1813 }, /* unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\000event=0x22,umask=0x81\000\00000\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\0000,1\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_imc[] = { -{ 2376 }, /* uncore_imc.cache_hits\000uncore\000Total cache hits\000event=0x34\000\00000\000Total cache hits\000 */ +{ 2412 }, /* uncore_imc.cache_hits\000uncore\000Total cache hits\000event=0x34\000\00000\000Total cache hits\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_imc_free_running[] = { -{ 2270 }, /* uncore_imc_free_running.cache_miss\000uncore\000Total cache misses\000event=0x12\000\00000\000Total cache misses\000 */ +{ 2305 }, /* uncore_imc_free_running.cache_miss\000uncore\000Total cache misses\000event=0x12\000\00000\000Total cache misses\000\000 */ }; @@ -129,51 +129,51 @@ const struct pmu_table_entry pmu_events__test_soc_cpu[] = { { .entries = pmu_events__test_soc_cpu_default_core, .num_entries = ARRAY_SIZE(pmu_events__test_soc_cpu_default_core), - .pmu_name = { 1102 /* default_core\000 */ }, + .pmu_name = { 1114 /* default_core\000 */ }, }, { .entries = pmu_events__test_soc_cpu_hisi_sccl_ddrc, .num_entries = ARRAY_SIZE(pmu_events__test_soc_cpu_hisi_sccl_ddrc), - .pmu_name = { 1672 /* hisi_sccl,ddrc\000 */ }, + .pmu_name = { 1699 /* hisi_sccl,ddrc\000 */ }, }, { .entries = pmu_events__test_soc_cpu_hisi_sccl_l3c, .num_entries = ARRAY_SIZE(pmu_events__test_soc_cpu_hisi_sccl_l3c), - .pmu_name = { 2152 /* hisi_sccl,l3c\000 */ }, + .pmu_name = { 2186 /* hisi_sccl,l3c\000 */ }, }, { .entries = pmu_events__test_soc_cpu_uncore_cbox, .num_entries = ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_cbox), - .pmu_name = { 1773 /* uncore_cbox\000 */ }, + .pmu_name = { 1801 /* uncore_cbox\000 */ }, }, { .entries = pmu_events__test_soc_cpu_uncore_imc, .num_entries = ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_imc), - .pmu_name = { 2365 /* uncore_imc\000 */ }, + .pmu_name = { 2401 /* uncore_imc\000 */ }, }, { .entries = pmu_events__test_soc_cpu_uncore_imc_free_running, .num_entries = ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_imc_free_running), - .pmu_name = { 2246 /* uncore_imc_free_running\000 */ }, + .pmu_name = { 2281 /* uncore_imc_free_running\000 */ }, }, }; static const struct compact_pmu_event pmu_metrics__test_soc_cpu_default_core[] = { -{ 2798 }, /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000 */ -{ 3479 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\000\000\000\000\000\000\000\00000 */ -{ 3251 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000 */ -{ 3345 }, /* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000\000\000\000\000\000\000\00000 */ -{ 3543 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_All)\000\000\000\000\000\000\000\00000 */ -{ 3611 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2_All)\000\000\000\000\000\000\000\00000 */ -{ 2883 }, /* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000 */ -{ 2820 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\000\000\000\000\000\000\000\00000 */ -{ 3745 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duration_time\000\000\000\000\000\000\000\00000 */ -{ 3681 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\00000 */ -{ 3703 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\00000 */ -{ 3725 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\00000 */ -{ 3180 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_cycles\000\000\000\000\000\000\000\00000 */ -{ 3049 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000 */ -{ 3113 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000 */ +{ 2838 }, /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000 */ +{ 3519 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\000\000\000\000\000\000\000\00000 */ +{ 3291 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000 */ +{ 3385 }, /* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000\000\000\000\000\000\000\00000 */ +{ 3583 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_All)\000\000\000\000\000\000\000\00000 */ +{ 3651 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2_All)\000\000\000\000\000\000\000\00000 */ +{ 2923 }, /* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000 */ +{ 2860 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\000\000\000\000\000\000\000\00000 */ +{ 3785 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duration_time\000\000\000\000\000\000\000\00000 */ +{ 3721 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\00000 */ +{ 3743 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\00000 */ +{ 3765 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\00000 */ +{ 3220 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_cycles\000\000\000\000\000\000\000\00000 */ +{ 3089 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000 */ +{ 3153 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000 */ }; @@ -181,18 +181,18 @@ const struct pmu_table_entry pmu_metrics__test_soc_cpu[] = { { .entries = pmu_metrics__test_soc_cpu_default_core, .num_entries = ARRAY_SIZE(pmu_metrics__test_soc_cpu_default_core), - .pmu_name = { 1102 /* default_core\000 */ }, + .pmu_name = { 1114 /* default_core\000 */ }, }, }; static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_ccn_pmu[] = { -{ 2565 }, /* sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\000config=0x2c\0000x01\00000\000\000 */ +{ 2603 }, /* sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\000config=0x2c\0000x01\00000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_cmn_pmu[] = { -{ 2658 }, /* sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache misses in first lookup result (high priority)\000eventid=1,type=5\000(434|436|43c|43a).*\00000\000\000 */ +{ 2697 }, /* sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache misses in first lookup result (high priority)\000eventid=1,type=5\000(434|436|43c|43a).*\00000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_ddr_pmu[] = { -{ 2473 }, /* sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\000event=0x2b\000v8\00000\000\000 */ +{ 2510 }, /* sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\000event=0x2b\000v8\00000\000\000\000 */ }; @@ -200,17 +200,17 @@ const struct pmu_table_entry pmu_events__test_soc_sys[] = { { .entries = pmu_events__test_soc_sys_uncore_sys_ccn_pmu, .num_entries = ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_ccn_pmu), - .pmu_name = { 2546 /* uncore_sys_ccn_pmu\000 */ }, + .pmu_name = { 2584 /* uncore_sys_ccn_pmu\000 */ }, }, { .entries = pmu_events__test_soc_sys_uncore_sys_cmn_pmu, .num_entries = ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_cmn_pmu), - .pmu_name = { 2639 /* uncore_sys_cmn_pmu\000 */ }, + .pmu_name = { 2678 /* uncore_sys_cmn_pmu\000 */ }, }, { .entries = pmu_events__test_soc_sys_uncore_sys_ddr_pmu, .num_entries = ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_ddr_pmu), - .pmu_name = { 2454 /* uncore_sys_ddr_pmu\000 */ }, + .pmu_name = { 2491 /* uncore_sys_ddr_pmu\000 */ }, }, }; @@ -227,6 +227,12 @@ struct pmu_metrics_table { uint32_t num_pmus; }; +/* Struct used to make the PMU counter layout table implementation opaque to callers. */ +struct pmu_layouts_table { + const struct compact_pmu_event *entries; + size_t length; +}; + /* * Map a CPU to its table of PMU events. The CPU is identified by the * cpuid field, which is an arch-specific identifier for the CPU. @@ -240,6 +246,7 @@ struct pmu_events_map { const char *cpuid; struct pmu_events_table event_table; struct pmu_metrics_table metric_table; + struct pmu_layouts_table layout_table; }; /* @@ -273,6 +280,7 @@ const struct pmu_events_map pmu_events_map[] = { .cpuid = 0, .event_table = { 0, 0 }, .metric_table = { 0, 0 }, + .layout_table = { 0, 0 }, } }; @@ -317,6 +325,8 @@ static void decompress_event(int offset, struct pmu_event *pe) pe->unit = (*p == '\0' ? NULL : p); while (*p++); pe->long_desc = (*p == '\0' ? NULL : p); + while (*p++); + pe->counters_list = (*p == '\0' ? NULL : p); } static void decompress_metric(int offset, struct pmu_metric *pm) @@ -348,6 +358,19 @@ static void decompress_metric(int offset, struct pmu_metric *pm) pm->event_grouping = *p - '0'; } +static void decompress_layout(int offset, struct pmu_layout *pm) +{ + const char *p = &big_c_string[offset]; + + pm->pmu = (*p == '\0' ? NULL : p); + while (*p++); + pm->desc = (*p == '\0' ? NULL : p); + p++; + pm->counters_num_gp = *p - '0'; + p++; + pm->counters_num_fixed = *p - '0'; +} + static int pmu_events_table__for_each_event_pmu(const struct pmu_events_table *table, const struct pmu_table_entry *pmu, pmu_event_iter_fn fn, @@ -503,6 +526,21 @@ int pmu_metrics_table__for_each_metric(const struct pmu_metrics_table *table, return 0; } +int pmu_layouts_table__for_each_layout(const struct pmu_layouts_table *table, + pmu_layout_iter_fn fn, + void *data) { + for (size_t i = 0; i < table->length; i++) { + struct pmu_layout pm; + int ret; + + decompress_layout(table->entries[i].offset, &pm); + ret = fn(&pm, data); + if (ret) + return ret; + } + return 0; +} + static const struct pmu_events_map *map_for_cpu(struct perf_cpu cpu) { static struct { @@ -595,6 +633,34 @@ const struct pmu_metrics_table *pmu_metrics_table__find(void) return map ? &map->metric_table : NULL; } +const struct pmu_layouts_table *perf_pmu__find_layouts_table(void) +{ + const struct pmu_layouts_table *table = NULL; + struct perf_cpu cpu = {-1}; + char *cpuid = get_cpuid_allow_env_override(cpu); + int i; + + /* on some platforms which uses cpus map, cpuid can be NULL for + * PMUs other than CORE PMUs. + */ + if (!cpuid) + return NULL; + + i = 0; + for (;;) { + const struct pmu_events_map *map = &pmu_events_map[i++]; + if (!map->arch) + break; + + if (!strcmp_cpuid_str(map->cpuid, cpuid)) { + table = &map->layout_table; + break; + } + } + free(cpuid); + return table; +} + const struct pmu_events_table *find_core_events_table(const char *arch, const char *cpuid) { for (const struct pmu_events_map *tables = &pmu_events_map[0]; @@ -616,6 +682,16 @@ const struct pmu_metrics_table *find_core_metrics_table(const char *arch, const } return NULL; } +const struct pmu_layouts_table *find_core_layouts_table(const char *arch, const char *cpuid) +{ + for (const struct pmu_events_map *tables = &pmu_events_map[0]; + tables->arch; + tables++) { + if (!strcmp(tables->arch, arch) && !strcmp_cpuid_str(tables->cpuid, cpuid)) + return &tables->layout_table; + } + return NULL; +} int pmu_for_each_core_event(pmu_event_iter_fn fn, void *data) { @@ -644,6 +720,19 @@ int pmu_for_each_core_metric(pmu_metric_iter_fn fn, void *data) return 0; } +int pmu_for_each_core_layout(pmu_layout_iter_fn fn, void *data) +{ + for (const struct pmu_events_map *tables = &pmu_events_map[0]; + tables->arch; + tables++) { + int ret = pmu_layouts_table__for_each_layout(&tables->layout_table, fn, data); + + if (ret) + return ret; + } + return 0; +} + const struct pmu_events_table *find_sys_events_table(const char *name) { for (const struct pmu_sys_events *tables = &pmu_sys_event_tables[0]; diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index d781a377757a..5fd906ac6642 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -23,6 +23,8 @@ _metric_tables = [] _sys_metric_tables = [] # Mapping between sys event table names and sys metric table names. _sys_event_table_to_metric_table_mapping = {} +# List of regular PMU counter layout tables. +_pmu_layouts_tables = [] # Map from an event name to an architecture standard # JsonEvent. Architecture standard events are in json files in the top # f'{_args.starting_dir}/{_args.arch}' directory. @@ -31,6 +33,10 @@ _arch_std_events = {} _pending_events = [] # Name of events table to be written out _pending_events_tblname = None +# PMU counter layout to write out when the layout table is closed +_pending_pmu_counts = [] +# Name of PMU counter layout table to be written out +_pending_pmu_counts_tblname = None # Metrics to write out when the table is closed _pending_metrics = [] # Name of metrics table to be written out @@ -51,6 +57,11 @@ _json_event_attributes = [ 'long_desc' ] +# Attributes that are in pmu_unit_layout. +_json_layout_attributes = [ + 'pmu', 'desc' +] + # Attributes that are in pmu_metric rather than pmu_event. _json_metric_attributes = [ 'metric_name', 'metric_group', 'metric_expr', 'metric_threshold', @@ -265,7 +276,7 @@ class JsonEvent: def unit_to_pmu(unit: str) -> Optional[str]: """Convert a JSON Unit to Linux PMU name.""" - if not unit: + if not unit or unit == "core": return 'default_core' # Comment brought over from jevents.c: # it's not realistic to keep adding these, we need something more scalable ... @@ -336,6 +347,19 @@ class JsonEvent: if 'Errata' in jd: extra_desc += ' Spec update: ' + jd['Errata'] self.pmu = unit_to_pmu(jd.get('Unit')) + # The list of counter(s) the event could be collected with + class Counter: + gp = str() + fixed = str() + self.counters = {'list': str(), 'num': Counter()} + self.counters['list'] = jd.get('Counter') + # Number of generic counter + self.counters['num'].gp = jd.get('CountersNumGeneric') + # Number of fixed counter + self.counters['num'].fixed = jd.get('CountersNumFixed') + # If the event uses an MSR, other event uses the same MSR could not be + # schedule to collect at the same time. + self.msr = jd.get('MSRIndex') filter = jd.get('Filter') self.unit = jd.get('ScaleUnit') self.perpkg = jd.get('PerPkg') @@ -411,8 +435,20 @@ class JsonEvent: s += f'\t{attr} = {value},\n' return s + '}' - def build_c_string(self, metric: bool) -> str: + def build_c_string(self, metric: bool, layout: bool) -> str: s = '' + if layout: + for attr in _json_layout_attributes: + x = getattr(self, attr) + if attr in _json_enum_attributes: + s += x if x else '0' + else: + s += f'{x}\\000' if x else '\\000' + x = self.counters['num'].gp + s += x if x else '0' + x = self.counters['num'].fixed + s += x if x else '0' + return s for attr in _json_metric_attributes if metric else _json_event_attributes: x = getattr(self, attr) if metric and x and attr == 'metric_expr': @@ -425,12 +461,15 @@ class JsonEvent: s += x if x else '0' else: s += f'{x}\\000' if x else '\\000' + if not metric: + x = self.counters['list'] + s += f'{x}\\000' if x else '\\000' return s - def to_c_string(self, metric: bool) -> str: + def to_c_string(self, metric: bool, layout: bool) -> str: """Representation of the event as a C struct initializer.""" - s = self.build_c_string(metric) + s = self.build_c_string(metric, layout) return f'{{ { _bcs.offsets[s] } }}, /* {s} */\n' @@ -467,6 +506,8 @@ def preprocess_arch_std_files(archpath: str) -> None: _arch_std_events[event.name.lower()] = event if event.metric_name: _arch_std_events[event.metric_name.lower()] = event + if event.counters['num'].gp: + _arch_std_events[event.pmu.lower()] = event def add_events_table_entries(item: os.DirEntry, topic: str) -> None: @@ -476,6 +517,8 @@ def add_events_table_entries(item: os.DirEntry, topic: str) -> None: _pending_events.append(e) if e.metric_name: _pending_metrics.append(e) + if e.counters['num'].gp: + _pending_pmu_counts.append(e) def print_pending_events() -> None: @@ -519,8 +562,8 @@ def print_pending_events() -> None: last_pmu = event.pmu pmus.add((event.pmu, pmu_name)) - _args.output_file.write(event.to_c_string(metric=False)) last_name = event.name + _args.output_file.write(event.to_c_string(metric=False, layout=False)) _pending_events = [] _args.output_file.write(f""" @@ -575,7 +618,7 @@ def print_pending_metrics() -> None: last_pmu = metric.pmu pmus.add((metric.pmu, pmu_name)) - _args.output_file.write(metric.to_c_string(metric=True)) + _args.output_file.write(metric.to_c_string(metric=True, layout=False)) _pending_metrics = [] _args.output_file.write(f""" @@ -593,6 +636,35 @@ const struct pmu_table_entry {_pending_metrics_tblname}[] = {{ """) _args.output_file.write('};\n\n') +def print_pending_pmu_counter_layout_table() -> None: + '''Print counter layout data from counter.json file to counter layout table in + c-string''' + + def pmu_counts_cmp_key(j: JsonEvent) -> Tuple[bool, str, str]: + def fix_none(s: Optional[str]) -> str: + if s is None: + return '' + return s + + return (j.desc is not None, fix_none(j.pmu)) + + global _pending_pmu_counts + if not _pending_pmu_counts: + return + + global _pending_pmu_counts_tblname + global pmu_layouts_tables + _pmu_layouts_tables.append(_pending_pmu_counts_tblname) + + _args.output_file.write( + f'static const struct compact_pmu_event {_pending_pmu_counts_tblname}[] = {{\n') + + for pmu_layout in sorted(_pending_pmu_counts, key=pmu_counts_cmp_key): + _args.output_file.write(pmu_layout.to_c_string(metric=False, layout=True)) + _pending_pmu_counts = [] + + _args.output_file.write('};\n\n') + def get_topic(topic: str) -> str: if topic.endswith('metrics.json'): return 'metrics' @@ -629,10 +701,12 @@ def preprocess_one_file(parents: Sequence[str], item: os.DirEntry) -> None: pmu_name = f"{event.pmu}\\000" if event.name: _bcs.add(pmu_name, metric=False) - _bcs.add(event.build_c_string(metric=False), metric=False) + _bcs.add(event.build_c_string(metric=False, layout=False), metric=False) if event.metric_name: _bcs.add(pmu_name, metric=True) - _bcs.add(event.build_c_string(metric=True), metric=True) + _bcs.add(event.build_c_string(metric=True, layout=False), metric=True) + if event.counters['num'].gp: + _bcs.add(event.build_c_string(metric=False, layout=True), metric=False) def process_one_file(parents: Sequence[str], item: os.DirEntry) -> None: """Process a JSON file during the main walk.""" @@ -649,11 +723,14 @@ def process_one_file(parents: Sequence[str], item: os.DirEntry) -> None: if item.is_dir() and is_leaf_dir_ignoring_sys(item.path): print_pending_events() print_pending_metrics() + print_pending_pmu_counter_layout_table() global _pending_events_tblname _pending_events_tblname = file_name_to_table_name('pmu_events_', parents, item.name) global _pending_metrics_tblname _pending_metrics_tblname = file_name_to_table_name('pmu_metrics_', parents, item.name) + global _pending_pmu_counts_tblname + _pending_pmu_counts_tblname = file_name_to_table_name('pmu_layouts_', parents, item.name) if item.name == 'sys': _sys_event_table_to_metric_table_mapping[_pending_events_tblname] = _pending_metrics_tblname @@ -687,6 +764,12 @@ struct pmu_metrics_table { uint32_t num_pmus; }; +/* Struct used to make the PMU counter layout table implementation opaque to callers. */ +struct pmu_layouts_table { + const struct compact_pmu_event *entries; + size_t length; +}; + /* * Map a CPU to its table of PMU events. The CPU is identified by the * cpuid field, which is an arch-specific identifier for the CPU. @@ -700,6 +783,7 @@ struct pmu_events_map { const char *cpuid; struct pmu_events_table event_table; struct pmu_metrics_table metric_table; + struct pmu_layouts_table layout_table; }; /* @@ -755,6 +839,12 @@ const struct pmu_events_map pmu_events_map[] = { metric_size = '0' if event_size == '0' and metric_size == '0': continue + layout_tblname = file_name_to_table_name('pmu_layouts_', [], row[2].replace('/', '_')) + if layout_tblname in _pmu_layouts_tables: + layout_size = f'ARRAY_SIZE({layout_tblname})' + else: + layout_tblname = 'NULL' + layout_size = '0' cpuid = row[0].replace('\\', '\\\\') _args.output_file.write(f"""{{ \t.arch = "{arch}", @@ -766,6 +856,10 @@ const struct pmu_events_map pmu_events_map[] = { \t.metric_table = {{ \t\t.pmus = {metric_tblname}, \t\t.num_pmus = {metric_size} +\t}}, +\t.layout_table = {{ +\t\t.entries = {layout_tblname}, +\t\t.length = {layout_size} \t}} }}, """) @@ -776,6 +870,7 @@ const struct pmu_events_map pmu_events_map[] = { \t.cpuid = 0, \t.event_table = { 0, 0 }, \t.metric_table = { 0, 0 }, +\t.layout_table = { 0, 0 }, } }; """) @@ -844,6 +939,9 @@ static void decompress_event(int offset, struct pmu_event *pe) _args.output_file.write('\tp++;') else: _args.output_file.write('\twhile (*p++);') + _args.output_file.write('\twhile (*p++);') + _args.output_file.write(f'\n\tpe->counters_list = ') + _args.output_file.write("(*p == '\\0' ? NULL : p);\n") _args.output_file.write("""} static void decompress_metric(int offset, struct pmu_metric *pm) @@ -864,6 +962,30 @@ static void decompress_metric(int offset, struct pmu_metric *pm) _args.output_file.write('\twhile (*p++);') _args.output_file.write("""} +static void decompress_layout(int offset, struct pmu_layout *pm) +{ +\tconst char *p = &big_c_string[offset]; +""") + for attr in _json_layout_attributes: + _args.output_file.write(f'\n\tpm->{attr} = ') + if attr in _json_enum_attributes: + _args.output_file.write("*p - '0';\n") + else: + _args.output_file.write("(*p == '\\0' ? NULL : p);\n") + if attr == _json_layout_attributes[-1]: + continue + if attr in _json_enum_attributes: + _args.output_file.write('\tp++;') + else: + _args.output_file.write('\twhile (*p++);') + _args.output_file.write('\tp++;') + _args.output_file.write(f'\n\tpm->counters_num_gp = ') + _args.output_file.write("*p - '0';\n") + _args.output_file.write('\tp++;') + _args.output_file.write(f'\n\tpm->counters_num_fixed = ') + _args.output_file.write("*p - '0';\n") + _args.output_file.write("""} + static int pmu_events_table__for_each_event_pmu(const struct pmu_events_table *table, const struct pmu_table_entry *pmu, pmu_event_iter_fn fn, @@ -1019,6 +1141,21 @@ int pmu_metrics_table__for_each_metric(const struct pmu_metrics_table *table, return 0; } +int pmu_layouts_table__for_each_layout(const struct pmu_layouts_table *table, + pmu_layout_iter_fn fn, + void *data) { + for (size_t i = 0; i < table->length; i++) { + struct pmu_layout pm; + int ret; + + decompress_layout(table->entries[i].offset, &pm); + ret = fn(&pm, data); + if (ret) + return ret; + } + return 0; +} + static const struct pmu_events_map *map_for_cpu(struct perf_cpu cpu) { static struct { @@ -1111,6 +1248,34 @@ const struct pmu_metrics_table *pmu_metrics_table__find(void) return map ? &map->metric_table : NULL; } +const struct pmu_layouts_table *perf_pmu__find_layouts_table(void) +{ + const struct pmu_layouts_table *table = NULL; + struct perf_cpu cpu = {-1}; + char *cpuid = get_cpuid_allow_env_override(cpu); + int i; + + /* on some platforms which uses cpus map, cpuid can be NULL for + * PMUs other than CORE PMUs. + */ + if (!cpuid) + return NULL; + + i = 0; + for (;;) { + const struct pmu_events_map *map = &pmu_events_map[i++]; + if (!map->arch) + break; + + if (!strcmp_cpuid_str(map->cpuid, cpuid)) { + table = &map->layout_table; + break; + } + } + free(cpuid); + return table; +} + const struct pmu_events_table *find_core_events_table(const char *arch, const char *cpuid) { for (const struct pmu_events_map *tables = &pmu_events_map[0]; @@ -1132,6 +1297,16 @@ const struct pmu_metrics_table *find_core_metrics_table(const char *arch, const } return NULL; } +const struct pmu_layouts_table *find_core_layouts_table(const char *arch, const char *cpuid) +{ + for (const struct pmu_events_map *tables = &pmu_events_map[0]; + tables->arch; + tables++) { + if (!strcmp(tables->arch, arch) && !strcmp_cpuid_str(tables->cpuid, cpuid)) + return &tables->layout_table; + } + return NULL; +} int pmu_for_each_core_event(pmu_event_iter_fn fn, void *data) { @@ -1160,6 +1335,19 @@ int pmu_for_each_core_metric(pmu_metric_iter_fn fn, void *data) return 0; } +int pmu_for_each_core_layout(pmu_layout_iter_fn fn, void *data) +{ + for (const struct pmu_events_map *tables = &pmu_events_map[0]; + tables->arch; + tables++) { + int ret = pmu_layouts_table__for_each_layout(&tables->layout_table, fn, data); + + if (ret) + return ret; + } + return 0; +} + const struct pmu_events_table *find_sys_events_table(const char *name) { for (const struct pmu_sys_events *tables = &pmu_sys_event_tables[0]; @@ -1320,6 +1508,7 @@ struct pmu_table_entry { ftw(arch_path, [], process_one_file) print_pending_events() print_pending_metrics() + print_pending_pmu_counter_layout_table() print_mapping_table(archs) print_system_mapping_table() diff --git a/tools/perf/pmu-events/pmu-events.h b/tools/perf/pmu-events/pmu-events.h index 675562e6f770..9a5cbec32513 100644 --- a/tools/perf/pmu-events/pmu-events.h +++ b/tools/perf/pmu-events/pmu-events.h @@ -45,6 +45,11 @@ struct pmu_event { const char *desc; const char *topic; const char *long_desc; + /** + * The list of counter(s) the event could be collected on. + * eg., "0,1,2,3,4,5,6,7". + */ + const char *counters_list; const char *pmu; const char *unit; bool perpkg; @@ -67,8 +72,18 @@ struct pmu_metric { enum metric_event_groups event_grouping; }; +struct pmu_layout { + const char *pmu; + const char *desc; + /** Total number of generic counters*/ + int counters_num_gp; + /** Total number of fixed counters. Set to zero if no fixed counter on the unit.*/ + int counters_num_fixed; +}; + struct pmu_events_table; struct pmu_metrics_table; +struct pmu_layouts_table; #define PMU_EVENTS__NOT_FOUND -1000 @@ -80,6 +95,9 @@ typedef int (*pmu_metric_iter_fn)(const struct pmu_metric *pm, const struct pmu_metrics_table *table, void *data); +typedef int (*pmu_layout_iter_fn)(const struct pmu_layout *pm, + void *data); + int pmu_events_table__for_each_event(const struct pmu_events_table *table, struct perf_pmu *pmu, pmu_event_iter_fn fn, @@ -92,10 +110,13 @@ int pmu_events_table__for_each_event(const struct pmu_events_table *table, * search of all tables. */ int pmu_events_table__find_event(const struct pmu_events_table *table, - struct perf_pmu *pmu, - const char *name, - pmu_event_iter_fn fn, - void *data); + struct perf_pmu *pmu, + const char *name, + pmu_event_iter_fn fn, + void *data); +int pmu_layouts_table__for_each_layout(const struct pmu_layouts_table *table, + pmu_layout_iter_fn fn, + void *data); size_t pmu_events_table__num_events(const struct pmu_events_table *table, struct perf_pmu *pmu); @@ -104,10 +125,13 @@ int pmu_metrics_table__for_each_metric(const struct pmu_metrics_table *table, pm const struct pmu_events_table *perf_pmu__find_events_table(struct perf_pmu *pmu); const struct pmu_metrics_table *pmu_metrics_table__find(void); +const struct pmu_layouts_table *perf_pmu__find_layouts_table(void); const struct pmu_events_table *find_core_events_table(const char *arch, const char *cpuid); const struct pmu_metrics_table *find_core_metrics_table(const char *arch, const char *cpuid); +const struct pmu_layouts_table *find_core_layouts_table(const char *arch, const char *cpuid); int pmu_for_each_core_event(pmu_event_iter_fn fn, void *data); int pmu_for_each_core_metric(pmu_metric_iter_fn fn, void *data); +int pmu_for_each_core_layout(pmu_layout_iter_fn fn, void *data); const struct pmu_events_table *find_sys_events_table(const char *name); const struct pmu_metrics_table *find_sys_metrics_table(const char *name); From patchwork Thu Feb 6 07:23:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13962490 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39BECC02198 for ; Thu, 6 Feb 2025 07:24:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bxx54/7BE5n8m8yOgMV/kWmYUlzD4M+T9C0Dz/6jqs0=; b=XBHYYWsPL/l1nF mJ8Aeb2J10p9EQA6Dg1EuuVkjbYtV6npshNC6oKIAt2Ujjfim2x/96h3dhCqwZ/6PR8gP+pDT8sJv 73SeG55t+Hdhr/J98AChwt9G/iQeyHTxfkeW5MmOj2H+STZh4zy911uMgxJwx4g+AEXQ9GxqbWehI jyEEPeR33JTNujOkCjfrURR0sVcV41hllun8eXjtC2DSi6VnMLdslU5XV/CndzSqk0RxP3Uh8w2kM adqA7Ggsts4gClplq7nOdH+m6PRk4gB0riaUCOzq5bHIhcE5LNoJbO2AgUFS/7RU5Lz4NeoBsFB2M GU33J/bry5QMOLM3tWgA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfwFi-00000005Ygq-1HNO; Thu, 06 Feb 2025 07:24:46 +0000 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfwEJ-00000005XuY-1XQw for linux-riscv@lists.infradead.org; Thu, 06 Feb 2025 07:23:22 +0000 Received: by mail-pj1-x102d.google.com with SMTP id 98e67ed59e1d1-2ee9a780de4so788001a91.3 for ; Wed, 05 Feb 2025 23:23:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1738826599; x=1739431399; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=XpU79JAmkI/euhUSjfGzozskMgtqeVAFHucAlKFsR6c=; b=sn50xTzec3uGwtF43ZkIwEvB18tlDOmxe7hIscJxuuh9zeNBySgKj/YfvVp3/BmkrL 01mpoZNxvdgxEabh2t8Z6NiI+stb05di3nWKFNJKq6Ha7mR0HxHKoTeewu9izpgPI7Q0 eAN3kapm0gaY46OuPPzOPKtnnXvaJb28pmtSeLzo7rKMWnmPnmugNK34/VzUiMym+9Ea 9PSRXFcf4l7Ke+u7g1WG/Ccmo6iHeP/64hBTXrgcDRIdebdGJaalzylJHXRwl6+hNmG0 L2Y0W4V8dr8SS1aRgrlorlcwVGlgAowpNFXFNKqVf67zOQ8zqTDky+wjayPI0ZB/k0AP dLtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738826599; x=1739431399; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XpU79JAmkI/euhUSjfGzozskMgtqeVAFHucAlKFsR6c=; b=IPdOEbsJ5ZpAjXuYBaAs/rJ5xqHAvldDhvpTv6bhn8/A+iIqq4ZkybIz0imJ3ftU5/ vwRL5U9J+1qHO+6JYhAtQ3RQdeqXa1rnbCi07A4qni934AanZF1IP1HL64b4TzjBoa0g ngV6YGAX9S5GiTTGckfN3kLgDE3G/rw1OH4DkdU4sn26ffmraM4qKSqay8WkiSNeW4ke avLqztgNc+T2KHl73hmlqbLVVw2PhYvFixey/nQCvX265iW+dB+SL8Una/ICCnAW2pDG fo0NYBg8DPW0kSi06sh3thDsEoFX4lXVPOrcNjzB0xTQXR1y/UESfbqa1r1eS9MbhbaA vJOw== X-Gm-Message-State: AOJu0YytIpRELmzcVLfEYdOpZr9Td4F9J8PH6B4/fwmsobaqXDcdh8N+ z5ROJ8qVSbFs6a3UVHaNMX6DO/dxaQwtbmfT6WOwJ36bWE8Hx4eQk1Gf7BWZie4= X-Gm-Gg: ASbGnctc2WdFJWN5hGCrRED/awWGwTUNJAqMmCK+U16f2iHGTOjIu/Cppbhh7RDU7Gc d1NVGkCKd00QzVDi15F7cW/IYYcRFtulEfRyKKIFAt6wRVitEIY3NwOx97O1RrsZMTd84Siehy3 obyc95Jx47yacXdj9PY+kYTs67CWDFSIbnx1CpeKlOxWWpfG0Rzg2Nvh4Meg/6OasCoZ6iuo2sN 6yWWrZ1lYeBGQaR5HwWnhLOZArrLJfPjLyPHdp+BJFGK3KlMoEPzANAMwciriwjWvV3UEaL/TkY pjMb07tMQfDiiC5wItAE9xcHJoho X-Google-Smtp-Source: AGHT+IESyqIBQACISlQQVueV5obgLnnWc+HDOijngEV9yfltfz+MqhbZ4NE+KJYEXiM6dtB0C1mfdQ== X-Received: by 2002:a17:90b:3d91:b0:2ee:d824:b594 with SMTP id 98e67ed59e1d1-2f9e083cd43mr8885048a91.31.1738826598796; Wed, 05 Feb 2025 23:23:18 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a72292sm630883a91.27.2025.02.05.23.23.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 23:23:18 -0800 (PST) From: Atish Patra Date: Wed, 05 Feb 2025 23:23:07 -0800 Subject: [PATCH v4 02/21] RISC-V: Add Sxcsrind ISA extension CSR definitions MIME-Version: 1.0 Message-Id: <20250205-counter_delegation-v4-2-835cfa88e3b1@rivosinc.com> References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> In-Reply-To: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra , Kaiwen Xue X-Mailer: b4 0.15-dev-13183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_232319_470839_AC5338B4 X-CRM114-Status: UNSURE ( 9.56 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Kaiwen Xue This adds definitions of new CSRs and bits defined in Sxcsrind ISA extension. These CSR enables indirect accesses mechanism to access any CSRs in M-, S-, and VS-mode. The range of the select values and ireg will be define by the ISA extension using Sxcsrind extension. Signed-off-by: Kaiwen Xue Signed-off-by: Atish Patra Reviewed-by: Clément Léger --- arch/riscv/include/asm/csr.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 37bdea65bbd8..2ad2d492e6b4 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -318,6 +318,12 @@ /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ #define CSR_SISELECT 0x150 #define CSR_SIREG 0x151 +/* Supervisor-Level Window to Indirectly Accessed Registers (Sxcsrind) */ +#define CSR_SIREG2 0x152 +#define CSR_SIREG3 0x153 +#define CSR_SIREG4 0x155 +#define CSR_SIREG5 0x156 +#define CSR_SIREG6 0x157 /* Supervisor-Level Interrupts (AIA) */ #define CSR_STOPEI 0x15c @@ -365,6 +371,14 @@ /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */ #define CSR_VSISELECT 0x250 #define CSR_VSIREG 0x251 +/* + * VS-Level Window to Indirectly Accessed Registers (H-extension with Sxcsrind) + */ +#define CSR_VSIREG2 0x252 +#define CSR_VSIREG3 0x253 +#define CSR_VSIREG4 0x255 +#define CSR_VSIREG5 0x256 +#define CSR_VISREG6 0x257 /* VS-Level Interrupts (H-extension with AIA) */ #define CSR_VSTOPEI 0x25c @@ -407,6 +421,12 @@ /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ #define CSR_MISELECT 0x350 #define CSR_MIREG 0x351 +/* Machine-Level Window to Indrecitly Accessed Registers (Sxcsrind) */ +#define CSR_MIREG2 0x352 +#define CSR_MIREG3 0x353 +#define CSR_MIREG4 0x355 +#define CSR_MIREG5 0x356 +#define CSR_MIREG6 0x357 /* Machine-Level Interrupts (AIA) */ #define CSR_MTOPEI 0x35c @@ -452,6 +472,11 @@ # define CSR_IEH CSR_MIEH # define CSR_ISELECT CSR_MISELECT # define CSR_IREG CSR_MIREG +# define CSR_IREG2 CSR_MIREG2 +# define CSR_IREG3 CSR_MIREG3 +# define CSR_IREG4 CSR_MIREG4 +# define CSR_IREG5 CSR_MIREG5 +# define CSR_IREG6 CSR_MIREG6 # define CSR_IPH CSR_MIPH # define CSR_TOPEI CSR_MTOPEI # define CSR_TOPI CSR_MTOPI @@ -477,6 +502,11 @@ # define CSR_IEH CSR_SIEH # define CSR_ISELECT CSR_SISELECT # define CSR_IREG CSR_SIREG +# define CSR_IREG2 CSR_SIREG2 +# define CSR_IREG3 CSR_SIREG3 +# define CSR_IREG4 CSR_SIREG4 +# define CSR_IREG5 CSR_SIREG5 +# define CSR_IREG6 CSR_SIREG6 # define CSR_IPH CSR_SIPH # define CSR_TOPEI CSR_STOPEI # define CSR_TOPI CSR_STOPI From patchwork Thu Feb 6 07:23:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13962496 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1642DC02198 for ; Thu, 6 Feb 2025 07:27:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=L/iyjD65mYbVebMqrSO2mIeSnuiV3T3SSHf/Zm3Bsmo=; b=SdbN5sUk3+4J6B LjrLSUPvqffi/iuWkSkHtPA4sgkMp/1LvE7wt38tBBRxoXr6KhgNFIXyBRh5r2vTLhwAtt7T7X8Ft mMU8pleuCow7JsVNsyE6PZ5MmJlsekMGkEvq/uvJIIkVGJUW36Y6W0vnnOYzwzu2el+m+svj8F11j FyCusFOcnj+aDovGgx1qzo7yzuPjfXXVzJlT7wbRC5DxZ3eZpscR0q3ATzHPDe7sTEYqLATOn9Avy 9ava6CACOcf559wSGwqlkbLNUPs/JlUMIUo4JVkB23JqknNZuveg6+M8SyVLxYF46shEjkwp1ccsm VVapkD50sQdesV/vxOlg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfwIO-00000005ZZS-3rR7; Thu, 06 Feb 2025 07:27:32 +0000 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfwEL-00000005XwI-1UCe for linux-riscv@lists.infradead.org; Thu, 06 Feb 2025 07:23:25 +0000 Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-2f9c3ef6849so1034731a91.3 for ; Wed, 05 Feb 2025 23:23:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1738826600; x=1739431400; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=lJ5m0Zv/n9Oaz8jMiZ4dpuMO84fRe+qZfct3W6wk+oc=; b=XOuom2o7CejXTmtIgXTdp5A3J5IxCuaXql6z/EdhjPpp7ip1QRGSA5hn17UJRppWy0 +VnR+85RIpsvSsJxMaHJWmluwxX9eIMoORwOmpu9+dY2aZPWIZObsujRefELkwr3gxml yKuyGHcC7Sr4eRZ1jiw9N+mFKFOV+FiIwPM+jzOtGQTcjN6OC/Izfy1IoIzmRDn/8VF9 VhDS2NWThtgK2rWgvxaabnoPJaasYCOFlL+rRa/E4SHhyBy1uqF2beZGemGGz7nIaxgJ W7kPmDYesnjl9GMzdVGS2RUBHmhGabZYVBbP7aaE5638KA/mllvbqe2F4k9LLeoJ5TE6 b1xA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738826600; x=1739431400; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lJ5m0Zv/n9Oaz8jMiZ4dpuMO84fRe+qZfct3W6wk+oc=; b=O3g3lXCcUcBgpBAu1FGqc6qWRSzr9hJUiY/NVZEw3pe1NtKNFJFXuL8h9CtLphRYda MNoKSOA4oiG5LIwUpjGVNsohJLvet+xZaF+VtjdTXw5QJd7APviMTfhckgEYH1ZdfXeT mwK+6jFwuDMth/Klk3gAn6Wa9AGi+QMaNQT4mqh5eiQbCj3yhCV+UZ7xVXCq6UCpOQ1R wu6pshqXXslZNl6tL3Qs01cwHT7duwrs2e41VuV9g4sM7m1txH6kmxoKi8DKohwgsguY 7mv7P+7nFobKG5/GV5CUXiKEen2f8mo0621tkCFqhLGeUSnmVHZjkfxNXKWhd/9tLOQE 7yjA== X-Gm-Message-State: AOJu0Yx8hxpaNq4HOMghibrJIyrC072XHxQ/vv9ZuhGMf2/WHZR0R7JN QKpOh/sPUTHndyT4KLQoRJfWGfqcHkUN8TWn3lKUVk/Gjq8r9b2PcSzGLE+gsSI= X-Gm-Gg: ASbGnctUTG/7yH+WAQJhMkJFXsim5BJpzyiScct+gkItg/1vyP9e2U6Euy9ju3FMTcu +J1iwMkpB+qi8mex5z3XEl/NqnTuYMzslub4n9ZrU46wt72bsGYphVAmkQiPUWSVVeJScCRChU7 ZsWwcAiF9MHl5Ow5TlE/Bsqe77winBhnDhp85EOHhdYnCw6p7ojtEKEmg64jSoYzwYQBaL2Yr5J MT+RyEaEQDhu5yYd7r8zn/sJoPDQDUqBqiAOKgn18TeZhoUmpDXLQhs9CvFVBX/xao/HJhRbHq6 OFS1tX3OYtfU2BqzD3Cwh6A2knYy X-Google-Smtp-Source: AGHT+IF7N62GzT6UR79bVSug46033WXYgVAcquwI6oHxNyG08rwtx9LdnCcav0B0Haf/hbAqjbl9EQ== X-Received: by 2002:a17:90a:12c3:b0:2fa:ba3:5451 with SMTP id 98e67ed59e1d1-2fa0ba37cd6mr1441805a91.35.1738826600432; Wed, 05 Feb 2025 23:23:20 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a72292sm630883a91.27.2025.02.05.23.23.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 23:23:20 -0800 (PST) From: Atish Patra Date: Wed, 05 Feb 2025 23:23:08 -0800 Subject: [PATCH v4 03/21] RISC-V: Add Sxcsrind ISA extension definition and parsing MIME-Version: 1.0 Message-Id: <20250205-counter_delegation-v4-3-835cfa88e3b1@rivosinc.com> References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> In-Reply-To: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_232321_427981_A5F79A28 X-CRM114-Status: GOOD ( 11.03 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The S[m|s]csrind extension extends the indirect CSR access mechanism defined in Smaia/Ssaia extensions. This patch just enables the definition and parsing. Signed-off-by: Atish Patra --- arch/riscv/include/asm/hwcap.h | 5 +++++ arch/riscv/kernel/cpufeature.c | 2 ++ 2 files changed, 7 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 869da082252a..3d6e706fc5b2 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -100,6 +100,8 @@ #define RISCV_ISA_EXT_ZICCRSE 91 #define RISCV_ISA_EXT_SVADE 92 #define RISCV_ISA_EXT_SVADU 93 +#define RISCV_ISA_EXT_SSCSRIND 94 +#define RISCV_ISA_EXT_SMCSRIND 95 #define RISCV_ISA_EXT_XLINUXENVCFG 127 @@ -109,9 +111,12 @@ #ifdef CONFIG_RISCV_M_MODE #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA #define RISCV_ISA_EXT_SUPM RISCV_ISA_EXT_SMNPM +#define RISCV_ISA_EXT_SxCSRIND RISCV_ISA_EXT_SMCSRIND #else #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA #define RISCV_ISA_EXT_SUPM RISCV_ISA_EXT_SSNPM +#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA +#define RISCV_ISA_EXT_SxCSRIND RISCV_ISA_EXT_SSCSRIND #endif #endif /* _ASM_RISCV_HWCAP_H */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c0916ed318c2..c6da81aa48aa 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -390,11 +390,13 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), + __RISCV_ISA_EXT_DATA(smcsrind, RISCV_ISA_EXT_SMCSRIND), __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM), __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_exts), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), + __RISCV_ISA_EXT_DATA(sscsrind, RISCV_ISA_EXT_SSCSRIND), __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_exts), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE), From patchwork Thu Feb 6 07:23:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13962529 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1E91C02196 for ; Thu, 6 Feb 2025 07:41:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=zcLaNGEvcyKq3AjMgKpHhxgriuLFr7JUxE7w9BN49WE=; b=VgrLrcmFx05Kds 2pGnEP3iBEE/qj1YzmmecxoKvLB8jjW9pR3DM9+kQzo921DBbMShaAMEuB3zisUWpEchUgeU/z3c6 CCy/+92rJG07GqOHgO2MfaiUal4BSkQvDBOz7tkJaBjno45x72Bpb5Rjkk895/8rRNA7jSxZRQ78/ xmq2WScWExPxZxqFbWdDOOm29JujBHc423a/0uwPOn45PK4n9/JVjIVONzk4ueKwIl2oRJvM7geyM Y7qFT1kIvd+cNeu/Gua5fvYifLktOTp1MYMup0pRLczJm0twz6TKeTb2BqJy9aaYMcFFhoWMjUlvl +aRMgHC8eBFSoTcZKFTw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfwVw-00000005crh-0Djz; Thu, 06 Feb 2025 07:41:32 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfwEf-00000005YHQ-1ec0 for linux-riscv@bombadil.infradead.org; Thu, 06 Feb 2025 07:23:41 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Cc:To:In-Reply-To:References: Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Sender:Reply-To:Content-ID:Content-Description; bh=p2CXRkSzd4LW5IV8mtGWOkMlVaZyNScQT8kSGB+ZHxc=; b=kLOX4u3eiuPS5I89Uw0Q8d7N3i BH93Pu1rJ58z9YGeUCGPQuTJ7ZvOgx8+Dxu9gwhftfenEMZdrkoBQuV7leM9NnOseibaT+3n3pGB3 JlSdZ5vmsFni0ZCkHWgzmcWggBS+OXiqV2L/SVxnV9gW8dPuS77vjCWmoe+UTKfiDYE1qGZ6fCPnS jwHDGPXk3hmv6kcWMn3I3WyMxnejlhmXINhm33J1cEPcoJhE0Rnsffiy7+BAmQxwrCNx3SvT1o9mM Xfc6sihoAVtA2Vq9ZzGI+dGV1B7Y9LbKB46iJwK0iVoCrmYx3kV/KkMiM4agF8lH6fDeqkzvbIfsa PC12h25A==; Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by desiato.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfwES-0000000Gqma-2pFg for linux-riscv@lists.infradead.org; Thu, 06 Feb 2025 07:23:40 +0000 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-2f9d627b5fbso955456a91.2 for ; Wed, 05 Feb 2025 23:23:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1738826602; x=1739431402; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=p2CXRkSzd4LW5IV8mtGWOkMlVaZyNScQT8kSGB+ZHxc=; b=BrPiFDy76FGI+TDP/fj/cJv/czjB6vwGe7i3zMfTEWSz4F6ryDOQOhJo5t+p3D1QJh OQNYh/lDLwsPZ7vVFTXiAU5t4SQaCCYUa8Q44ISRsn/Uv4OcFWF6+OMEr6TFA0B4tGly coU4VaJNxo+G8JDxu+m8/FdHlewcGQH87hNEhXCQ25xHvarSFUTEXIdkWSXtTE2gpAXM ksO4vLabA0vBIJpieOCrW28T2uQq5nJYEHuAmZ4jUVgtA7PVlx8rFdIBNPbZk99QJwZF lum3icJB8LVp5ceJhYL3OOeS9z1h5Tt3cpnN/kDaj+KjUZs8bOEs++7AxJ7CZ/auMtj9 OELQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738826602; x=1739431402; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p2CXRkSzd4LW5IV8mtGWOkMlVaZyNScQT8kSGB+ZHxc=; b=VKVPG+H8xc64J4TAe4xn36rc1yn1d/T8OxNqXkPOKl16sxMGgiYPUDnkfD0pw+HbPu ZZvCWwW7509miYxq177PVl1HSZIU4Yqt+rJFum4EHjjr+cYpc/Y0JoBhyKJD+tqAUsza kTN5s9lHSO/AAKSvaNLLmwkmkqi2hOrvzA132BWLKPev24ztQYCD1abCriLvcWtR5hDB rqdNhm0nf+RQJrnth+5OTkQ46wQd5EPvENbFpwC5KtvGdmiueYVF8udiFb8x9Npd6y8P 2DmOr6QxnVkYhfhfXt5YilgL6XKdA6Q0ZoY5zQkV4+pdvtMJNVlcPrKcleSiqnnxaand jLDw== X-Gm-Message-State: AOJu0YxYhSEqKZtzGSIQyh2VDqimlF+XrM+SU82QsTSfcmznEhpWVHks wi/VNaPUjtXrGf2XVyqeCyuFUHK1uLausG0gEP5IAPDDgPAdvefReM0KZCZu+nQ= X-Gm-Gg: ASbGncuLj1jDHYiY2iG32NYfEclYIw0x6LOXbdylULAuxIoebwJE8ceOi23oo5Qic4R o6e3PDHCnY3s4sCHYCPXjlDCT5W9njg/f/nKuJyZwhVoSRC8xxgOw/CBmpzC3bAZa68K6TYyxZ8 eGWXzha1Wikx20pfC2u3pkNO2u6TzQONQS7JSZWVIkosvptDqq4HudTlrpU8knj7Ptm6MvUZSGh SleqpVq6MCBM72CjQlQb/XyaLFcLPtalvtuwXr7+opujcixPeQvedLE/8pGCkU2/zIYDTleURGW SVXIAxzipH0saUaRedBESsBQWEKd X-Google-Smtp-Source: AGHT+IEsdW7e0nnU+hOuQNSvBNjT6hUmPYli2IAeU6lmXJs5V7j20UKpuutlBvTAACwmkO+Xy8ldvg== X-Received: by 2002:a17:90b:17d1:b0:2ee:df70:1ff3 with SMTP id 98e67ed59e1d1-2f9e06a1b1dmr11330512a91.0.1738826601990; Wed, 05 Feb 2025 23:23:21 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a72292sm630883a91.27.2025.02.05.23.23.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 23:23:21 -0800 (PST) From: Atish Patra Date: Wed, 05 Feb 2025 23:23:09 -0800 Subject: [PATCH v4 04/21] dt-bindings: riscv: add Sxcsrind ISA extension description MIME-Version: 1.0 Message-Id: <20250205-counter_delegation-v4-4-835cfa88e3b1@rivosinc.com> References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> In-Reply-To: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250206_072338_238822_A7E37C19 X-CRM114-Status: UNSURE ( 8.92 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add the S[m|s]csrind ISA extension description. Signed-off-by: Atish Patra Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/riscv/extensions.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 9c7dd7e75e0c..42e2494b126d 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -128,6 +128,14 @@ properties: changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. + - const: smcsrind + description: | + The standard Smcsrind supervisor-level extension extends the + indirect CSR access mechanism defined by the Smaia extension. This + extension allows other ISA extension to use indirect CSR access + mechanism in M-mode as ratified in the 20240326 version of the + privileged ISA specification. + - const: smmpm description: | The standard Smmpm extension for M-mode pointer masking as @@ -146,6 +154,14 @@ properties: added by other RISC-V extensions in H/S/VS/U/VU modes and as ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable. + - const: sscsrind + description: | + The standard Sscsrind supervisor-level extension extends the + indirect CSR access mechanism defined by the Ssaia extension. This + extension allows other ISA extension to use indirect CSR access + mechanism in S-mode as ratified in the 20240326 version of the + privileged ISA specification. + - const: ssaia description: | The standard Ssaia supervisor-level extension for the advanced From patchwork Thu Feb 6 07:23:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13962500 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 33C51C02196 for ; Thu, 6 Feb 2025 07:30:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=W8YQJjvBNrfIHs98gIR7STfTJGc7uQSo41bg6vm+cbU=; b=eus8E7e8r7YyH7 bztIcaFcgmotdYWRTD/WHafYS6FATkYpUNGod2foUg/MllqnQlksfUyizaR3MWog/qAtzFCFjvu6z mvlNUcB1h8vUsAqINYgksjNY3LJcph3/j7qRYCIbYY5gi6ETP59Wnye/hYVA2u2KB0QLLEeMhHkyl PJ+J7Pv46PMVqXD7mMH9ZMPNsoVWFNQdZrRwXkzwnbGWJrqt23TRm1jhCHbvNBh3njrTbyBRcQdVM F7LMg5MrwJcfTHrM2DhdLcYwqHnyMnSp+RTtSyiEXnOhP5JNbPMq2ASGoLlZ3FflhZM0yxyWsSrb3 kv+Hf538R3Qwv02pt/Mg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfwL4-00000005aT4-2EBu; Thu, 06 Feb 2025 07:30:18 +0000 Received: from mail-pj1-f43.google.com ([209.85.216.43]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfwEO-00000005Xz4-2IdQ for linux-riscv@lists.infradead.org; Thu, 06 Feb 2025 07:23:27 +0000 Received: by mail-pj1-f43.google.com with SMTP id 98e67ed59e1d1-2f9c69aefdbso1070568a91.2 for ; Wed, 05 Feb 2025 23:23:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1738826604; x=1739431404; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=zw3zbGTAqHMsJs8YvOYpRy60tVdSbXNH77zwDO4GVCI=; b=vZmutt9f54VoYaUnb3MkhrTtoGHbCz/DmqO3QhMJc9yhhPkhuLJZr2Vy/QheIzuKOS cEajGZdghij8YpDVj0Jmp0uZb6otZ3pSLUHg+sE3/Fx9s72eGdmDHO8iNLTbfBsmxbtA I+HCnDlqvKvfhV7y7c+HjxKBWksaiyEOeQ8Fu8noPUYL++yjhWjGecgWJGBM4dFOpuFg 9AG/W9NVo5Dlh96IS6I2b5jnXmzK6L+kVpesXYShphg1K+upLAq6idWEjSLDxcFRTqdM LBR9UdiozZGX6iOIcFaQpQSI8XgYNVRnYSaoIrQHVRh865PEO3rNEdHdW/UwQi+3zGzq 20/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738826604; x=1739431404; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zw3zbGTAqHMsJs8YvOYpRy60tVdSbXNH77zwDO4GVCI=; b=V6loqj71TDyDCzt8VGmRr6pzqaHPeYMquBhSuk0S61Q/6OhicSG2BaUuosneA5NlqL fFW09fDC2V+pyEA+N4BdsEHJUZRelrB25nri2EtYMYBkMSVup1HmuUHSLeIqxcM/ad1y 7JwEdDMdduv4+tdTusMpsYHXJYHbA3yR47xtWIjUjUA0PLiST0hW9SQsSJDN0yj6ELzq fjdup0bhtXaTENKWHDAAQkakZgTcSklAqWZyJ0MUl7Gqu4eMzVgaG4n5ppkjfa7G7KW/ Yfk4ZWFXJEzZoNWmULpxFCPY4dniddHzeX/8iAmknloqoIYH6s+XU9YBCr8XCLSWC78v 1BZg== X-Gm-Message-State: AOJu0YyaLKJeYjcF2eKWyopBWQy0V+cqfVpvf3rRVjWE7ol06OWeMDh0 dqVwUbmwuPs1rZ2FWeC4DnPDKrqoKyHskhiqrkQb4BquHgbwAcg5FBg4qVoG3S0= X-Gm-Gg: ASbGnctiL7uv4UOQgzn8izlVTu1mSAAQmZN4828PU8xIXiNCSEIIaIhiKgSna0tepbi j+cdbHjxJD4zVfo1+qP9tLAr74kJEw0xTxZzcrcYekr+DffcQftI4VQQ/gBWCgXUNw5bTO1DEcG xGoTO+lCUxGWB5qKAuPtaO4OY/wCmcUqDtGpKckzRRlI8QdLa8GSMV2ahTaTEt6eP+rA9TSFfY0 RyxxpINE30PFavla3dDvWDXIoZPxiiitsi908HD5HjWSREQuCPpP8EuS8BDuV7gvW1wHy7Jv3Rl 5y4v35oiSad9UYdbPwnSP4JYIqvH X-Google-Smtp-Source: AGHT+IG32go+lZuwjCgg/zbLptZ9A9o5+Wocjk0VyZkgS2Pr3FK1vOOJ1tss0czCWnqvvWKX+hfRsQ== X-Received: by 2002:a17:90b:4c4b:b0:2ee:aed6:9ec2 with SMTP id 98e67ed59e1d1-2f9e075fa50mr10140486a91.14.1738826603728; Wed, 05 Feb 2025 23:23:23 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a72292sm630883a91.27.2025.02.05.23.23.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 23:23:23 -0800 (PST) From: Atish Patra Date: Wed, 05 Feb 2025 23:23:10 -0800 Subject: [PATCH v4 05/21] RISC-V: Define indirect CSR access helpers MIME-Version: 1.0 Message-Id: <20250205-counter_delegation-v4-5-835cfa88e3b1@rivosinc.com> References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> In-Reply-To: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_232324_615357_24F42637 X-CRM114-Status: GOOD ( 11.13 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The indriect CSR requires multiple instructions to read/write CSR. Add a few helper functions for ease of usage. Signed-off-by: Atish Patra --- arch/riscv/include/asm/csr_ind.h | 42 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/riscv/include/asm/csr_ind.h b/arch/riscv/include/asm/csr_ind.h new file mode 100644 index 000000000000..d36e1e06ed2b --- /dev/null +++ b/arch/riscv/include/asm/csr_ind.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2024 Rivos Inc. + */ + +#ifndef _ASM_RISCV_CSR_IND_H +#define _ASM_RISCV_CSR_IND_H + +#include + +#define csr_ind_read(iregcsr, iselbase, iseloff) ({ \ + unsigned long value = 0; \ + unsigned long flags; \ + local_irq_save(flags); \ + csr_write(CSR_ISELECT, iselbase + iseloff); \ + value = csr_read(iregcsr); \ + local_irq_restore(flags); \ + value; \ +}) + +#define csr_ind_write(iregcsr, iselbase, iseloff, value) ({ \ + unsigned long flags; \ + local_irq_save(flags); \ + csr_write(CSR_ISELECT, iselbase + iseloff); \ + csr_write(iregcsr, value); \ + local_irq_restore(flags); \ +}) + +#define csr_ind_warl(iregcsr, iselbase, iseloff, warl_val) ({ \ + unsigned long old_val = 0, value = 0; \ + unsigned long flags; \ + local_irq_save(flags); \ + csr_write(CSR_ISELECT, iselbase + iseloff); \ + old_val = csr_read(iregcsr); \ + csr_write(iregcsr, warl_val); \ + value = csr_read(iregcsr); \ + csr_write(iregcsr, old_val); \ + local_irq_restore(flags); \ + value; \ +}) + +#endif From patchwork Thu Feb 6 07:23:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13962501 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76993C0219B for ; Thu, 6 Feb 2025 07:30:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+4BWsVQNiB35+JhqIjjs2TnXwmRHTjT75W3+2MiKbCI=; b=adfWVhSAv+/6B7 ai/fwRfx0JD2n+BTdVmWuyp3lbjiXW/Ngc0UcyI/MNjcpQI1NNJTIOTsCX4d85TYxya31hQcSTfV4 ip8oRB5pkOs53R4AyPDjm6hbGaAAd8FSicAMA+GYouQq5QHqG5/ICqJNt402gzSXLyaS2XtOoM1q0 RNHv/W6sbVKuiw4fsITjgQRihREC8Iwa61YrSagHDueBd6uLv96ZLJbV8+gNMqbs7wFk5LQNybblr 533qxhuqAzzRuWgKDZeLl2KyjrS6jVULTwWxNP72boYBQr/FBI9Rbj9kOWKhveob7N9D+RWDx7CVs ClOmELWCqrlTF0Rhopkw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfwL5-00000005aT9-0jiE; Thu, 06 Feb 2025 07:30:19 +0000 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfwEP-00000005Y0S-40nQ for linux-riscv@lists.infradead.org; Thu, 06 Feb 2025 07:23:27 +0000 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-21f3c119fe6so3452765ad.0 for ; Wed, 05 Feb 2025 23:23:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1738826605; x=1739431405; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=5jEaYEVzjt3yKFEUjA3mSdxHjzs+ekk92pc880MhBaw=; b=aYwR7zKrgKnDm91al2EfnhvrOlsOJFd7Pr+usjUIFS7D4sz8js2aiCTyp2mkkQcfJF Kb30e58qc/9/u66Ni9fmXVDTJQs2fmtTO91rvJ5WxwavrmMK5Qe/Xhr7pGObblYkHQWU y8sHwJtMMyCDz4iqwMifwQ38bgx42JUOSmfQic/QtVHh41vu7jcpFd4xYDL/sTJ/gkXl kTWUA5Gh5q4y3NcPIPsrXm3LHCZK199QFVeCgA+/OEyFFEeb4PwHLF2yiloQmrqYfPCe fg1qn2kivbhY+oB9+xeTMtT9JKK4llItZ3VSUOEPXFFbdW/qbZGebDrOA8nHsZ6n9SWX tAtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738826605; x=1739431405; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5jEaYEVzjt3yKFEUjA3mSdxHjzs+ekk92pc880MhBaw=; b=VJsRtMpkcbDkSNcvFt+rq15DUN/cy1WhYUJgOdHcYLoVtWPS5vzooAE+WRa4CuUWKF cCebpiBRNdEs+lyWnpguj+jgZRgXIt4vJuydcVzMTifEaYh8zHuuko8wBYEKBlNXF1tx qziqx4A8lThjl57EUbWWhuDOFNjaF6Zt5ni1rUpnD3CHYHXppHN+VehyWf25DdRLDhYh Zx67g8/itTUIjXk5Fb3dJXZokEP5pfuyNyDW1mw5zPO/hiHt0Ca2EeQ/JdTp4LEhMbpv PSUNij1OfYBbba+71IcATJ0PhPXPbe0sVqEkTl5z4bgCppiaGBMqFh1DJcPAmif4o4yz 95zA== X-Gm-Message-State: AOJu0YweHBXmND/QL5U3kamBKjLfGH/587n6ic9iCukeAWDIc279c1Dq UhM0UBevE6TOvFNOqR4WPq40ntX2Le0+fZh6e6lmNzkF0pWNmjuaHtG9bfgxKIo= X-Gm-Gg: ASbGncvBh3CT1UduVQ4ciPY8fZsyAIN/ua8ZhayM7YtKxG8Rz7w/wFbStm4fIAICh6B x/k84CwMJlSZ7MPifdHSdwCddQSTdf1nnu7Q14b2pe/JOC/M/PRVFDCxOvg8SISR+be8qCdm7Gk iaMrchJ/YoU96wBt2tNLKTxhMBBhLyKH0uCu9uPl+Af6myy8ePdK5cdbFagk108Mubyk1RqavZZ 31FFe7XZZ3orYh0aQ8jn9WTKgykDAcuSdDLpjmCYTgfiLZw3IwGoB85ARS7AzM2vsmo70iJhpua KMqhRthEdTD8Hzj/t/IIremFlUDC X-Google-Smtp-Source: AGHT+IHzp0J+mwXj/o4qdyn5Yi/oH9R23yiqLBnusAGlaJls5faLTlCjx6NHAGuTvmvHDO4dBQO+Rg== X-Received: by 2002:a17:903:2f92:b0:215:b190:de6 with SMTP id d9443c01a7336-21f17e2c950mr98353905ad.3.1738826605265; Wed, 05 Feb 2025 23:23:25 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a72292sm630883a91.27.2025.02.05.23.23.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 23:23:25 -0800 (PST) From: Atish Patra Date: Wed, 05 Feb 2025 23:23:11 -0800 Subject: [PATCH v4 06/21] RISC-V: Add Smcntrpmf extension parsing MIME-Version: 1.0 Message-Id: <20250205-counter_delegation-v4-6-835cfa88e3b1@rivosinc.com> References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> In-Reply-To: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_232326_002859_B2E28A2C X-CRM114-Status: GOOD ( 11.26 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Smcntrpmf extension allows M-mode to enable privilege mode filtering for cycle/instret counters. However, the cyclecfg/instretcfg CSRs are only available only in Ssccfg only Smcntrpmf is present. That's why, kernel needs to detect presence of Smcntrpmf extension and enable privilege mode filtering for cycle/instret counters. Signed-off-by: Atish Patra Reviewed-by: Clément Léger --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 3d6e706fc5b2..b4eddcb57842 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -102,6 +102,7 @@ #define RISCV_ISA_EXT_SVADU 93 #define RISCV_ISA_EXT_SSCSRIND 94 #define RISCV_ISA_EXT_SMCSRIND 95 +#define RISCV_ISA_EXT_SMCNTRPMF 96 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c6da81aa48aa..8f225c9c3055 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -390,6 +390,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), + __RISCV_ISA_EXT_DATA(smcntrpmf, RISCV_ISA_EXT_SMCNTRPMF), __RISCV_ISA_EXT_DATA(smcsrind, RISCV_ISA_EXT_SMCSRIND), __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM), __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_exts), From patchwork Thu Feb 6 07:23:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13962502 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A5535C02198 for ; Thu, 6 Feb 2025 07:31:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Lix5SmbZfrKca7YHGqoI2Sdp9+yO5HC+T7X0NFJSbAg=; b=Y5GWnq0ejj36Q0 lcWGtnWyCcJANStvQdWyMeWz9J/kbBSHdXZS+njzscLoEY5b2k5a1RnAm6cVp+Ki59XBsGMv8wtIt PhoAWj+G6h8Dlkky/oaT53QRq8DoTF837MI/5g85yH9D12QSBgYLhqVqAUd+CRGejTBbObjtpUXyI v1BKGA1crcIarJMLj/5kRSklGa2kDQfg48Wm6ZZJOMZl7ZHAzJ4yR/OMAC3x+UpVSjP73cegHook9 YSaXZBvbvJhiFcVDqnDnhvZAs3ZpDsH9hJXSfthCO+hq651HQjekP0Qnhs6O1UCWEQtL+D6c2PyIw KeZ/rWBIsNFuOfDhMQ/g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfwMQ-00000005b2i-2Cr3; Thu, 06 Feb 2025 07:31:42 +0000 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfwER-00000005Y2P-2ynt for linux-riscv@lists.infradead.org; Thu, 06 Feb 2025 07:23:28 +0000 Received: by mail-pj1-x102f.google.com with SMTP id 98e67ed59e1d1-2f441791e40so770613a91.3 for ; Wed, 05 Feb 2025 23:23:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1738826607; x=1739431407; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=d05MBVkD267pj0+O4130zpeTcKFWk4W9qDVXtG5klp0=; b=ox2hM89X/h2Q7gAIvwpIenb6JJX5gJwZJPK2rjhnMlfNNrR8z1ab1XIcxjE8MltzIL YddkLF2u3Zz8ZLKfCxa7gv6A6LUV6HNtHUBP8VYGdf3a7B9dpmv1J6Sk7K80Bb7QPSS1 BA6nSsokEKc9oGDyK/AYa+04LMJnXEaI6y7sBJ2FTRzfgQE8SU7cBAxCfeLUUV6Lwh+N nH6SH1uwsr+uOgO3BZ0uUYOW/xWTvAPT8XBm+6uJldMCDwKSoQrqRy2iptrLAhUquCyW 07SA3JMfzlDbN8Ixx7xEZGELPhnjMz9DUbUJQ3adj+7q1lkEP0RGoC+mjLqZkubyfPXV tGzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738826607; x=1739431407; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d05MBVkD267pj0+O4130zpeTcKFWk4W9qDVXtG5klp0=; b=X4towd7ui28EBANMIaPjFMOAb1cq0rCcHSQvEWA+Z/lCEiV9cukUmogtB+8roUuoxR 7rtfAb/GSH2K9z56BU9zCGn6tdyH6E8R6ghTD/kXujibMnFyuh+JtgfqUJRJ5p4Al0GP gBCjJtqxKuDtetlVhwXQFlcyslkKfx7+ULcFUjyuNssZ60T0CBQ8nuAou1l43fzLLF3F +kOKSfnpbFexzgNUTb6MQKGvVlJ6FDYrjSUPD1N6mypFVciEb1S+mwJKJ+G/I70xkAQ3 tcR1XSmHREGl9/Sa7meeBCSdz0uCGStPu5S0Brsj6oUhX5fNbpAneqSk0zMVUUonQCa1 64xw== X-Gm-Message-State: AOJu0YxDH6t+zHFDcHnxnMQEooadq93pootGw4TrW97M+c9+r7lfNlbW eukHtWE/Vp958fUD6rqp0cJNg2gCy79COrKbJvXlMYfNECzLcbb0HctauY+2/ps= X-Gm-Gg: ASbGncvvoHpyWvoxbb+58raaspF27fVLhaSa57bRi7wmaB1Rq7rlE97NMMSOkFkPV6J HHsCPM1BBjf4tWhPSNXtxiopYNCQ1fWA/BwgRiWh5r2gJryDoU54zV2Xak2bN1gcQWy+A1/lptr NVNNHV0rlNzH2zVlite26IgAgCqt3o42lchn87bhlDd2s7sb943k2iSFGf5QGfXG6O/Kr94X+BN EDVP+8K8qWB7qRLnqNsih7A6lxoAnSCWyY67nO47S01CxES9Siie03sB7Ix/0TTO6CcZtR7FZnt r/y1NKYmq6Ei4s5L7VbZ1x9OWFOC X-Google-Smtp-Source: AGHT+IFKe2kQczxclY80PslHuvYzWPmjNnKAp1q2ypYQZ9arePKPx5YXWSLFOApkuW37i5EznoN6cQ== X-Received: by 2002:a17:90a:d410:b0:2ee:cd83:8fe7 with SMTP id 98e67ed59e1d1-2f9e08682a8mr9427110a91.35.1738826606814; Wed, 05 Feb 2025 23:23:26 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a72292sm630883a91.27.2025.02.05.23.23.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 23:23:26 -0800 (PST) From: Atish Patra Date: Wed, 05 Feb 2025 23:23:12 -0800 Subject: [PATCH v4 07/21] dt-bindings: riscv: add Smcntrpmf ISA extension description MIME-Version: 1.0 Message-Id: <20250205-counter_delegation-v4-7-835cfa88e3b1@rivosinc.com> References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> In-Reply-To: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_232327_772962_6BBDA106 X-CRM114-Status: UNSURE ( 9.06 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add the description for Smcntrpmf ISA extension Signed-off-by: Atish Patra Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 42e2494b126d..be9ebe927a64 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -136,6 +136,12 @@ properties: mechanism in M-mode as ratified in the 20240326 version of the privileged ISA specification. + - const: smcntrpmf + description: | + The standard Smcntrpmf supervisor-level extension for the machine mode + to enable privilege mode filtering for cycle and instret counters as + ratified in the 20240326 version of the privileged ISA specification. + - const: smmpm description: | The standard Smmpm extension for M-mode pointer masking as From patchwork Thu Feb 6 07:23:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13962503 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AA4D4C02196 for ; Thu, 6 Feb 2025 07:33:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gAQBeFz/6CxoeA1WohaBrdqPzmplktLxPC852Z07h1o=; b=jp6QtCChX/RzcW vyaLh8Xd/h7wgUnhqnkQM+/JP2Vw5sq6rvgR0hQ19nqEFXy+HZEbP7hcAusbNgYnM0UiLj/8vFjq8 U8UGtgmJYnGN1rfKfZfNxjJFsZ18ktkpv2h36FN+oZPW28xlgbLYgyUmaLbH6bAvyRP6wBUzDqRyt WvX7l519lXjxSLaq9l8AlJ3wh2gQSFg5ak4sprQioSEjs90dFTDWtrM4PK4UfTNxA49Ijg8WL3Dqp 7CpAZmlAmk8YGop/9ownGNC5cxOCa95bpa7TU5Y6VuLoJuEW0Op6SfFMrsTkoHkXh76iRVsOE43Av 26FsXCISHlBAC+ZXTlkQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfwNl-00000005bPu-3Cmk; Thu, 06 Feb 2025 07:33:05 +0000 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfwET-00000005Y41-0A9w for linux-riscv@lists.infradead.org; Thu, 06 Feb 2025 07:23:30 +0000 Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-2f441791e40so770638a91.3 for ; Wed, 05 Feb 2025 23:23:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1738826608; x=1739431408; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=S1ycQPnopfj+lIzIUm/dRgw4jBMxR4nO8n6QcQamF/g=; b=mc8nAo9wWTvAIrckkmuOi+IXMoJhEiibAQyZjYJoho6IZMGWj+Prf9BI+UKf2qor0f ow2WL48/Bm9ATkQ5X46f0yLXKN96Xw5SWP9qmiqpMHYR7PuLansLe0Jl3T1DiYrXRS+E zQQQ9a1znYwI3CV+M0xhQXvMYCl6jj8pwKlIaf/cMVfk8CWtWlZSHnz3UT8kZDGxfzg2 fSEoGu6FIvouCGSn2LDhZ1OzJzOV7R1SCdh2bxbGM1Q8yjOZGB8KE366GZSHTTJIrhgN UnqRgPasjWkApz14rXu0M9ffUaEsVoWpWjCxeZ4NGlkuoyxpvj49gOuIleLpnKUkFRln BByQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738826608; x=1739431408; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=S1ycQPnopfj+lIzIUm/dRgw4jBMxR4nO8n6QcQamF/g=; b=WesMFOSydmtJSxlQkjKbAS6/HG2kTs5PEErg6/Iwg2OHIsQwl/NOpEteFHYyEudTW8 dfbrIMsezhq53sudyxKSbZCnEntpbameMx9yLLX/o5RKL2uQVwEXbpT4wsSklyaLDk6G qO7tdejZUfLTkq5YtkEXybjMpUvUuJxln6W+8GRodzsemFUJxvnNNnB+2xBm8tpam54w L0cbRLRQLgNiabndNBst0xm7br3lAknqQ9nGUGaguC3LAnOWPfqzVuwJdjtIMN8a9env GVXf5t3XElpiPa7IGlHx/mtazdY0pG4aEydyxHpEg93kTHiFE5seSptYBxjvK9AEkE8G zQLA== X-Gm-Message-State: AOJu0Ywjwj6q9HO/Rhg0+KXczR+E4waEHyLflNyVEp4OuWMpyag1yN4D hIC+lDVN8YmvHkohryMB9M0Ub39dd0MJHrii8gCvxXEAmRCY0fNdaoWFcJpt2Xg= X-Gm-Gg: ASbGncsMt17A0UNJtZZ20woHbudExpS6QI5lZn9tl4STzW0oKjlB52bF70R3QqP6qwh cPwATUnq1wFmWVCTuuH6SYTevpgKmEYsSqqv07a7vAvHe15FVJgnlcpAycWZBvx3q3zq+WgySiD 5pW6GPvrkfyffvSZhRM9Ok3YfN5JfdLFw5qSnf4c/GxgnXk+vgOm586tsycfJZ2xoyF3P98AwTR Q8wOL7OrFhxRnP6jkFx9Zyw5XXSz85s/26YIbtz8D7HBuoKvSy5lEzQ4hRWcTXfK2CwD1h0rsdc UjETWiKwN7c0/XrZ+MLvz4H6lBN1 X-Google-Smtp-Source: AGHT+IFwe864GICHNnq9EVCYpLvbwfcMr9HibfAj+2D5yDDYG7ZeHAVPjVfRo7yQfH146FLB/di+WQ== X-Received: by 2002:a17:90b:1d87:b0:2ee:edae:780 with SMTP id 98e67ed59e1d1-2f9e0793401mr10185856a91.15.1738826608431; Wed, 05 Feb 2025 23:23:28 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a72292sm630883a91.27.2025.02.05.23.23.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 23:23:28 -0800 (PST) From: Atish Patra Date: Wed, 05 Feb 2025 23:23:13 -0800 Subject: [PATCH v4 08/21] RISC-V: Add Sscfg extension CSR definition MIME-Version: 1.0 Message-Id: <20250205-counter_delegation-v4-8-835cfa88e3b1@rivosinc.com> References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> In-Reply-To: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra , Kaiwen Xue X-Mailer: b4 0.15-dev-13183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_232329_081919_B1410F99 X-CRM114-Status: UNSURE ( 9.48 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Kaiwen Xue This adds the scountinhibit CSR definition and S-mode accessible hpmevent bits defined by smcdeleg/ssccfg. scountinhibit allows S-mode to start/stop counters directly from S-mode without invoking SBI calls to M-mode. It is also used to figure out the counters delegated to S-mode by the M-mode as well. Signed-off-by: Kaiwen Xue Reviewed-by: Clément Léger --- arch/riscv/include/asm/csr.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 2ad2d492e6b4..42b7f4f7ec0f 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -224,6 +224,31 @@ #define SMSTATEEN0_HSENVCFG (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT) #define SMSTATEEN0_SSTATEEN0_SHIFT 63 #define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT) +/* HPMEVENT bits. These are accessible in S-mode via Smcdeleg/Ssccfg */ +#ifdef CONFIG_64BIT +#define HPMEVENT_OF (_UL(1) << 63) +#define HPMEVENT_MINH (_UL(1) << 62) +#define HPMEVENT_SINH (_UL(1) << 61) +#define HPMEVENT_UINH (_UL(1) << 60) +#define HPMEVENT_VSINH (_UL(1) << 59) +#define HPMEVENT_VUINH (_UL(1) << 58) +#else +#define HPMEVENTH_OF (_ULL(1) << 31) +#define HPMEVENTH_MINH (_ULL(1) << 30) +#define HPMEVENTH_SINH (_ULL(1) << 29) +#define HPMEVENTH_UINH (_ULL(1) << 28) +#define HPMEVENTH_VSINH (_ULL(1) << 27) +#define HPMEVENTH_VUINH (_ULL(1) << 26) + +#define HPMEVENT_OF (HPMEVENTH_OF << 32) +#define HPMEVENT_MINH (HPMEVENTH_MINH << 32) +#define HPMEVENT_SINH (HPMEVENTH_SINH << 32) +#define HPMEVENT_UINH (HPMEVENTH_UINH << 32) +#define HPMEVENT_VSINH (HPMEVENTH_VSINH << 32) +#define HPMEVENT_VUINH (HPMEVENTH_VUINH << 32) +#endif + +#define SISELECT_SSCCFG_BASE 0x40 /* mseccfg bits */ #define MSECCFG_PMM ENVCFG_PMM @@ -305,6 +330,7 @@ #define CSR_SCOUNTEREN 0x106 #define CSR_SENVCFG 0x10a #define CSR_SSTATEEN0 0x10c +#define CSR_SCOUNTINHIBIT 0x120 #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 #define CSR_SCAUSE 0x142 From patchwork Thu Feb 6 07:23:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13962508 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 80E8DC0219B for ; Thu, 6 Feb 2025 07:35:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1UBAK5/lHCdHkrhXUxWzRQyQL4FrHp20YbQi5M8VSZ4=; b=IxTSrnUEmY4AXW tiosbks7aaVLR3ex1AX8XK4pYlMdQZg/5mpYMAWJ7ZUbRHipFWQJFWjzTZk9Ad/ke44+CDXq5GeyM bTJsoFtqOl+TDiYSN39bdKYy0+CYiEVB4EIDwoTdAdgo8sSc8Rsd9hwfEom5V2dtIkktXSGKk9F87 5XblN+gWh2U7NopxRa/OnGnYEYReNVUqwhI7aNBL06/VdSDR1whDrW8qZlNc+g6wLeDaG8kwN/7A8 Pm+ytKdXEOinGwaIeTCP20hLZ2dE+fLSkMDUllWjgA+ijvt8vn/CVj68mKwqzWkDd8B3LJ1cJf0Pn 97xzD7pCWo+LZK+BhK/g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfwQR-00000005boO-1RQV; Thu, 06 Feb 2025 07:35:51 +0000 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfwEU-00000005Y5h-2IYC for linux-riscv@lists.infradead.org; Thu, 06 Feb 2025 07:23:32 +0000 Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-2f9e415fa42so968230a91.1 for ; Wed, 05 Feb 2025 23:23:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1738826610; x=1739431410; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=nYw8eDaBPoa3lZTMqvm38RPB8/mlpG4q3+7Mk5EH9kg=; b=xvLjzbVwNxJdf5bic6yw+CSr9TLJmODEG2Uax4QhRTKYOEZNpS/iMmm662Ta2wjEe4 ntH5rODq15GTB5i+MRLQE2P2uCxbGmQg8gmeMDjALtHJc5+pNWrN+/UrUQemp1CgJtwn 1nu4rT4syaZCx5JDPqAQ/Z/eJwuLCEgIeQmo4mlfN/CwAeRRwj2+VB5oXLgjHOl669Zk nQBOdGsPohpbvGTU4Og592uX7vgMb18pJ74+AV5h1uIFrna8bfsS4TKwF1CQ1OBxrGTX V1sUMRlOb17q+Iwu4IeENjLdth1eIIzJEVzSnZQZw8/JWmu0yIiwjzS2NPYRSfXUQEuF MwJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738826610; x=1739431410; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nYw8eDaBPoa3lZTMqvm38RPB8/mlpG4q3+7Mk5EH9kg=; b=w2pQS3zLNv4LNAv1+LqET0nARcNApXx0cCLUgFHJ37u+9y9wsJn12lOlavH5ARSowE beOsGmvgHv4UntFWb10hVHbXSZn7cMB83GP+v1pmD0t4sWucnnatpHkEzh4wvqCSn5kE gc0X/ft4teFjgW5ZZpKFzSXcqRiJ/PtCtsUlvCgcHqdfQLE5+1NVlHCJb19TDmeCxN/1 /pcZv5C8vd6y2HXUMcGZIMwY/EmKFkBIxEsO5B5SV6rWQBu4Km6i+zITvwpvAfyBu8n5 fNovsu+Wjk8HdHMqEuYtIS9bJltcFQbMzurhrsMbkqUL4sNDxXq36rdwWqGAn1maH/Ov iQIw== X-Gm-Message-State: AOJu0Ywp2arJpMAD7aq5Sfl6L2AWQxjgyfnMxa4J4zYqaVfr42zmLYDz BLRrR3k55HZWbPuAIlPot5WJ8gMmFdt5DsXQ6r4BaK1aSOJg9qYW0csg1zXwDoc= X-Gm-Gg: ASbGncvI2T6K6rv9GWOqs/ff8ocUQm6bfIGZWj92ARo9fiLIYDgO9OXLopBclUZwD0g QAQBJrt8GSB2EFYshZng0skCj38qJmeY5JJnxixXvMd/861b9PB7CUAT3jJPrVNNfLoaN76DHMU n1yiZ57oqb/t68+/M6WmjzvmK6ksyNS1irLUEBzsq8LyomTFNdw+XV/13Z8GWRs0TG3K4jts9rf EaKnkzi5Ri3GuAhqYbcSloPgQunIOLJ6mceXpWsTDE8LeprwpXeNqu5L3WbLWZcVmu0n6BC+lCT dhOKHbZLA0y4oPBwIlDKXzmAAkuZ X-Google-Smtp-Source: AGHT+IFmp7b1yh0QEKdLgrjIIYD49wESbW2YfC1lavQg5SmkfBv2dPjIMLPytR1zKx8iqVccmwXu3w== X-Received: by 2002:a17:90b:2b4d:b0:2ee:f687:6acb with SMTP id 98e67ed59e1d1-2f9e07673b6mr8850611a91.13.1738826610015; Wed, 05 Feb 2025 23:23:30 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a72292sm630883a91.27.2025.02.05.23.23.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 23:23:29 -0800 (PST) From: Atish Patra Date: Wed, 05 Feb 2025 23:23:14 -0800 Subject: [PATCH v4 09/21] RISC-V: Add Ssccfg ISA extension definition and parsing MIME-Version: 1.0 Message-Id: <20250205-counter_delegation-v4-9-835cfa88e3b1@rivosinc.com> References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> In-Reply-To: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_232330_591796_3244DE5E X-CRM114-Status: UNSURE ( 9.64 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Ssccfg (‘Ss’ for Privileged architecture and Supervisor-level extension, ‘ccfg’ for Counter Configuration) provides access to delegated counters and new supervisor-level state. This patch just enables the definitions and enable parsing. Signed-off-by: Atish Patra --- arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpufeature.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index b4eddcb57842..fa5e01bcb990 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -103,6 +103,8 @@ #define RISCV_ISA_EXT_SSCSRIND 94 #define RISCV_ISA_EXT_SMCSRIND 95 #define RISCV_ISA_EXT_SMCNTRPMF 96 +#define RISCV_ISA_EXT_SSCCFG 97 +#define RISCV_ISA_EXT_SMCDELEG 98 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 8f225c9c3055..3cb208d4913e 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -390,12 +390,14 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), + __RISCV_ISA_EXT_DATA(smcdeleg, RISCV_ISA_EXT_SMCDELEG), __RISCV_ISA_EXT_DATA(smcntrpmf, RISCV_ISA_EXT_SMCNTRPMF), __RISCV_ISA_EXT_DATA(smcsrind, RISCV_ISA_EXT_SMCSRIND), __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM), __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_exts), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), + __RISCV_ISA_EXT_DATA(ssccfg, RISCV_ISA_EXT_SSCCFG), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sscsrind, RISCV_ISA_EXT_SSCSRIND), __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_exts), From patchwork Thu Feb 6 07:23:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13962507 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7276CC02198 for ; Thu, 6 Feb 2025 07:35:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hQkl3iX4U0A6+7QJQu3k2gi21dtPaYtng0v1njg1xf8=; b=xORjN635N566pe qB2+Xa3tBF+EvVOz8DD7xz9USqieNzS1p53SgSCCEsO842MHLQJJXqRlVrywiiUuaPnrsz6ucsthp QbXuaRKUBKNLvNXZx9PRRpcNTah6cX9kvXjLOrgz12SUcvYSJaVtSMZU5lsJp10FgspW42TjZG+Ej pkHw2uGlYbKWb4o2VVqXufqQAZGkhR801hFgO6IH2C6XcIKqD/rskNe3rhs2NWjMBf7UHQWEy3OPx kT2/HYU7UbNVRwF/4arhrTV7I3C7QDz3Oiu0s4LsTsFk9bLO4pARSV584KnJg59WwZUv1qMY9hVMA ea4if1kGW+la5SiIfhTw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfwQS-00000005bor-1A03; Thu, 06 Feb 2025 07:35:52 +0000 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfwEW-00000005Y7H-1pQU for linux-riscv@lists.infradead.org; Thu, 06 Feb 2025 07:23:34 +0000 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-21f20666e72so12263645ad.1 for ; Wed, 05 Feb 2025 23:23:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1738826612; x=1739431412; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=bxHoYiVqgOBhm1wpVoVRMHPjl115bpEgggXMBP5Q3iA=; b=xzLy8Fit/VigAm9+binRgu0zhGOGFcp74CH9QJqHO12aUVBIu4wDcoBy1k48+mD1GS 1XknV1LKkDqOmzWz5x71B8rqsTsBiK3zmSbmOTs0gQ9kr1qfmXdVzY8Q70riaRExPpV8 DxE5yJ+IXr+CAiGxp9/q5iruyMXcGkUpDK77uLrWlkXk4yvsh3tzPiuqnLqe8jUBsblu HU51Kl8KmA/64kYCdmADu/iFiOckgdc7oyOHn0UmQweFwmtISk7ow139jhLGPPG1bBen dZFUxIBWPsikZCW+u/oqJHCl4OpUHRrPGQg3YTpdzi9gicXOWmUk3vd8Cb2BktzMcBi9 ByUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738826612; x=1739431412; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bxHoYiVqgOBhm1wpVoVRMHPjl115bpEgggXMBP5Q3iA=; b=WGg/b4TFwGOfMR1s6lG8CxSZ/O38vlo8kiEz+7sAZZ8Kp6XmceulP3kIWSjETf9jg6 Px0zmNM2y7/DTJH3IB1/YWy2pttm9hxFtbPnRhRxk3f3xsJV98EfthsHPPPEdssKFcqa JVPlXvxWwRcP9CgPF2iiAwNjszeBIUHy+tgyTHkwqVxQlgOMm6doqtlGl5HgMnggDS8q lP5ktP9B7i/WTnB3pFiBOHSEEI643evT+zY4IQmiz8ZLllshkHcLI3/kR9m5ytp7mAyu jBbiehpDDD0uHCX4JWH8RnMxiMnC1zrDeZo28z8oOEjemNaarEa/e1hwPjEgUuvjlJFq I9Jw== X-Gm-Message-State: AOJu0Yx8DxaRp1wPohjWou8xLe24RH6+1niLXetelxPd2OmKKkeSCv46 4Z9cVPLLeuWohHnmmI3i+pxqysFCJvg/ysae18xtB92njOlPaDAdk75Y/0uyWQI= X-Gm-Gg: ASbGncvARFRt+xrvAgVibj50wXkSDsrJGWLaTRKgHs+ib58VoogOjLKDVrvDSDWkgND tNnaJNydGFubKlfNzltH10+m1U7rb6aTEZ2+5QPfJ2KXMTudKE4ACqvWo+Xw429HvCTznKNTgHg 8EQnZlsNehVaKhyfUC5yA39iYKIy//Lj/PdspnpgtepzYc+MxCRy7ND1nkVByCrTdwrWDIb3nzJ Ut07cp2Xjys6HqnUGjbBZxuitDegdbut38ffF1Q10JLHsKCTXTlN6phRRqbaNyaglHV1jLupwYS bYafmbYsbd18Z5woQ7ZEDUBN0EhB X-Google-Smtp-Source: AGHT+IHdxb765FF/tuEHMIXniBEbzBGChueSqoBlXVwelYSzs5G+a6kTSb+Hcc24wmC4wtSYLVHKkg== X-Received: by 2002:a17:902:f64b:b0:216:7c33:8994 with SMTP id d9443c01a7336-21f17f32366mr113621535ad.53.1738826611778; Wed, 05 Feb 2025 23:23:31 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a72292sm630883a91.27.2025.02.05.23.23.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 23:23:31 -0800 (PST) From: Atish Patra Date: Wed, 05 Feb 2025 23:23:15 -0800 Subject: [PATCH v4 10/21] dt-bindings: riscv: add Counter delegation ISA extensions description MIME-Version: 1.0 Message-Id: <20250205-counter_delegation-v4-10-835cfa88e3b1@rivosinc.com> References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> In-Reply-To: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_232332_523112_2DC18FF4 X-CRM114-Status: GOOD ( 11.24 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add description for the Smcdeleg/Ssccfg extension. Signed-off-by: Atish Patra --- .../devicetree/bindings/riscv/extensions.yaml | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index be9ebe927a64..b20dc75457d2 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -128,6 +128,13 @@ properties: changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. + - const: smcdeleg + description: | + The standard Smcdeleg supervisor-level extension for the machine mode + to delegate the hpmcounters to supvervisor mode so that they are + directlyi accessible in the supervisor mode as ratified in the + 20240213 version of the privileged ISA specification. + - const: smcsrind description: | The standard Smcsrind supervisor-level extension extends the @@ -175,6 +182,14 @@ properties: behavioural changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. + - const: ssccfg + description: | + The standard Ssccfg supervisor-level extension for configuring + the delegated hpmcounters to be accessible directly in supervisor + mode as ratified in the 20240213 version of the privileged ISA + specification. This extension depends on Sscsrind, Smcdeleg, Zihpm, + Zicntr extensions. + - const: sscofpmf description: | The standard Sscofpmf supervisor-level extension for count overflow @@ -685,6 +700,36 @@ properties: then: contains: const: zca + # Smcdeleg depends on Sscsrind, Zihpm, Zicntr + - If: + contains: + const: smcdeleg + then: + allOf: + - contains: + const: sscsrind + - contains: + const: zihpm + - contains: + const: zicntr + # Ssccfg depends on Smcdeleg, Sscsrind, Zihpm, Zicntr, Sscofpmf, Smcntrpmf + - If: + contains: + const: ssccfg + then: + allOf: + - contains: + const: smcdeleg + - contains: + const: sscsrind + - contains: + const: sscofpmf + - contains: + const: smcntrpmf + - contains: + const: zihpm + - contains: + const: zicntr allOf: # Zcf extension does not exist on rv64 From patchwork Thu Feb 6 07:23:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13962510 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18F0FC02196 for ; Thu, 6 Feb 2025 07:38:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=MvrrfcuRBlzg5XzJp//PK3kdYd7q5v4YLh4cwbXaoUw=; b=XusV3L7Z0Rg6w8 D6ymPpupX2huoENaQoKQuA39tCstk6GvsNJAgfhljsqga5Yj/UY23pwXf55EqcdFsahg8cSyV5GMJ 5DQmeq3WbqBKV9cWnETnakDIxi4JRynV9QW6tqkPeciMWxgrf19wzWcKbFY0XHc1gQo9Mzu890TQs 0Bh3cbs8lwdGZldZUkrkb0ZwRKP0sjyocayOYO4bWEndSiqqJGRHxk6QVihzr5iTwJrtZ2qml+ak2 Lu4rT79MN6yVZ6P2MBPKbEyxhRUPu9+Ss/YWSj9ztviGoun9tuxtSfehaOm0ACSv8aG3kvUH9nbMo +47utEPjlmgt4qFdhe7Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfwT6-00000005cDD-06EI; Thu, 06 Feb 2025 07:38:36 +0000 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfwEY-00000005Y9D-15Rc for linux-riscv@lists.infradead.org; Thu, 06 Feb 2025 07:23:36 +0000 Received: by mail-pj1-x102b.google.com with SMTP id 98e67ed59e1d1-2f9b91dff71so790394a91.2 for ; Wed, 05 Feb 2025 23:23:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1738826614; x=1739431414; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=anXe/CtOz/oIHjbwGvwPwkbrxEowv5h83zk+NamuRlw=; b=PsqHlD7VmTgHK2um6i7kmnKSPcaLP5mgkeg1wQXk92VnsFU7pJ+UzUGbl4T0gUveVt D6AcsGu8wMhwfXiSX4NHQK6Zl8GHY60s110xRkmMqgrQelLVg+qX2oQaK2A530vGY8kD WWy1dmmau7QCGufZOJF59NbsJtoa9ZrCfier3bu3/eg71a6fnOcZZZF7/1JW+L7t0QBR ZaI67PITGXNDSy8ln0EEvV3ACb8aR/+O1FToV/7JrQBDBXYUJ34+OZ9aat4576saEZrM IleDZ9YRA5oqecSAK2JuNDxy7wbQMqoUB/EmocA54PepxoyBYrfzuLx/+kpRxcolFyk6 fouw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738826614; x=1739431414; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=anXe/CtOz/oIHjbwGvwPwkbrxEowv5h83zk+NamuRlw=; b=nqYnWZInifExRWqJpfV5ZAiS/rHaxwfF2Im0KpiutAx+xI5VAde8wqp7w6Iaob3WiP C8qB3t3aVadPhujEPkFFzp6cicX7n7Ujt5uvTTdviTsSto3tn88gMFLmZDuyXJSDrvdK QYr231YtRFAKfgJBHmOh42V7gc5cepk78HPAsMIioNXWhQKYklViKgZ9nke84kPCkKk2 m0WgnwN5owC/2zp5fheSjx1eiHqEMifLvg5z07HimgJxDlzbaoa3kHJ8z2mOK+/Z+V0u H6cXxgH04bV20s9nQQKwIJvp5MOtlUGuTdg8n2Ln3NORbn9JVKyKUzqkZ4AwnOl42vrg CiQA== X-Gm-Message-State: AOJu0YxgtIhZZKaFDNAyorD/l7404m09E+VRKHkKWUwGKZ/gLpqAH29K vRK9E/LF5PrCZoZ/+H9msFU7n6rpTS7oK4qxsmyM8Cc70mGmJJuni3K6AX4HHkw= X-Gm-Gg: ASbGncvItplAWFHTJ8LbsP06bblCD/B1UQUjohvIsOd2imp65b4pfysdaWvvG4hg1yT ChN78wQVeX7YQoLcHA5eZflURRuVf1i9oLRFRGOu2K59I4OuDbgK4jijp2iLX919yRYffDaXhgD WkBSoMyPQNMe7Rf8xRtHoCUoM6tVL+Zc0BgiByxFr9fa1JYunUla4uvwlft+EQHuff9vxYXBrOV Xtnph/Q8bhUp0SOc3x0/H+8EDEkS9Ks/+Vz4FAUJmbdfPJ0PuAFHb981JehJ2A0RFp0rF7/nGJq sMv4FRWICCwwhmvVTz1jRnRl7L50 X-Google-Smtp-Source: AGHT+IG9ErDsuwbTkF9cQ+fybvLxqYghUN6MYzwdKNRfVONm64cNf/y4/XcpEr/iia3MPgHHlS2RcA== X-Received: by 2002:a17:90b:1d44:b0:2ee:cdea:ad91 with SMTP id 98e67ed59e1d1-2f9e0785075mr9990147a91.15.1738826613453; Wed, 05 Feb 2025 23:23:33 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a72292sm630883a91.27.2025.02.05.23.23.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 23:23:33 -0800 (PST) From: Atish Patra Date: Wed, 05 Feb 2025 23:23:16 -0800 Subject: [PATCH v4 11/21] RISC-V: perf: Restructure the SBI PMU code MIME-Version: 1.0 Message-Id: <20250205-counter_delegation-v4-11-835cfa88e3b1@rivosinc.com> References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> In-Reply-To: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_232334_350927_4E5AEBCC X-CRM114-Status: GOOD ( 24.24 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org With Ssccfg/Smcdeleg, we no longer need SBI PMU extension to program/ access hpmcounter/events. However, we do need it for firmware counters. Rename the driver and its related code to represent generic name that will handle both sbi and ISA mechanism for hpmcounter related operations. Take this opportunity to update the Kconfig names to match the new driver name closely. No functional change intended. Signed-off-by: Atish Patra Reviewed-by: Clément Léger --- MAINTAINERS | 4 +- arch/riscv/include/asm/kvm_vcpu_pmu.h | 4 +- arch/riscv/include/asm/kvm_vcpu_sbi.h | 2 +- arch/riscv/kvm/Makefile | 4 +- arch/riscv/kvm/vcpu_sbi.c | 2 +- drivers/perf/Kconfig | 16 +- drivers/perf/Makefile | 4 +- drivers/perf/{riscv_pmu.c => riscv_pmu_common.c} | 0 drivers/perf/{riscv_pmu_sbi.c => riscv_pmu_dev.c} | 214 +++++++++++++--------- include/linux/perf/riscv_pmu.h | 8 +- 10 files changed, 151 insertions(+), 107 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 30cbc3d44cd5..2ef7ff933266 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20177,9 +20177,9 @@ M: Atish Patra R: Anup Patel L: linux-riscv@lists.infradead.org S: Supported -F: drivers/perf/riscv_pmu.c +F: drivers/perf/riscv_pmu_common.c +F: drivers/perf/riscv_pmu_dev.c F: drivers/perf/riscv_pmu_legacy.c -F: drivers/perf/riscv_pmu_sbi.c RISC-V THEAD SoC SUPPORT M: Drew Fustini diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm/kvm_vcpu_pmu.h index 1d85b6617508..aa75f52e9092 100644 --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -13,7 +13,7 @@ #include #include -#ifdef CONFIG_RISCV_PMU_SBI +#ifdef CONFIG_RISCV_PMU #define RISCV_KVM_MAX_FW_CTRS 32 #define RISCV_KVM_MAX_HW_CTRS 32 #define RISCV_KVM_MAX_COUNTERS (RISCV_KVM_MAX_HW_CTRS + RISCV_KVM_MAX_FW_CTRS) @@ -128,5 +128,5 @@ static inline int kvm_riscv_vcpu_pmu_incr_fw(struct kvm_vcpu *vcpu, unsigned lon static inline void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu) {} static inline void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu) {} -#endif /* CONFIG_RISCV_PMU_SBI */ +#endif /* CONFIG_RISCV_PMU */ #endif /* !__KVM_VCPU_RISCV_PMU_H */ diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm/kvm_vcpu_sbi.h index b96705258cf9..764bb158e760 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -89,7 +89,7 @@ extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_sta; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor; -#ifdef CONFIG_RISCV_PMU_SBI +#ifdef CONFIG_RISCV_PMU extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_pmu; #endif #endif /* __RISCV_KVM_VCPU_SBI_H__ */ diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index 0fb1840c3e0a..f4ad7af0bdab 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -23,11 +23,11 @@ kvm-y += vcpu_exit.o kvm-y += vcpu_fp.o kvm-y += vcpu_insn.o kvm-y += vcpu_onereg.o -kvm-$(CONFIG_RISCV_PMU_SBI) += vcpu_pmu.o +kvm-$(CONFIG_RISCV_PMU) += vcpu_pmu.o kvm-y += vcpu_sbi.o kvm-y += vcpu_sbi_base.o kvm-y += vcpu_sbi_hsm.o -kvm-$(CONFIG_RISCV_PMU_SBI) += vcpu_sbi_pmu.o +kvm-$(CONFIG_RISCV_PMU) += vcpu_sbi_pmu.o kvm-y += vcpu_sbi_replace.o kvm-y += vcpu_sbi_sta.o kvm-$(CONFIG_RISCV_SBI_V01) += vcpu_sbi_v01.o diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index 6e704ed86a83..4eaf9b0f736b 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -20,7 +20,7 @@ static const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01 = { }; #endif -#ifndef CONFIG_RISCV_PMU_SBI +#ifndef CONFIG_RISCV_PMU static const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_pmu = { .extid_start = -1UL, .extid_end = -1UL, diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index 4e268de351c4..b3bdff2a99a4 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -75,7 +75,7 @@ config ARM_XSCALE_PMU depends on ARM_PMU && CPU_XSCALE def_bool y -config RISCV_PMU +config RISCV_PMU_COMMON depends on RISCV bool "RISC-V PMU framework" default y @@ -86,7 +86,7 @@ config RISCV_PMU can reuse it. config RISCV_PMU_LEGACY - depends on RISCV_PMU + depends on RISCV_PMU_COMMON bool "RISC-V legacy PMU implementation" default y help @@ -95,15 +95,15 @@ config RISCV_PMU_LEGACY of cycle/instruction counter and doesn't support counter overflow, or programmable counters. It will be removed in future. -config RISCV_PMU_SBI - depends on RISCV_PMU && RISCV_SBI - bool "RISC-V PMU based on SBI PMU extension" +config RISCV_PMU + depends on RISCV_PMU_COMMON && RISCV_SBI + bool "RISC-V PMU based on SBI PMU extension and/or Counter delegation extension" default y help Say y if you want to use the CPU performance monitor - using SBI PMU extension on RISC-V based systems. This option provides - full perf feature support i.e. counter overflow, privilege mode - filtering, counter configuration. + using SBI PMU extension or counter delegation ISA extension on RISC-V + based systems. This option provides full perf feature support i.e. + counter overflow, privilege mode filtering, counter configuration. config STARFIVE_STARLINK_PMU depends on ARCH_STARFIVE || COMPILE_TEST diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile index de71d2574857..0805d740c773 100644 --- a/drivers/perf/Makefile +++ b/drivers/perf/Makefile @@ -16,9 +16,9 @@ obj-$(CONFIG_FSL_IMX9_DDR_PMU) += fsl_imx9_ddr_perf.o obj-$(CONFIG_HISI_PMU) += hisilicon/ obj-$(CONFIG_QCOM_L2_PMU) += qcom_l2_pmu.o obj-$(CONFIG_QCOM_L3_PMU) += qcom_l3_pmu.o -obj-$(CONFIG_RISCV_PMU) += riscv_pmu.o +obj-$(CONFIG_RISCV_PMU_COMMON) += riscv_pmu_common.o obj-$(CONFIG_RISCV_PMU_LEGACY) += riscv_pmu_legacy.o -obj-$(CONFIG_RISCV_PMU_SBI) += riscv_pmu_sbi.o +obj-$(CONFIG_RISCV_PMU) += riscv_pmu_dev.o obj-$(CONFIG_STARFIVE_STARLINK_PMU) += starfive_starlink_pmu.o obj-$(CONFIG_THUNDERX2_PMU) += thunderx2_pmu.o obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu_common.c similarity index 100% rename from drivers/perf/riscv_pmu.c rename to drivers/perf/riscv_pmu_common.c diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_dev.c similarity index 87% rename from drivers/perf/riscv_pmu_sbi.c rename to drivers/perf/riscv_pmu_dev.c index 1aa303f76cc7..6b43d844eaea 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_dev.c @@ -8,7 +8,7 @@ * sparc64 and x86 code. */ -#define pr_fmt(fmt) "riscv-pmu-sbi: " fmt +#define pr_fmt(fmt) "riscv-pmu-dev: " fmt #include #include @@ -87,6 +87,8 @@ static const struct attribute_group *riscv_pmu_attr_groups[] = { static int sysctl_perf_user_access __read_mostly = SYSCTL_USER_ACCESS; /* + * This structure is SBI specific but counter delegation also require counter + * width, csr mapping. Reuse it for now. * RISC-V doesn't have heterogeneous harts yet. This need to be part of * per_cpu in case of harts with different pmu counters */ @@ -119,7 +121,7 @@ struct sbi_pmu_event_data { }; }; -static struct sbi_pmu_event_data pmu_hw_event_map[] = { +static struct sbi_pmu_event_data pmu_hw_event_sbi_map[] = { [PERF_COUNT_HW_CPU_CYCLES] = {.hw_gen_event = { SBI_PMU_HW_CPU_CYCLES, SBI_PMU_EVENT_TYPE_HW, 0}}, @@ -153,7 +155,7 @@ static struct sbi_pmu_event_data pmu_hw_event_map[] = { }; #define C(x) PERF_COUNT_HW_CACHE_##x -static struct sbi_pmu_event_data pmu_cache_event_map[PERF_COUNT_HW_CACHE_MAX] +static struct sbi_pmu_event_data pmu_cache_event_sbi_map[PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_RESULT_MAX] = { [C(L1D)] = { @@ -298,7 +300,7 @@ static struct sbi_pmu_event_data pmu_cache_event_map[PERF_COUNT_HW_CACHE_MAX] }, }; -static void pmu_sbi_check_event(struct sbi_pmu_event_data *edata) +static void rvpmu_sbi_check_event(struct sbi_pmu_event_data *edata) { struct sbiret ret; @@ -313,25 +315,25 @@ static void pmu_sbi_check_event(struct sbi_pmu_event_data *edata) } } -static void pmu_sbi_check_std_events(struct work_struct *work) +static void rvpmu_sbi_check_std_events(struct work_struct *work) { - for (int i = 0; i < ARRAY_SIZE(pmu_hw_event_map); i++) - pmu_sbi_check_event(&pmu_hw_event_map[i]); + for (int i = 0; i < ARRAY_SIZE(pmu_hw_event_sbi_map); i++) + rvpmu_sbi_check_event(&pmu_hw_event_sbi_map[i]); - for (int i = 0; i < ARRAY_SIZE(pmu_cache_event_map); i++) - for (int j = 0; j < ARRAY_SIZE(pmu_cache_event_map[i]); j++) - for (int k = 0; k < ARRAY_SIZE(pmu_cache_event_map[i][j]); k++) - pmu_sbi_check_event(&pmu_cache_event_map[i][j][k]); + for (int i = 0; i < ARRAY_SIZE(pmu_cache_event_sbi_map); i++) + for (int j = 0; j < ARRAY_SIZE(pmu_cache_event_sbi_map[i]); j++) + for (int k = 0; k < ARRAY_SIZE(pmu_cache_event_sbi_map[i][j]); k++) + rvpmu_sbi_check_event(&pmu_cache_event_sbi_map[i][j][k]); } -static DECLARE_WORK(check_std_events_work, pmu_sbi_check_std_events); +static DECLARE_WORK(check_std_events_work, rvpmu_sbi_check_std_events); -static int pmu_sbi_ctr_get_width(int idx) +static int rvpmu_ctr_get_width(int idx) { return pmu_ctr_list[idx].width; } -static bool pmu_sbi_ctr_is_fw(int cidx) +static bool rvpmu_ctr_is_fw(int cidx) { union sbi_pmu_ctr_info *info; @@ -373,12 +375,12 @@ int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr) } EXPORT_SYMBOL_GPL(riscv_pmu_get_hpm_info); -static uint8_t pmu_sbi_csr_index(struct perf_event *event) +static uint8_t rvpmu_csr_index(struct perf_event *event) { return pmu_ctr_list[event->hw.idx].csr - CSR_CYCLE; } -static unsigned long pmu_sbi_get_filter_flags(struct perf_event *event) +static unsigned long rvpmu_sbi_get_filter_flags(struct perf_event *event) { unsigned long cflags = 0; bool guest_events = false; @@ -399,7 +401,7 @@ static unsigned long pmu_sbi_get_filter_flags(struct perf_event *event) return cflags; } -static int pmu_sbi_ctr_get_idx(struct perf_event *event) +static int rvpmu_sbi_ctr_get_idx(struct perf_event *event) { struct hw_perf_event *hwc = &event->hw; struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu); @@ -409,7 +411,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event) uint64_t cbase = 0, cmask = rvpmu->cmask; unsigned long cflags = 0; - cflags = pmu_sbi_get_filter_flags(event); + cflags = rvpmu_sbi_get_filter_flags(event); /* * In legacy mode, we have to force the fixed counters for those events @@ -446,7 +448,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event) return -ENOENT; /* Additional sanity check for the counter id */ - if (pmu_sbi_ctr_is_fw(idx)) { + if (rvpmu_ctr_is_fw(idx)) { if (!test_and_set_bit(idx, cpuc->used_fw_ctrs)) return idx; } else { @@ -457,7 +459,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event) return -ENOENT; } -static void pmu_sbi_ctr_clear_idx(struct perf_event *event) +static void rvpmu_ctr_clear_idx(struct perf_event *event) { struct hw_perf_event *hwc = &event->hw; @@ -465,13 +467,13 @@ static void pmu_sbi_ctr_clear_idx(struct perf_event *event) struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events); int idx = hwc->idx; - if (pmu_sbi_ctr_is_fw(idx)) + if (rvpmu_ctr_is_fw(idx)) clear_bit(idx, cpuc->used_fw_ctrs); else clear_bit(idx, cpuc->used_hw_ctrs); } -static int pmu_event_find_cache(u64 config) +static int sbi_pmu_event_find_cache(u64 config) { unsigned int cache_type, cache_op, cache_result, ret; @@ -487,7 +489,7 @@ static int pmu_event_find_cache(u64 config) if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) return -EINVAL; - ret = pmu_cache_event_map[cache_type][cache_op][cache_result].event_idx; + ret = pmu_cache_event_sbi_map[cache_type][cache_op][cache_result].event_idx; return ret; } @@ -503,7 +505,7 @@ static bool pmu_sbi_is_fw_event(struct perf_event *event) return false; } -static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig) +static int rvpmu_sbi_event_map(struct perf_event *event, u64 *econfig) { u32 type = event->attr.type; u64 config = event->attr.config; @@ -520,10 +522,10 @@ static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig) case PERF_TYPE_HARDWARE: if (config >= PERF_COUNT_HW_MAX) return -EINVAL; - ret = pmu_hw_event_map[event->attr.config].event_idx; + ret = pmu_hw_event_sbi_map[event->attr.config].event_idx; break; case PERF_TYPE_HW_CACHE: - ret = pmu_event_find_cache(config); + ret = sbi_pmu_event_find_cache(config); break; case PERF_TYPE_RAW: /* @@ -646,7 +648,7 @@ static int pmu_sbi_snapshot_setup(struct riscv_pmu *pmu, int cpu) return 0; } -static u64 pmu_sbi_ctr_read(struct perf_event *event) +static u64 rvpmu_sbi_ctr_read(struct perf_event *event) { struct hw_perf_event *hwc = &event->hw; int idx = hwc->idx; @@ -688,25 +690,25 @@ static u64 pmu_sbi_ctr_read(struct perf_event *event) return val; } -static void pmu_sbi_set_scounteren(void *arg) +static void rvpmu_set_scounteren(void *arg) { struct perf_event *event = (struct perf_event *)arg; if (event->hw.idx != -1) csr_write(CSR_SCOUNTEREN, - csr_read(CSR_SCOUNTEREN) | BIT(pmu_sbi_csr_index(event))); + csr_read(CSR_SCOUNTEREN) | BIT(rvpmu_csr_index(event))); } -static void pmu_sbi_reset_scounteren(void *arg) +static void rvpmu_reset_scounteren(void *arg) { struct perf_event *event = (struct perf_event *)arg; if (event->hw.idx != -1) csr_write(CSR_SCOUNTEREN, - csr_read(CSR_SCOUNTEREN) & ~BIT(pmu_sbi_csr_index(event))); + csr_read(CSR_SCOUNTEREN) & ~BIT(rvpmu_csr_index(event))); } -static void pmu_sbi_ctr_start(struct perf_event *event, u64 ival) +static void rvpmu_sbi_ctr_start(struct perf_event *event, u64 ival) { struct sbiret ret; struct hw_perf_event *hwc = &event->hw; @@ -726,10 +728,10 @@ static void pmu_sbi_ctr_start(struct perf_event *event, u64 ival) if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) && (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) - pmu_sbi_set_scounteren((void *)event); + rvpmu_set_scounteren((void *)event); } -static void pmu_sbi_ctr_stop(struct perf_event *event, unsigned long flag) +static void rvpmu_sbi_ctr_stop(struct perf_event *event, unsigned long flag) { struct sbiret ret; struct hw_perf_event *hwc = &event->hw; @@ -739,7 +741,7 @@ static void pmu_sbi_ctr_stop(struct perf_event *event, unsigned long flag) if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) && (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) - pmu_sbi_reset_scounteren((void *)event); + rvpmu_reset_scounteren((void *)event); if (sbi_pmu_snapshot_available()) flag |= SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT; @@ -765,7 +767,7 @@ static void pmu_sbi_ctr_stop(struct perf_event *event, unsigned long flag) } } -static int pmu_sbi_find_num_ctrs(void) +static int rvpmu_sbi_find_num_ctrs(void) { struct sbiret ret; @@ -776,7 +778,7 @@ static int pmu_sbi_find_num_ctrs(void) return sbi_err_map_linux_errno(ret.error); } -static int pmu_sbi_get_ctrinfo(int nctr, unsigned long *mask) +static int rvpmu_sbi_get_ctrinfo(int nctr, unsigned long *mask) { struct sbiret ret; int i, num_hw_ctr = 0, num_fw_ctr = 0; @@ -807,7 +809,7 @@ static int pmu_sbi_get_ctrinfo(int nctr, unsigned long *mask) return 0; } -static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu) +static inline void rvpmu_sbi_stop_all(struct riscv_pmu *pmu) { /* * No need to check the error because we are disabling all the counters @@ -817,7 +819,7 @@ static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu) 0, pmu->cmask, SBI_PMU_STOP_FLAG_RESET, 0, 0, 0); } -static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu) +static inline void rvpmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu) { struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events); struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr; @@ -861,8 +863,8 @@ static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu) * while the overflowed counters need to be started with updated initialization * value. */ -static inline void pmu_sbi_start_ovf_ctrs_sbi(struct cpu_hw_events *cpu_hw_evt, - u64 ctr_ovf_mask) +static inline void rvpmu_sbi_start_ovf_ctrs_sbi(struct cpu_hw_events *cpu_hw_evt, + u64 ctr_ovf_mask) { int idx = 0, i; struct perf_event *event; @@ -900,8 +902,8 @@ static inline void pmu_sbi_start_ovf_ctrs_sbi(struct cpu_hw_events *cpu_hw_evt, } } -static inline void pmu_sbi_start_ovf_ctrs_snapshot(struct cpu_hw_events *cpu_hw_evt, - u64 ctr_ovf_mask) +static inline void rvpmu_sbi_start_ovf_ctrs_snapshot(struct cpu_hw_events *cpu_hw_evt, + u64 ctr_ovf_mask) { int i, idx = 0; struct perf_event *event; @@ -935,18 +937,18 @@ static inline void pmu_sbi_start_ovf_ctrs_snapshot(struct cpu_hw_events *cpu_hw_ } } -static void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, - u64 ctr_ovf_mask) +static void rvpmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, + u64 ctr_ovf_mask) { struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events); if (sbi_pmu_snapshot_available()) - pmu_sbi_start_ovf_ctrs_snapshot(cpu_hw_evt, ctr_ovf_mask); + rvpmu_sbi_start_ovf_ctrs_snapshot(cpu_hw_evt, ctr_ovf_mask); else - pmu_sbi_start_ovf_ctrs_sbi(cpu_hw_evt, ctr_ovf_mask); + rvpmu_sbi_start_ovf_ctrs_sbi(cpu_hw_evt, ctr_ovf_mask); } -static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev) +static irqreturn_t rvpmu_ovf_handler(int irq, void *dev) { struct perf_sample_data data; struct pt_regs *regs; @@ -978,7 +980,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev) } pmu = to_riscv_pmu(event->pmu); - pmu_sbi_stop_hw_ctrs(pmu); + rvpmu_sbi_stop_hw_ctrs(pmu); /* Overflow status register should only be read after counter are stopped */ if (sbi_pmu_snapshot_available()) @@ -1047,13 +1049,55 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev) hw_evt->state = 0; } - pmu_sbi_start_overflow_mask(pmu, overflowed_ctrs); + rvpmu_sbi_start_overflow_mask(pmu, overflowed_ctrs); perf_sample_event_took(sched_clock() - start_clock); return IRQ_HANDLED; } -static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) +static void rvpmu_ctr_start(struct perf_event *event, u64 ival) +{ + rvpmu_sbi_ctr_start(event, ival); + /* TODO: Counter delegation implementation */ +} + +static void rvpmu_ctr_stop(struct perf_event *event, unsigned long flag) +{ + rvpmu_sbi_ctr_stop(event, flag); + /* TODO: Counter delegation implementation */ +} + +static int rvpmu_find_num_ctrs(void) +{ + return rvpmu_sbi_find_num_ctrs(); + /* TODO: Counter delegation implementation */ +} + +static int rvpmu_get_ctrinfo(int nctr, unsigned long *mask) +{ + return rvpmu_sbi_get_ctrinfo(nctr, mask); + /* TODO: Counter delegation implementation */ +} + +static int rvpmu_event_map(struct perf_event *event, u64 *econfig) +{ + return rvpmu_sbi_event_map(event, econfig); + /* TODO: Counter delegation implementation */ +} + +static int rvpmu_ctr_get_idx(struct perf_event *event) +{ + return rvpmu_sbi_ctr_get_idx(event); + /* TODO: Counter delegation implementation */ +} + +static u64 rvpmu_ctr_read(struct perf_event *event) +{ + return rvpmu_sbi_ctr_read(event); + /* TODO: Counter delegation implementation */ +} + +static int rvpmu_starting_cpu(unsigned int cpu, struct hlist_node *node) { struct riscv_pmu *pmu = hlist_entry_safe(node, struct riscv_pmu, node); struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events); @@ -1068,7 +1112,7 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) csr_write(CSR_SCOUNTEREN, 0x2); /* Stop all the counters so that they can be enabled from perf */ - pmu_sbi_stop_all(pmu); + rvpmu_sbi_stop_all(pmu); if (riscv_pmu_use_irq) { cpu_hw_evt->irq = riscv_pmu_irq; @@ -1082,7 +1126,7 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) return 0; } -static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node) +static int rvpmu_dying_cpu(unsigned int cpu, struct hlist_node *node) { if (riscv_pmu_use_irq) { disable_percpu_irq(riscv_pmu_irq); @@ -1097,7 +1141,7 @@ static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node) return 0; } -static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pdev) +static int rvpmu_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pdev) { int ret; struct cpu_hw_events __percpu *hw_events = pmu->hw_events; @@ -1137,7 +1181,7 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde return -ENODEV; } - ret = request_percpu_irq(riscv_pmu_irq, pmu_sbi_ovf_handler, "riscv-pmu", hw_events); + ret = request_percpu_irq(riscv_pmu_irq, rvpmu_ovf_handler, "riscv-pmu", hw_events); if (ret) { pr_err("registering percpu irq failed [%d]\n", ret); return ret; @@ -1213,7 +1257,7 @@ static void riscv_pmu_destroy(struct riscv_pmu *pmu) cpuhp_state_remove_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node); } -static void pmu_sbi_event_init(struct perf_event *event) +static void rvpmu_event_init(struct perf_event *event) { /* * The permissions are set at event_init so that we do not depend @@ -1227,7 +1271,7 @@ static void pmu_sbi_event_init(struct perf_event *event) event->hw.flags |= PERF_EVENT_FLAG_LEGACY; } -static void pmu_sbi_event_mapped(struct perf_event *event, struct mm_struct *mm) +static void rvpmu_event_mapped(struct perf_event *event, struct mm_struct *mm) { if (event->hw.flags & PERF_EVENT_FLAG_NO_USER_ACCESS) return; @@ -1255,14 +1299,14 @@ static void pmu_sbi_event_mapped(struct perf_event *event, struct mm_struct *mm) * that it is possible to do so to avoid any race. * And we must notify all cpus here because threads that currently run * on other cpus will try to directly access the counter too without - * calling pmu_sbi_ctr_start. + * calling rvpmu_sbi_ctr_start. */ if (event->hw.flags & PERF_EVENT_FLAG_USER_ACCESS) on_each_cpu_mask(mm_cpumask(mm), - pmu_sbi_set_scounteren, (void *)event, 1); + rvpmu_set_scounteren, (void *)event, 1); } -static void pmu_sbi_event_unmapped(struct perf_event *event, struct mm_struct *mm) +static void rvpmu_event_unmapped(struct perf_event *event, struct mm_struct *mm) { if (event->hw.flags & PERF_EVENT_FLAG_NO_USER_ACCESS) return; @@ -1284,7 +1328,7 @@ static void pmu_sbi_event_unmapped(struct perf_event *event, struct mm_struct *m if (event->hw.flags & PERF_EVENT_FLAG_USER_ACCESS) on_each_cpu_mask(mm_cpumask(mm), - pmu_sbi_reset_scounteren, (void *)event, 1); + rvpmu_reset_scounteren, (void *)event, 1); } static void riscv_pmu_update_counter_access(void *info) @@ -1327,7 +1371,7 @@ static struct ctl_table sbi_pmu_sysctl_table[] = { }, }; -static int pmu_sbi_device_probe(struct platform_device *pdev) +static int rvpmu_device_probe(struct platform_device *pdev) { struct riscv_pmu *pmu = NULL; int ret = -ENODEV; @@ -1338,7 +1382,7 @@ static int pmu_sbi_device_probe(struct platform_device *pdev) if (!pmu) return -ENOMEM; - num_counters = pmu_sbi_find_num_ctrs(); + num_counters = rvpmu_find_num_ctrs(); if (num_counters < 0) { pr_err("SBI PMU extension doesn't provide any counters\n"); goto out_free; @@ -1351,10 +1395,10 @@ static int pmu_sbi_device_probe(struct platform_device *pdev) } /* cache all the information about counters now */ - if (pmu_sbi_get_ctrinfo(num_counters, &cmask)) + if (rvpmu_get_ctrinfo(num_counters, &cmask)) goto out_free; - ret = pmu_sbi_setup_irqs(pmu, pdev); + ret = rvpmu_setup_irqs(pmu, pdev); if (ret < 0) { pr_info("Perf sampling/filtering is not supported as sscof extension is not available\n"); pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; @@ -1364,17 +1408,17 @@ static int pmu_sbi_device_probe(struct platform_device *pdev) pmu->pmu.attr_groups = riscv_pmu_attr_groups; pmu->pmu.parent = &pdev->dev; pmu->cmask = cmask; - pmu->ctr_start = pmu_sbi_ctr_start; - pmu->ctr_stop = pmu_sbi_ctr_stop; - pmu->event_map = pmu_sbi_event_map; - pmu->ctr_get_idx = pmu_sbi_ctr_get_idx; - pmu->ctr_get_width = pmu_sbi_ctr_get_width; - pmu->ctr_clear_idx = pmu_sbi_ctr_clear_idx; - pmu->ctr_read = pmu_sbi_ctr_read; - pmu->event_init = pmu_sbi_event_init; - pmu->event_mapped = pmu_sbi_event_mapped; - pmu->event_unmapped = pmu_sbi_event_unmapped; - pmu->csr_index = pmu_sbi_csr_index; + pmu->ctr_start = rvpmu_ctr_start; + pmu->ctr_stop = rvpmu_ctr_stop; + pmu->event_map = rvpmu_event_map; + pmu->ctr_get_idx = rvpmu_ctr_get_idx; + pmu->ctr_get_width = rvpmu_ctr_get_width; + pmu->ctr_clear_idx = rvpmu_ctr_clear_idx; + pmu->ctr_read = rvpmu_ctr_read; + pmu->event_init = rvpmu_event_init; + pmu->event_mapped = rvpmu_event_mapped; + pmu->event_unmapped = rvpmu_event_unmapped; + pmu->csr_index = rvpmu_csr_index; ret = riscv_pm_pmu_register(pmu); if (ret) @@ -1430,14 +1474,14 @@ static int pmu_sbi_device_probe(struct platform_device *pdev) return ret; } -static struct platform_driver pmu_sbi_driver = { - .probe = pmu_sbi_device_probe, +static struct platform_driver rvpmu_driver = { + .probe = rvpmu_device_probe, .driver = { - .name = RISCV_PMU_SBI_PDEV_NAME, + .name = RISCV_PMU_PDEV_NAME, }, }; -static int __init pmu_sbi_devinit(void) +static int __init rvpmu_devinit(void) { int ret; struct platform_device *pdev; @@ -1452,20 +1496,20 @@ static int __init pmu_sbi_devinit(void) ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_RISCV_STARTING, "perf/riscv/pmu:starting", - pmu_sbi_starting_cpu, pmu_sbi_dying_cpu); + rvpmu_starting_cpu, rvpmu_dying_cpu); if (ret) { pr_err("CPU hotplug notifier could not be registered: %d\n", ret); return ret; } - ret = platform_driver_register(&pmu_sbi_driver); + ret = platform_driver_register(&rvpmu_driver); if (ret) return ret; - pdev = platform_device_register_simple(RISCV_PMU_SBI_PDEV_NAME, -1, NULL, 0); + pdev = platform_device_register_simple(RISCV_PMU_PDEV_NAME, -1, NULL, 0); if (IS_ERR(pdev)) { - platform_driver_unregister(&pmu_sbi_driver); + platform_driver_unregister(&rvpmu_driver); return PTR_ERR(pdev); } @@ -1474,4 +1518,4 @@ static int __init pmu_sbi_devinit(void) return ret; } -device_initcall(pmu_sbi_devinit) +device_initcall(rvpmu_devinit) diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index 701974639ff2..525acd6d96d0 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -13,7 +13,7 @@ #include #include -#ifdef CONFIG_RISCV_PMU +#ifdef CONFIG_RISCV_PMU_COMMON /* * The RISCV_MAX_COUNTERS parameter should be specified. @@ -21,7 +21,7 @@ #define RISCV_MAX_COUNTERS 64 #define RISCV_OP_UNSUPP (-EOPNOTSUPP) -#define RISCV_PMU_SBI_PDEV_NAME "riscv-pmu-sbi" +#define RISCV_PMU_PDEV_NAME "riscv-pmu" #define RISCV_PMU_LEGACY_PDEV_NAME "riscv-pmu-legacy" #define RISCV_PMU_STOP_FLAG_RESET 1 @@ -87,10 +87,10 @@ void riscv_pmu_legacy_skip_init(void); static inline void riscv_pmu_legacy_skip_init(void) {}; #endif struct riscv_pmu *riscv_pmu_alloc(void); -#ifdef CONFIG_RISCV_PMU_SBI +#ifdef CONFIG_RISCV_PMU int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr); #endif -#endif /* CONFIG_RISCV_PMU */ +#endif /* CONFIG_RISCV_PMU_COMMON */ #endif /* _RISCV_PMU_H */ From patchwork Thu Feb 6 07:23:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13962509 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 31AAAC0219B for ; Thu, 6 Feb 2025 07:38:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=CHmvhuJrw2wmPusjLEvnhA/hf2rG0cDO8Rbf6kwP5KA=; b=LLVUNUWgnNaONK OqACkZFnV9NqoBvSiORg+YakSa4nTqsL+cH8QVHVvVtGkQvgygRC9T6nGS0KiFa8KtwIQY/4LLsnx m7sgGQ6wVRliKYBWQzFL5Tv4XTPrxOOwSrMmetb9P5cNjrUnoT7qhJb+zqOreSSO0JW1PjB0tSjRB 04+GqUskIaf3QQktewOVWNLMjfRieGdhKnrzXSBgk3mjv6z63rVZxVNtAbzV5AZ/FpUbuYCw9CQIJ kHa+y3TPwmthv8HMWl1ZMW7YHVqBuNlz9qT3lPf7F3Vc7EDEUetn9f3p8C67a1his6cRjyp4+gEpT l22R0WAQmRsW4A3SoOdA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfwT6-00000005cDm-3v8I; Thu, 06 Feb 2025 07:38:36 +0000 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfwEZ-00000005YBH-2a5O for linux-riscv@lists.infradead.org; Thu, 06 Feb 2025 07:23:37 +0000 Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-2ee9a780de4so788281a91.3 for ; Wed, 05 Feb 2025 23:23:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1738826615; x=1739431415; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=jEmj8DVMBSDONaOAMSnkme1snOH35jPSjqon+nV/oLM=; b=2ijaDfv/WF0sQCKf9sSVPFsXc+aisRp7bdO4hkP1UK77c540yVF4/mCh5v3+4uEfJq jPov6JROy1Tvu+mDgJlDRRgHRdIjACNTXwJqS57Q1f08xIv7RyWXdWdFRPKBoI8s5qAw MHbxW1PRsoin2tvQIJjeOWgB0oTq5vfsTfehJJpTg8fLMmBoIbHb1OS5W8eaVxjJ7gdF luzL/CQzoxNntGnL+S8/2yNz4z+/ihQXNdtdymd/LWGGJGtH+G54VyTNl+Si9Fskjo6/ 6k6qGOJeNVCVaMEzkyI5FV3W/RFm+HK9EWFjbG7DGcfXs3TGe9B2kNPuV04RJbHUdVvA Rokw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738826615; x=1739431415; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jEmj8DVMBSDONaOAMSnkme1snOH35jPSjqon+nV/oLM=; b=QxntpbL5lN5EzCfZ+XQeLmL6dvjJ9i0myj9PBZ/nJYCE2tGrWxDxIRI6xgO8jRny9Y JgpYI+Qgzrf/ruhk+hIMnLyHqmwSFkBT8R/QGJ5yQZUUDlM24UwElyU2bOmzKjGXtFu0 rhaDd+ID3K9hJjlTquHruHZmFxSQMKF5lVCxNQD6j9o7kjY5XADa5UDI4vIfHuoZUt2F J3Cud5kTxAVi+yINH96U0PBjNS2vOLm03whmQNga+BERRbDS5jmqk2oh1NygocJklvSO HI/SMsAbqJNQjDOrXwHPvxxyNnZZKX13+gPIkNXBuF+s5RksGsrKwtMT2Va7GfqoRDL0 aEDw== X-Gm-Message-State: AOJu0YxPS7teXXqHIXzGXgxC28KWKg5d1PfHaXCe1QIhXRBzSHSTr5k9 JMAfjT2ODIzIrNgy7tAp9yHSQux0ewxLngTbk2CdwmNib5IfPsWCgxJA+jAWiJ4= X-Gm-Gg: ASbGncvpyNV0IltT1SpSPB9B8B+iT3i3HhqmadqnYV+kFp/LaibpsDmpYGThx2Hkpo0 gGBLmPEIHj7kR0cpWhU5HJafRQ8sTvX6MBp68lc0bFAVaHJEQveT9zmRDskvQgfFYUyfh70dCKs fNTFOpI9gjG5DDcdE2GfzZEh4kfx2/Ya5Sma/crtafFPnks6vO7xsmtWgf5a71D8hU4mpJ0FNAi 8+8cZGt7bW0BosTnMa4vLpsgF8m+IUIZh/jzMLfZdiYVeJhSKQIrzkPESjJGavrzx4Yn9bl4mk3 pvCYqwIDWdFHOWme5r2gTSFslir1 X-Google-Smtp-Source: AGHT+IGj8B7K0A3SeZQU+rxnVnMyUu5PFTc58BZIXIzUWOA7tBSdLa1HA/cppXNHnn2s7VfTdqOU4Q== X-Received: by 2002:a17:90b:1d44:b0:2ee:cdea:ad91 with SMTP id 98e67ed59e1d1-2f9e0785075mr9990255a91.15.1738826615039; Wed, 05 Feb 2025 23:23:35 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a72292sm630883a91.27.2025.02.05.23.23.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 23:23:34 -0800 (PST) From: Atish Patra Date: Wed, 05 Feb 2025 23:23:17 -0800 Subject: [PATCH v4 12/21] RISC-V: perf: Modify the counter discovery mechanism MIME-Version: 1.0 Message-Id: <20250205-counter_delegation-v4-12-835cfa88e3b1@rivosinc.com> References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> In-Reply-To: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_232335_705062_DB326043 X-CRM114-Status: GOOD ( 26.64 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org If both counter delegation and SBI PMU is present, the counter delegation will be used for hardware pmu counters while the SBI PMU will be used for firmware counters. Thus, the driver has to probe the counters info via SBI PMU to distinguish the firmware counters. The hybrid scheme also requires improvements of the informational logging messages to indicate the user about underlying interface used for each use case. Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_dev.c | 118 ++++++++++++++++++++++++++++++++----------- 1 file changed, 88 insertions(+), 30 deletions(-) diff --git a/drivers/perf/riscv_pmu_dev.c b/drivers/perf/riscv_pmu_dev.c index 6b43d844eaea..5ddf4924c5b3 100644 --- a/drivers/perf/riscv_pmu_dev.c +++ b/drivers/perf/riscv_pmu_dev.c @@ -66,6 +66,10 @@ static bool sbi_v2_available; static DEFINE_STATIC_KEY_FALSE(sbi_pmu_snapshot_available); #define sbi_pmu_snapshot_available() \ static_branch_unlikely(&sbi_pmu_snapshot_available) +static DEFINE_STATIC_KEY_FALSE(riscv_pmu_sbi_available); +static DEFINE_STATIC_KEY_FALSE(riscv_pmu_cdeleg_available); +static bool cdeleg_available; +static bool sbi_available; static struct attribute *riscv_arch_formats_attr[] = { &format_attr_event.attr, @@ -88,7 +92,8 @@ static int sysctl_perf_user_access __read_mostly = SYSCTL_USER_ACCESS; /* * This structure is SBI specific but counter delegation also require counter - * width, csr mapping. Reuse it for now. + * width, csr mapping. Reuse it for now we can have firmware counters for + * platfroms with counter delegation support. * RISC-V doesn't have heterogeneous harts yet. This need to be part of * per_cpu in case of harts with different pmu counters */ @@ -100,6 +105,8 @@ static unsigned int riscv_pmu_irq; /* Cache the available counters in a bitmask */ static unsigned long cmask; +/* Cache the available firmware counters in another bitmask */ +static unsigned long firmware_cmask; struct sbi_pmu_event_data { union { @@ -778,35 +785,49 @@ static int rvpmu_sbi_find_num_ctrs(void) return sbi_err_map_linux_errno(ret.error); } -static int rvpmu_sbi_get_ctrinfo(int nctr, unsigned long *mask) +static int rvpmu_deleg_find_ctrs(void) +{ + /* TODO */ + return -1; +} + +static int rvpmu_sbi_get_ctrinfo(int nsbi_ctr, int ndeleg_ctr) { struct sbiret ret; - int i, num_hw_ctr = 0, num_fw_ctr = 0; + int i, num_hw_ctr = 0, num_fw_ctr = 0, num_ctr = 0; union sbi_pmu_ctr_info cinfo; - pmu_ctr_list = kcalloc(nctr, sizeof(*pmu_ctr_list), GFP_KERNEL); - if (!pmu_ctr_list) - return -ENOMEM; - - for (i = 0; i < nctr; i++) { + for (i = 0; i < nsbi_ctr; i++) { ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_GET_INFO, i, 0, 0, 0, 0, 0); if (ret.error) /* The logical counter ids are not expected to be contiguous */ continue; - *mask |= BIT(i); - cinfo.value = ret.value; if (cinfo.type == SBI_PMU_CTR_TYPE_FW) num_fw_ctr++; - else + + if (!cdeleg_available) { num_hw_ctr++; - pmu_ctr_list[i].value = cinfo.value; + cmask |= BIT(i); + pmu_ctr_list[i].value = cinfo.value; + } else if (cinfo.type == SBI_PMU_CTR_TYPE_FW) { + /* Track firmware counters in a different mask */ + firmware_cmask |= BIT(i); + pmu_ctr_list[i].value = cinfo.value; + } + } - pr_info("%d firmware and %d hardware counters\n", num_fw_ctr, num_hw_ctr); + if (cdeleg_available) { + pr_info("%d firmware and %d hardware counters\n", num_fw_ctr, ndeleg_ctr); + num_ctr = num_fw_ctr + ndeleg_ctr; + } else { + pr_info("%d firmware and %d hardware counters\n", num_fw_ctr, num_hw_ctr); + num_ctr = nsbi_ctr; + } - return 0; + return num_ctr; } static inline void rvpmu_sbi_stop_all(struct riscv_pmu *pmu) @@ -1067,16 +1088,33 @@ static void rvpmu_ctr_stop(struct perf_event *event, unsigned long flag) /* TODO: Counter delegation implementation */ } -static int rvpmu_find_num_ctrs(void) +static int rvpmu_find_ctrs(void) { - return rvpmu_sbi_find_num_ctrs(); - /* TODO: Counter delegation implementation */ -} + int num_sbi_counters = 0, num_deleg_counters = 0, num_counters = 0; -static int rvpmu_get_ctrinfo(int nctr, unsigned long *mask) -{ - return rvpmu_sbi_get_ctrinfo(nctr, mask); - /* TODO: Counter delegation implementation */ + /* + * We don't know how many firmware counters available. Just allocate + * for maximum counters driver can support. The default is 64 anyways. + */ + pmu_ctr_list = kcalloc(RISCV_MAX_COUNTERS, sizeof(*pmu_ctr_list), + GFP_KERNEL); + if (!pmu_ctr_list) + return -ENOMEM; + + if (cdeleg_available) + num_deleg_counters = rvpmu_deleg_find_ctrs(); + + /* This is required for firmware counters even if the above is true */ + if (sbi_available) + num_sbi_counters = rvpmu_sbi_find_num_ctrs(); + + if (num_sbi_counters >= RISCV_MAX_COUNTERS || num_deleg_counters >= RISCV_MAX_COUNTERS) + return -ENOSPC; + + /* cache all the information about counters now */ + num_counters = rvpmu_sbi_get_ctrinfo(num_sbi_counters, num_deleg_counters); + + return num_counters; } static int rvpmu_event_map(struct perf_event *event, u64 *econfig) @@ -1377,12 +1415,21 @@ static int rvpmu_device_probe(struct platform_device *pdev) int ret = -ENODEV; int num_counters; - pr_info("SBI PMU extension is available\n"); + if (cdeleg_available) { + pr_info("hpmcounters will use the counter delegation ISA extension\n"); + if (sbi_available) + pr_info("Firmware counters will be use SBI PMU extension\n"); + else + pr_info("Firmware counters will be not available as SBI PMU extension is not present\n"); + } else if (sbi_available) { + pr_info("Both hpmcounters and firmware counters will use SBI PMU extension\n"); + } + pmu = riscv_pmu_alloc(); if (!pmu) return -ENOMEM; - num_counters = rvpmu_find_num_ctrs(); + num_counters = rvpmu_find_ctrs(); if (num_counters < 0) { pr_err("SBI PMU extension doesn't provide any counters\n"); goto out_free; @@ -1394,9 +1441,6 @@ static int rvpmu_device_probe(struct platform_device *pdev) pr_info("SBI returned more than maximum number of counters. Limiting the number of counters to %d\n", num_counters); } - /* cache all the information about counters now */ - if (rvpmu_get_ctrinfo(num_counters, &cmask)) - goto out_free; ret = rvpmu_setup_irqs(pmu, pdev); if (ret < 0) { @@ -1486,13 +1530,27 @@ static int __init rvpmu_devinit(void) int ret; struct platform_device *pdev; - if (sbi_spec_version < sbi_mk_version(0, 3) || - !sbi_probe_extension(SBI_EXT_PMU)) { - return 0; + if (sbi_spec_version >= sbi_mk_version(0, 3) && + sbi_probe_extension(SBI_EXT_PMU)) { + static_branch_enable(&riscv_pmu_sbi_available); + sbi_available = true; } if (sbi_spec_version >= sbi_mk_version(2, 0)) sbi_v2_available = true; + /* + * We need all three extensions to be present to access the counters + * in S-mode via Supervisor Counter delegation. + */ + if (riscv_isa_extension_available(NULL, SSCCFG) && + riscv_isa_extension_available(NULL, SMCDELEG) && + riscv_isa_extension_available(NULL, SSCSRIND)) { + static_branch_enable(&riscv_pmu_cdeleg_available); + cdeleg_available = true; + } + + if (!(sbi_available || cdeleg_available)) + return 0; ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_RISCV_STARTING, "perf/riscv/pmu:starting", From patchwork Thu Feb 6 07:23:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13962528 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4EDB6C02196 for ; Thu, 6 Feb 2025 07:40:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=FXwEiAOfYdSejj+LBwbZdjeEg+uzhG5JHhnNuTvIAsU=; b=psubuppS0I6e0T HPbOOhNSLcQVbdkZoKrglzlzAnU8/Qss2C1IM8b0EHvbw09aiqcJ0WVOwMShk47nl+rEkM32S8THT 1NShqQW1mjrXOeCj8e/9YfmHxWl/IncAPJxcYu8M9umvDgxhjN4Y0odIEKJPPURq769LqmIycPYPE qIizy531NV+KdUx1LVRlYUmKq4RkS7kW4lsLz1VqtHKS+gfZ3O+Sic5H9tWZoEm600++Zcq81zNdh HPWpfD4uBPeva2i2zvRGDmgmusqZ7P1KIJiSf0h8zBam20mi3Stlarckb+yrnvlJEDsGOfwyLIpxJ E91LPhxpPOg16+ic+iqQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfwUZ-00000005cUT-4Bdy; Thu, 06 Feb 2025 07:40:08 +0000 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfwEb-00000005YCr-0Mtp for linux-riscv@lists.infradead.org; Thu, 06 Feb 2025 07:23:39 +0000 Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-2f441791e40so770767a91.3 for ; Wed, 05 Feb 2025 23:23:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1738826616; x=1739431416; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=LgFNQleQh/rKyQJtr5gK6tFb1jww+ogex5C6sOF/Bv0=; b=nfwTultbl9Fw6Qpp+/I4SQ886j8tT+lzG2z2E+3Bzg5yVQdxeBy8Y0UvUzMBEhnv/h qri5x+EcKE8X6YDsLyh1q6enVSA6PQLbByAe6FhGW+gdWNrS8+lX5dssbpEh6D+13wFW vz2mUlBaNrI5S7fiVxaasoWVSbJtI5Qi2+ypBEQAMUuuQ9X4F7o1TMIZofKzJb7dFPjh ERDxceKjE8YnVjclNXWRHjWP7NFBWuc9h1S5W1kBbkIlaTelBvpgiee6Pyvd76IMMps/ DVXTixEde6JfWl67lJsCCnMOT5NAcTZ4hijF/wxtl9rT/2dfgQPE1T78xXAlADSykDeU +GBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738826616; x=1739431416; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LgFNQleQh/rKyQJtr5gK6tFb1jww+ogex5C6sOF/Bv0=; b=rH+GgiQ+D+LHEDh64iLHkomN3GPFbGeWQQRzgdCM7ORz9IFPiEkE+iTyVX3kNIkKe7 YgdQPJ3S4YDY1/uWUb0n27s44s4fjSE8Ff+DloOMvEqVbqWOsvuTHgiQkxpPVc3wy1lB jZdfFLGxBWjDXOz+VTj7M3CVyguPEnmB92jLt7VTt6xo3Jf+hKVei9AMet5RdvbAqyvR BnG/d43/CzU9KMmhiwMU/kSIGzdLCS9Obs7LZk7+fCcD5dX7Di6QZ9t4ASMnwMvXpQn0 +09/k9rbIs4ioNZ3aRVKDpy9C6+9wb0SVj/JEu1dyCnJvkVoeqkbyoxoXn/HuLGI5EDF UjXg== X-Gm-Message-State: AOJu0YwYqh+6YMfpk409GbyjQoDJUHXtAEq9d/WqUq7sV50DAx/1Pxz3 D3HD/36RVVJfIogX+xaESERw3Q59G/ZvK3T9HwlXypcqngJ4PP+cWIGrPo9ktuM= X-Gm-Gg: ASbGncv3B3i5TlCBDmF26H8ty0lMd/QtuaVArWj6O9mLjfe6PWfC4N+2yAMqvItvzjn 2HgELus7G9limcPMSuwGY/sPcOV72T559DiTrot6TrYHKs/unZrdrlHcGBvEHKHhJsc5EnYm0f5 +J4ml5fvAA9X35oS1In79cLzSnw3oQraLfJ9bJ8HRL+SA+njl3jOgkby9zlB5bQ/klCJrCxiDGQ MhJSraW/ji6RXDyZUmEnESgnPXOPSBBaJabJ3uqFz/Bs6AZ0Hcp0ZisaepgJgQfB5vGwUKN9Hcl mYo+aHJF43PmdMQo+r7JJeDLfp5Y X-Google-Smtp-Source: AGHT+IHC0uM6MKO6WJlQMIOHrq37adlEkVa8Q/0ld10wE8fTHq/Aau2QSOpqmWEdj7z9+naSpofcKQ== X-Received: by 2002:a17:90b:2f85:b0:2ee:ab29:1a65 with SMTP id 98e67ed59e1d1-2f9e0753e18mr9830024a91.4.1738826616579; Wed, 05 Feb 2025 23:23:36 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a72292sm630883a91.27.2025.02.05.23.23.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 23:23:36 -0800 (PST) From: Atish Patra Date: Wed, 05 Feb 2025 23:23:18 -0800 Subject: [PATCH v4 13/21] RISC-V: perf: Add a mechanism to defined legacy event encoding MIME-Version: 1.0 Message-Id: <20250205-counter_delegation-v4-13-835cfa88e3b1@rivosinc.com> References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> In-Reply-To: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_232337_169936_14386E8C X-CRM114-Status: GOOD ( 15.87 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org RISC-V ISA doesn't define any standard event encodings or specify any event to counter mapping. Thus, event encoding information and corresponding counter mapping fot those events needs to be provided in the driver for each vendor. Add a framework to support that. The individual platform events will be added later. Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_dev.c | 51 ++++++++++++++++++++++++++++++++++++++++++ include/linux/perf/riscv_pmu.h | 13 +++++++++++ 2 files changed, 64 insertions(+) diff --git a/drivers/perf/riscv_pmu_dev.c b/drivers/perf/riscv_pmu_dev.c index 5ddf4924c5b3..2eb58b248c88 100644 --- a/drivers/perf/riscv_pmu_dev.c +++ b/drivers/perf/riscv_pmu_dev.c @@ -307,6 +307,56 @@ static struct sbi_pmu_event_data pmu_cache_event_sbi_map[PERF_COUNT_HW_CACHE_MAX }, }; +/* + * Vendor specific PMU events. + */ +struct riscv_pmu_event { + u64 event_id; + u32 counter_mask; +}; + +struct riscv_vendor_pmu_events { + unsigned long vendorid; + unsigned long archid; + unsigned long implid; + const struct riscv_pmu_event *hw_event_map; + const struct riscv_pmu_event (*cache_event_map)[PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX]; +}; + +#define RISCV_VENDOR_PMU_EVENTS(_vendorid, _archid, _implid, _hw_event_map, _cache_event_map) \ + { .vendorid = _vendorid, .archid = _archid, .implid = _implid, \ + .hw_event_map = _hw_event_map, .cache_event_map = _cache_event_map }, + +static struct riscv_vendor_pmu_events pmu_vendor_events_table[] = { +}; + +const struct riscv_pmu_event *current_pmu_hw_event_map; +const struct riscv_pmu_event (*current_pmu_cache_event_map)[PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX]; + +static void rvpmu_vendor_register_events(void) +{ + int cpu = raw_smp_processor_id(); + unsigned long vendor_id = riscv_cached_mvendorid(cpu); + unsigned long impl_id = riscv_cached_mimpid(cpu); + unsigned long arch_id = riscv_cached_marchid(cpu); + + for (int i = 0; i < ARRAY_SIZE(pmu_vendor_events_table); i++) { + if (pmu_vendor_events_table[i].vendorid == vendor_id && + pmu_vendor_events_table[i].implid == impl_id && + pmu_vendor_events_table[i].archid == arch_id) { + current_pmu_hw_event_map = pmu_vendor_events_table[i].hw_event_map; + current_pmu_cache_event_map = pmu_vendor_events_table[i].cache_event_map; + break; + } + } + + if (!current_pmu_hw_event_map || !current_pmu_cache_event_map) { + pr_info("No default PMU events found\n"); + } +} + static void rvpmu_sbi_check_event(struct sbi_pmu_event_data *edata) { struct sbiret ret; @@ -1547,6 +1597,7 @@ static int __init rvpmu_devinit(void) riscv_isa_extension_available(NULL, SSCSRIND)) { static_branch_enable(&riscv_pmu_cdeleg_available); cdeleg_available = true; + rvpmu_vendor_register_events(); } if (!(sbi_available || cdeleg_available)) diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index 525acd6d96d0..a3e1fdd5084a 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -28,6 +28,19 @@ #define RISCV_PMU_CONFIG1_GUEST_EVENTS 0x1 +#define HW_OP_UNSUPPORTED 0xFFFF +#define CACHE_OP_UNSUPPORTED 0xFFFF + +#define PERF_MAP_ALL_UNSUPPORTED \ + [0 ... PERF_COUNT_HW_MAX - 1] = {HW_OP_UNSUPPORTED, 0x0} + +#define PERF_CACHE_MAP_ALL_UNSUPPORTED \ +[0 ... C(MAX) - 1] = { \ + [0 ... C(OP_MAX) - 1] = { \ + [0 ... C(RESULT_MAX) - 1] = {CACHE_OP_UNSUPPORTED, 0x0} \ + }, \ +} + struct cpu_hw_events { /* currently enabled events */ int n_events; From patchwork Thu Feb 6 07:23:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13962531 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D453FC0219B for ; Thu, 6 Feb 2025 07:42:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=kHgQGRQvkkcm3dBLfvZayIcFg3ZLdHTxRjRjdcfinpo=; b=YyZLihsWDujr6H 11TNozEQYZ45Hc3SQSjTek5AiOMhWMq0PrBVam3FtS2GQRYT+a8BCV4E41GGNKGMqq2vV8l4q5pda 9ooaY380RbGqMj1L/1/BH7CN3GKr25o4KVusKPbdpAdyHZWWWPKD7xLcvYEPdDy6Q3Yw+J7aBF9DD pH25ruqfelF1gTMzZxnOHmG0KBEJrHvFRNFSFaSc90bxOTCFYMQrnkMzKVLDcLKANiqdP74suIXZ1 fOkBjlo/vYK9nb4e6u416n1uF8eaupPC9gO3WVHRXT0HMG7K2GjawkV1qSGH+uW+QC24qa/6/aYd+ ot6cdiI1pkzoAAFRR95g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfwXH-00000005dF8-2B04; Thu, 06 Feb 2025 07:42:55 +0000 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfwEd-00000005YF4-1SRl for linux-riscv@lists.infradead.org; Thu, 06 Feb 2025 07:23:43 +0000 Received: by mail-pj1-x1033.google.com with SMTP id 98e67ed59e1d1-2f9b91dff71so790485a91.2 for ; Wed, 05 Feb 2025 23:23:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1738826618; x=1739431418; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=8YMJZgVY1otqFkvY1S6X1nasUdQkp1/Rdt1qQGVI5D4=; b=dqS4W2EVudOY8sLtkD3WyVY9mDf2g9VINAW1iHSHVia92pYKlzrp8W1kg66VqserfT BszQPZB4JXa+/ed4LIX/aHd9xOHy74qAyJfPb2Qm771MxtjPvn2jrFxt5XGgSHIFRs6U kUCYES69dlHO1B6d15ZumcIrYixW4UqzAwpWtQTqqA3YCr/OBiqpi9fRfnlDeElxMKQB hVmSlUd/LFj01zi7FARsw3AdB3jdY7HgYAyUFLh8Ekhgk2oJq0Jn6ebw3cPb+L2KK63C JVvK2ZgWFiqIJEwoQqkA+P+ZwgxZ6vlWCFMFMY4dCpjEz91VApsNaYtlKicbxUE/Xj1o O3FA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738826618; x=1739431418; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8YMJZgVY1otqFkvY1S6X1nasUdQkp1/Rdt1qQGVI5D4=; b=cJKozupErkT15RE81xfPQMKlWO+hZJ+39qDOPYl6+M0JKSgWC1L1jUTIa9IGOyM7cs xAe/3sdnnwz70K9kFC0Ih36uB/TqIK/Eq4jvZAvpv4SFtH7v4Au3kbbfQwr4YPBgNZCp QuTUZ4PYhH7XmhgYPmmbHoQEKh+oaUys2qKzU1xWo88wrK+NLIFbLxRMZ7MPPJPqWh8j UOj4WMrSUhFGZTEzz0slP/GgF6EgLj+PDbR7ulOfAYJglHNaRhsv89hW4x4FNz+Zg3bW U5F26HPIx3n/ZQqNlKcV2leFKcIaQ1sUT7qoY0i4u8adkJ6M2h22SILBC4faXIE+FApe OlNw== X-Gm-Message-State: AOJu0Yx18ketdo6zDCPCQ6otkTyEZF3P7nFcJ8pOQaEExxSGeZy3C5Se KleCa2qavCDzz9I4aDVdIuh1nkUq6sHlvSH9YXdXNRU/UFhMjDiz9N3xvED99C0= X-Gm-Gg: ASbGncvX6hpsnOl0RjH1ebMUwM34/pzL3rPZPYNn1c0sExizXmGj5BN0bJcVw+7B2Fz GYh7QR0Ew0wA2Slz3+LWpyHZ4WsvyjGjqN2AebuOdnGoegZBmXhDVLZ0286nbNEz0u8wcUnPqxS 7Y7KVMd/TBRpoXt9HmFRqi3bObkSDp1q1tPQ0kIM0i/7NuJLER/gDD6GKsWm+4sXbwpBmK6Jo5H egKovTlqO0fntrHH0lZ2nSbMcHKWSBQX/pcSfChmddep9hRLPIVV2E0i2spbsIIhVJBXZZT875U +PzgmvK/bRKyRxg77WKx3Ld3Js9v X-Google-Smtp-Source: AGHT+IGwieIUw3OD2xuFePKXWdPQZa0PbeVamSKcJqy8fo6Kk++WSJlvSU1k3/yLYbkFJ7iAJww3kA== X-Received: by 2002:a17:90b:3810:b0:2ee:5691:774e with SMTP id 98e67ed59e1d1-2f9e074fa58mr9546573a91.2.1738826618250; Wed, 05 Feb 2025 23:23:38 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a72292sm630883a91.27.2025.02.05.23.23.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 23:23:37 -0800 (PST) From: Atish Patra Date: Wed, 05 Feb 2025 23:23:19 -0800 Subject: [PATCH v4 14/21] RISC-V: perf: Implement supervisor counter delegation support MIME-Version: 1.0 Message-Id: <20250205-counter_delegation-v4-14-835cfa88e3b1@rivosinc.com> References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> In-Reply-To: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_232339_405727_76B15631 X-CRM114-Status: GOOD ( 30.80 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org There are few new RISC-V ISA exensions (ssccfg, sscsrind, smcntrpmf) which allows the hpmcounter/hpmevents to be programmed directly from S-mode. The implementation detects the ISA extension at runtime and uses them if available instead of SBI PMU extension. SBI PMU extension will still be used for firmware counters if the user requests it. The current linux driver relies on event encoding defined by SBI PMU specification for standard perf events. However, there are no standard event encoding available in the ISA. In the future, we may want to decouple the counter delegation and SBI PMU completely. In that case, counter delegation supported platforms must rely on the event encoding defined in the perf json file or in the pmu driver. For firmware events, it will continue to use the SBI PMU encoding as one can not support firmware event without SBI PMU. Signed-off-by: Atish Patra --- arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/sbi.h | 2 +- arch/riscv/kvm/vcpu_pmu.c | 2 +- drivers/perf/riscv_pmu_dev.c | 564 +++++++++++++++++++++++++++++++++-------- include/linux/perf/riscv_pmu.h | 3 + 5 files changed, 468 insertions(+), 104 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 42b7f4f7ec0f..a06d5fec6e6d 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -249,6 +249,7 @@ #endif #define SISELECT_SSCCFG_BASE 0x40 +#define HPMEVENT_MASK GENMASK_ULL(63, 56) /* mseccfg bits */ #define MSECCFG_PMM ENVCFG_PMM diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 6c82318065cf..1107795cc3cf 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -158,7 +158,7 @@ struct riscv_pmu_snapshot_data { u64 reserved[447]; }; -#define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0) +#define RISCV_PMU_SBI_RAW_EVENT_MASK GENMASK_ULL(47, 0) #define RISCV_PMU_RAW_EVENT_IDX 0x20000 #define RISCV_PLAT_FW_EVENT 0xFFFF diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index 2707a51b082c..0f4ecb6010d6 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -126,7 +126,7 @@ static u64 kvm_pmu_get_perf_event_config(unsigned long eidx, uint64_t evt_data) config = kvm_pmu_get_perf_event_cache_config(ecode); break; case SBI_PMU_EVENT_TYPE_RAW: - config = evt_data & RISCV_PMU_RAW_EVENT_MASK; + config = evt_data & RISCV_PMU_SBI_RAW_EVENT_MASK; break; case SBI_PMU_EVENT_TYPE_FW: if (ecode < SBI_PMU_FW_MAX) diff --git a/drivers/perf/riscv_pmu_dev.c b/drivers/perf/riscv_pmu_dev.c index 2eb58b248c88..5112049b491c 100644 --- a/drivers/perf/riscv_pmu_dev.c +++ b/drivers/perf/riscv_pmu_dev.c @@ -27,6 +27,8 @@ #include #include #include +#include +#include #define ALT_SBI_PMU_OVERFLOW(__ovl) \ asm volatile(ALTERNATIVE_2( \ @@ -59,31 +61,67 @@ asm volatile(ALTERNATIVE( \ #define PERF_EVENT_FLAG_USER_ACCESS BIT(SYSCTL_USER_ACCESS) #define PERF_EVENT_FLAG_LEGACY BIT(SYSCTL_LEGACY) -PMU_FORMAT_ATTR(event, "config:0-47"); +#define RVPMU_SBI_PMU_FORMAT_ATTR "config:0-47" +#define RVPMU_CDELEG_PMU_FORMAT_ATTR "config:0-55" + +static ssize_t __maybe_unused rvpmu_format_show(struct device *dev, struct device_attribute *attr, + char *buf); + +#define RVPMU_ATTR_ENTRY(_name, _func, _config) ( \ + &((struct dev_ext_attribute[]) { \ + { __ATTR(_name, 0444, _func, NULL), (void *)_config } \ + })[0].attr.attr) + +#define RVPMU_FORMAT_ATTR_ENTRY(_name, _config) \ + RVPMU_ATTR_ENTRY(_name, rvpmu_format_show, (char *)_config) + PMU_FORMAT_ATTR(firmware, "config:62-63"); static bool sbi_v2_available; static DEFINE_STATIC_KEY_FALSE(sbi_pmu_snapshot_available); #define sbi_pmu_snapshot_available() \ static_branch_unlikely(&sbi_pmu_snapshot_available) + static DEFINE_STATIC_KEY_FALSE(riscv_pmu_sbi_available); +#define riscv_pmu_sbi_available() \ + static_branch_likely(&riscv_pmu_sbi_available) + static DEFINE_STATIC_KEY_FALSE(riscv_pmu_cdeleg_available); +#define riscv_pmu_cdeleg_available() \ + static_branch_unlikely(&riscv_pmu_cdeleg_available) + static bool cdeleg_available; static bool sbi_available; -static struct attribute *riscv_arch_formats_attr[] = { - &format_attr_event.attr, +static struct attribute *riscv_sbi_pmu_formats_attr[] = { + RVPMU_FORMAT_ATTR_ENTRY(event, RVPMU_SBI_PMU_FORMAT_ATTR), + &format_attr_firmware.attr, + NULL, +}; + +static struct attribute_group riscv_sbi_pmu_format_group = { + .name = "format", + .attrs = riscv_sbi_pmu_formats_attr, +}; + +static const struct attribute_group *riscv_sbi_pmu_attr_groups[] = { + &riscv_sbi_pmu_format_group, + NULL, +}; + +static struct attribute *riscv_cdeleg_pmu_formats_attr[] = { + RVPMU_FORMAT_ATTR_ENTRY(event, RVPMU_CDELEG_PMU_FORMAT_ATTR), &format_attr_firmware.attr, NULL, }; -static struct attribute_group riscv_pmu_format_group = { +static struct attribute_group riscv_cdeleg_pmu_format_group = { .name = "format", - .attrs = riscv_arch_formats_attr, + .attrs = riscv_cdeleg_pmu_formats_attr, }; -static const struct attribute_group *riscv_pmu_attr_groups[] = { - &riscv_pmu_format_group, +static const struct attribute_group *riscv_cdeleg_pmu_attr_groups[] = { + &riscv_cdeleg_pmu_format_group, NULL, }; @@ -385,6 +423,14 @@ static void rvpmu_sbi_check_std_events(struct work_struct *work) static DECLARE_WORK(check_std_events_work, rvpmu_sbi_check_std_events); +static ssize_t rvpmu_format_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dev_ext_attribute *eattr = container_of(attr, + struct dev_ext_attribute, attr); + return sysfs_emit(buf, "%s\n", (char *)eattr->var); +} + static int rvpmu_ctr_get_width(int idx) { return pmu_ctr_list[idx].width; @@ -437,6 +483,38 @@ static uint8_t rvpmu_csr_index(struct perf_event *event) return pmu_ctr_list[event->hw.idx].csr - CSR_CYCLE; } +static uint64_t get_deleg_priv_filter_bits(struct perf_event *event) +{ + u64 priv_filter_bits = 0; + bool guest_events = false; + + if (event->attr.config1 & RISCV_PMU_CONFIG1_GUEST_EVENTS) + guest_events = true; + if (event->attr.exclude_kernel) + priv_filter_bits |= guest_events ? HPMEVENT_VSINH : HPMEVENT_SINH; + if (event->attr.exclude_user) + priv_filter_bits |= guest_events ? HPMEVENT_VUINH : HPMEVENT_UINH; + if (guest_events && event->attr.exclude_hv) + priv_filter_bits |= HPMEVENT_SINH; + if (event->attr.exclude_host) + priv_filter_bits |= HPMEVENT_UINH | HPMEVENT_SINH; + if (event->attr.exclude_guest) + priv_filter_bits |= HPMEVENT_VSINH | HPMEVENT_VUINH; + + return priv_filter_bits; +} + +static bool pmu_sbi_is_fw_event(struct perf_event *event) +{ + u32 type = event->attr.type; + u64 config = event->attr.config; + + if (type == PERF_TYPE_RAW && ((config >> 63) == 1)) + return true; + else + return false; +} + static unsigned long rvpmu_sbi_get_filter_flags(struct perf_event *event) { unsigned long cflags = 0; @@ -465,7 +543,8 @@ static int rvpmu_sbi_ctr_get_idx(struct perf_event *event) struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events); struct sbiret ret; int idx; - uint64_t cbase = 0, cmask = rvpmu->cmask; + u64 cbase = 0; + unsigned long ctr_mask = rvpmu->cmask; unsigned long cflags = 0; cflags = rvpmu_sbi_get_filter_flags(event); @@ -478,21 +557,24 @@ static int rvpmu_sbi_ctr_get_idx(struct perf_event *event) if ((hwc->flags & PERF_EVENT_FLAG_LEGACY) && (event->attr.type == PERF_TYPE_HARDWARE)) { if (event->attr.config == PERF_COUNT_HW_CPU_CYCLES) { cflags |= SBI_PMU_CFG_FLAG_SKIP_MATCH; - cmask = 1; + ctr_mask = 1; } else if (event->attr.config == PERF_COUNT_HW_INSTRUCTIONS) { cflags |= SBI_PMU_CFG_FLAG_SKIP_MATCH; - cmask = BIT(CSR_INSTRET - CSR_CYCLE); + ctr_mask = BIT(CSR_INSTRET - CSR_CYCLE); } } + if (pmu_sbi_is_fw_event(event) && cdeleg_available) + ctr_mask = firmware_cmask; + /* retrieve the available counter index */ #if defined(CONFIG_32BIT) ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, - cmask, cflags, hwc->event_base, hwc->config, + ctr_mask, cflags, hwc->event_base, hwc->config, hwc->config >> 32); #else ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, - cmask, cflags, hwc->event_base, hwc->config, 0); + ctr_mask, cflags, hwc->event_base, hwc->config, 0); #endif if (ret.error) { pr_debug("Not able to find a counter for event %lx config %llx\n", @@ -501,7 +583,7 @@ static int rvpmu_sbi_ctr_get_idx(struct perf_event *event) } idx = ret.value; - if (!test_bit(idx, &rvpmu->cmask) || !pmu_ctr_list[idx].value) + if (!test_bit(idx, &ctr_mask) || !pmu_ctr_list[idx].value) return -ENOENT; /* Additional sanity check for the counter id */ @@ -551,17 +633,6 @@ static int sbi_pmu_event_find_cache(u64 config) return ret; } -static bool pmu_sbi_is_fw_event(struct perf_event *event) -{ - u32 type = event->attr.type; - u64 config = event->attr.config; - - if ((type == PERF_TYPE_RAW) && ((config >> 63) == 1)) - return true; - else - return false; -} - static int rvpmu_sbi_event_map(struct perf_event *event, u64 *econfig) { u32 type = event->attr.type; @@ -593,7 +664,7 @@ static int rvpmu_sbi_event_map(struct perf_event *event, u64 *econfig) * 10 - SBI firmware events * 11 - Risc-V platform specific firmware event */ - raw_config_val = config & RISCV_PMU_RAW_EVENT_MASK; + raw_config_val = config & RISCV_PMU_SBI_RAW_EVENT_MASK; switch (config >> 62) { case 0: ret = RISCV_PMU_RAW_EVENT_IDX; @@ -622,6 +693,84 @@ static int rvpmu_sbi_event_map(struct perf_event *event, u64 *econfig) return ret; } +static int cdeleg_pmu_event_find_cache(u64 config, u64 *eventid, uint32_t *counter_mask) +{ + unsigned int cache_type, cache_op, cache_result; + + if (!current_pmu_cache_event_map) + return -ENOENT; + + cache_type = (config >> 0) & 0xff; + if (cache_type >= PERF_COUNT_HW_CACHE_MAX) + return -EINVAL; + + cache_op = (config >> 8) & 0xff; + if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) + return -EINVAL; + + cache_result = (config >> 16) & 0xff; + if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) + return -EINVAL; + + if (eventid) + *eventid = current_pmu_cache_event_map[cache_type][cache_op] + [cache_result].event_id; + if (counter_mask) + *counter_mask = current_pmu_cache_event_map[cache_type][cache_op] + [cache_result].counter_mask; + + return 0; +} + +static int rvpmu_cdeleg_event_map(struct perf_event *event, u64 *econfig) +{ + u32 type = event->attr.type; + u64 config = event->attr.config; + int ret = 0; + + /* + * There are two ways standard perf events can be mapped to platform specific + * encoding. + * 1. The vendor may specify the encodings in the driver. + * 2. The Perf tool for RISC-V may remap the standard perf event to platform + * specific encoding. + * + * As RISC-V ISA doesn't define any standard event encoding. Thus, perf tool allows + * vendor to define it via json file. The encoding defined in the json will override + * the perf legacy encoding. However, some user may want to run performance + * monitoring without perf tool as well. That's why, vendors may specify the event + * encoding in the driver as well if they want to support that use case too. + * If an encoding is defined in the json, it will be encoded as a raw event. + */ + + switch (type) { + case PERF_TYPE_HARDWARE: + if (config >= PERF_COUNT_HW_MAX) + return -EINVAL; + if (!current_pmu_hw_event_map) + return -ENOENT; + + *econfig = current_pmu_hw_event_map[config].event_id; + if (*econfig == HW_OP_UNSUPPORTED) + ret = -ENOENT; + break; + case PERF_TYPE_HW_CACHE: + ret = cdeleg_pmu_event_find_cache(config, econfig, NULL); + if (*econfig == HW_OP_UNSUPPORTED) + ret = -ENOENT; + break; + case PERF_TYPE_RAW: + *econfig = config & RISCV_PMU_DELEG_RAW_EVENT_MASK; + break; + default: + ret = -ENOENT; + break; + } + + /* event_base is not used for counter delegation */ + return ret; +} + static void pmu_sbi_snapshot_free(struct riscv_pmu *pmu) { int cpu; @@ -705,7 +854,7 @@ static int pmu_sbi_snapshot_setup(struct riscv_pmu *pmu, int cpu) return 0; } -static u64 rvpmu_sbi_ctr_read(struct perf_event *event) +static u64 rvpmu_ctr_read(struct perf_event *event) { struct hw_perf_event *hwc = &event->hw; int idx = hwc->idx; @@ -782,10 +931,6 @@ static void rvpmu_sbi_ctr_start(struct perf_event *event, u64 ival) if (ret.error && (ret.error != SBI_ERR_ALREADY_STARTED)) pr_err("Starting counter idx %d failed with error %d\n", hwc->idx, sbi_err_map_linux_errno(ret.error)); - - if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) && - (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) - rvpmu_set_scounteren((void *)event); } static void rvpmu_sbi_ctr_stop(struct perf_event *event, unsigned long flag) @@ -796,10 +941,6 @@ static void rvpmu_sbi_ctr_stop(struct perf_event *event, unsigned long flag) struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events); struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr; - if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) && - (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) - rvpmu_reset_scounteren((void *)event); - if (sbi_pmu_snapshot_available()) flag |= SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT; @@ -835,12 +976,6 @@ static int rvpmu_sbi_find_num_ctrs(void) return sbi_err_map_linux_errno(ret.error); } -static int rvpmu_deleg_find_ctrs(void) -{ - /* TODO */ - return -1; -} - static int rvpmu_sbi_get_ctrinfo(int nsbi_ctr, int ndeleg_ctr) { struct sbiret ret; @@ -928,53 +1063,75 @@ static inline void rvpmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu) } } -/* - * This function starts all the used counters in two step approach. - * Any counter that did not overflow can be start in a single step - * while the overflowed counters need to be started with updated initialization - * value. - */ -static inline void rvpmu_sbi_start_ovf_ctrs_sbi(struct cpu_hw_events *cpu_hw_evt, - u64 ctr_ovf_mask) +static void rvpmu_deleg_ctr_start_mask(unsigned long mask) { - int idx = 0, i; - struct perf_event *event; - unsigned long flag = SBI_PMU_START_FLAG_SET_INIT_VALUE; - unsigned long ctr_start_mask = 0; - uint64_t max_period; - struct hw_perf_event *hwc; - u64 init_val = 0; + unsigned long scountinhibit_val = 0; - for (i = 0; i < BITS_TO_LONGS(RISCV_MAX_COUNTERS); i++) { - ctr_start_mask = cpu_hw_evt->used_hw_ctrs[i] & ~ctr_ovf_mask; - /* Start all the counters that did not overflow in a single shot */ - sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, i * BITS_PER_LONG, ctr_start_mask, - 0, 0, 0, 0); - } + scountinhibit_val = csr_read(CSR_SCOUNTINHIBIT); + scountinhibit_val &= ~mask; + + csr_write(CSR_SCOUNTINHIBIT, scountinhibit_val); +} + +static void rvpmu_deleg_ctr_enable_irq(struct perf_event *event) +{ + unsigned long hpmevent_curr; + unsigned long of_mask; + struct hw_perf_event *hwc = &event->hw; + int counter_idx = hwc->idx; + unsigned long sip_val = csr_read(CSR_SIP); + + if (!is_sampling_event(event) || (sip_val & SIP_LCOFIP)) + return; - /* Reinitialize and start all the counter that overflowed */ - while (ctr_ovf_mask) { - if (ctr_ovf_mask & 0x01) { - event = cpu_hw_evt->events[idx]; - hwc = &event->hw; - max_period = riscv_pmu_ctr_get_width_mask(event); - init_val = local64_read(&hwc->prev_count) & max_period; #if defined(CONFIG_32BIT) - sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, - flag, init_val, init_val >> 32, 0); + hpmevent_curr = csr_ind_read(CSR_SIREG5, SISELECT_SSCCFG_BASE, counter_idx); + of_mask = (u32)~HPMEVENTH_OF; #else - sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, - flag, init_val, 0, 0); + hpmevent_curr = csr_ind_read(CSR_SIREG2, SISELECT_SSCCFG_BASE, counter_idx); + of_mask = ~HPMEVENT_OF; +#endif + + hpmevent_curr &= of_mask; +#if defined(CONFIG_32BIT) + csr_ind_write(CSR_SIREG4, SISELECT_SSCCFG_BASE, counter_idx, hpmevent_curr); +#else + csr_ind_write(CSR_SIREG2, SISELECT_SSCCFG_BASE, counter_idx, hpmevent_curr); #endif - perf_event_update_userpage(event); - } - ctr_ovf_mask = ctr_ovf_mask >> 1; - idx++; - } } -static inline void rvpmu_sbi_start_ovf_ctrs_snapshot(struct cpu_hw_events *cpu_hw_evt, - u64 ctr_ovf_mask) +static void rvpmu_deleg_ctr_start(struct perf_event *event, u64 ival) +{ + unsigned long scountinhibit_val = 0; + struct hw_perf_event *hwc = &event->hw; + +#if defined(CONFIG_32BIT) + csr_ind_write(CSR_SIREG, SISELECT_SSCCFG_BASE, hwc->idx, ival & 0xFFFFFFFF); + csr_ind_write(CSR_SIREG4, SISELECT_SSCCFG_BASE, hwc->idx, ival >> BITS_PER_LONG); +#else + csr_ind_write(CSR_SIREG, SISELECT_SSCCFG_BASE, hwc->idx, ival); +#endif + + rvpmu_deleg_ctr_enable_irq(event); + + scountinhibit_val = csr_read(CSR_SCOUNTINHIBIT); + scountinhibit_val &= ~(1 << hwc->idx); + + csr_write(CSR_SCOUNTINHIBIT, scountinhibit_val); +} + +static void rvpmu_deleg_ctr_stop_mask(unsigned long mask) +{ + unsigned long scountinhibit_val = 0; + + scountinhibit_val = csr_read(CSR_SCOUNTINHIBIT); + scountinhibit_val |= mask; + + csr_write(CSR_SCOUNTINHIBIT, scountinhibit_val); +} + +static void rvpmu_sbi_start_ovf_ctrs_snapshot(struct cpu_hw_events *cpu_hw_evt, + u64 ctr_ovf_mask) { int i, idx = 0; struct perf_event *event; @@ -1008,15 +1165,53 @@ static inline void rvpmu_sbi_start_ovf_ctrs_snapshot(struct cpu_hw_events *cpu_h } } -static void rvpmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, - u64 ctr_ovf_mask) +/* + * This function starts all the used counters in two step approach. + * Any counter that did not overflow can be start in a single step + * while the overflowed counters need to be started with updated initialization + * value. + */ +static void rvpmu_start_overflow_mask(struct riscv_pmu *pmu, u64 ctr_ovf_mask) { + int idx = 0, i; + struct perf_event *event; + unsigned long ctr_start_mask = 0; + u64 max_period, init_val = 0; + struct hw_perf_event *hwc; struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events); if (sbi_pmu_snapshot_available()) - rvpmu_sbi_start_ovf_ctrs_snapshot(cpu_hw_evt, ctr_ovf_mask); - else - rvpmu_sbi_start_ovf_ctrs_sbi(cpu_hw_evt, ctr_ovf_mask); + return rvpmu_sbi_start_ovf_ctrs_snapshot(cpu_hw_evt, ctr_ovf_mask); + + /* Start all the counters that did not overflow */ + if (riscv_pmu_cdeleg_available()) { + ctr_start_mask = cpu_hw_evt->used_hw_ctrs[i] & ~ctr_ovf_mask; + rvpmu_deleg_ctr_start_mask(ctr_start_mask); + } else { + for (i = 0; i < BITS_TO_LONGS(RISCV_MAX_COUNTERS); i++) { + ctr_start_mask = cpu_hw_evt->used_hw_ctrs[i] & ~ctr_ovf_mask; + /* Start all the counters that did not overflow in a single shot */ + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, i * BITS_PER_LONG, + ctr_start_mask, 0, 0, 0, 0); + } + } + + /* Reinitialize and start all the counter that overflowed */ + while (ctr_ovf_mask) { + if (ctr_ovf_mask & 0x01) { + event = cpu_hw_evt->events[idx]; + hwc = &event->hw; + max_period = riscv_pmu_ctr_get_width_mask(event); + init_val = local64_read(&hwc->prev_count) & max_period; + if (riscv_pmu_cdeleg_available()) + rvpmu_deleg_ctr_start(event, init_val); + else + rvpmu_sbi_ctr_start(event, init_val); + perf_event_update_userpage(event); + } + ctr_ovf_mask = ctr_ovf_mask >> 1; + idx++; + } } static irqreturn_t rvpmu_ovf_handler(int irq, void *dev) @@ -1051,7 +1246,10 @@ static irqreturn_t rvpmu_ovf_handler(int irq, void *dev) } pmu = to_riscv_pmu(event->pmu); - rvpmu_sbi_stop_hw_ctrs(pmu); + if (riscv_pmu_cdeleg_available()) + rvpmu_deleg_ctr_stop_mask(cpu_hw_evt->used_hw_ctrs[0]); + else + rvpmu_sbi_stop_hw_ctrs(pmu); /* Overflow status register should only be read after counter are stopped */ if (sbi_pmu_snapshot_available()) @@ -1120,22 +1318,174 @@ static irqreturn_t rvpmu_ovf_handler(int irq, void *dev) hw_evt->state = 0; } - rvpmu_sbi_start_overflow_mask(pmu, overflowed_ctrs); + rvpmu_start_overflow_mask(pmu, overflowed_ctrs); perf_sample_event_took(sched_clock() - start_clock); return IRQ_HANDLED; } +static int get_deleg_hw_ctr_width(int counter_offset) +{ + unsigned long hpm_warl; + int num_bits; + + if (counter_offset < 3 || counter_offset > 31) + return 0; + + hpm_warl = csr_ind_warl(CSR_SIREG, SISELECT_SSCCFG_BASE, counter_offset, -1); + num_bits = __fls(hpm_warl); + +#if defined(CONFIG_32BIT) + hpm_warl = csr_ind_warl(CSR_SIREG4, SISELECT_SSCCFG_BASE, counter_offset, -1); + num_bits += __fls(hpm_warl); +#endif + return num_bits; +} + +static int rvpmu_deleg_find_ctrs(void) +{ + int i, num_hw_ctr = 0; + union sbi_pmu_ctr_info cinfo; + unsigned long scountinhibit_old = 0; + + /* Do a WARL write/read to detect which hpmcounters have been delegated */ + scountinhibit_old = csr_read(CSR_SCOUNTINHIBIT); + csr_write(CSR_SCOUNTINHIBIT, -1); + cmask = csr_read(CSR_SCOUNTINHIBIT); + + csr_write(CSR_SCOUNTINHIBIT, scountinhibit_old); + + for_each_set_bit(i, &cmask, RISCV_MAX_HW_COUNTERS) { + if (unlikely(i == 1)) + continue; /* This should never happen as TM is read only */ + cinfo.value = 0; + cinfo.type = SBI_PMU_CTR_TYPE_HW; + /* + * If counter delegation is enabled, the csr stored to the cinfo will + * be a virtual counter that the delegation attempts to read. + */ + cinfo.csr = CSR_CYCLE + i; + if (i == 0 || i == 2) + cinfo.width = 63; + else + cinfo.width = get_deleg_hw_ctr_width(i); + + num_hw_ctr++; + pmu_ctr_list[i].value = cinfo.value; + } + + return num_hw_ctr; +} + +static int get_deleg_fixed_hw_idx(struct cpu_hw_events *cpuc, struct perf_event *event) +{ + return -EINVAL; +} + +static int get_deleg_next_hpm_hw_idx(struct cpu_hw_events *cpuc, struct perf_event *event) +{ + unsigned long hw_ctr_mask = 0; + + /* + * TODO: Treat every hpmcounter can monitor every event for now. + * The event to counter mapping should come from the json file. + * The mapping should also tell if sampling is supported or not. + */ + + /* Select only hpmcounters */ + hw_ctr_mask = cmask & (~0x7); + hw_ctr_mask &= ~(cpuc->used_hw_ctrs[0]); + return __ffs(hw_ctr_mask); +} + +static void update_deleg_hpmevent(int counter_idx, uint64_t event_value, uint64_t filter_bits) +{ + u64 hpmevent_value = 0; + + /* OF bit should be enable during the start if sampling is requested */ + hpmevent_value = (event_value & ~HPMEVENT_MASK) | filter_bits | HPMEVENT_OF; +#if defined(CONFIG_32BIT) + csr_ind_write(CSR_SIREG2, SISELECT_SSCCFG_BASE, counter_idx, hpmevent_value & 0xFFFFFFFF); + if (riscv_isa_extension_available(NULL, SSCOFPMF)) + csr_ind_write(CSR_SIREG5, SISELECT_SSCCFG_BASE, counter_idx, + hpmevent_value >> BITS_PER_LONG); +#else + csr_ind_write(CSR_SIREG2, SISELECT_SSCCFG_BASE, counter_idx, hpmevent_value); +#endif +} + +static int rvpmu_deleg_ctr_get_idx(struct perf_event *event) +{ + struct hw_perf_event *hwc = &event->hw; + struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu); + struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events); + unsigned long hw_ctr_max_id; + u64 priv_filter; + int idx; + + /* + * TODO: We should not rely on SBI Perf encoding to check if the event + * is a fixed one or not. + */ + if (!is_sampling_event(event)) { + idx = get_deleg_fixed_hw_idx(cpuc, event); + if (idx == 0 || idx == 2) { + /* Priv mode filter bits are only available if smcntrpmf is present */ + if (riscv_isa_extension_available(NULL, SMCNTRPMF)) + goto found_idx; + else + goto skip_update; + } + } + + hw_ctr_max_id = __fls(cmask); + idx = get_deleg_next_hpm_hw_idx(cpuc, event); + if (idx < 3 || idx > hw_ctr_max_id) + goto out_err; +found_idx: + priv_filter = get_deleg_priv_filter_bits(event); + update_deleg_hpmevent(idx, hwc->config, priv_filter); +skip_update: + if (!test_and_set_bit(idx, cpuc->used_hw_ctrs)) + return idx; +out_err: + return -ENOENT; +} + static void rvpmu_ctr_start(struct perf_event *event, u64 ival) { - rvpmu_sbi_ctr_start(event, ival); - /* TODO: Counter delegation implementation */ + struct hw_perf_event *hwc = &event->hw; + + if (riscv_pmu_cdeleg_available() && !pmu_sbi_is_fw_event(event)) + rvpmu_deleg_ctr_start(event, ival); + else + rvpmu_sbi_ctr_start(event, ival); + + if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) && + (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) + rvpmu_set_scounteren((void *)event); } static void rvpmu_ctr_stop(struct perf_event *event, unsigned long flag) { - rvpmu_sbi_ctr_stop(event, flag); - /* TODO: Counter delegation implementation */ + struct hw_perf_event *hwc = &event->hw; + + if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) && + (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) + rvpmu_reset_scounteren((void *)event); + + if (riscv_pmu_cdeleg_available() && !pmu_sbi_is_fw_event(event)) { + /* + * The counter is already stopped. No need to stop again. Counter + * mapping will be reset in clear_idx function. + */ + if (flag != RISCV_PMU_STOP_FLAG_RESET) + rvpmu_deleg_ctr_stop_mask((1 << hwc->idx)); + else + update_deleg_hpmevent(hwc->idx, 0, 0); + } else { + rvpmu_sbi_ctr_stop(event, flag); + } } static int rvpmu_find_ctrs(void) @@ -1169,20 +1519,18 @@ static int rvpmu_find_ctrs(void) static int rvpmu_event_map(struct perf_event *event, u64 *econfig) { - return rvpmu_sbi_event_map(event, econfig); - /* TODO: Counter delegation implementation */ + if (riscv_pmu_cdeleg_available() && !pmu_sbi_is_fw_event(event)) + return rvpmu_cdeleg_event_map(event, econfig); + else + return rvpmu_sbi_event_map(event, econfig); } static int rvpmu_ctr_get_idx(struct perf_event *event) { - return rvpmu_sbi_ctr_get_idx(event); - /* TODO: Counter delegation implementation */ -} - -static u64 rvpmu_ctr_read(struct perf_event *event) -{ - return rvpmu_sbi_ctr_read(event); - /* TODO: Counter delegation implementation */ + if (riscv_pmu_cdeleg_available() && !pmu_sbi_is_fw_event(event)) + return rvpmu_deleg_ctr_get_idx(event); + else + return rvpmu_sbi_ctr_get_idx(event); } static int rvpmu_starting_cpu(unsigned int cpu, struct hlist_node *node) @@ -1200,7 +1548,16 @@ static int rvpmu_starting_cpu(unsigned int cpu, struct hlist_node *node) csr_write(CSR_SCOUNTEREN, 0x2); /* Stop all the counters so that they can be enabled from perf */ - rvpmu_sbi_stop_all(pmu); + if (riscv_pmu_cdeleg_available()) { + rvpmu_deleg_ctr_stop_mask(cmask); + if (riscv_pmu_sbi_available()) { + /* Stop the firmware counters as well */ + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, 0, firmware_cmask, + 0, 0, 0, 0); + } + } else { + rvpmu_sbi_stop_all(pmu); + } if (riscv_pmu_use_irq) { cpu_hw_evt->irq = riscv_pmu_irq; @@ -1499,8 +1856,11 @@ static int rvpmu_device_probe(struct platform_device *pdev) pmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE; } - pmu->pmu.attr_groups = riscv_pmu_attr_groups; pmu->pmu.parent = &pdev->dev; + if (cdeleg_available) + pmu->pmu.attr_groups = riscv_cdeleg_pmu_attr_groups; + else + pmu->pmu.attr_groups = riscv_sbi_pmu_attr_groups; pmu->cmask = cmask; pmu->ctr_start = rvpmu_ctr_start; pmu->ctr_stop = rvpmu_ctr_stop; diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index a3e1fdd5084a..9e2758c32e8b 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -20,6 +20,7 @@ */ #define RISCV_MAX_COUNTERS 64 +#define RISCV_MAX_HW_COUNTERS 32 #define RISCV_OP_UNSUPP (-EOPNOTSUPP) #define RISCV_PMU_PDEV_NAME "riscv-pmu" #define RISCV_PMU_LEGACY_PDEV_NAME "riscv-pmu-legacy" @@ -28,6 +29,8 @@ #define RISCV_PMU_CONFIG1_GUEST_EVENTS 0x1 +#define RISCV_PMU_DELEG_RAW_EVENT_MASK GENMASK_ULL(55, 0) + #define HW_OP_UNSUPPORTED 0xFFFF #define CACHE_OP_UNSUPPORTED 0xFFFF From patchwork Thu Feb 6 07:23:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13962530 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BD176C02196 for ; Thu, 6 Feb 2025 07:42:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=iRQVXC6gFLzWtWbfiEzQ410Qhnf0vFx257IEQmKev50=; b=Yv4sicGTb/LLMq rn0skdTRlTVC9LvGdzygU8rSxsdZzQDXECKpZ4kZ9r9WVBu+uIkJNNRHiCYigk3tBaox56rGGQ/S/ s+E3orF8AskpppPa75FuvM6Z4vTAx8Tsb6twHWw2eKORoJcQ5iUwB7y69ePXsrdqBmRuACeIeSsw8 tRArKUtitVgRhOqJLJxVxip7BS8Ck/Q9xYHlw7xuMhLkZ1dIezB1xAUH8SOVR8kicb5WTiCRyja/p FN4hwHqHSlCUnNxgjnvdbbN/bNjC8f63T7vKX5TBZLUX7Cv9o5rzruK1SCRabW5sMY+NwMWdWXKc1 fkowKcbGQLUNKeqOE1yg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfwXG-00000005dEU-2XeM; Thu, 06 Feb 2025 07:42:54 +0000 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfwEe-00000005YGc-25bC for linux-riscv@lists.infradead.org; Thu, 06 Feb 2025 07:23:42 +0000 Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-2f9cd9601b8so953214a91.3 for ; Wed, 05 Feb 2025 23:23:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1738826620; x=1739431420; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=YQ1bM+mdYO24XpbpY93Gza0u/hfSg2U52kt5rlPb2uw=; b=eDrumcNty6D85nHbDA2bKP3QQVTcCpLtqOg5jlx7O3MK7YBTEOlaj1/tfGvm7N3S0r e2Z+hftb2T1F9HE8lHICDVPD0t1vKMJ7XnHN5xOG69oZryFZhhFL/wb8zmMAyy4WUSVX Bu8PJQgg0w1KyApAAZKgOI4/PlFleKhUTLq/eyCwXY1tHZsYEgleUy8SdBDgaoYkHqVG 1iG3XrKKlad7qm9DxKojHfd85d8ea2BAIVFxbT2CbvsLk8hZiIb4WFo6zVNlkBNs9FLi WGeYKOFjbXhsLCnP9hqquasH7a+WcQAScuCC6LKHAP1J64NQDrvIFow4cm9bSazrrL9I nyLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738826620; x=1739431420; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YQ1bM+mdYO24XpbpY93Gza0u/hfSg2U52kt5rlPb2uw=; b=AyeDvpLqWQfzse/yzIqqHQ+g+60NoWVPj9nst90SgyTBso9WKyR0YqSclAmKEDLZLD Ra07OpYVWX/99iaI8ytXEZJkfNsj8Lph0lz38hMEGLGt6bdIAdFgXF2X3Kv7NJfB/15b Hi2FtfN5HMyK9HdYn7EKxbuBaPuuLPzr/iWTyF3TUABs3VvfKjzpZuQEbnSF37SNu5CE ueyO6ui63bCATRnCO07h4678mMipPDyF1Qyh5pLrbvTZZ23OHS+Ql1ePTi5gsv8vIEOe hd7sow8enUMS7sx3tkZmA9hynlZVCxQd2twBncIXzFAoQtgdatHDhOawtUPaDhPxcump IsnQ== X-Gm-Message-State: AOJu0YzruGhZOxcoLRy/BJU0DgHnRtO32MWo2iLCiXPxKBS2yB1oJtMo 0fprW66517aTWrFZsSKi3zkqTCyFu9LA144ZGmONXMLgmbSOy1dNvVlbKSoiHNM= X-Gm-Gg: ASbGncs5GSew8eDDZ2kTGDoZmKrUd5t+W8rqMoWikUJjQdKDfGgWFlIwl68m12T5Ao6 9vDpZkej3OJnW7V/AqcjVltWIL+TsVWr7tDv6EqcXwKnbHUqZqymLnRgWHQUQhEfZMIfnkimph1 NufhuO4uGv6YW46ANSXU3MtGyuWqjTGrqC5h3UbYwtZ7XmnqBkVSieEopgeaoMIwr5bkjiO8Cw/ Oo05TIcsuvG+NuPTMb+XLXc6KqzctO31ZqgVl762g8Vooj1mQCnFvRwCGMubGWn55mtI2m2EP5/ aqxuYby0K1PpQy0MMtJndcJhTiOS X-Google-Smtp-Source: AGHT+IHr3HVst/0GQEzeOnoyNAyzJUxG9J5qyTanVRpVP7lxbmu+OPESYtyRFZuabnz8KqnI9biZIQ== X-Received: by 2002:a17:90b:4c43:b0:2ee:fdf3:390d with SMTP id 98e67ed59e1d1-2f9e084fcc0mr8578133a91.31.1738826619909; Wed, 05 Feb 2025 23:23:39 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a72292sm630883a91.27.2025.02.05.23.23.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 23:23:39 -0800 (PST) From: Atish Patra Date: Wed, 05 Feb 2025 23:23:20 -0800 Subject: [PATCH v4 15/21] RISC-V: perf: Skip PMU SBI extension when not implemented MIME-Version: 1.0 Message-Id: <20250205-counter_delegation-v4-15-835cfa88e3b1@rivosinc.com> References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> In-Reply-To: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra , Charlie Jenkins X-Mailer: b4 0.15-dev-13183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_232340_581191_202B4822 X-CRM114-Status: GOOD ( 16.54 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Charlie Jenkins When the PMU SBI extension is not implemented, sbi_v2_available should not be set to true. The SBI implementation for counter config matching and firmware counter read should also be skipped when the SBI extension is not implemented. Signed-off-by: Atish Patra Signed-off-by: Charlie Jenkins --- drivers/perf/riscv_pmu_dev.c | 46 ++++++++++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 19 deletions(-) diff --git a/drivers/perf/riscv_pmu_dev.c b/drivers/perf/riscv_pmu_dev.c index 5112049b491c..219f65eb167c 100644 --- a/drivers/perf/riscv_pmu_dev.c +++ b/drivers/perf/riscv_pmu_dev.c @@ -410,18 +410,22 @@ static void rvpmu_sbi_check_event(struct sbi_pmu_event_data *edata) } } -static void rvpmu_sbi_check_std_events(struct work_struct *work) +static void rvpmu_check_std_events(struct work_struct *work) { - for (int i = 0; i < ARRAY_SIZE(pmu_hw_event_sbi_map); i++) - rvpmu_sbi_check_event(&pmu_hw_event_sbi_map[i]); - - for (int i = 0; i < ARRAY_SIZE(pmu_cache_event_sbi_map); i++) - for (int j = 0; j < ARRAY_SIZE(pmu_cache_event_sbi_map[i]); j++) - for (int k = 0; k < ARRAY_SIZE(pmu_cache_event_sbi_map[i][j]); k++) - rvpmu_sbi_check_event(&pmu_cache_event_sbi_map[i][j][k]); + if (riscv_pmu_sbi_available()) { + for (int i = 0; i < ARRAY_SIZE(pmu_hw_event_sbi_map); i++) + rvpmu_sbi_check_event(&pmu_hw_event_sbi_map[i]); + + for (int i = 0; i < ARRAY_SIZE(pmu_cache_event_sbi_map); i++) + for (int j = 0; j < ARRAY_SIZE(pmu_cache_event_sbi_map[i]); j++) + for (int k = 0; k < ARRAY_SIZE(pmu_cache_event_sbi_map[i][j]); k++) + rvpmu_sbi_check_event(&pmu_cache_event_sbi_map[i][j][k]); + } else { + DO_ONCE_LITE_IF(1, pr_err, "Boot time config matching not required for smcdeleg\n"); + } } -static DECLARE_WORK(check_std_events_work, rvpmu_sbi_check_std_events); +static DECLARE_WORK(check_std_events_work, rvpmu_check_std_events); static ssize_t rvpmu_format_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -549,6 +553,9 @@ static int rvpmu_sbi_ctr_get_idx(struct perf_event *event) cflags = rvpmu_sbi_get_filter_flags(event); + if (!riscv_pmu_sbi_available()) + return -ENOENT; + /* * In legacy mode, we have to force the fixed counters for those events * but not in the user access mode as we want to use the other counters @@ -562,10 +569,9 @@ static int rvpmu_sbi_ctr_get_idx(struct perf_event *event) cflags |= SBI_PMU_CFG_FLAG_SKIP_MATCH; ctr_mask = BIT(CSR_INSTRET - CSR_CYCLE); } - } - - if (pmu_sbi_is_fw_event(event) && cdeleg_available) + } else if (pmu_sbi_is_fw_event(event) && cdeleg_available) { ctr_mask = firmware_cmask; + } /* retrieve the available counter index */ #if defined(CONFIG_32BIT) @@ -871,7 +877,7 @@ static u64 rvpmu_ctr_read(struct perf_event *event) return val; } - if (pmu_sbi_is_fw_event(event)) { + if (pmu_sbi_is_fw_event(event) && riscv_pmu_sbi_available()) { ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ, hwc->idx, 0, 0, 0, 0, 0); if (ret.error) @@ -1940,14 +1946,16 @@ static int __init rvpmu_devinit(void) int ret; struct platform_device *pdev; - if (sbi_spec_version >= sbi_mk_version(0, 3) && - sbi_probe_extension(SBI_EXT_PMU)) { - static_branch_enable(&riscv_pmu_sbi_available); - sbi_available = true; + if (sbi_probe_extension(SBI_EXT_PMU)) { + if (sbi_spec_version >= sbi_mk_version(0, 3)) { + static_branch_enable(&riscv_pmu_sbi_available); + sbi_available = true; + } + + if (sbi_spec_version >= sbi_mk_version(2, 0)) + sbi_v2_available = true; } - if (sbi_spec_version >= sbi_mk_version(2, 0)) - sbi_v2_available = true; /* * We need all three extensions to be present to access the counters * in S-mode via Supervisor Counter delegation. From patchwork Thu Feb 6 07:23:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13962631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC91FC02198 for ; Thu, 6 Feb 2025 08:46:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6DIFBbXz/X+0owfi3215FQnE5VyqNkayfoQeMkLyA4M=; b=oxrBhv548TfyFV akq/qDELLEmgwdsCThn+3o9Tv2VoIWnJ+Czykm1ZIHA0AydvBtTSwExEFcsw0zMsLTfuzUMiJd6p8 3Zo+PRGILxLQUynnP+zqPiHKoFux/WcCblqD2BT7ZXf7zX4Z925ETe8u4BU1tvgUOYP+m7LpO90Z9 oDUYEecXgen9jOzD0sGsA64FXEMGFKBdb9hTCIIMemHRmDUtcniMxdw6FqUPftOmkzJQiH34Jwu9s cNp2gWg67ZE3yLKdS7FQ+sop5j7GQoc25lCFP+BthmvfJZ8Bgy1P9STt4jibZOZSTaQfGLaPZpuqW mncg5WsAZW11NS9puWqg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfxWf-00000005k9H-0PCc; Thu, 06 Feb 2025 08:46:21 +0000 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfwEg-00000005YI2-0bFF for linux-riscv@lists.infradead.org; Thu, 06 Feb 2025 07:23:44 +0000 Received: by mail-pj1-x102d.google.com with SMTP id 98e67ed59e1d1-2f43d17b0e3so988535a91.0 for ; Wed, 05 Feb 2025 23:23:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1738826621; x=1739431421; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=I88Es5nW96kSoOcv6Dbr94uSnbNRzJurf3m4q8mKZlI=; b=a1aduA+zQqFCWxcAUl/VsUEjZf801HcGxqpYvFlvv5kBN0aYTybOLh/mZ2tRJEk+jT b0buqoZvFwFsKfnae4FAz+qac71xgx+I/cpWC1r+RoDOsKlK6sJ+EK2Fn1dJvrMMBcXk pZY17kw8Gd8juCYJtGeSaufL6vpzLr1DvzT+PRXLxlnWVsgPpXh83BwoCeMroqtAOGZq msQogjCzpLv0aYlAFNUVYFLJtNH+2PCQm7Ppf0rqLR4ia1wTkoqGYzmXhDbl4/DBA7jC lqyIsf3BOguAXeyleOTcG5OInISY4Yu+AhbPofss72hJmVqgWX+8DjRu/X85R5SzaNPk CJ5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738826621; x=1739431421; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I88Es5nW96kSoOcv6Dbr94uSnbNRzJurf3m4q8mKZlI=; b=wlNFvHOEIsQLgZDTkwut35qw3HGOXRzD5zvxAQiKHCSWpZojxCKxmWpP1xami8FlTM jeNqkT8czR9gS6Yt/IB4IHMmnQ1mtGhhQjyv96MvDcgIO2j1BSqqwRUrG/L/1SuvvlHb m07Od2RpqWhFdDHX1PkJdxzi17Ui3AoPn1yOT2H25FpyLhWcya4EEpHDqOxSxax+SL/A s/zvU3pJHxDFExF4P4NVH5ZUXWjOTyXqdtJIdbWTuWCqXqaTyVYokcQoZebnZY6fJbxi cGqagJD7UfEH/AAbRXmV3wvLIRgmLYGFW4ap637b0O2odBW+XgXJryaaoiz/TrmDnnMa L7NA== X-Gm-Message-State: AOJu0YyWs8SIugm83YvbqOY7armWSme6fi5lietUiYdHuf7c8dR95/H6 /jNT1BER4KFqaaiUaI7lOwkU9NNvndzR+0kJ1N6Vh4iHydG/E7tbLxDu7+edQuA= X-Gm-Gg: ASbGncteJ2Zxq0iA2MV7E1BBh79t9fjRw+Bk7AxxSYK9bq16trPJVRRQbcbGN2O0CUx qYdy+9FP8rHoTMmxc/HdC7hJRr7wCGmZVe/H0KsxlxlFf/6PbhBVwY3VjsjJW9NarBsyjzUafHa qrmK5LWqm0BJGXd+cLrOZmrbKHyptJY7sxSJZn2jlcNFfmDtv4XHiaD3zK5C/X9lDs4JQ+XYXqj g5MUSrtNX7o/TsYhTydr+YwVzm/HFWxUyO/wOO9qwBQe8bQBhzXHGc6NtdaHLLnIvWEh8c2jJpQ aa3f8QND6HG4EQqqGF3DhSbsv7Fh X-Google-Smtp-Source: AGHT+IHw8z00oYKwQWOlOfDB9fO1eIwPs/hkvMz9GejIoBfl+7Quq44eHbwbfyI2Rhdhk6N6OB3X8w== X-Received: by 2002:a17:90a:12c8:b0:2fa:b84:b31f with SMTP id 98e67ed59e1d1-2fa0b84b6ffmr1530733a91.25.1738826621487; Wed, 05 Feb 2025 23:23:41 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a72292sm630883a91.27.2025.02.05.23.23.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 23:23:41 -0800 (PST) From: Atish Patra Date: Wed, 05 Feb 2025 23:23:21 -0800 Subject: [PATCH v4 16/21] RISC-V: perf: Use config2/vendor table for event to counter mapping MIME-Version: 1.0 Message-Id: <20250205-counter_delegation-v4-16-835cfa88e3b1@rivosinc.com> References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> In-Reply-To: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_232342_275372_C0ED0D2E X-CRM114-Status: GOOD ( 26.87 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The counter restriction specified in the json file is passed to the drivers via config2 paarameter in perf attributes. This allows any platform vendor to define their custom mapping between event and hpmcounters without any rules defined in the ISA. For legacy events, the platform vendor may define the mapping in the driver in the vendor event table. The fixed cycle and instruction counters are fixed (0 and 2 respectively) by the ISA and maps to the legacy events. The platform vendor must specify this in the driver if intended to be used while profiling. Otherwise, they can just specify the alternate hpmcounters that may monitor and/or sample the cycle/instruction counts. Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_dev.c | 79 ++++++++++++++++++++++++++++++++++-------- include/linux/perf/riscv_pmu.h | 2 ++ 2 files changed, 67 insertions(+), 14 deletions(-) diff --git a/drivers/perf/riscv_pmu_dev.c b/drivers/perf/riscv_pmu_dev.c index 219f65eb167c..bbf5bcff51fc 100644 --- a/drivers/perf/riscv_pmu_dev.c +++ b/drivers/perf/riscv_pmu_dev.c @@ -76,6 +76,7 @@ static ssize_t __maybe_unused rvpmu_format_show(struct device *dev, struct devic RVPMU_ATTR_ENTRY(_name, rvpmu_format_show, (char *)_config) PMU_FORMAT_ATTR(firmware, "config:62-63"); +PMU_FORMAT_ATTR(counterid_mask, "config2:0-31"); static bool sbi_v2_available; static DEFINE_STATIC_KEY_FALSE(sbi_pmu_snapshot_available); @@ -112,6 +113,7 @@ static const struct attribute_group *riscv_sbi_pmu_attr_groups[] = { static struct attribute *riscv_cdeleg_pmu_formats_attr[] = { RVPMU_FORMAT_ATTR_ENTRY(event, RVPMU_CDELEG_PMU_FORMAT_ATTR), &format_attr_firmware.attr, + &format_attr_counterid_mask.attr, NULL, }; @@ -1383,24 +1385,77 @@ static int rvpmu_deleg_find_ctrs(void) return num_hw_ctr; } +/* + * The json file must correctly specify counter 0 or counter 2 is available + * in the counter lists for cycle/instret events. Otherwise, the drivers have + * no way to figure out if a fixed counter must be used and pick a programmable + * counter if available. + */ static int get_deleg_fixed_hw_idx(struct cpu_hw_events *cpuc, struct perf_event *event) { - return -EINVAL; + struct hw_perf_event *hwc = &event->hw; + bool guest_events = event->attr.config1 & RISCV_PMU_CONFIG1_GUEST_EVENTS; + + if (guest_events) { + if (hwc->event_base == SBI_PMU_HW_CPU_CYCLES) + return 0; + if (hwc->event_base == SBI_PMU_HW_INSTRUCTIONS) + return 2; + else + return -EINVAL; + } + + if (!event->attr.config2) + return -EINVAL; + + if (event->attr.config2 & RISCV_PMU_CYCLE_FIXED_CTR_MASK) + return 0; /* CY counter */ + else if (event->attr.config2 & RISCV_PMU_INSTRUCTION_FIXED_CTR_MASK) + return 2; /* IR counter */ + else + return -EINVAL; } static int get_deleg_next_hpm_hw_idx(struct cpu_hw_events *cpuc, struct perf_event *event) { - unsigned long hw_ctr_mask = 0; + u32 hw_ctr_mask = 0, temp_mask = 0; + u32 type = event->attr.type; + u64 config = event->attr.config; + int ret; - /* - * TODO: Treat every hpmcounter can monitor every event for now. - * The event to counter mapping should come from the json file. - * The mapping should also tell if sampling is supported or not. - */ + /* Select only available hpmcounters */ + hw_ctr_mask = cmask & (~0x7) & ~(cpuc->used_hw_ctrs[0]); + + switch (type) { + case PERF_TYPE_HARDWARE: + temp_mask = current_pmu_hw_event_map[config].counter_mask; + break; + case PERF_TYPE_HW_CACHE: + ret = cdeleg_pmu_event_find_cache(config, NULL, &temp_mask); + if (ret) + return ret; + break; + case PERF_TYPE_RAW: + /* + * Mask off the counters that can't monitor this event (specified via json) + * The counter mask for this event is set in config2 via the property 'Counter' + * in the json file or manual configuration of config2. If the config2 is not set, + * it is assumed all the available hpmcounters can monitor this event. + * Note: This assumption may fail for virtualization use case where they hypervisor + * (e.g. KVM) virtualizes the counter. Any event to counter mapping provided by the + * guest is meaningless from a hypervisor perspective. Thus, the hypervisor doesn't + * set config2 when creating kernel counter and relies default host mapping. + */ + if (event->attr.config2) + temp_mask = event->attr.config2; + break; + default: + break; + } + + if (temp_mask) + hw_ctr_mask &= temp_mask; - /* Select only hpmcounters */ - hw_ctr_mask = cmask & (~0x7); - hw_ctr_mask &= ~(cpuc->used_hw_ctrs[0]); return __ffs(hw_ctr_mask); } @@ -1429,10 +1484,6 @@ static int rvpmu_deleg_ctr_get_idx(struct perf_event *event) u64 priv_filter; int idx; - /* - * TODO: We should not rely on SBI Perf encoding to check if the event - * is a fixed one or not. - */ if (!is_sampling_event(event)) { idx = get_deleg_fixed_hw_idx(cpuc, event); if (idx == 0 || idx == 2) { diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index 9e2758c32e8b..e58f83811988 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -30,6 +30,8 @@ #define RISCV_PMU_CONFIG1_GUEST_EVENTS 0x1 #define RISCV_PMU_DELEG_RAW_EVENT_MASK GENMASK_ULL(55, 0) +#define RISCV_PMU_CYCLE_FIXED_CTR_MASK 0x01 +#define RISCV_PMU_INSTRUCTION_FIXED_CTR_MASK 0x04 #define HW_OP_UNSUPPORTED 0xFFFF #define CACHE_OP_UNSUPPORTED 0xFFFF From patchwork Thu Feb 6 07:23:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13962632 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CCCD7C02196 for ; Thu, 6 Feb 2025 08:46:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=sb5FYFUwu/mEbGrCOObyvJ6Pa10MuSqyG5/mlf02gW0=; b=e8dyeF5lVS2h8v PDDiudSepBCrkYDUPeZhRSYs84wOR+LKLR5qdE/KhfIaWSfwEJGvFdxzSKi7/1+z9xbEcPfkqjDQM FHEFTy4UeL3xRr7DgMmywFlnGmaZdD/2NIV/cbJox8l3H1/DtWxS1tm2apw+69BtwiJXbzgz1stfC aHb8Hftd0THMkeUES0R1eH1Z0ba4SvOIER6pYb4uWcxujZz39t76v2rroZAGJbUwDWnD15asvpnHM I8hwURIc0a53+BSypS7vVjWFjdWJH7aXkYI7+zFYm0pQ9TUXeAhwSYTQtGGAD1yJXXS8qQqBI0KY6 IhEMwiXMz0U96+NwdlVQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfxWf-00000005k9W-2zjk; Thu, 06 Feb 2025 08:46:21 +0000 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfwEh-00000005YJr-2p5o for linux-riscv@lists.infradead.org; Thu, 06 Feb 2025 07:23:45 +0000 Received: by mail-pj1-x102b.google.com with SMTP id 98e67ed59e1d1-2f9f5caa37cso1712812a91.0 for ; Wed, 05 Feb 2025 23:23:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1738826623; x=1739431423; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=mLt3uQ+5mVFCD4CpzivJzFeQzs8sYQp9bQK+aL0eLxQ=; b=JkUd2FdA3e9SzRPPqk/w7/7jTtDFwUqlM/ITm6MoJqu9onSIOxn9FhjA4d/AO0XfMc AegqM7zrKkkXHoO6CElsFLypPkOZsFczSRvdDu5QfGRn+o4NrtplqlxnZq2WY2zxdWi4 pHm+rY55dUJt8SLuPKQ26lT5BwAyo8eMkEhWmHdEG4SpNV4vvGlTbiTV1yCzKc3KDQR5 ILyoygiso7wd6U08YofzYWdzwejJO3MSbEzK7C2aIHdrEsSXRw/4jD81d2kk/XdhKI2B RdOUao3LI3vO/0yXqtQ8CCbYKhhj1NFA27mpocp4C3BYgvKz9uiXh7fDRHpT2GrCL5Kk 7LKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738826623; x=1739431423; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mLt3uQ+5mVFCD4CpzivJzFeQzs8sYQp9bQK+aL0eLxQ=; b=aXHgNWlpQ48++wnnSvNtWUcWIvOsU7QGviE1+vwqNykx193gU41kV70BO1rEb52aPy p0stAXdbbxfYBOeZVDmZxcAgnESINWOOQR284RiNzLB2zmk/hMkGxsQFUxISW/ZOhAxH xsYBXhJ4LhXyl3pSK1PLnY0Cmltvhe4ueWHgduJp9ykadViS1H2wUF+p/M9eiaI/uBw9 c5UzVMDNreh4AhkHcWEtfc7qTRbxc0n7HiYGhRw0ChBbw52GuTYdFUss0E2qa7iw4CZT GbCA4+bv1ydOZ5Z49UvelcCB0ecVqqZnfh2vdQunHAyxqNlKEk6nUwPYITUedpJyvHpA Eitg== X-Gm-Message-State: AOJu0YxV8BdsthY9Oo3H5Umbv/uNhgXhNHJJfqc6CKuxVQFsvG+uv3PW J7+RJczbxzuub9ZkTlSvV2+aa3DIdsjFSRcCOtZkPIDuReRo7B+687qb98IwAmg= X-Gm-Gg: ASbGncuwHgU6+kHEQwD68uk/KjpTeTaEwZYRiLdaHUvNNmlMMDFviTAADMJxsFXR1l8 VBUksi22loS/JxhjxHBjHMRPRUy0JPYyVu0v+S5a/HN+06nUFkPws2W5vNJennQP5QSoFDXqnqJ 86sU3V1FEXaUuSPbMq7vACa/NUyI6QYRQOxfJecBkUmdUPbke4S05DIV5l9KD4RWCrDYYhtWHp7 qaLPSxsv3vD6zcLIrDeLUPW3n1Nu2xGYlsredVy4cJsvopsbVZSlZC/4GhQk58c13GO5sYhd0sn qlMdMfM7poAMs/BnVSL50tl+yGGx X-Google-Smtp-Source: AGHT+IE+zm5bTYTXugTwpHU711moyOZkgKemcMPApk5i6Nyzgk504/702jQ6OsU4eVbUvVfR2YHglw== X-Received: by 2002:a17:90b:4fd1:b0:2f9:e730:1601 with SMTP id 98e67ed59e1d1-2f9ff8a1befmr4045975a91.7.1738826623101; Wed, 05 Feb 2025 23:23:43 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a72292sm630883a91.27.2025.02.05.23.23.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 23:23:42 -0800 (PST) From: Atish Patra Date: Wed, 05 Feb 2025 23:23:22 -0800 Subject: [PATCH v4 17/21] RISC-V: perf: Add legacy event encodings via sysfs MIME-Version: 1.0 Message-Id: <20250205-counter_delegation-v4-17-835cfa88e3b1@rivosinc.com> References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> In-Reply-To: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_232343_792100_462BF081 X-CRM114-Status: GOOD ( 14.87 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Define sysfs details for the legacy events so that any tool can parse these to understand the minimum set of legacy events supported by the platform. The sysfs entry will describe both event encoding and corresponding counter map so that an perf event can be programmed accordingly. Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_dev.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/perf/riscv_pmu_dev.c b/drivers/perf/riscv_pmu_dev.c index bbf5bcff51fc..dd4627055e7a 100644 --- a/drivers/perf/riscv_pmu_dev.c +++ b/drivers/perf/riscv_pmu_dev.c @@ -122,7 +122,20 @@ static struct attribute_group riscv_cdeleg_pmu_format_group = { .attrs = riscv_cdeleg_pmu_formats_attr, }; +#define RVPMU_EVENT_ATTR_RESOLVE(m) #m +#define RVPMU_EVENT_CMASK_ATTR(_name, _var, config, mask) \ + PMU_EVENT_ATTR_STRING(_name, rvpmu_event_attr_##_var, \ + "event=" RVPMU_EVENT_ATTR_RESOLVE(config) \ + ",counterid_mask=" RVPMU_EVENT_ATTR_RESOLVE(mask) "\n") + +#define RVPMU_EVENT_ATTR_PTR(name) (&rvpmu_event_attr_##name.attr.attr) + +static struct attribute_group riscv_cdeleg_pmu_event_group __ro_after_init = { + .name = "events", +}; + static const struct attribute_group *riscv_cdeleg_pmu_attr_groups[] = { + &riscv_cdeleg_pmu_event_group, &riscv_cdeleg_pmu_format_group, NULL, }; @@ -362,11 +375,14 @@ struct riscv_vendor_pmu_events { const struct riscv_pmu_event *hw_event_map; const struct riscv_pmu_event (*cache_event_map)[PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_RESULT_MAX]; + struct attribute **attrs_events; }; -#define RISCV_VENDOR_PMU_EVENTS(_vendorid, _archid, _implid, _hw_event_map, _cache_event_map) \ +#define RISCV_VENDOR_PMU_EVENTS(_vendorid, _archid, _implid, _hw_event_map, \ + _cache_event_map, _attrs) \ { .vendorid = _vendorid, .archid = _archid, .implid = _implid, \ - .hw_event_map = _hw_event_map, .cache_event_map = _cache_event_map }, + .hw_event_map = _hw_event_map, .cache_event_map = _cache_event_map, \ + .attrs_events = _attrs }, static struct riscv_vendor_pmu_events pmu_vendor_events_table[] = { }; @@ -388,6 +404,8 @@ static void rvpmu_vendor_register_events(void) pmu_vendor_events_table[i].archid == arch_id) { current_pmu_hw_event_map = pmu_vendor_events_table[i].hw_event_map; current_pmu_cache_event_map = pmu_vendor_events_table[i].cache_event_map; + riscv_cdeleg_pmu_event_group.attrs = + pmu_vendor_events_table[i].attrs_events; break; } } From patchwork Thu Feb 6 07:23:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13962534 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9ADDCC02196 for ; Thu, 6 Feb 2025 07:47:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=7etuPpkxZxtnGVR7GnydWAsSVWeMFhwaLHv5NX0LnJc=; b=QPuN+H155BFq3W qcLvBGRdJwmwMxppXjoU3Ey3M3IcqS9FWxHWa+M0CX76E17ZXHqsvSrYARXGR0KzDb9V0dEJhdaPl uXpiUyjaZq0Zgb+ptDxi5X/vu7wSBBy9KBGKvnM+kYSvCcKrLl5UMc3qyN4N2jb8t5o6b8SUfVufy YBwwSZxOLchsxfkUETEQqlOW41YY+fm/WdeeZkNM9ghF8OYo5zsKYv6gHIPpbUJJxmAp0w69W5gWU zEzTiT5sH39DH79KYbfhJy/UpO8Y546l5pHh19e7p+GDACEeyXJGLBKzEY1NRDNLZcMZ0xS8BYFWz DzbGakIROCDieElpneaA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfwbG-00000005dn0-3Voh; Thu, 06 Feb 2025 07:47:02 +0000 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfwEj-00000005YLe-0oRM for linux-riscv@lists.infradead.org; Thu, 06 Feb 2025 07:23:46 +0000 Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-2fa0c039d47so302809a91.1 for ; Wed, 05 Feb 2025 23:23:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1738826624; x=1739431424; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=j+uvKlLnv4557Icjif9h7ezpBJYOQndwpRbHYJUOt04=; b=murxL00NC2opG11rgDM7LVAQkMvXHX/P5zusStgbaObaHlfAH7fd3wTJQSflcmfSE7 nKpXo0vBBKXfDcM4DS7ijd51B78T2hX4n5NlUpKBzrwu6+xHYEGI+Kd2KdBBreTcY21A 7MkQhrJ/TuVYX+STCaWbkPNC40znU0XgnFYJkUDwyLOn/GbRjLb75uwzFb1VJzUwJnid bJPKbKLa8XFYNZpruF9E2nXHtN+8l4UclaQUIJyXycP/Hy30hP5y/rCCBrJx93M8ckNo 18plBj/XA7fMhHJ5RVU+JfCXhTueEZobj+V+iYi+nHrlDua3tFqwvZbmC3fciE3j3X0D MYIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738826624; x=1739431424; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j+uvKlLnv4557Icjif9h7ezpBJYOQndwpRbHYJUOt04=; b=kxSir1fx8A/GBJYx0CGFbhnU3i9C1cpaYOk9DOaA3B37yiV/fWc9aTZyQw4ZptNcb9 q4mQ4AWgdBfHuifZjz2egqHX7NSOP4fZYRoPVd/YKPmbjQh0h+LwCvkOSDkLAARVPodY 2a1+gPvYIV1hfhG2dnOIoyZTFp0nTkfrZ13zVmlqxBwK+nrWKmGfJQTXtxa0awLtrp47 NsEDIFJksT978bZq4vmM6Utg1fLPJM2OZ+XDlYjFJj6S6Yb2ODSVS4U2XQDbIrDrqXom EsItrnrLYs4nldcYo2axpecKjfVnny2kevXrSYlRlwhnQgyzkIGfr4UT6VD6qJ1EDqU0 hANg== X-Gm-Message-State: AOJu0YzLrVLqWyF9/6iKIqDqAH+Du+h+WwZEOyp0/Z3/iqCvgEjyQ0Yt i6yBIK5Gf+LOHwb8RuVxlt5sBQ27kPxBYnPfY+ZteqSTwh8vqVmUN291wsPsto4= X-Gm-Gg: ASbGncsIjgi48u9kX6R+NDUQowrTdAUdvIxBINWCIdKWrXoYIRtCE+Oj2h9zI8DADry UXf9xK3vlwiDclH3CgwTdID+iUGT6zaIsX6Ha6XiXgjhr63padO6ZYB7+zWaNMXkY829GrhMjrx httZThm/ScxDd6q6FKM8BCCbmy9QnB02lCNITwaO9NtjqVnbXH0v4I0hhEmzsboFCZaeDC/ctLh R/vGiqeQibmHKnJF3DOSp90swwwvYrBEB8n20WL4i5rK7OUmJidfXRCtXiRF8xZS+YiQM5RRBLU cNegu3wbKp5KLuBsB3EanVGJ6I8e X-Google-Smtp-Source: AGHT+IHVvUPUTgP+795doXG0yWQz3ag++6JLrXz9noZOmxRc/vzTQhLTg6Ot+5lngwjxV29P2MJVrQ== X-Received: by 2002:a17:90a:dfc8:b0:2f5:63a:449c with SMTP id 98e67ed59e1d1-2f9e07fbf59mr9122811a91.28.1738826624682; Wed, 05 Feb 2025 23:23:44 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a72292sm630883a91.27.2025.02.05.23.23.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 23:23:44 -0800 (PST) From: Atish Patra Date: Wed, 05 Feb 2025 23:23:23 -0800 Subject: [PATCH v4 18/21] RISC-V: perf: Add Qemu virt machine events MIME-Version: 1.0 Message-Id: <20250205-counter_delegation-v4-18-835cfa88e3b1@rivosinc.com> References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> In-Reply-To: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_232345_307676_4498A1A8 X-CRM114-Status: GOOD ( 12.41 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Qemu virt machine supports a very minimal set of legacy perf events. Add them to the vendor table so that users can use them when counter delegation is enabled. Signed-off-by: Atish Patra --- arch/riscv/include/asm/vendorid_list.h | 4 ++++ drivers/perf/riscv_pmu_dev.c | 36 ++++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h index 2f2bb0c84f9a..ef22b03552bc 100644 --- a/arch/riscv/include/asm/vendorid_list.h +++ b/arch/riscv/include/asm/vendorid_list.h @@ -9,4 +9,8 @@ #define SIFIVE_VENDOR_ID 0x489 #define THEAD_VENDOR_ID 0x5b7 +#define QEMU_VIRT_VENDOR_ID 0x000 +#define QEMU_VIRT_IMPL_ID 0x000 +#define QEMU_VIRT_ARCH_ID 0x000 + #endif diff --git a/drivers/perf/riscv_pmu_dev.c b/drivers/perf/riscv_pmu_dev.c index dd4627055e7a..b315f361ae79 100644 --- a/drivers/perf/riscv_pmu_dev.c +++ b/drivers/perf/riscv_pmu_dev.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -384,7 +385,42 @@ struct riscv_vendor_pmu_events { .hw_event_map = _hw_event_map, .cache_event_map = _cache_event_map, \ .attrs_events = _attrs }, +/* QEMU virt PMU events */ +static const struct riscv_pmu_event qemu_virt_hw_event_map[PERF_COUNT_HW_MAX] = { + PERF_MAP_ALL_UNSUPPORTED, + [PERF_COUNT_HW_CPU_CYCLES] = {0x01, 0xFFFFFFF8}, + [PERF_COUNT_HW_INSTRUCTIONS] = {0x02, 0xFFFFFFF8} +}; + +static const struct riscv_pmu_event qemu_virt_cache_event_map[PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = { + PERF_CACHE_MAP_ALL_UNSUPPORTED, + [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = {0x10019, 0xFFFFFFF8}, + [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = {0x1001B, 0xFFFFFFF8}, + + [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = {0x10021, 0xFFFFFFF8}, +}; + +RVPMU_EVENT_CMASK_ATTR(cycles, cycles, 0x01, 0xFFFFFFF8); +RVPMU_EVENT_CMASK_ATTR(instructions, instructions, 0x02, 0xFFFFFFF8); +RVPMU_EVENT_CMASK_ATTR(dTLB-load-misses, dTLB_load_miss, 0x10019, 0xFFFFFFF8); +RVPMU_EVENT_CMASK_ATTR(dTLB-store-misses, dTLB_store_miss, 0x1001B, 0xFFFFFFF8); +RVPMU_EVENT_CMASK_ATTR(iTLB-load-misses, iTLB_load_miss, 0x10021, 0xFFFFFFF8); + +static struct attribute *qemu_virt_event_group[] = { + RVPMU_EVENT_ATTR_PTR(cycles), + RVPMU_EVENT_ATTR_PTR(instructions), + RVPMU_EVENT_ATTR_PTR(dTLB_load_miss), + RVPMU_EVENT_ATTR_PTR(dTLB_store_miss), + RVPMU_EVENT_ATTR_PTR(iTLB_load_miss), + NULL, +}; + static struct riscv_vendor_pmu_events pmu_vendor_events_table[] = { + RISCV_VENDOR_PMU_EVENTS(QEMU_VIRT_VENDOR_ID, QEMU_VIRT_ARCH_ID, QEMU_VIRT_IMPL_ID, + qemu_virt_hw_event_map, qemu_virt_cache_event_map, + qemu_virt_event_group) }; const struct riscv_pmu_event *current_pmu_hw_event_map; From patchwork Thu Feb 6 07:23:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13962535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 156DDC02196 for ; Thu, 6 Feb 2025 07:48:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KmaPGs8e8DXPfSsLgC7dscvDm4DoJQrSkcIY8tVmfec=; b=LMIgkbKmS4dOy8 o427KV88NoigJv2cqh1InUyk5m7kAiEMkE0DTvR7eOKUy+p72ELRPUzcfOMDzxhqLlpywDTDfpvJp yV0TbxovlU1CZJNjJtXKRYxqS7a9uxd2VVcUnYv39LBLOs1dZcXnMAiITtvwIHRhwTyUg8rOVl0sq pwqkj0pJAahuD+K8KJLdH2unKluP2l9nwTfy7f6IL3tRH351qYG1hTYI1Tn3RIdyuYoSGxJJ4LpBz yPJXHIW80K2JAcMUmSz2QW0vsTZbxfBDMNbpvQl9mFWtF9bHr2eo3JQwen4HM7z6d4M27pK2CnLUV hLY5nKm2Wrwpz/rmiy0A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfwcb-00000005e0I-2R3X; Thu, 06 Feb 2025 07:48:25 +0000 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfwEk-00000005YNh-35JO for linux-riscv@lists.infradead.org; Thu, 06 Feb 2025 07:23:47 +0000 Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-2f42992f608so812976a91.0 for ; Wed, 05 Feb 2025 23:23:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1738826626; x=1739431426; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=h0m90EFTzPOvQUeRyWgUOuFclvonVx+b+5YG0+Kl+Is=; b=25mAzrR6G6+LR9cot68yLUitPle0Lr9Oi67+cZSAQEQp5wvOtMg2HfuxNj/rc01F/i Jrpwz7Uk+8tWFRvMCiz91MuGosP7aGrTbwDocXBUUMetw1tEp9WdV+UNfG6Na5EYtxKP x9tDM8VaBdy4LVTjbeK/8GCCHP7PWULP4XcVxUfYKn2A9Ww367XmQO5ozUexaZvZFxAV xs0xUGi5m9/kPjGYXIau+EvkR+HU86HhqX/GgB30Eo9D1gBXZRH6va4sEWINT5M7HHF1 6tqwCGRvD9ieaJald3Z60cDJBH/lkRoDUevZ348Qjhf4cI4WLrzVRa3pkSy2nangNWOm pKGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738826626; x=1739431426; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h0m90EFTzPOvQUeRyWgUOuFclvonVx+b+5YG0+Kl+Is=; b=e4YDcPwcyFgDcZSFcHmuNMOAf0y+mNVfDiqLtglMM13EBQbTp6+BT/A0R4eWzrbre/ 8EOMoXCtqsgeUB6ofPOysTOy9OyHLFfg6n+tuCgAXTjzwpA+pzLQ9WzQD1VNeGgZ0kO1 o+xp/4uGn961cQJc9HF4g7F9yyUuQv9iNstKk3dIKeemt3qIRAbebZuBhMVyFFpNMxb/ Bay0wJlGa1sdNNcE2KR0YW9ZrHl0+1hDSp7nss6Uq6CXYVsaFg3MJE5UqSNguYzTkR6A SpZUHbMagNTGkjoOuWBZhFn72s6sn53Aao95QaQjFQgmYiNgoSuL1C5HMVGpXvjAML6S F0fw== X-Gm-Message-State: AOJu0Ywb8GyPZfB/H8GM3mg+D/OeeFSFbh5orVSaQiqo/B4SbzJGUrEb VhXzTgjtJZ5+F0wjaNoBe++7srcCuwKhk9N1gr/O1zLcX2aZF6dTUCuireJzOuY= X-Gm-Gg: ASbGncuq2lFVABGWTaNFJiT6Lz1ATSSVpyfztpL4wb8ECXfBuhCweiKJYlhMjeZvmUn BuDSQFDFbDqqiEM6PRN2Bv7CNYnvjtoA+Nxf9kNrUAXzqY9/JFp+FK8Fbybp6PFeU2GMIrCncV0 kuAqGp+Kvw2DDlhsxCNgPm96rCLE6vc8B6hDx7Wam6JL0cNRGfMz2GeSlA5eKZFLCWOXfO6HzYG u1JrARIpE0YFRgvLRIuvhyYSlawjbMsXtY6184z7vDVSN/hJWihf5BIe3TJ2wt1agQ/bvmXepPD L/x9A9wn1N0/o2rKI3RRFmmGfiLK X-Google-Smtp-Source: AGHT+IEr4tlm3eTboE2LI3UyhaNgjHemEhg+pKT/VKS7IwKjrB4u5O4IbJdLoprF/7S1D0FzPib5Yg== X-Received: by 2002:a17:90b:1e4d:b0:2f6:be57:49cd with SMTP id 98e67ed59e1d1-2f9e080012dmr8950112a91.25.1738826626207; Wed, 05 Feb 2025 23:23:46 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a72292sm630883a91.27.2025.02.05.23.23.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 23:23:45 -0800 (PST) From: Atish Patra Date: Wed, 05 Feb 2025 23:23:24 -0800 Subject: [PATCH v4 19/21] tools/perf: Support event code for arch standard events MIME-Version: 1.0 Message-Id: <20250205-counter_delegation-v4-19-835cfa88e3b1@rivosinc.com> References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> In-Reply-To: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_232346_800966_0540AEAF X-CRM114-Status: GOOD ( 15.89 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org RISC-V relies on the event encoding from the json file. That includes arch standard events. If event code is present, event is already updated with correct encoding. No need to update it again which results in losing the event encoding. Signed-off-by: Atish Patra --- tools/perf/pmu-events/arch/riscv/arch-standard.json | 10 ++++++++++ tools/perf/pmu-events/jevents.py | 4 +++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/arch/riscv/arch-standard.json b/tools/perf/pmu-events/arch/riscv/arch-standard.json new file mode 100644 index 000000000000..96e21f088558 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/arch-standard.json @@ -0,0 +1,10 @@ +[ + { + "EventName": "cycles", + "BriefDescription": "cycle executed" + }, + { + "EventName": "instructions", + "BriefDescription": "instruction retired" + } +] diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index 5fd906ac6642..28acd598dd7c 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -417,7 +417,9 @@ class JsonEvent: self.long_desc += extra_desc if arch_std: if arch_std.lower() in _arch_std_events: - event = _arch_std_events[arch_std.lower()].event + # No need to replace as evencode would have updated the event before + if not eventcode: + event = _arch_std_events[arch_std.lower()].event # Copy from the architecture standard event to self for undefined fields. for attr, value in _arch_std_events[arch_std.lower()].__dict__.items(): if hasattr(self, attr) and not getattr(self, attr): From patchwork Thu Feb 6 07:23:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13962647 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3ADFEC02194 for ; Thu, 6 Feb 2025 09:01:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=cCKaky2Vz8YRJ0nqhqq1zCrXJzzY5iOy21PZLvaWL6U=; b=BOuZwTnv8P+J0Q LUCjBzxL0dqVVT1WSzSyExIIA7quvc00EPVxEXilPz8+6o9Ncd3dy4z/zc2Na+FG8hd7xZUmLlGGY oaIVtAMnZWJX1cpqAHoI2w40BfdhRdCZifzHupoT04Kr2uWXALL2iWBmKBuX1rX5XRSJod0Up2yrb Qt6moQL7WtuivqOe9K/mkB5JUshI1HY+YyGC3pPVdvc5iYux02vT9LNMG4/Q666NIcAEf5eX5Y1Dz 7Qsb3N1KrGdfaMSvALwVWxcJME+lrVtAqu6ohCi+gdLe/m6axCgXjZgdv6l5HJ3x7OH2gYbNIr27c GvhlRcWA7EIa/PfNBTww==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfxl8-00000005m6V-1mj5; Thu, 06 Feb 2025 09:01:18 +0000 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfwEm-00000005YPT-1B54 for linux-riscv@lists.infradead.org; Thu, 06 Feb 2025 07:23:49 +0000 Received: by mail-pj1-x102c.google.com with SMTP id 98e67ed59e1d1-2f9d17ac130so746866a91.3 for ; Wed, 05 Feb 2025 23:23:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1738826628; x=1739431428; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=EEHs3b5phPFn3BF7F+ULl9Hz6SGERFY3irR7WbMG6GA=; b=f7/jHbAvKj0AJ7bnIUnvmip8pbymK1FCKAqeO030qoI5V5r/Y53DmAE+RVUgxp2cNX TGWsrdQ0FNpLnUfAPuAl/JG83MKoVcvjPkPbYFBQTenKO6UkzbC2Y6tupoZ8GvefhsHx R2y9oAwyL+hGkfgDbMMdA6qrym5UCnw89XJ03qOXac5U93Kzf8uCSr12bW8yTLtRlYyD xrpg9nAB2viERR4CQcJLMfRE9FpZfUeEg4aYstQVAQ8eKMBaJXndsX4ohoT6/nbIfvie HyqyVkloknqu7YduLiFTQhZzzy/2YYy+LEvzI3zGatU9mY1XoDViqROa+xcEUIS/UW1j hF/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738826628; x=1739431428; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EEHs3b5phPFn3BF7F+ULl9Hz6SGERFY3irR7WbMG6GA=; b=L/27U/+LO0ZroRX696VPfcKoDGJcbUaGllx43MbUAuOHCra+4Pf+v4Krd8XakmIfjO Zo80oEgtHc9F9Ly9Obwuqp5ZwFT7c9n/A32lkN7jtvMDW7IpXdV+44vQ0qXQxteeHEI1 QhFDSvcxr4fHI3fQiJrCraUSBJbohS8TgIWapwxCgncc9hVJwt9alXNMqjonxOfvvE4I AT3uFwrWbllnauQga1T4fKQ2MHwFHG0Fy+xZCxO8oU7yS63SLZcC0fV8fe+5U6yLI1tW wZg1cry2pwG8bQ7l+wc/kkz3I1DbV3N5t8razcTGI7ZwQ+pc0ZhkjFdmVGB/1Yb12u4y v3Tw== X-Gm-Message-State: AOJu0YxVHePkV7jRUSFtcbDZ1BbviiVcvTQPKaWtEplzPclbOhZKjTTY GjRoxg42tcaqtPl9fIQdlNBTpSKIFrwaZ2ugniVTXWKyU3X0Mtxk3uY9epz+GxQ= X-Gm-Gg: ASbGncvyo4xbbNkQiNujvWiLGkoibwCc6sp2WzSvum5oyWWOtCb9hE891Pb515whniy Qs/MY5lmpXpsKcJ11CfSMG0auze/WL0mhp2p7hQ1KH6dvP+6hdfbyfZ1OH3Vz22FI6wtUa82bW3 834jROUGaQ5I3kyW1tfZgYijXjzW0uwTvojqt6GpnSTz+MpYhXJeoaX2xMSgVOmI/g2txh+w5hQ 7PHz/fHOGfMpxkQItCTapouNkUKutlPkDizcDlCFKLP9xbay5SMXRlr32DBiZ06XhxSfDnGtr2y wkKVkLSkP9fYUMvmqDEn85kIZfTD X-Google-Smtp-Source: AGHT+IEP7EfP8VYTZfd5HpBEgA2d9buHDVtURDszS/7//CqJNqgdAtdkSc3vqiKyaUdxMxfHiRPc5Q== X-Received: by 2002:a17:90b:5108:b0:2ee:ba84:5cac with SMTP id 98e67ed59e1d1-2f9e0753cc2mr9646959a91.7.1738826627792; Wed, 05 Feb 2025 23:23:47 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a72292sm630883a91.27.2025.02.05.23.23.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 23:23:47 -0800 (PST) From: Atish Patra Date: Wed, 05 Feb 2025 23:23:25 -0800 Subject: [PATCH v4 20/21] tools/perf: Pass the Counter constraint values in the pmu events MIME-Version: 1.0 Message-Id: <20250205-counter_delegation-v4-20-835cfa88e3b1@rivosinc.com> References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> In-Reply-To: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_232348_434587_A9906665 X-CRM114-Status: GOOD ( 11.84 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org RISC-V doesn't have any standard event to counter mapping discovery mechanism in the ISA. The ISA defines 29 programmable counters and platforms can choose to implement any number of them and map any events to any counters. Thus, the perf tool need to inform the driver about the counter mapping of each events. The current perf infrastructure only parses the 'Counter' constraints in metrics. This patch extends that to pass in the pmu events so that any driver can retrieve those values via perf attributes if defined accordingly. Signed-off-by: Atish Patra --- tools/perf/pmu-events/jevents.py | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index 28acd598dd7c..c21945238469 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -274,6 +274,11 @@ class JsonEvent: return fixed[name.lower()] return event + def counter_list_to_bitmask(counterlist): + counter_ids = list(map(int, counterlist.split(','))) + bitmask = sum(1 << pos for pos in counter_ids) + return bitmask + def unit_to_pmu(unit: str) -> Optional[str]: """Convert a JSON Unit to Linux PMU name.""" if not unit or unit == "core": @@ -427,6 +432,10 @@ class JsonEvent: else: raise argparse.ArgumentTypeError('Cannot find arch std event:', arch_std) + if self.counters['list']: + bitmask = counter_list_to_bitmask(self.counters['list']) + event += f',counterid_mask={bitmask:#x}' + self.event = real_event(self.name, event) def __repr__(self) -> str: From patchwork Thu Feb 6 07:23:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 13962559 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 027C7C02198 for ; Thu, 6 Feb 2025 07:52:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=42QoaekAwbVx60wX8VhJuf9C1xjt72dboGmlQk3PTq4=; b=qL8ezRHAfSQGhL 7/AKUJzBJXvLtcWNZ66S8HJZjPPZQuZgk7kXMvSCSjyvecmeJy4LsoUdVQ7/QSc9X7WOwPqRK4CJj gxklgyS3JLjJbG6FqDhCjPEgWiFeeH45KcWU3NhADYjtQMjxmHIk2SehXXWw+5htiq1U+I798jyKD 6atWTfgyPS+7fGi3esBbwf5tl0qmBQ7yR3hOh0/S1pepD27rwycBqjlXf/07HYhm6UZ03fPWdmG5B CXPl6zs2KWQ/mPODUhEHPohztmEsaSorWYlSqJCcY7QRR4mu1tEgcW5+85mDnEYkp8DhxJ5DWlbx0 jVLdRSIApFhIEZY6hFlw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfwgb-00000005eSK-0fVP; Thu, 06 Feb 2025 07:52:33 +0000 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfwEo-00000005YRP-1SzX for linux-riscv@lists.infradead.org; Thu, 06 Feb 2025 07:23:52 +0000 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-21f3c119fe6so3460585ad.0 for ; Wed, 05 Feb 2025 23:23:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1738826629; x=1739431429; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=3rXBekgxwrWqHmt4oM/pU0sf9hDrHDVKf/jA5yAU2uU=; b=BuZs+lEKBVcWiu2LLFu/Lx5WOeoBy3GOuVoYY+61FUXXOqd4IMKF+N6AEn2tqvg0Uy yuuayJjxjkOVmFkNEF1+aS2VDI4IPmnJYEGDmVdFDQHycmx+9seUwnsJ/zVAKL61KU3S ZBnK3SCXOMeaIQAIkxv88SbPliSy3ysbfvrp6IwqR3xDXnM96NGPg8MGQ2qtQqkNA54T Xaj4P5jb7ZEAJhWJWeO7PzRz+uQsfR3becOInQVWiCAiKKjM7hbdfhZQYjGhqHTXhao7 9CUUzl3AW3y9L3/HClzRGT5aUjjH6asYfaSszmdEZh62clR85GSMCPMOdzH6cEgP9Hvx h/nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738826629; x=1739431429; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3rXBekgxwrWqHmt4oM/pU0sf9hDrHDVKf/jA5yAU2uU=; b=AiN5RKjgWjIsthQF0DuaVESPqqeZzY5HO98phoiuRsHHe8SqPtSAApnbX45mP/B4JO dE8CXNJX9ffMgNVIn9juoMRE00J+ZYbrm4EmI5E1b7k7FfT6EbwLZ1b8ZJYuoRQYSwO9 8OQ+kEb3LaICx4FBBjQKoOLahXnuoZV6nAZYgkv50pDeJH6sOLNgRuxZxCWGDtNUbzhe OAmbQdDDeTjzbmMI7t+j1YZEr0ZjjPAt022sb9UYze+b+fnTenDuGVzH9DJo14GgZf08 QF/ZclJsrFUAS1A/Vl2PU+YaiovcmuXR/o7ZaQX2skQwRWloKTCZGMMh6LczFno7FvaM BiEA== X-Gm-Message-State: AOJu0YyVJB/8Iud40aPJLMWjFHGlWQr0SJhOUk35GMZ0JEBWZ2HtKk0y 7/aM1EtKSQRagUpLOy4bfSNzJek7SGtYKDw1MSj2CFPQwwkmOf8Ql/3JAyM5slE= X-Gm-Gg: ASbGncuPTtaxro8C27R2cv5wR6zuS1BYttlohB69yW6llxLB4moHiXOfD9/reExo8At 1lmsrDyulYRWFmiRem5SZXRiH67+UuLQkk25TtQ/Y+vAC55iwU3Eqz5NlOWJaS13L1uNS+oyx8w zcJXyyO9ox6DAje/izdFOpKKJ3wUqcVg74XG5dHGZq5AUXnzDogBDIZEmMrwACKrNzKIFIJrrz9 5r+wbTPp7HvZJ1xbfg1y4EGL3+eA2PGvEe5Xr7oIb6i232Sll/mWaek5cNjH1/gnpAyNerRPPtr hBz8shAVcxW44Qz1H+nMfjU4lpLb X-Google-Smtp-Source: AGHT+IEa71V3dAQMzlW1coBP9GpcYnAZy8MgrA6Jkwq3aId/xS02HFJyHmPPn3F7l6BTr74BjlvPKQ== X-Received: by 2002:a17:903:1a06:b0:215:7719:24f6 with SMTP id d9443c01a7336-21f17e7472bmr101410705ad.23.1738826629449; Wed, 05 Feb 2025 23:23:49 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a72292sm630883a91.27.2025.02.05.23.23.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 23:23:49 -0800 (PST) From: Atish Patra Date: Wed, 05 Feb 2025 23:23:26 -0800 Subject: [PATCH v4 21/21] Sync empty-pmu-events.c with autogenerated one MIME-Version: 1.0 Message-Id: <20250205-counter_delegation-v4-21-835cfa88e3b1@rivosinc.com> References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> In-Reply-To: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_232350_443112_D9F122D9 X-CRM114-Status: GOOD ( 10.00 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Signed-off-by: Atish Patra --- tools/perf/pmu-events/empty-pmu-events.c | 144 +++++++++++++++---------------- 1 file changed, 72 insertions(+), 72 deletions(-) diff --git a/tools/perf/pmu-events/empty-pmu-events.c b/tools/perf/pmu-events/empty-pmu-events.c index 3a7ec31576f5..22f0463dc522 100644 --- a/tools/perf/pmu-events/empty-pmu-events.c +++ b/tools/perf/pmu-events/empty-pmu-events.c @@ -36,42 +36,42 @@ static const char *const big_c_string = /* offset=1127 */ "bp_l1_btb_correct\000branch\000L1 BTB Correction\000event=0x8a\000\00000\000\000\000" /* offset=1187 */ "bp_l2_btb_correct\000branch\000L2 BTB Correction\000event=0x8b\000\00000\000\000\000" /* offset=1247 */ "l3_cache_rd\000cache\000L3 cache access, read\000event=0x40\000\00000\000Attributable Level 3 cache access, read\000\000" -/* offset=1343 */ "segment_reg_loads.any\000other\000Number of segment register loads\000event=6,period=200000,umask=0x80\000\00000\000\0000,1\000" -/* offset=1446 */ "dispatch_blocked.any\000other\000Memory cluster signals to block micro-op dispatch for any reason\000event=9,period=200000,umask=0x20\000\00000\000\0000,1\000" -/* offset=1580 */ "eist_trans\000other\000Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions\000event=0x3a,period=200000\000\00000\000\0000,1\000" -/* offset=1699 */ "hisi_sccl,ddrc\000" -/* offset=1714 */ "uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\000event=2\000\00000\000DDRC write commands\000\000" -/* offset=1801 */ "uncore_cbox\000" -/* offset=1813 */ "unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\000event=0x22,umask=0x81\000\00000\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\0000,1\000" -/* offset=2048 */ "event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=0xe0\000\00000\000UNC_CBO_HYPHEN\000\000" -/* offset=2114 */ "event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=0xc0\000\00000\000UNC_CBO_TWO_HYPH\000\000" -/* offset=2186 */ "hisi_sccl,l3c\000" -/* offset=2200 */ "uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000event=7\000\00000\000Total read hits\000\000" -/* offset=2281 */ "uncore_imc_free_running\000" -/* offset=2305 */ "uncore_imc_free_running.cache_miss\000uncore\000Total cache misses\000event=0x12\000\00000\000Total cache misses\000\000" -/* offset=2401 */ "uncore_imc\000" -/* offset=2412 */ "uncore_imc.cache_hits\000uncore\000Total cache hits\000event=0x34\000\00000\000Total cache hits\000\000" -/* offset=2491 */ "uncore_sys_ddr_pmu\000" -/* offset=2510 */ "sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\000event=0x2b\000v8\00000\000\000\000" -/* offset=2584 */ "uncore_sys_ccn_pmu\000" -/* offset=2603 */ "sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\000config=0x2c\0000x01\00000\000\000\000" -/* offset=2678 */ "uncore_sys_cmn_pmu\000" -/* offset=2697 */ "sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache misses in first lookup result (high priority)\000eventid=1,type=5\000(434|436|43c|43a).*\00000\000\000\000" -/* offset=2838 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000" -/* offset=2860 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\000\000\000\000\000\000\000\00000" -/* offset=2923 */ "Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000" -/* offset=3089 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000" -/* offset=3153 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000" -/* offset=3220 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_cycles\000\000\000\000\000\000\000\00000" -/* offset=3291 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000" -/* offset=3385 */ "DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000\000\000\000\000\000\000\00000" -/* offset=3519 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\000\000\000\000\000\000\000\00000" -/* offset=3583 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_All)\000\000\000\000\000\000\000\00000" -/* offset=3651 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2_All)\000\000\000\000\000\000\000\00000" -/* offset=3721 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\00000" -/* offset=3743 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\00000" -/* offset=3765 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\00000" -/* offset=3785 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duration_time\000\000\000\000\000\000\000\00000" +/* offset=1343 */ "segment_reg_loads.any\000other\000Number of segment register loads\000event=6,period=200000,umask=0x80,counterid_mask=0x3\000\00000\000\0000,1\000" +/* offset=1465 */ "dispatch_blocked.any\000other\000Memory cluster signals to block micro-op dispatch for any reason\000event=9,period=200000,umask=0x20,counterid_mask=0x3\000\00000\000\0000,1\000" +/* offset=1618 */ "eist_trans\000other\000Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions\000event=0x3a,period=200000,counterid_mask=0x3\000\00000\000\0000,1\000" +/* offset=1756 */ "hisi_sccl,ddrc\000" +/* offset=1771 */ "uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\000event=2\000\00000\000DDRC write commands\000\000" +/* offset=1858 */ "uncore_cbox\000" +/* offset=1870 */ "unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\000event=0x22,umask=0x81,counterid_mask=0x3\000\00000\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\0000,1\000" +/* offset=2124 */ "event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=0xe0\000\00000\000UNC_CBO_HYPHEN\000\000" +/* offset=2190 */ "event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=0xc0\000\00000\000UNC_CBO_TWO_HYPH\000\000" +/* offset=2262 */ "hisi_sccl,l3c\000" +/* offset=2276 */ "uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000event=7\000\00000\000Total read hits\000\000" +/* offset=2357 */ "uncore_imc_free_running\000" +/* offset=2381 */ "uncore_imc_free_running.cache_miss\000uncore\000Total cache misses\000event=0x12\000\00000\000Total cache misses\000\000" +/* offset=2477 */ "uncore_imc\000" +/* offset=2488 */ "uncore_imc.cache_hits\000uncore\000Total cache hits\000event=0x34\000\00000\000Total cache hits\000\000" +/* offset=2567 */ "uncore_sys_ddr_pmu\000" +/* offset=2586 */ "sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\000event=0x2b\000v8\00000\000\000\000" +/* offset=2660 */ "uncore_sys_ccn_pmu\000" +/* offset=2679 */ "sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\000config=0x2c\0000x01\00000\000\000\000" +/* offset=2754 */ "uncore_sys_cmn_pmu\000" +/* offset=2773 */ "sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache misses in first lookup result (high priority)\000eventid=1,type=5\000(434|436|43c|43a).*\00000\000\000\000" +/* offset=2914 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000" +/* offset=2936 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\000\000\000\000\000\000\000\00000" +/* offset=2999 */ "Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000" +/* offset=3165 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000" +/* offset=3229 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000" +/* offset=3296 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_cycles\000\000\000\000\000\000\000\00000" +/* offset=3367 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000" +/* offset=3461 */ "DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000\000\000\000\000\000\000\00000" +/* offset=3595 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\000\000\000\000\000\000\000\00000" +/* offset=3659 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_All)\000\000\000\000\000\000\000\00000" +/* offset=3727 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2_All)\000\000\000\000\000\000\000\00000" +/* offset=3797 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\00000" +/* offset=3819 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\00000" +/* offset=3841 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\00000" +/* offset=3861 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duration_time\000\000\000\000\000\000\000\00000" ; static const struct compact_pmu_event pmu_events__common_tool[] = { @@ -101,27 +101,27 @@ const struct pmu_table_entry pmu_events__common[] = { static const struct compact_pmu_event pmu_events__test_soc_cpu_default_core[] = { { 1127 }, /* bp_l1_btb_correct\000branch\000L1 BTB Correction\000event=0x8a\000\00000\000\000\000 */ { 1187 }, /* bp_l2_btb_correct\000branch\000L2 BTB Correction\000event=0x8b\000\00000\000\000\000 */ -{ 1446 }, /* dispatch_blocked.any\000other\000Memory cluster signals to block micro-op dispatch for any reason\000event=9,period=200000,umask=0x20\000\00000\000\0000,1\000 */ -{ 1580 }, /* eist_trans\000other\000Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions\000event=0x3a,period=200000\000\00000\000\0000,1\000 */ +{ 1465 }, /* dispatch_blocked.any\000other\000Memory cluster signals to block micro-op dispatch for any reason\000event=9,period=200000,umask=0x20,counterid_mask=0x3\000\00000\000\0000,1\000 */ +{ 1618 }, /* eist_trans\000other\000Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions\000event=0x3a,period=200000,counterid_mask=0x3\000\00000\000\0000,1\000 */ { 1247 }, /* l3_cache_rd\000cache\000L3 cache access, read\000event=0x40\000\00000\000Attributable Level 3 cache access, read\000\000 */ -{ 1343 }, /* segment_reg_loads.any\000other\000Number of segment register loads\000event=6,period=200000,umask=0x80\000\00000\000\0000,1\000 */ +{ 1343 }, /* segment_reg_loads.any\000other\000Number of segment register loads\000event=6,period=200000,umask=0x80,counterid_mask=0x3\000\00000\000\0000,1\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_hisi_sccl_ddrc[] = { -{ 1714 }, /* uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\000event=2\000\00000\000DDRC write commands\000\000 */ +{ 1771 }, /* uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\000event=2\000\00000\000DDRC write commands\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_hisi_sccl_l3c[] = { -{ 2200 }, /* uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000event=7\000\00000\000Total read hits\000\000 */ +{ 2276 }, /* uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000event=7\000\00000\000Total read hits\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_cbox[] = { -{ 2048 }, /* event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=0xe0\000\00000\000UNC_CBO_HYPHEN\000\000 */ -{ 2114 }, /* event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=0xc0\000\00000\000UNC_CBO_TWO_HYPH\000\000 */ -{ 1813 }, /* unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\000event=0x22,umask=0x81\000\00000\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\0000,1\000 */ +{ 2124 }, /* event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=0xe0\000\00000\000UNC_CBO_HYPHEN\000\000 */ +{ 2190 }, /* event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=0xc0\000\00000\000UNC_CBO_TWO_HYPH\000\000 */ +{ 1870 }, /* unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\000event=0x22,umask=0x81,counterid_mask=0x3\000\00000\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\0000,1\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_imc[] = { -{ 2412 }, /* uncore_imc.cache_hits\000uncore\000Total cache hits\000event=0x34\000\00000\000Total cache hits\000\000 */ +{ 2488 }, /* uncore_imc.cache_hits\000uncore\000Total cache hits\000event=0x34\000\00000\000Total cache hits\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_imc_free_running[] = { -{ 2305 }, /* uncore_imc_free_running.cache_miss\000uncore\000Total cache misses\000event=0x12\000\00000\000Total cache misses\000\000 */ +{ 2381 }, /* uncore_imc_free_running.cache_miss\000uncore\000Total cache misses\000event=0x12\000\00000\000Total cache misses\000\000 */ }; @@ -134,46 +134,46 @@ const struct pmu_table_entry pmu_events__test_soc_cpu[] = { { .entries = pmu_events__test_soc_cpu_hisi_sccl_ddrc, .num_entries = ARRAY_SIZE(pmu_events__test_soc_cpu_hisi_sccl_ddrc), - .pmu_name = { 1699 /* hisi_sccl,ddrc\000 */ }, + .pmu_name = { 1756 /* hisi_sccl,ddrc\000 */ }, }, { .entries = pmu_events__test_soc_cpu_hisi_sccl_l3c, .num_entries = ARRAY_SIZE(pmu_events__test_soc_cpu_hisi_sccl_l3c), - .pmu_name = { 2186 /* hisi_sccl,l3c\000 */ }, + .pmu_name = { 2262 /* hisi_sccl,l3c\000 */ }, }, { .entries = pmu_events__test_soc_cpu_uncore_cbox, .num_entries = ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_cbox), - .pmu_name = { 1801 /* uncore_cbox\000 */ }, + .pmu_name = { 1858 /* uncore_cbox\000 */ }, }, { .entries = pmu_events__test_soc_cpu_uncore_imc, .num_entries = ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_imc), - .pmu_name = { 2401 /* uncore_imc\000 */ }, + .pmu_name = { 2477 /* uncore_imc\000 */ }, }, { .entries = pmu_events__test_soc_cpu_uncore_imc_free_running, .num_entries = ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_imc_free_running), - .pmu_name = { 2281 /* uncore_imc_free_running\000 */ }, + .pmu_name = { 2357 /* uncore_imc_free_running\000 */ }, }, }; static const struct compact_pmu_event pmu_metrics__test_soc_cpu_default_core[] = { -{ 2838 }, /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000 */ -{ 3519 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\000\000\000\000\000\000\000\00000 */ -{ 3291 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000 */ -{ 3385 }, /* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000\000\000\000\000\000\000\00000 */ -{ 3583 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_All)\000\000\000\000\000\000\000\00000 */ -{ 3651 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2_All)\000\000\000\000\000\000\000\00000 */ -{ 2923 }, /* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000 */ -{ 2860 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\000\000\000\000\000\000\000\00000 */ -{ 3785 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duration_time\000\000\000\000\000\000\000\00000 */ -{ 3721 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\00000 */ -{ 3743 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\00000 */ -{ 3765 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\00000 */ -{ 3220 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_cycles\000\000\000\000\000\000\000\00000 */ -{ 3089 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000 */ -{ 3153 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000 */ +{ 2914 }, /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000 */ +{ 3595 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\000\000\000\000\000\000\000\00000 */ +{ 3367 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000 */ +{ 3461 }, /* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000\000\000\000\000\000\000\00000 */ +{ 3659 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_All)\000\000\000\000\000\000\000\00000 */ +{ 3727 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2_All)\000\000\000\000\000\000\000\00000 */ +{ 2999 }, /* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000 */ +{ 2936 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\000\000\000\000\000\000\000\00000 */ +{ 3861 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duration_time\000\000\000\000\000\000\000\00000 */ +{ 3797 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\00000 */ +{ 3819 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\00000 */ +{ 3841 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\00000 */ +{ 3296 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_cycles\000\000\000\000\000\000\000\00000 */ +{ 3165 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000 */ +{ 3229 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000 */ }; @@ -186,13 +186,13 @@ const struct pmu_table_entry pmu_metrics__test_soc_cpu[] = { }; static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_ccn_pmu[] = { -{ 2603 }, /* sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\000config=0x2c\0000x01\00000\000\000\000 */ +{ 2679 }, /* sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\000config=0x2c\0000x01\00000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_cmn_pmu[] = { -{ 2697 }, /* sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache misses in first lookup result (high priority)\000eventid=1,type=5\000(434|436|43c|43a).*\00000\000\000\000 */ +{ 2773 }, /* sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache misses in first lookup result (high priority)\000eventid=1,type=5\000(434|436|43c|43a).*\00000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_ddr_pmu[] = { -{ 2510 }, /* sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\000event=0x2b\000v8\00000\000\000\000 */ +{ 2586 }, /* sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\000event=0x2b\000v8\00000\000\000\000 */ }; @@ -200,17 +200,17 @@ const struct pmu_table_entry pmu_events__test_soc_sys[] = { { .entries = pmu_events__test_soc_sys_uncore_sys_ccn_pmu, .num_entries = ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_ccn_pmu), - .pmu_name = { 2584 /* uncore_sys_ccn_pmu\000 */ }, + .pmu_name = { 2660 /* uncore_sys_ccn_pmu\000 */ }, }, { .entries = pmu_events__test_soc_sys_uncore_sys_cmn_pmu, .num_entries = ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_cmn_pmu), - .pmu_name = { 2678 /* uncore_sys_cmn_pmu\000 */ }, + .pmu_name = { 2754 /* uncore_sys_cmn_pmu\000 */ }, }, { .entries = pmu_events__test_soc_sys_uncore_sys_ddr_pmu, .num_entries = ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_ddr_pmu), - .pmu_name = { 2491 /* uncore_sys_ddr_pmu\000 */ }, + .pmu_name = { 2567 /* uncore_sys_ddr_pmu\000 */ }, }, };