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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Feb 2025 08:33:20.8531 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ad0c470a-aec4-4232-fee4-08dd4688e9d6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468C.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4424 Add Collaborative Processor Performance Control feature flag for AMD processors. amd-cppc is the AMD CPU performance scaling driver that introduces a new CPU frequency control mechanism on modern AMD APU and CPU series. There are two types of hardware implementations: "Full MSR Support" and "Shared Memory Support". Right now, xen will only implement "Full MSR Support", and this new feature flag indicates whether processor has this feature or not. Signed-off-by: Penny Zheng Reviewed-by: Jan Beulich --- v1 -> v2: - Remove A flag, as the feature is Xen-only --- xen/arch/x86/include/asm/cpufeature.h | 1 + xen/include/public/arch-x86/cpufeatureset.h | 1 + 2 files changed, 2 insertions(+) diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/asm/cpufeature.h index 3a06b6f297..6935703e71 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -170,6 +170,7 @@ static inline bool boot_cpu_has(unsigned int feat) #define cpu_has_amd_ssbd boot_cpu_has(X86_FEATURE_AMD_SSBD) #define cpu_has_virt_ssbd boot_cpu_has(X86_FEATURE_VIRT_SSBD) #define cpu_has_ssb_no boot_cpu_has(X86_FEATURE_SSB_NO) +#define cpu_has_cppc boot_cpu_has(X86_FEATURE_CPPC) #define cpu_has_auto_ibrs boot_cpu_has(X86_FEATURE_AUTO_IBRS) /* CPUID level 0x00000007:0.edx */ diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 16207e3817..cc6e984a88 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -265,6 +265,7 @@ XEN_CPUFEATURE(AMD_PPIN, 8*32+23) /* Protected Processor Inventory Number XEN_CPUFEATURE(AMD_SSBD, 8*32+24) /*S MSR_SPEC_CTRL.SSBD available */ XEN_CPUFEATURE(VIRT_SSBD, 8*32+25) /*! MSR_VIRT_SPEC_CTRL.SSBD */ XEN_CPUFEATURE(SSB_NO, 8*32+26) /*A Hardware not vulnerable to SSB */ +XEN_CPUFEATURE(CPPC, 8*32+27) /* Collaborative Processor Performance Control */ XEN_CPUFEATURE(PSFD, 8*32+28) /*S MSR_SPEC_CTRL.PSFD */ XEN_CPUFEATURE(BTC_NO, 8*32+29) /*A Hardware not vulnerable to Branch Type Confusion */ XEN_CPUFEATURE(IBPB_RET, 8*32+30) /*A IBPB clears RSB/RAS too. */ From patchwork Thu Feb 6 08:32:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Penny, Zheng" X-Patchwork-Id: 13962604 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0A5A6C02198 for ; Thu, 6 Feb 2025 08:33:42 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.882556.1292679 (Exim 4.92) (envelope-from ) id 1tfxKG-0001AE-FT; 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pr=C From: Penny Zheng To: CC: , , Penny Zheng , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Anthony PERARD , "Michal Orzel" , Julien Grall , "Stefano Stabellini" Subject: [PATCH v2 02/11] xen/x86: introduce new sub-hypercall to propagate CPPC data Date: Thu, 6 Feb 2025 16:32:46 +0800 Message-ID: <20250206083255.1296363-3-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250206083255.1296363-1-Penny.Zheng@amd.com> References: <20250206083255.1296363-1-Penny.Zheng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000468B:EE_|DS0PR12MB8294:EE_ X-MS-Office365-Filtering-Correlation-Id: e6b7305a-0514-4307-5c83-08dd4688eb76 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Feb 2025 08:33:23.5596 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e6b7305a-0514-4307-5c83-08dd4688eb76 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468B.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8294 In order to provide backward compatibility with existing governors that represent performance as frequencies, like ondemand, the _CPC table can optionally provide processor frequency range values, Lowest frequency and Norminal frequency, to let OS use Lowest Frequency/ Performance and Nominal Frequency/Performance as anchor points to create linear mapping of CPPC abstract performance to CPU frequency. As Xen is uncapable of parsing the ACPI dynamic table, this commit introduces a new sub-hypercall to propagate required CPPC data from dom0 kernel. Signed-off-by: Penny Zheng --- v1 -> v2: - Remove unnecessary figure braces - Pointer-to-const for print_CPPC and set_cppc_pminfo - Structure allocation shall use xvzalloc() - Unnecessary memcpy(), and change it to a (type safe) structure assignment - Add comment for struct xen_processor_cppc, and keep the chosen fields in the order _CPC has them - Obey to alphabetic sorting, and prefix compat structures with ? instead of ! --- xen/arch/x86/platform_hypercall.c | 4 ++ xen/arch/x86/x86_64/cpufreq.c | 2 + xen/drivers/cpufreq/cpufreq.c | 48 +++++++++++++++++++++++ xen/include/acpi/cpufreq/processor_perf.h | 1 + xen/include/public/platform.h | 16 ++++++++ xen/include/xen/pmstat.h | 1 + xen/include/xlat.lst | 1 + 7 files changed, 73 insertions(+) diff --git a/xen/arch/x86/platform_hypercall.c b/xen/arch/x86/platform_hypercall.c index 67f851237d..735c71b0e7 100644 --- a/xen/arch/x86/platform_hypercall.c +++ b/xen/arch/x86/platform_hypercall.c @@ -572,6 +572,10 @@ ret_t do_platform_op( break; } + case XEN_PM_CPPC: + ret = set_cppc_pminfo(op->u.set_pminfo.id, &op->u.set_pminfo.u.cppc_data); + break; + default: ret = -EINVAL; break; diff --git a/xen/arch/x86/x86_64/cpufreq.c b/xen/arch/x86/x86_64/cpufreq.c index e4f3d5b436..aa72037401 100644 --- a/xen/arch/x86/x86_64/cpufreq.c +++ b/xen/arch/x86/x86_64/cpufreq.c @@ -26,6 +26,8 @@ #include #include +CHECK_processor_cppc; + CHECK_processor_px; DEFINE_XEN_GUEST_HANDLE(compat_processor_px_t); diff --git a/xen/drivers/cpufreq/cpufreq.c b/xen/drivers/cpufreq/cpufreq.c index 4a103c6de9..f5e8bfa09e 100644 --- a/xen/drivers/cpufreq/cpufreq.c +++ b/xen/drivers/cpufreq/cpufreq.c @@ -40,6 +40,7 @@ #include #include #include +#include #include #include @@ -458,6 +459,53 @@ static void print_PPC(unsigned int platform_limit) printk("\t_PPC: %d\n", platform_limit); } +static void print_CPPC(const struct xen_processor_cppc *cppc_data) +{ + printk("\t_CPC: highest_perf=%u, lowest_perf=%u, " + "nominal_perf=%u, lowest_nonlinear_perf=%u, " + "nominal_freq=%uMhz, lowest_freq=%uMhz\n", + cppc_data->highest_perf, cppc_data->lowest_perf, + cppc_data->nominal_perf, cppc_data->lowest_nonlinear_perf, + cppc_data->nominal_freq, cppc_data->lowest_freq); +} + +int set_cppc_pminfo(uint32_t acpi_id, const struct xen_processor_cppc *cppc_data) +{ + int ret = 0, cpuid; + struct processor_pminfo *pm_info; + + cpuid = get_cpu_id(acpi_id); + if ( cpuid < 0 || !cppc_data ) + { + ret = -EINVAL; + goto out; + } + if ( cpufreq_verbose ) + printk("Set CPU acpi_id(%d) cpuid(%d) CPPC State info:\n", + acpi_id, cpuid); + + pm_info = processor_pminfo[cpuid]; + if ( !pm_info ) + { + pm_info = xvzalloc(struct processor_pminfo); + if ( !pm_info ) + { + ret = -ENOMEM; + goto out; + } + processor_pminfo[cpuid] = pm_info; + } + pm_info->acpi_id = acpi_id; + pm_info->id = cpuid; + pm_info->cppc_data = *cppc_data; + + if ( cpufreq_verbose ) + print_CPPC(&pm_info->cppc_data); + + out: + return ret; +} + int set_px_pminfo(uint32_t acpi_id, struct xen_processor_performance *perf) { int ret = 0, cpu; diff --git a/xen/include/acpi/cpufreq/processor_perf.h b/xen/include/acpi/cpufreq/processor_perf.h index 301104e16f..cfa0fed647 100644 --- a/xen/include/acpi/cpufreq/processor_perf.h +++ b/xen/include/acpi/cpufreq/processor_perf.h @@ -37,6 +37,7 @@ struct processor_pminfo { uint32_t acpi_id; uint32_t id; struct processor_performance perf; + struct xen_processor_cppc cppc_data; }; extern struct processor_pminfo *processor_pminfo[NR_CPUS]; diff --git a/xen/include/public/platform.h b/xen/include/public/platform.h index 2725b8d104..b8daa8fc42 100644 --- a/xen/include/public/platform.h +++ b/xen/include/public/platform.h @@ -363,6 +363,7 @@ DEFINE_XEN_GUEST_HANDLE(xenpf_getidletime_t); #define XEN_PM_PX 1 #define XEN_PM_TX 2 #define XEN_PM_PDC 3 +#define XEN_PM_CPPC 4 /* Px sub info type */ #define XEN_PX_PCT 1 @@ -432,6 +433,20 @@ struct xen_processor_px { typedef struct xen_processor_px xen_processor_px_t; DEFINE_XEN_GUEST_HANDLE(xen_processor_px_t); +/* + * Subset _CPC fields useful for CPPC-compatible cpufreq + * driver's initialization + */ +struct xen_processor_cppc { + uint32_t highest_perf; + uint32_t nominal_perf; + uint32_t lowest_nonlinear_perf; + uint32_t lowest_perf; + uint32_t lowest_freq; + uint32_t nominal_freq; +}; +typedef struct xen_processor_cppc xen_processor_cppc_t; + struct xen_psd_package { uint64_t num_entries; uint64_t revision; @@ -465,6 +480,7 @@ struct xenpf_set_processor_pminfo { struct xen_processor_power power;/* Cx: _CST/_CSD */ struct xen_processor_performance perf; /* Px: _PPC/_PCT/_PSS/_PSD */ XEN_GUEST_HANDLE(uint32) pdc; /* _PDC */ + xen_processor_cppc_t cppc_data; /*_CPC */ } u; }; typedef struct xenpf_set_processor_pminfo xenpf_set_processor_pminfo_t; diff --git a/xen/include/xen/pmstat.h b/xen/include/xen/pmstat.h index 8350403e95..d2fe74ef0b 100644 --- a/xen/include/xen/pmstat.h +++ b/xen/include/xen/pmstat.h @@ -5,6 +5,7 @@ #include /* for struct xen_processor_power */ #include /* for struct pm_cx_stat */ +int set_cppc_pminfo(uint32_t cpu, const struct xen_processor_cppc *cppc_data); int set_px_pminfo(uint32_t acpi_id, struct xen_processor_performance *perf); long set_cx_pminfo(uint32_t acpi_id, struct xen_processor_power *power); diff --git a/xen/include/xlat.lst b/xen/include/xlat.lst index 3c7b6c6830..20201c1667 100644 --- a/xen/include/xlat.lst +++ b/xen/include/xlat.lst @@ -162,6 +162,7 @@ ! pct_register platform.h ! power_register platform.h +? processor_cppc platform.h ? processor_csd platform.h ! processor_cx platform.h ! processor_flags platform.h From patchwork Thu Feb 6 08:32:47 2025 Content-Type: text/plain; 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h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=HIYAHS617XWb70f28NLKG8AMMu6VOMiSFmi1uNOolgQ=; b=2fwg0Wt3AoMVaEltT5LhoSEjbYVnHuNHXUuasiFdJzTZnxgErTJ/BMjh5ZBwRPMBVZU0AzBgL+9zuBW7kWrs654aRDQ2oKp2HlxFHNcA3vWZVGMd/9XO5cXSUJvU4nKPAb3xQDYsCfYVrjzst8VCtXKJ3EETiJOkYlGG/0+V8wM= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Penny Zheng To: CC: , , Penny Zheng , Andrew Cooper , "Anthony PERARD" , Michal Orzel , "Jan Beulich" , Julien Grall , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , "Stefano Stabellini" Subject: [PATCH v2 03/11] xen/x86: introduce "cpufreq=amd-cppc" xen cmdline Date: Thu, 6 Feb 2025 16:32:47 +0800 Message-ID: <20250206083255.1296363-4-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250206083255.1296363-1-Penny.Zheng@amd.com> References: <20250206083255.1296363-1-Penny.Zheng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000468E:EE_|IA1PR12MB6260:EE_ X-MS-Office365-Filtering-Correlation-Id: 6217dd0e-791c-46ca-8ded-08dd4688ed4d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Feb 2025 08:33:26.6632 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6217dd0e-791c-46ca-8ded-08dd4688ed4d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6260 Users need to set "cpufreq=amd-cppc" in xen cmdline to enable amd-cppc driver, which selects ACPI Collaborative Performance and Power Control (CPPC) on supported AMD hardware to provide a finer grained frequency control mechanism. `verbose` option can also be included to support verbose print. When users setting "cpufreq=amd-cppc", a new amd-cppc driver shall be registered and used. Actual implmentation will be introduced in the following commits. Signed-off-by: Penny Zheng --- v1 -> v2: - Obey to alphabetic sorting and also strict it with CONFIG_AMD - Remove unnecessary empty comment line - Use __initconst_cf_clobber for pre-filled structure cpufreq_driver - Make new switch-case code apply to Hygon CPUs too - Change ENOSYS with EOPNOTSUPP - Blanks around binary operator - Change all amd_/-pstate defined values to amd_/-cppc --- docs/misc/xen-command-line.pandoc | 8 +++- xen/arch/x86/acpi/cpufreq/Makefile | 1 + xen/arch/x86/acpi/cpufreq/amd-cppc.c | 64 ++++++++++++++++++++++++++++ xen/arch/x86/acpi/cpufreq/cpufreq.c | 32 +++++++++++++- xen/arch/x86/platform_hypercall.c | 6 +++ xen/drivers/cpufreq/cpufreq.c | 13 +++++- xen/include/acpi/cpufreq/cpufreq.h | 4 ++ xen/include/public/platform.h | 1 + xen/include/public/sysctl.h | 1 + 9 files changed, 125 insertions(+), 5 deletions(-) create mode 100644 xen/arch/x86/acpi/cpufreq/amd-cppc.c diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc index 9bbd00baef..78cfb8a02e 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -515,7 +515,7 @@ If set, force use of the performance counters for oprofile, rather than detectin available support. ### cpufreq -> `= none | {{ | xen } { [:[powersave|performance|ondemand|userspace][,[]][,[]]] } [,verbose]} | dom0-kernel | hwp[:[][,verbose]]` +> `= none | {{ | xen } { [:[powersave|performance|ondemand|userspace][,[]][,[]]] } [,verbose]} | dom0-kernel | hwp[:[][,verbose]] | amd-cppc[:[verbose]]` > Default: `xen` @@ -526,7 +526,7 @@ choice of `dom0-kernel` is deprecated and not supported by all Dom0 kernels. * `` and `` are integers which represent max and min processor frequencies respectively. * `verbose` option can be included as a string or also as `verbose=` - for `xen`. It is a boolean for `hwp`. + for `xen`. It is a boolean for `hwp` and `amd-cppc`. * `hwp` selects Hardware-Controlled Performance States (HWP) on supported Intel hardware. HWP is a Skylake+ feature which provides better CPU power management. The default is disabled. If `hwp` is selected, but hardware @@ -534,6 +534,10 @@ choice of `dom0-kernel` is deprecated and not supported by all Dom0 kernels. * `` is a boolean to enable Hardware Duty Cycling (HDC). HDC enables the processor to autonomously force physical package components into idle state. The default is enabled, but the option only applies when `hwp` is enabled. +* `amd-cppc` selects ACPI Collaborative Performance and Power Control (CPPC) + on supported AMD hardware to provide finer grained frequency control mechanism. + The default is disabled. If `amd-cppc` is selected, but hardware support + is not available, Xen will fallback to cpufreq=xen. There is also support for `;`-separated fallback options: `cpufreq=hwp;xen,verbose`. This first tries `hwp` and falls back to `xen` if diff --git a/xen/arch/x86/acpi/cpufreq/Makefile b/xen/arch/x86/acpi/cpufreq/Makefile index e7dbe434a8..a2ba34bda0 100644 --- a/xen/arch/x86/acpi/cpufreq/Makefile +++ b/xen/arch/x86/acpi/cpufreq/Makefile @@ -1,4 +1,5 @@ obj-$(CONFIG_INTEL) += acpi.o +obj-$(CONFIG_AMD) += amd-cppc.o obj-y += cpufreq.o obj-$(CONFIG_INTEL) += hwp.o obj-$(CONFIG_AMD) += powernow.o diff --git a/xen/arch/x86/acpi/cpufreq/amd-cppc.c b/xen/arch/x86/acpi/cpufreq/amd-cppc.c new file mode 100644 index 0000000000..2dca4a00f3 --- /dev/null +++ b/xen/arch/x86/acpi/cpufreq/amd-cppc.c @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * amd-cppc.c - AMD Processor CPPC Frequency Driver + * + * Copyright (C) 2025 Advanced Micro Devices, Inc. All Rights Reserved. + * + * Author: Penny Zheng + * + * AMD CPPC cpufreq driver introduces a new CPU performance scaling design + * for AMD processors using the ACPI Collaborative Performance and Power + * Control (CPPC) feature which provides finer grained frequency control range. + */ + +#include +#include +#include + +static bool __init amd_cppc_handle_option(const char *s, const char *end) +{ + int ret; + + ret = parse_boolean("verbose", s, end); + if ( ret >= 0 ) + { + cpufreq_verbose = ret; + return true; + } + + return false; +} + +int __init amd_cppc_cmdline_parse(const char *s, const char *e) +{ + do + { + const char *end = strpbrk(s, ",;"); + + if ( !amd_cppc_handle_option(s, end) ) + { + printk(XENLOG_WARNING + "cpufreq/amd-cppc: option '%.*s' not recognized\n", + (int)((end ?: e) - s), s); + + return -EINVAL; + } + + s = end ? ++end : end; + } while ( s && s < e ); + + return 0; +} + +static const struct cpufreq_driver __initconst_cf_clobber amd_cppc_cpufreq_driver = +{ + .name = XEN_AMD_CPPC_DRIVER_NAME, +}; + +int __init amd_cppc_register_driver(void) +{ + if ( !cpu_has_cppc ) + return -ENODEV; + + return cpufreq_register_driver(&amd_cppc_cpufreq_driver); +} diff --git a/xen/arch/x86/acpi/cpufreq/cpufreq.c b/xen/arch/x86/acpi/cpufreq/cpufreq.c index 61e98b67bd..4bcaca1a01 100644 --- a/xen/arch/x86/acpi/cpufreq/cpufreq.c +++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c @@ -148,6 +148,9 @@ static int __init cf_check cpufreq_driver_init(void) case CPUFREQ_none: ret = 0; break; + default: + printk(XENLOG_WARNING "Unsupported cpufreq driver for vendor Intel\n"); + break; } if ( ret != -ENODEV ) @@ -157,7 +160,34 @@ static int __init cf_check cpufreq_driver_init(void) case X86_VENDOR_AMD: case X86_VENDOR_HYGON: - ret = IS_ENABLED(CONFIG_AMD) ? powernow_register_driver() : -ENODEV; + if ( !IS_ENABLED(CONFIG_AMD) ) + { + ret = -ENODEV; + break; + } + ret = -ENOENT; + + for ( unsigned int i = 0; i < cpufreq_xen_cnt; i++ ) + { + switch ( cpufreq_xen_opts[i] ) + { + case CPUFREQ_xen: + ret = powernow_register_driver(); + break; + case CPUFREQ_amd_cppc: + ret = amd_cppc_register_driver(); + break; + case CPUFREQ_none: + ret = 0; + break; + default: + printk(XENLOG_WARNING "Unsupported cpufreq driver for vendor AMD\n"); + break; + } + + if ( ret != -ENODEV ) + break; + } break; } } diff --git a/xen/arch/x86/platform_hypercall.c b/xen/arch/x86/platform_hypercall.c index 735c71b0e7..3d10827930 100644 --- a/xen/arch/x86/platform_hypercall.c +++ b/xen/arch/x86/platform_hypercall.c @@ -573,6 +573,12 @@ ret_t do_platform_op( } case XEN_PM_CPPC: + if ( !(xen_processor_pmbits & XEN_PROCESSOR_PM_CPPC) ) + { + ret = -EOPNOTSUPP; + break; + } + ret = set_cppc_pminfo(op->u.set_pminfo.id, &op->u.set_pminfo.u.cppc_data); break; diff --git a/xen/drivers/cpufreq/cpufreq.c b/xen/drivers/cpufreq/cpufreq.c index f5e8bfa09e..c0c6dc4c42 100644 --- a/xen/drivers/cpufreq/cpufreq.c +++ b/xen/drivers/cpufreq/cpufreq.c @@ -85,7 +85,7 @@ static int __init cf_check setup_cpufreq_option(const char *str) if ( choice < 0 && !cmdline_strcmp(str, "dom0-kernel") ) { - xen_processor_pmbits &= ~XEN_PROCESSOR_PM_PX; + xen_processor_pmbits &= ~(XEN_PROCESSOR_PM_PX | XEN_PROCESSOR_PM_CPPC); cpufreq_controller = FREQCTL_dom0_kernel; opt_dom0_vcpus_pin = 1; return 0; @@ -93,7 +93,7 @@ static int __init cf_check setup_cpufreq_option(const char *str) if ( choice == 0 || !cmdline_strcmp(str, "none") ) { - xen_processor_pmbits &= ~XEN_PROCESSOR_PM_PX; + xen_processor_pmbits &= ~(XEN_PROCESSOR_PM_PX | XEN_PROCESSOR_PM_CPPC); cpufreq_controller = FREQCTL_none; return 0; } @@ -131,6 +131,15 @@ static int __init cf_check setup_cpufreq_option(const char *str) if ( arg[0] && arg[1] ) ret = hwp_cmdline_parse(arg + 1, end); } + else if ( choice < 0 && !cmdline_strcmp(str, "amd-cppc") ) + { + xen_processor_pmbits |= XEN_PROCESSOR_PM_CPPC; + cpufreq_controller = FREQCTL_xen; + cpufreq_xen_opts[cpufreq_xen_cnt++] = CPUFREQ_amd_cppc; + ret = 0; + if ( arg[0] && arg[1] ) + ret = amd_cppc_cmdline_parse(arg + 1, end); + } else ret = -EINVAL; diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/cpufreq.h index 3f1b05a02e..a6fb10ea27 100644 --- a/xen/include/acpi/cpufreq/cpufreq.h +++ b/xen/include/acpi/cpufreq/cpufreq.h @@ -28,6 +28,7 @@ enum cpufreq_xen_opt { CPUFREQ_none, CPUFREQ_xen, CPUFREQ_hwp, + CPUFREQ_amd_cppc, }; extern enum cpufreq_xen_opt cpufreq_xen_opts[2]; extern unsigned int cpufreq_xen_cnt; @@ -267,4 +268,7 @@ int set_hwp_para(struct cpufreq_policy *policy, int acpi_cpufreq_register(void); +int amd_cppc_cmdline_parse(const char *s, const char *e); +int amd_cppc_register_driver(void); + #endif /* __XEN_CPUFREQ_PM_H__ */ diff --git a/xen/include/public/platform.h b/xen/include/public/platform.h index b8daa8fc42..11d30c894e 100644 --- a/xen/include/public/platform.h +++ b/xen/include/public/platform.h @@ -357,6 +357,7 @@ DEFINE_XEN_GUEST_HANDLE(xenpf_getidletime_t); #define XEN_PROCESSOR_PM_CX 1 #define XEN_PROCESSOR_PM_PX 2 #define XEN_PROCESSOR_PM_TX 4 +#define XEN_PROCESSOR_PM_CPPC 8 /* cmd type */ #define XEN_PM_CX 0 diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h index b0fec271d3..42997252ef 100644 --- a/xen/include/public/sysctl.h +++ b/xen/include/public/sysctl.h @@ -423,6 +423,7 @@ struct xen_set_cppc_para { uint32_t activity_window; }; +#define XEN_AMD_CPPC_DRIVER_NAME "amd-cppc" #define XEN_HWP_DRIVER_NAME "hwp" /* From patchwork Thu Feb 6 08:32:48 2025 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Feb 2025 08:33:28.8391 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 88db1faa-49b2-45d4-9194-08dd4688ee99 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004687.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4087 When _CPC table could not provide processor frequency range values for OS governor, we need to read processor max frequency as anchor point. For AMD processors, we export max frequency value from amd_log_freq() Signed-off-by: Penny Zheng --- v1 -> v2: - new commit --- xen/arch/x86/cpu/amd.c | 7 +++++++ xen/arch/x86/include/asm/amd.h | 1 + 2 files changed, 8 insertions(+) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 597b0f073d..489e092815 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -56,6 +56,8 @@ bool __initdata amd_virt_spec_ctrl; static bool __read_mostly fam17_c6_disabled; +DEFINE_PER_CPU_READ_MOSTLY(uint64_t, max_freq_mhz); + static inline int rdmsr_amd_safe(unsigned int msr, unsigned int *lo, unsigned int *hi) { @@ -669,7 +671,12 @@ void amd_log_freq(const struct cpuinfo_x86 *c) printk("CPU%u: %lu ... %lu MHz\n", smp_processor_id(), FREQ(lo), FREQ(hi)); else + { printk("CPU%u: %lu MHz\n", smp_processor_id(), FREQ(lo)); + return; + } + + per_cpu(max_freq_mhz, smp_processor_id()) = FREQ(hi); #undef FREQ } diff --git a/xen/arch/x86/include/asm/amd.h b/xen/arch/x86/include/asm/amd.h index 9c9599a622..96367ba646 100644 --- a/xen/arch/x86/include/asm/amd.h +++ b/xen/arch/x86/include/asm/amd.h @@ -174,4 +174,5 @@ bool amd_setup_legacy_ssbd(void); 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pr=C From: Penny Zheng To: CC: , , Penny Zheng , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH v2 05/11] xen/x86: introduce a new amd cppc driver for cpufreq scaling Date: Thu, 6 Feb 2025 16:32:49 +0800 Message-ID: <20250206083255.1296363-6-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250206083255.1296363-1-Penny.Zheng@amd.com> References: <20250206083255.1296363-1-Penny.Zheng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004687:EE_|MN0PR12MB5834:EE_ X-MS-Office365-Filtering-Correlation-Id: bb1c3972-8afa-4e38-1ebf-08dd4688efec X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?utf-8?q?0BR1jSQKBY3J6JHgjoZiUjHcq7ezi1c?= =?utf-8?q?Ov8XIFYrYvahtvRXRtYjwdPt5X5mWUtoTsbX3RMWn1xPKO1dlfpGf9ob6YU1O+m1P?= =?utf-8?q?uOaN/e8PYY4Lh8twzhHO7195RgIqol8enuMQ7+PGUrvnHPjc2Vfjj5scEwzVghp/a?= =?utf-8?q?i3OS5KyydqVU83FrAsBTM807ZPg449VntD4n1aaQP28pO+d0l0pPKk4yY1FNdh0Ru?= =?utf-8?q?8RqX63IpUnZwH/3h5eMYG05d3kU1th2P917IVH+f5R62YylKaThsU7eQ2uo7Y/kGE?= =?utf-8?q?d57YvSJnQn9LkX0c8IGDdqf8KVe0+ErGPUIkJkOXktzTctR2DRTl154DToajaU4E+?= =?utf-8?q?ugYozXZ0cmUAhTp+md/NsUOI+V6Wl0PJv8zxWZVeP+7gKKjHlorKcXTu8BejCakMH?= =?utf-8?q?HHeQWXCbagnKxaGgWw4fGlck3cbxeTSrF9MaVF3pFefQlbDS36q0gc66TmjDnqM8X?= =?utf-8?q?yxRwoT5JNfvIDTtHI8WZcdGVMQ0NtHZzdxydd7UNpmJAPi0lDc9TheZV6FYBrlBy9?= =?utf-8?q?N1X10+AS4r4HQYpNXV10xzRTMTvDl2CgYJZ73aTcwxSzaZ3Akp7picKCt7x/QXzS/?= =?utf-8?q?vOsYYzMu33gYjv2zelGLs0xy/rjNTNIziKN8ddbS2wZJjtKJ5wcho3gjYT1muYKEv?= =?utf-8?q?uZ2GF4AMqXZnV1oG4Z3LjkOCKnzC7jmYjzCO2+GDmB2cAKNB3SSzAGkL0WXDXmZvB?= =?utf-8?q?jIvCjE8+PZ1pvA90jZE2IMzV6HGGa1wirFMszwaRKED5tPEzIWoHKYZClwkwNOonb?= =?utf-8?q?PWdgS0ZV6v/n9JGU/+PzmqnpW1so0b9U57ohKdz6l3UBp5zUA4cwhKapb8ojbtdgy?= =?utf-8?q?FWg07/qsAqZDEvdMLkQ7q6m3Hom0jm337i3FZVePq4B4Gb+cbmQyXp+zJeSCsn3yT?= =?utf-8?q?e6+4QHwsTKHJ771KuuhHjUoJObxPkEMCCfd1WhNeYP0uMXLywgTShCDO/E/YPU0NJ?= =?utf-8?q?EvM6XuOg2hVBDFVzFain2388WOfSmBb0cNjQF98Zhu1ueK2oaobGAvLVi6vw5DGqn?= =?utf-8?q?ZR5B7JKTySJNI69mRxzjTnG4Ab34Zszdc63NyGEFGG7V4s/JDZsU1B+ckWn5UVcEd?= =?utf-8?q?LHsPX/Ue2VoAJC7jz7rQaFrcWE7V3ecHQZa712bZRtOYindyu4gBBn0MTbVMvk2OE?= =?utf-8?q?OgsM4+bNjwaEOHJoYdtKqmIiuJN70jQ5+SNCCw0mWXff/W05r6KQ9h27f7K5sh8/k?= =?utf-8?q?re/jScAwFkojPtIzrvYIO7EnYPjYe/kVsiDp+YLl66TRv4hWPBBKivZ4+QnGLw2Rr?= =?utf-8?q?uqhcyICnz1KPz/U/90RR0IPynDhTIC/jdLh2+XJdM6I7CsFwN6Rto6trM6ulkxqV/?= =?utf-8?q?RyyfX69S3BdufERJQwvM+roj2vLn4sJVSv63k+q0PVTQ/mQOQtRMxVZKn5Uu+AdTp?= =?utf-8?q?yO3ux7UqI6P+eviCMbHe516G0wk3hGtchezFxozf5S41AIdQZEhDzs=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Feb 2025 08:33:31.0579 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bb1c3972-8afa-4e38-1ebf-08dd4688efec X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004687.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5834 amd-cppc is the AMD CPU performance scaling driver that introduces a new CPU frequency control mechanism firstly on AMD Zen based CPU series. The new mechanism is based on Collaborative Processor Performance Control (CPPC) which is a finer grain frequency management than legacy ACPI hardware P-States. Current AMD CPU platforms are using the ACPI P-states driver to manage CPU frequency and clocks with switching only in 3 P-states. The new amd-cppc allows a more flexible, low-latency interface for Xen to directly communicate the performance hints to hardware. The first version "amd-cppc" could leverage common governors such as *ondemand*, *performance*, etc, to manage the performance hints. In the future, we will introduce an advanced active mode to enable autonomous performence level selection. Signed-off-by: Penny Zheng --- v1 -> v2: - re-construct union caps and req to have anonymous struct instead - avoid "else" when the earlier if() ends in an unconditional control flow statement - Add check to avoid chopping off set bits from cast - make pointers pointer-to-const wherever possible - remove noisy log - exclude families before 0x17 before CPPC-feature MSR op - remove useless variable helpers - use xvzalloc and XVFREE - refactor error handling as ENABLE bit can only be cleared by reset --- xen/arch/x86/acpi/cpufreq/amd-cppc.c | 388 +++++++++++++++++++++++++++ 1 file changed, 388 insertions(+) diff --git a/xen/arch/x86/acpi/cpufreq/amd-cppc.c b/xen/arch/x86/acpi/cpufreq/amd-cppc.c index 2dca4a00f3..f14e7a6638 100644 --- a/xen/arch/x86/acpi/cpufreq/amd-cppc.c +++ b/xen/arch/x86/acpi/cpufreq/amd-cppc.c @@ -13,7 +13,61 @@ #include #include +#include +#include #include +#include + +#define MSR_AMD_CPPC_CAP1 0xc00102b0 +#define MSR_AMD_CPPC_ENABLE 0xc00102b1 +#define AMD_CPPC_ENABLE BIT(0, ULL) +#define MSR_AMD_CPPC_REQ 0xc00102b3 + +#define amd_cppc_err(cpu, fmt, args...) \ + printk(XENLOG_ERR "AMD_CPPC: CPU%u error: " fmt, cpu, ## args) +#define amd_cppc_verbose(fmt, args...) \ +({ \ + if ( cpufreq_verbose ) \ + printk(XENLOG_DEBUG "AMD_CPPC: " fmt, ## args); \ +}) +#define amd_cppc_warn(fmt, args...) \ + printk(XENLOG_WARNING "AMD_CPPC: CPU%u warning: " fmt, cpu, ## args) + +struct amd_cppc_drv_data +{ + struct xen_processor_cppc *cppc_data; + union + { + uint64_t raw; + struct + { + unsigned int lowest_perf:8; + unsigned int lowest_nonlinear_perf:8; + unsigned int nominal_perf:8; + unsigned int highest_perf:8; + unsigned int :32; + }; + } caps; + union + { + uint64_t raw; + struct + { + unsigned int max_perf:8; + unsigned int min_perf:8; + unsigned int des_perf:8; + unsigned int epp:8; + unsigned int :32; + }; + } req; + int err; + + uint32_t max_freq; + uint32_t min_freq; + uint32_t nominal_freq; +}; + +static DEFINE_PER_CPU_READ_MOSTLY(struct amd_cppc_drv_data *, amd_cppc_drv_data); static bool __init amd_cppc_handle_option(const char *s, const char *end) { @@ -50,9 +104,343 @@ int __init amd_cppc_cmdline_parse(const char *s, const char *e) return 0; } +/* + * If CPPC lowest_freq and nominal_freq registers are exposed then we can + * use them to convert perf to freq and vice versa. The conversion is + * extrapolated as an affine function passing by the 2 points: + * - (Low perf, Low freq) + * - (Nominal perf, Nominal freq) + */ +static int amd_cppc_khz_to_perf(const struct amd_cppc_drv_data *data, unsigned int freq, uint8_t *perf) +{ + const struct xen_processor_cppc *cppc_data = data->cppc_data; + uint64_t mul, div, offset = 0, res; + + if ( freq == (cppc_data->nominal_freq * 1000) ) + { + *perf = data->caps.nominal_perf; + return 0; + } + + if ( freq == (cppc_data->lowest_freq * 1000) ) + { + *perf = data->caps.lowest_perf; + return 0; + } + + if ( (cppc_data->lowest_freq) && (cppc_data->nominal_freq) ) + { + mul = data->caps.nominal_perf - data->caps.lowest_perf; + div = cppc_data->nominal_freq - cppc_data->lowest_freq; + /* + * We don't need to convert to kHz for computing offset and can + * directly use nominal_freq and lowest_freq as the division + * will remove the frequency unit. + */ + div = div ?: 1; + offset = data->caps.nominal_perf - (mul * cppc_data->nominal_freq) / div; + } + else + { + /* Read Processor Max Speed(mhz) as anchor point */ + mul = data->caps.highest_perf; + div = this_cpu(max_freq_mhz); + if ( !div ) + return -EINVAL; + } + + res = offset + (mul * freq) / (div * 1000); + if ( res > UINT8_MAX ) + { + printk(XENLOG_ERR "Perf value exceeds maximum value 255: %lu\n", res); + return -EINVAL; + } + *perf = (uint8_t)res; + + return 0; +} + +static int amd_get_min_freq(const struct amd_cppc_drv_data *data, unsigned int *min_freq) +{ + const struct xen_processor_cppc *cppc_data = data->cppc_data; + uint64_t mul, div, res; + + if ( cppc_data->lowest_freq ) + { + /* Switch to khz */ + *min_freq = cppc_data->lowest_freq * 1000; + return 0; + } + + /* Read Processor Max Speed(mhz) as anchor point */ + mul = this_cpu(max_freq_mhz); + div = data->caps.highest_perf; + res = (mul * data->caps.lowest_perf * 1000) / div; + if ( res > UINT_MAX ) + { + printk(XENLOG_ERR "Min freq exceeds maximum value UINT_MAX: %lu\n", res); + return -EINVAL; + } + + *min_freq = (unsigned int)res; + return 0; +} + +static int amd_get_nominal_freq(const struct amd_cppc_drv_data *data, unsigned int *nom_freq) +{ + const struct xen_processor_cppc *cppc_data = data->cppc_data; + uint64_t mul, div, res; + + if ( cppc_data->nominal_freq ) + { + /* Switch to khz */ + *nom_freq = cppc_data->nominal_freq * 1000; + return 0; + } + + /* Read Processor Max Speed(mhz) as anchor point */ + mul = this_cpu(max_freq_mhz); + div = data->caps.highest_perf; + res = (mul * data->caps.nominal_perf * 1000) / div; + if ( res > UINT_MAX ) + { + printk(XENLOG_ERR "Nominal freq exceeds maximum value UINT_MAX: %lu\n", res); + return -EINVAL; + } + + *nom_freq = (unsigned int)res; + return 0; +} + +static int amd_get_max_freq(const struct amd_cppc_drv_data *data, unsigned int *max_freq) +{ + unsigned int nom_freq, boost_ratio; + int res; + + res = amd_get_nominal_freq(data, &nom_freq); + if ( res ) + return res; + + boost_ratio = (unsigned int)(data->caps.highest_perf / data->caps.nominal_perf); + *max_freq = nom_freq * boost_ratio; + + return 0; +} + +static int cf_check amd_cppc_cpufreq_verify(struct cpufreq_policy *policy) +{ + const struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data, policy->cpu); + + cpufreq_verify_within_limits(policy, data->min_freq, data->max_freq); + + return 0; +} + +static void amd_cppc_write_request_msrs(void *info) +{ + struct amd_cppc_drv_data *data = info; + + if ( wrmsr_safe(MSR_AMD_CPPC_REQ, data->req.raw) ) + { + data->err = -EINVAL; + return; + } + data->err = 0; +} + +static int cf_check amd_cppc_write_request(int cpu, uint8_t min_perf, + uint8_t des_perf, uint8_t max_perf) +{ + struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data, cpu); + uint64_t prev = data->req.raw; + + data->req.min_perf = min_perf; + data->req.max_perf = max_perf; + data->req.des_perf = des_perf; + + if ( prev == data->req.raw ) + return 0; + + on_selected_cpus(cpumask_of(cpu), amd_cppc_write_request_msrs, data, 1); + + return data->err; +} + +static int cf_check amd_cppc_cpufreq_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + unsigned int cpu = policy->cpu; + const struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data, cpu); + uint8_t des_perf; + int res; + + if ( unlikely(!target_freq) ) + return 0; + + res = amd_cppc_khz_to_perf(data, target_freq, &des_perf); + if ( res ) + return res; + + return amd_cppc_write_request(policy->cpu, data->caps.lowest_nonlinear_perf, + des_perf, data->caps.highest_perf); +} + +static void cf_check amd_cppc_init_msrs(void *info) +{ + struct cpufreq_policy *policy = info; + struct amd_cppc_drv_data *data = this_cpu(amd_cppc_drv_data); + uint64_t val; + unsigned int min_freq, nominal_freq, max_freq; + const struct cpuinfo_x86 *c = cpu_data + policy->cpu; + + /* Feature CPPC is firstly introduiced on Zen2 */ + if ( c->x86 < 0x17 ) + { + amd_cppc_err(policy->cpu, "Unsupported cpu family: %x\n", c->x86); + data->err = -EOPNOTSUPP; + return; + } + + /* Package level MSR */ + if ( rdmsr_safe(MSR_AMD_CPPC_ENABLE, val) ) + { + amd_cppc_err(policy->cpu, "rdmsr_safe(MSR_AMD_CPPC_ENABLE)\n"); + goto err; + } + + /* + * Only when Enable bit is on, the hardware will calculate the processor’s + * performance capabilities and initialize the performance level fields in + * the CPPC capability registers. + */ + if ( !(val & AMD_CPPC_ENABLE) ) + { + val |= AMD_CPPC_ENABLE; + if ( wrmsr_safe(MSR_AMD_CPPC_ENABLE, val) ) + { + amd_cppc_err(policy->cpu, "wrmsr_safe(MSR_AMD_CPPC_ENABLE, %lx)\n", val); + goto err; + } + } + + if ( rdmsr_safe(MSR_AMD_CPPC_CAP1, data->caps.raw) ) + { + amd_cppc_err(policy->cpu, "rdmsr_safe(MSR_AMD_CPPC_CAP1)\n"); + goto err; + } + + if ( data->caps.highest_perf == 0 || data->caps.lowest_perf == 0 || + data->caps.nominal_perf == 0 || data->caps.lowest_nonlinear_perf == 0 ) + { + amd_cppc_err(policy->cpu, + "Platform malfunction, read CPPC highest_perf: %u, lowest_perf: %u, nominal_perf: %u, lowest_nonlinear_perf: %u zero value\n", + data->caps.highest_perf, data->caps.lowest_perf, + data->caps.nominal_perf, data->caps.lowest_nonlinear_perf); + goto err; + } + + data->err = amd_get_min_freq(data, &min_freq); + if ( data->err ) + return; + + data->err = amd_get_nominal_freq(data, &nominal_freq); + if ( data->err ) + return; + + data->err = amd_get_max_freq(data, &max_freq); + if ( data->err ) + return; + + if ( min_freq > max_freq ) + { + amd_cppc_err(policy->cpu, "min_freq(%u) or max_freq(%u) value is incorrect\n", + min_freq, max_freq); + goto err; + } + + policy->min = min_freq; + policy->max = max_freq; + + policy->cpuinfo.min_freq = min_freq; + policy->cpuinfo.max_freq = max_freq; + policy->cpuinfo.perf_freq = nominal_freq; + policy->cur = nominal_freq; + + /* Initial processor data capability frequencies */ + data->min_freq = min_freq; + data->nominal_freq = nominal_freq; + data->max_freq = max_freq; + + return; + + err: + data->err = -EINVAL; +} + +/* + * The new AMD CPPC driver is different than legacy ACPI hardware P-State, + * which has a finer grain frequency range between the highest and lowest + * frequency. And boost frequency is actually the frequency which is mapped on + * highest performance ratio. The legacy P0 frequency is actually mapped on + * nominal performance ratio. + */ +static void amd_cppc_boost_init(struct cpufreq_policy *policy, const struct amd_cppc_drv_data *data) +{ + if ( data->caps.highest_perf <= data->caps.nominal_perf ) + return; + + policy->turbo = CPUFREQ_TURBO_ENABLED; +} + +static int cf_check amd_cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) +{ + unsigned int cpu = policy->cpu; + struct amd_cppc_drv_data *data; + + data = xvzalloc(struct amd_cppc_drv_data); + if ( !data ) + return -ENOMEM; + + data->cppc_data = &processor_pminfo[cpu]->cppc_data; + + per_cpu(amd_cppc_drv_data, cpu) = data; + + on_selected_cpus(cpumask_of(cpu), amd_cppc_init_msrs, policy, 1); + + if ( data->err ) + { + amd_cppc_err(cpu, "Could not initialize AMD CPPC MSR properly\n"); + per_cpu(amd_cppc_drv_data, cpu) = NULL; + XVFREE(data); + return -ENODEV; + } + + policy->governor = cpufreq_opt_governor ? : CPUFREQ_DEFAULT_GOVERNOR; + + amd_cppc_boost_init(policy, data); + + amd_cppc_verbose("CPU %u initialized with amd-cppc passive mode\n", policy->cpu); + return 0; +} + +static int cf_check amd_cppc_cpufreq_cpu_exit(struct cpufreq_policy *policy) +{ + struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data, policy->cpu); + + per_cpu(amd_cppc_drv_data, policy->cpu) = NULL; + XVFREE(data); + + return 0; +} + static const struct cpufreq_driver __initconst_cf_clobber amd_cppc_cpufreq_driver = { .name = XEN_AMD_CPPC_DRIVER_NAME, + .verify = amd_cppc_cpufreq_verify, + .target = amd_cppc_cpufreq_target, + .init = amd_cppc_cpufreq_cpu_init, + .exit = amd_cppc_cpufreq_cpu_exit, }; int __init amd_cppc_register_driver(void) From patchwork Thu Feb 6 08:32:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Penny, Zheng" X-Patchwork-Id: 13962606 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BCDB6C02196 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Feb 2025 08:33:32.9648 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 76d80e51-d403-4a52-17c6-08dd4688f10f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB9030 From: Penny Zheng amd-cppc on active mode bypasses the scaling governor layer, and provides its own P-state selection algorithms in hardware. Consequently, when it is used, the driver's -> setpolicy() callback is invoked to register per-CPU utilization update callbacks, not the ->target() callback. So, only when cpufreq_driver.setpolicy is NULL, we need to deliberately set old gov as NULL to trigger the according gov starting. Signed-off-by: Penny Zheng Reviewed-by: Jan Beulich --- v1 -> v2: - Change condition check to .setpolicy being NULL --- xen/drivers/cpufreq/cpufreq.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/xen/drivers/cpufreq/cpufreq.c b/xen/drivers/cpufreq/cpufreq.c index c0c6dc4c42..860ae32c8a 100644 --- a/xen/drivers/cpufreq/cpufreq.c +++ b/xen/drivers/cpufreq/cpufreq.c @@ -317,7 +317,13 @@ int cpufreq_add_cpu(unsigned int cpu) if (hw_all || (cpumask_weight(cpufreq_dom->map) == perf->domain_info.num_processors)) { memcpy(&new_policy, policy, sizeof(struct cpufreq_policy)); - policy->governor = NULL; + + /* + * Only when cpufreq_driver.setpolicy == NULL, we need to deliberately + * set old gov as NULL to trigger the according gov starting. + */ + if ( cpufreq_driver.setpolicy == NULL ) + policy->governor = NULL; cpufreq_cmdline_common_para(&new_policy); From patchwork Thu Feb 6 08:32:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Penny, Zheng" X-Patchwork-Id: 13962608 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C3415C02198 for ; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Penny Zheng To: CC: , , Penny Zheng , Andrew Cooper , "Anthony PERARD" , Michal Orzel , "Jan Beulich" , Julien Grall , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , "Stefano Stabellini" , Penny Zheng Subject: [PATCH v2 07/11] x86/cpufreq: add "cpufreq=amd-cppc,active" para Date: Thu, 6 Feb 2025 16:32:51 +0800 Message-ID: <20250206083255.1296363-8-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250206083255.1296363-1-Penny.Zheng@amd.com> References: <20250206083255.1296363-1-Penny.Zheng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004688:EE_|IA1PR12MB6188:EE_ X-MS-Office365-Filtering-Correlation-Id: 5d834f5c-fa6c-400f-75fd-08dd4688f345 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Feb 2025 08:33:36.6765 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d834f5c-fa6c-400f-75fd-08dd4688f345 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004688.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6188 From: Penny Zheng The amd-cppc driver may support multiple working modes, passive and active. Introduce `active` tag for users to explicitly select active mode and a new variable `opt_cpufreq_active` to keep track of which mode is currently enabled. Specific implementation will be introduced in the following commits. Signed-off-by: Penny Zheng --- v1 -> v2: - Remove pointless initializer - Move driver registration change to the next commit --- docs/misc/xen-command-line.pandoc | 8 +++++++- xen/arch/x86/acpi/cpufreq/amd-cppc.c | 9 +++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc index 78cfb8a02e..13f650270d 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -515,7 +515,7 @@ If set, force use of the performance counters for oprofile, rather than detectin available support. ### cpufreq -> `= none | {{ | xen } { [:[powersave|performance|ondemand|userspace][,[]][,[]]] } [,verbose]} | dom0-kernel | hwp[:[][,verbose]] | amd-cppc[:[verbose]]` +> `= none | {{ | xen } { [:[powersave|performance|ondemand|userspace][,[]][,[]]] } [,verbose]} | dom0-kernel | hwp[:[][,verbose]] | amd-cppc[:[active][,verbose]]` > Default: `xen` @@ -538,6 +538,12 @@ choice of `dom0-kernel` is deprecated and not supported by all Dom0 kernels. on supported AMD hardware to provide finer grained frequency control mechanism. The default is disabled. If `amd-cppc` is selected, but hardware support is not available, Xen will fallback to cpufreq=xen. +* `active` is a boolean to enable amd-cppc driver in active(autonomous) mode. + In this mode, users could provide a hint with energy performance preference + register to the hardware if they want to bias toward performance(0x0) or + energy efficiency(0xff), then CPPC power algorithm will calculate the runtime + workload and adjust the realtime cores frequency according to the power supply + and thermal, core voltage and some other hardware conditions. There is also support for `;`-separated fallback options: `cpufreq=hwp;xen,verbose`. This first tries `hwp` and falls back to `xen` if diff --git a/xen/arch/x86/acpi/cpufreq/amd-cppc.c b/xen/arch/x86/acpi/cpufreq/amd-cppc.c index f14e7a6638..1742c57170 100644 --- a/xen/arch/x86/acpi/cpufreq/amd-cppc.c +++ b/xen/arch/x86/acpi/cpufreq/amd-cppc.c @@ -33,6 +33,8 @@ #define amd_cppc_warn(fmt, args...) \ printk(XENLOG_WARNING "AMD_CPPC: CPU%u warning: " fmt, cpu, ## args) +static bool __ro_after_init opt_cpufreq_active; + struct amd_cppc_drv_data { struct xen_processor_cppc *cppc_data; @@ -80,6 +82,13 @@ static bool __init amd_cppc_handle_option(const char *s, const char *end) return true; } + ret = parse_boolean("active", s, end); + if ( ret >= 0 ) + { + opt_cpufreq_active = ret; + return true; + } + return false; } From patchwork Thu Feb 6 08:32:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Penny, Zheng" X-Patchwork-Id: 13962609 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7874AC02196 for ; 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Signed-off-by: Penny Zheng --- v1 -> v2: - new commit --- xen/arch/x86/acpi/cpufreq/hwp.c | 10 +++------- xen/include/acpi/cpufreq/cpufreq.h | 10 ++++++++++ 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/xen/arch/x86/acpi/cpufreq/hwp.c b/xen/arch/x86/acpi/cpufreq/hwp.c index 59b57a4cef..d5fa3d47ca 100644 --- a/xen/arch/x86/acpi/cpufreq/hwp.c +++ b/xen/arch/x86/acpi/cpufreq/hwp.c @@ -21,10 +21,6 @@ static bool __ro_after_init feature_hdc; static bool __ro_after_init opt_cpufreq_hdc = true; -#define HWP_ENERGY_PERF_MAX_PERFORMANCE 0 -#define HWP_ENERGY_PERF_BALANCE 0x80 -#define HWP_ENERGY_PERF_MAX_POWERSAVE 0xff - union hwp_request { struct @@ -597,7 +593,7 @@ int set_hwp_para(struct cpufreq_policy *policy, data->minimum = data->hw.lowest; data->maximum = data->hw.lowest; data->activity_window = 0; - data->energy_perf = HWP_ENERGY_PERF_MAX_POWERSAVE; + data->energy_perf = CPPC_ENERGY_PERF_MAX_POWERSAVE; data->desired = 0; break; @@ -605,7 +601,7 @@ int set_hwp_para(struct cpufreq_policy *policy, data->minimum = data->hw.highest; data->maximum = data->hw.highest; data->activity_window = 0; - data->energy_perf = HWP_ENERGY_PERF_MAX_PERFORMANCE; + data->energy_perf = CPPC_ENERGY_PERF_MAX_PERFORMANCE; data->desired = 0; break; @@ -613,7 +609,7 @@ int set_hwp_para(struct cpufreq_policy *policy, data->minimum = data->hw.lowest; data->maximum = data->hw.highest; data->activity_window = 0; - data->energy_perf = HWP_ENERGY_PERF_BALANCE; + data->energy_perf = CPPC_ENERGY_PERF_BALANCE; data->desired = 0; break; diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/cpufreq.h index a6fb10ea27..3c2b951830 100644 --- a/xen/include/acpi/cpufreq/cpufreq.h +++ b/xen/include/acpi/cpufreq/cpufreq.h @@ -253,6 +253,16 @@ void cpufreq_dbs_timer_resume(void); void intel_feature_detect(struct cpufreq_policy *policy); +/* + * If Energy Performance Preference(epp) is supported in the platform, + * OSPM may write a range of values from 0(performance preference) + * to 0xFF(energy efficiency perference) to control the platform's + * energy efficiency and performance optimization policies + */ +#define CPPC_ENERGY_PERF_MAX_PERFORMANCE 0 +#define CPPC_ENERGY_PERF_BALANCE 0x80 +#define CPPC_ENERGY_PERF_MAX_POWERSAVE 0xff + int hwp_cmdline_parse(const char *s, const char *e); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Feb 2025 08:33:41.3374 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b50249d8-9b3d-4c87-a61f-08dd4688f60c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468C.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7807 amd-cppc has 2 operation modes: autonomous (active) mode, non-autonomous (passive) mode. In active mode, platform ignores the requestd done in the Desired Performance Target register and takes into account only the values set to the minimum, maximum and energy performance preference(EPP) registers. The EPP is used in the CCLK DPM controller to drive the frequency that a core is going to operate during short periods of activity. The SOC EPP targets are configured on a scale from 0 to 255 where 0 represents maximum performance and 255 represents maximum efficiency. This commit implements one new AMD CPU frequency driver `amd-cppc-epp` for active mode. Signed-off-by: Penny Zheng --- v1 -> v2: - Remove redundant epp_mode - Remove pointless initializer - Define sole caller read_epp_init_once and epp_init value to read pre-defined BIOS epp value only once - Combine the commit "xen/cpufreq: introduce policy type when cpufreq_driver->setpolicy exists" --- xen/arch/x86/acpi/cpufreq/amd-cppc.c | 114 +++++++++++++++++++++++++-- xen/drivers/cpufreq/utility.c | 11 +++ xen/include/acpi/cpufreq/cpufreq.h | 12 +++ xen/include/public/sysctl.h | 1 + 4 files changed, 132 insertions(+), 6 deletions(-) diff --git a/xen/arch/x86/acpi/cpufreq/amd-cppc.c b/xen/arch/x86/acpi/cpufreq/amd-cppc.c index 1742c57170..241cce330b 100644 --- a/xen/arch/x86/acpi/cpufreq/amd-cppc.c +++ b/xen/arch/x86/acpi/cpufreq/amd-cppc.c @@ -34,6 +34,7 @@ printk(XENLOG_WARNING "AMD_CPPC: CPU%u warning: " fmt, cpu, ## args) static bool __ro_after_init opt_cpufreq_active; +static uint8_t __read_mostly epp_init; struct amd_cppc_drv_data { @@ -258,14 +259,27 @@ static void amd_cppc_write_request_msrs(void *info) } static int cf_check amd_cppc_write_request(int cpu, uint8_t min_perf, - uint8_t des_perf, uint8_t max_perf) + uint8_t des_perf, uint8_t max_perf, + int epp) { struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data, cpu); uint64_t prev = data->req.raw; data->req.min_perf = min_perf; data->req.max_perf = max_perf; - data->req.des_perf = des_perf; + if ( !opt_cpufreq_active ) + data->req.des_perf = des_perf; + else + { + data->req.des_perf = 0; + /* Get pre-defined BIOS value */ + if ( epp < 0 ) + data->req.epp = epp_init; + else if ( epp > UINT8_MAX ) + return -EINVAL; + else + data->req.epp = epp; + } if ( prev == data->req.raw ) return 0; @@ -292,7 +306,25 @@ static int cf_check amd_cppc_cpufreq_target(struct cpufreq_policy *policy, return res; return amd_cppc_write_request(policy->cpu, data->caps.lowest_nonlinear_perf, - des_perf, data->caps.highest_perf); + des_perf, data->caps.highest_perf, -1); +} + +static int read_epp_init_once(void) +{ + uint64_t val; + static bool read_once = false; + + if ( !read_once ) + { + if ( rdmsr_safe(MSR_AMD_CPPC_REQ, val) ) + return -EINVAL; + epp_init = (val >> 24) & 0xFF; + + /* Read pre-defined BIOS value once */ + read_once = true; + } + + return 0; } static void cf_check amd_cppc_init_msrs(void *info) @@ -381,7 +413,8 @@ static void cf_check amd_cppc_init_msrs(void *info) data->nominal_freq = nominal_freq; data->max_freq = max_freq; - return; + if ( !read_epp_init_once() ) + return; err: data->err = -EINVAL; @@ -402,7 +435,7 @@ static void amd_cppc_boost_init(struct cpufreq_policy *policy, const struct amd_ policy->turbo = CPUFREQ_TURBO_ENABLED; } -static int cf_check amd_cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) +static int amd_cppc_cpufreq_init_perf(struct cpufreq_policy *policy) { unsigned int cpu = policy->cpu; struct amd_cppc_drv_data *data; @@ -429,6 +462,17 @@ static int cf_check amd_cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) amd_cppc_boost_init(policy, data); + return 0; +} + +static int cf_check amd_cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) +{ + int ret; + + ret = amd_cppc_cpufreq_init_perf(policy); + if ( ret ) + return ret; + amd_cppc_verbose("CPU %u initialized with amd-cppc passive mode\n", policy->cpu); return 0; } @@ -443,6 +487,52 @@ static int cf_check amd_cppc_cpufreq_cpu_exit(struct cpufreq_policy *policy) return 0; } +static int cf_check amd_cppc_epp_cpu_init(struct cpufreq_policy *policy) +{ + int ret; + + ret = amd_cppc_cpufreq_init_perf(policy); + if ( ret ) + return ret; + + policy->policy = cpufreq_parse_policy(policy->governor); + + amd_cppc_verbose("CPU %u initialized with amd-cppc active mode\n", policy->cpu); + + return 0; +} + +static int amd_cppc_epp_update_limit(const struct cpufreq_policy *policy) +{ + const struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data, policy->cpu); + uint8_t max_perf, min_perf, des_perf; + int epp = -1; + + /* Initial min/max values for CPPC Performance Controls Register */ + max_perf = data->caps.highest_perf; + min_perf = data->caps.lowest_perf; + + /* CPPC EPP feature require to set zero to the desire perf bit */ + des_perf = 0; + + if ( policy->policy == CPUFREQ_POLICY_PERFORMANCE ) + { + /* Force the epp value to be zero for performance policy */ + epp = CPPC_ENERGY_PERF_MAX_PERFORMANCE; + min_perf = max_perf; + } + else if ( policy->policy == CPUFREQ_POLICY_POWERSAVE ) + /* Force the epp value to be 0xff for powersave policy */ + epp = CPPC_ENERGY_PERF_MAX_POWERSAVE; + + return amd_cppc_write_request(policy->cpu, min_perf, des_perf, max_perf, epp); +} + +static int cf_check amd_cppc_epp_set_policy(struct cpufreq_policy *policy) +{ + return amd_cppc_epp_update_limit(policy); +} + static const struct cpufreq_driver __initconst_cf_clobber amd_cppc_cpufreq_driver = { .name = XEN_AMD_CPPC_DRIVER_NAME, @@ -452,10 +542,22 @@ static const struct cpufreq_driver __initconst_cf_clobber amd_cppc_cpufreq_drive .exit = amd_cppc_cpufreq_cpu_exit, }; +static const struct cpufreq_driver __initconst_cf_clobber amd_cppc_epp_driver = +{ + .name = XEN_AMD_CPPC_EPP_DRIVER_NAME, + .verify = amd_cppc_cpufreq_verify, + .setpolicy = amd_cppc_epp_set_policy, + .init = amd_cppc_epp_cpu_init, + .exit = amd_cppc_cpufreq_cpu_exit, +}; + int __init amd_cppc_register_driver(void) { if ( !cpu_has_cppc ) return -ENODEV; - return cpufreq_register_driver(&amd_cppc_cpufreq_driver); + if ( !opt_cpufreq_active ) + return cpufreq_register_driver(&amd_cppc_cpufreq_driver); + else + return cpufreq_register_driver(&amd_cppc_epp_driver); } diff --git a/xen/drivers/cpufreq/utility.c b/xen/drivers/cpufreq/utility.c index e690a484f1..13342e8469 100644 --- a/xen/drivers/cpufreq/utility.c +++ b/xen/drivers/cpufreq/utility.c @@ -484,3 +484,14 @@ int __cpufreq_set_policy(struct cpufreq_policy *data, return __cpufreq_governor(data, CPUFREQ_GOV_LIMITS); } + +unsigned int cpufreq_parse_policy(const struct cpufreq_governor *gov) +{ + if ( !strncasecmp(gov->name, "performance", CPUFREQ_NAME_LEN) ) + return CPUFREQ_POLICY_PERFORMANCE; + + if ( !strncasecmp(gov->name, "powersave", CPUFREQ_NAME_LEN) ) + return CPUFREQ_POLICY_POWERSAVE; + + return CPUFREQ_POLICY_UNKNOWN; +} diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/cpufreq.h index 3c2b951830..fb42d61567 100644 --- a/xen/include/acpi/cpufreq/cpufreq.h +++ b/xen/include/acpi/cpufreq/cpufreq.h @@ -83,6 +83,7 @@ struct cpufreq_policy { int8_t turbo; /* tristate flag: 0 for unsupported * -1 for disable, 1 for enabled * See CPUFREQ_TURBO_* below for defines */ + unsigned int policy; }; DECLARE_PER_CPU(struct cpufreq_policy *, cpufreq_cpu_policy); @@ -133,6 +134,17 @@ extern int cpufreq_register_governor(struct cpufreq_governor *governor); extern struct cpufreq_governor *__find_governor(const char *governor); #define CPUFREQ_DEFAULT_GOVERNOR &cpufreq_gov_dbs +#define CPUFREQ_POLICY_UNKNOWN 0 +/* + * If cpufreq_driver->target() exists, the ->governor decides what frequency + * within the limits is used. If cpufreq_driver->setpolicy() exists, these + * two generic policies are available: + */ +#define CPUFREQ_POLICY_POWERSAVE 1 +#define CPUFREQ_POLICY_PERFORMANCE 2 + +unsigned int cpufreq_parse_policy(const struct cpufreq_governor *gov); + /* pass a target to the cpufreq driver */ extern int __cpufreq_driver_target(struct cpufreq_policy *policy, unsigned int target_freq, diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h index 42997252ef..fa431fd983 100644 --- a/xen/include/public/sysctl.h +++ b/xen/include/public/sysctl.h @@ -424,6 +424,7 @@ struct xen_set_cppc_para { }; #define XEN_AMD_CPPC_DRIVER_NAME "amd-cppc" +#define XEN_AMD_CPPC_EPP_DRIVER_NAME "amd-cppc-epp" #define XEN_HWP_DRIVER_NAME "hwp" /* From patchwork Thu Feb 6 08:32:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Penny, Zheng" X-Patchwork-Id: 13962616 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 58D19C02198 for ; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Penny Zheng To: CC: , , Penny Zheng , Anthony PERARD , "Penny Zheng" , Jan Beulich Subject: [PATCH v2 10/11] tools/xenpm: Print CPPC parameters for amd-cppc driver Date: Thu, 6 Feb 2025 16:32:54 +0800 Message-ID: <20250206083255.1296363-11-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250206083255.1296363-1-Penny.Zheng@amd.com> References: <20250206083255.1296363-1-Penny.Zheng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000468E:EE_|CY8PR12MB8315:EE_ X-MS-Office365-Filtering-Correlation-Id: f5835a08-4070-4871-cd88-08dd4688f76a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Feb 2025 08:33:43.6321 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f5835a08-4070-4871-cd88-08dd4688f76a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8315 From: Penny Zheng HWP, amd-cppc, amd-cppc-epp are all the implementation of ACPI CPPC (Collaborative Processor Performace Control), so we introduce cppc_mode flag to print CPPC-related para. And HWP and amd-cppc-epp are both governor-less driver, so we introduce hw_auto flag to bypass governor-related print. Signed-off-by: Penny Zheng Acked-by: Jan Beulich --- tools/misc/xenpm.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c index 336d246346..a7aeaea35e 100644 --- a/tools/misc/xenpm.c +++ b/tools/misc/xenpm.c @@ -790,9 +790,18 @@ static unsigned int calculate_activity_window(const xc_cppc_para_t *cppc, /* print out parameters about cpu frequency */ static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cpufreq) { - bool hwp = strcmp(p_cpufreq->scaling_driver, XEN_HWP_DRIVER_NAME) == 0; + bool cppc_mode = false, hw_auto = false; int i; + if ( !strcmp(p_cpufreq->scaling_driver, XEN_HWP_DRIVER_NAME) || + !strcmp(p_cpufreq->scaling_driver, XEN_AMD_CPPC_DRIVER_NAME) || + !strcmp(p_cpufreq->scaling_driver, XEN_AMD_CPPC_EPP_DRIVER_NAME) ) + cppc_mode = true; + + if ( !strcmp(p_cpufreq->scaling_driver, XEN_HWP_DRIVER_NAME) || + !strcmp(p_cpufreq->scaling_driver, XEN_AMD_CPPC_EPP_DRIVER_NAME) ) + hw_auto = true; + printf("cpu id : %d\n", cpuid); printf("affected_cpus :"); @@ -800,7 +809,7 @@ static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cpufreq) printf(" %d", p_cpufreq->affected_cpus[i]); printf("\n"); - if ( hwp ) + if ( hw_auto ) printf("cpuinfo frequency : base [%"PRIu32"] max [%"PRIu32"]\n", p_cpufreq->cpuinfo_min_freq, p_cpufreq->cpuinfo_max_freq); @@ -812,7 +821,7 @@ static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cpufreq) printf("scaling_driver : %s\n", p_cpufreq->scaling_driver); - if ( hwp ) + if ( cppc_mode ) { const xc_cppc_para_t *cppc = &p_cpufreq->u.cppc_para; @@ -838,7 +847,8 @@ static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cpufreq) cppc->desired, cppc->desired ? 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pr=C From: Penny Zheng To: CC: , , Penny Zheng , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH v2 11/11] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC xen_sysctl_pm_op for amd-cppc driver Date: Thu, 6 Feb 2025 16:32:55 +0800 Message-ID: <20250206083255.1296363-12-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250206083255.1296363-1-Penny.Zheng@amd.com> References: <20250206083255.1296363-1-Penny.Zheng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000468E:EE_|SN7PR12MB8819:EE_ X-MS-Office365-Filtering-Correlation-Id: 82fc6546-d286-459f-c024-08dd4688f8a0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: Io4nhfol9dciydy7fmRC4LlTvPcuHdHHX4btAqnS8UzwaQ45zmNokd/P9XFpcXo9D8FDXVpxmvlBGrPB5EamPS/LVWn4A0nnob/RyNVOE30wmcD6cpt1+PpvYVedUiYABQ0IDjq2q9KUEMo0QKDzxYSAiCgQz/GLVrCdt9rbNh8nkAh20zVKZsIqYII94H9hnH3HTON8nr3Ev3fpughkBfrlv9QdlnZ5sARPaPVC/hZYLnxizags0te2gfWdZ2Cg5fZ/61f83US9/Sg07kKJVIt1x+FCO94BwrYbgqWlHfD50yj4Y5owg+U9tvBbRdwtmYzuXE8whDj9Z5+TLOeLRdoiNu3IIgDIZn8j063PoVE256DoCgNxUuk5JMVXZ89m1P8JV7y7YZXpPQY6z54VAmyalSJFxCdqgfwm8sXFNIKsWxhWqTuzglcn5bFnG0bwzyF1dAUNEdkL25tz9Pn9b0KLhKbspkeHURthsrR3d7ICMIqizPpprlkSrLqcgffuH5G26ZUI9+d+EHAbU81Xz80bxc1iAg6CfcwnLJHWE3FjYZc+aJMvyzyPxpRdxjgLdR3TV1XFEoBiFP3Lxmj9URUYNm9/aCGRyiAJLB44LYPMHTcB09yKZi9OjlHiX0RRKtacGZs/eFg/uz4+N6RcgDA/Yq0BVaCFdY3yCEczpkB8QWA1F079KG3+DiLXKLTO4QwVUhdAO/Ert7x7LWVsnqonJcSywJvrhuxqYtSbPgYNPItivWB+w4Ft7JIINHRMclrPayyp+/3Ry+pc5giFTPZYcp77sXp4BLzyROnLppdwXegX6RbC30IWxO5bAa96va5CosQdGd9nCq0FsIMHP1eR3xpZA2fkelKChInEB9nHFP8Ma+gh2ECt3m9oU3eVKNv7YZ2aiWejPWLua7zNLT7sVBVJyxl7thTB5M2gMpYXSJ41pzFj9R8HAZ5Nr49k4lSDo/mEklFbGplfZ9YbN0KaK+66rt0T6+e5dAByM2njzw5pd6SEFT/eV3b8TVG7MDXKLD1KjEXmEDmG/H14NpqeoS8Wwp21X1qitJXC3C+WSWfGxczISQb+MOCx2muqTttRSceL8iVW4kbdcOrVJWlh4OXE+DR8tAM2uOY/VrGN5cn4lfV8LqA47JBkHHSgkU3i8uFbHuWyuqyK3gAngza60YjwEB/eTfISwZlZTWaznzCOA4s29guqxMLonB+4tb4Hk5hIVSkLKb0FDSUv6y14n7YiWh1DDZy/rO42Ztui1Py/uh0VnQwHQuf9PIhlfyunkwAFBKbSA9RkjSlLrSouynSTFvKW5ZKSkXU8XRnAA5bxkmj4eLE33ez7waaH0ZWGG9UiqeJGvA0QB2QYRofWxSI08Sc2Kej/GpQtSipkv6ZFfprmvmWfzy+riarmdf6Qb8Pd7vmdmvKWT3Ta+r7miUylNj37WxsZcNKqZgBRcarhY6ckl3m51OwbsKeiGisjJPyRA1Sc91QFbLhBytCoQ2TVpHfGD6Hhy7A7iLc= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Feb 2025 08:33:45.6634 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 82fc6546-d286-459f-c024-08dd4688f8a0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8819 Introduce helper set_amd_cppc_para and get_amd_cppc_para to SET/GET CPPC-related para for amd-cppc/amd-cppc-epp driver. Signed-off-by: Penny Zheng --- v1 -> v2: - Give the variable des_perf an initializer of 0 - Use the strncmp()s directly in the if() --- xen/arch/x86/acpi/cpufreq/amd-cppc.c | 115 +++++++++++++++++++++++++++ xen/drivers/acpi/pmstat.c | 20 ++++- xen/include/acpi/cpufreq/cpufreq.h | 5 ++ 3 files changed, 136 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/acpi/cpufreq/amd-cppc.c b/xen/arch/x86/acpi/cpufreq/amd-cppc.c index 241cce330b..0e43e32979 100644 --- a/xen/arch/x86/acpi/cpufreq/amd-cppc.c +++ b/xen/arch/x86/acpi/cpufreq/amd-cppc.c @@ -35,6 +35,7 @@ static bool __ro_after_init opt_cpufreq_active; static uint8_t __read_mostly epp_init; +static bool __ro_after_init amd_cppc_in_use; struct amd_cppc_drv_data { @@ -533,6 +534,114 @@ static int cf_check amd_cppc_epp_set_policy(struct cpufreq_policy *policy) return amd_cppc_epp_update_limit(policy); } +int get_amd_cppc_para(unsigned int cpu, + struct xen_cppc_para *cppc_para) +{ + const struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data, cpu); + + if ( data == NULL ) + return -ENODATA; + + cppc_para->features = 0; + cppc_para->lowest = data->caps.lowest_perf; + cppc_para->lowest_nonlinear = data->caps.lowest_nonlinear_perf; + cppc_para->nominal = data->caps.nominal_perf; + cppc_para->highest = data->caps.highest_perf; + cppc_para->minimum = data->req.min_perf; + cppc_para->maximum = data->req.max_perf; + cppc_para->desired = data->req.des_perf; + cppc_para->energy_perf = data->req.epp; + + return 0; +} + +int set_amd_cppc_para(const struct cpufreq_policy *policy, + const struct xen_set_cppc_para *set_cppc) +{ + unsigned int cpu = policy->cpu; + struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data, cpu); + uint8_t max_perf, min_perf, des_perf = 0; + int epp = -1; + + if ( data == NULL ) + return -ENOENT; + + /* Validate all parameters - Disallow reserved bits. */ + if ( set_cppc->minimum > 255 || set_cppc->maximum > 255 || + set_cppc->desired > 255 || set_cppc->energy_perf > 255 ) + return -EINVAL; + + /* Only allow values if params bit is set. */ + if ( (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_DESIRED) && + set_cppc->desired) || + (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM) && + set_cppc->minimum) || + (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM) && + set_cppc->maximum) || + (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_ENERGY_PERF) && + set_cppc->energy_perf) ) + return -EINVAL; + + /* Activity window not supported */ + if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_ACT_WINDOW ) + return -EINVAL; + + /* Return if there is nothing to do. */ + if ( set_cppc->set_params == 0 ) + return 0; + + /* Apply presets */ + switch ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_PRESET_MASK ) + { + case XEN_SYSCTL_CPPC_SET_PRESET_POWERSAVE: + if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_DESIRED ) + return -EINVAL; + min_perf = data->caps.lowest_perf; + max_perf = data->caps.highest_perf; + epp = CPPC_ENERGY_PERF_MAX_POWERSAVE; + break; + + case XEN_SYSCTL_CPPC_SET_PRESET_PERFORMANCE: + if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_DESIRED ) + return -EINVAL; + min_perf = data->caps.highest_perf; + max_perf = data->caps.highest_perf; + epp = CPPC_ENERGY_PERF_MAX_PERFORMANCE; + break; + + case XEN_SYSCTL_CPPC_SET_PRESET_BALANCE: + if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_DESIRED ) + return -EINVAL; + min_perf = data->caps.lowest_perf; + max_perf = data->caps.highest_perf; + epp = CPPC_ENERGY_PERF_BALANCE; + break; + + case XEN_SYSCTL_CPPC_SET_PRESET_NONE: + min_perf = data->caps.lowest_nonlinear_perf; + max_perf = data->caps.highest_perf; + break; + + default: + return -EINVAL; + } + + /* Further customize presets if needed */ + if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM ) + min_perf = set_cppc->minimum; + + if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM ) + max_perf = set_cppc->maximum; + + if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_ENERGY_PERF ) + epp = set_cppc->energy_perf; + + if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_DESIRED ) + des_perf = set_cppc->desired; + + return amd_cppc_write_request(cpu, min_perf, des_perf, max_perf, epp); +} + static const struct cpufreq_driver __initconst_cf_clobber amd_cppc_cpufreq_driver = { .name = XEN_AMD_CPPC_DRIVER_NAME, @@ -551,11 +660,17 @@ static const struct cpufreq_driver __initconst_cf_clobber amd_cppc_epp_driver = .exit = amd_cppc_cpufreq_cpu_exit, }; +bool amd_cppc_active(void) +{ + return amd_cppc_in_use; +} + int __init amd_cppc_register_driver(void) { if ( !cpu_has_cppc ) return -ENODEV; + amd_cppc_in_use = true; if ( !opt_cpufreq_active ) return cpufreq_register_driver(&amd_cppc_cpufreq_driver); else diff --git a/xen/drivers/acpi/pmstat.c b/xen/drivers/acpi/pmstat.c index df309e27b4..46899d99d7 100644 --- a/xen/drivers/acpi/pmstat.c +++ b/xen/drivers/acpi/pmstat.c @@ -258,7 +258,16 @@ static int get_cpufreq_para(struct xen_sysctl_pm_op *op) !strncmp(op->u.get_para.scaling_driver, XEN_HWP_DRIVER_NAME, CPUFREQ_NAME_LEN) ) ret = get_hwp_para(policy->cpu, &op->u.get_para.u.cppc_para); - else + else if ( !strncmp(op->u.get_para.scaling_driver, XEN_AMD_CPPC_DRIVER_NAME, + CPUFREQ_NAME_LEN) || + !strncmp(op->u.get_para.scaling_driver, XEN_AMD_CPPC_EPP_DRIVER_NAME, + CPUFREQ_NAME_LEN) ) + ret = get_amd_cppc_para(policy->cpu, &op->u.get_para.u.cppc_para); + + if ( strncmp(op->u.get_para.scaling_driver, XEN_HWP_DRIVER_NAME, + CPUFREQ_NAME_LEN) && + strncmp(op->u.get_para.scaling_driver, XEN_AMD_CPPC_EPP_DRIVER_NAME, + CPUFREQ_NAME_LEN) ) { if ( !(scaling_available_governors = xzalloc_array(char, gov_num * CPUFREQ_NAME_LEN)) ) @@ -414,10 +423,13 @@ static int set_cpufreq_cppc(struct xen_sysctl_pm_op *op) if ( !policy || !policy->governor ) return -ENOENT; - if ( !hwp_active() ) - return -EOPNOTSUPP; + if ( hwp_active() ) + return set_hwp_para(policy, &op->u.set_cppc); + + if ( amd_cppc_active() ) + return set_amd_cppc_para(policy, &op->u.set_cppc); - return set_hwp_para(policy, &op->u.set_cppc); + return -EOPNOTSUPP; } int do_pm_op(struct xen_sysctl_pm_op *op) diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/cpufreq.h index fb42d61567..cc5a248193 100644 --- a/xen/include/acpi/cpufreq/cpufreq.h +++ b/xen/include/acpi/cpufreq/cpufreq.h @@ -292,5 +292,10 @@ int acpi_cpufreq_register(void); int amd_cppc_cmdline_parse(const char *s, const char *e); int amd_cppc_register_driver(void); +bool amd_cppc_active(void); +int get_amd_cppc_para(unsigned int cpu, + struct xen_cppc_para *cppc_para); +int set_amd_cppc_para(const struct cpufreq_policy *policy, + const struct xen_set_cppc_para *set_cppc); #endif /* __XEN_CPUFREQ_PM_H__ */