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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390692bbeesm42205645e9.0.2025.02.06.03.33.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:33:28 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 01/16] hw/intc/xilinx_intc: Make device endianness configurable Date: Thu, 6 Feb 2025 12:33:06 +0100 Message-ID: <20250206113321.94906-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness for each machine using the device. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/intc/xilinx_intc.c | 52 +++++++++++++++++------- hw/microblaze/petalogix_ml605_mmu.c | 1 + hw/microblaze/petalogix_s3adsp1800_mmu.c | 1 + 3 files changed, 40 insertions(+), 14 deletions(-) diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c index 6930f83907a..cd79ac4d4ff 100644 --- a/hw/intc/xilinx_intc.c +++ b/hw/intc/xilinx_intc.c @@ -3,6 +3,9 @@ * * Copyright (c) 2009 Edgar E. Iglesias. * + * https://docs.amd.com/v/u/en-US/xps_intc + * DS572: LogiCORE IP XPS Interrupt Controller (v2.01a) + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights @@ -49,6 +52,7 @@ struct XpsIntc { SysBusDevice parent_obj; + bool little_endian_model; MemoryRegion mmio; qemu_irq parent_irq; @@ -140,18 +144,29 @@ static void pic_write(void *opaque, hwaddr addr, update_irq(p); } -static const MemoryRegionOps pic_ops = { - .read = pic_read, - .write = pic_write, - .endianness = DEVICE_NATIVE_ENDIAN, - .impl = { - .min_access_size = 4, - .max_access_size = 4, +static const MemoryRegionOps pic_ops[2] = { + [0 ... 1] = { + .read = pic_read, + .write = pic_write, + .endianness = DEVICE_BIG_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, + .valid = { + /* + * All XPS INTC registers are accessed through the PLB interface. + * The base address for these registers is provided by the + * configuration parameter, C_BASEADDR. Each register is 32 bits + * although some bits may be unused and is accessed on a 4-byte + * boundary offset from the base address. + */ + .min_access_size = 4, + .max_access_size = 4, + }, }, - .valid = { - .min_access_size = 4, - .max_access_size = 4 - } + [0].endianness = DEVICE_BIG_ENDIAN, + [1].endianness = DEVICE_LITTLE_ENDIAN, }; static void irq_handler(void *opaque, int irq, int level) @@ -174,13 +189,21 @@ static void xilinx_intc_init(Object *obj) qdev_init_gpio_in(DEVICE(obj), irq_handler, 32); sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq); - - memory_region_init_io(&p->mmio, obj, &pic_ops, p, "xlnx.xps-intc", - R_MAX * 4); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio); } +static void xilinx_intc_realize(DeviceState *dev, Error **errp) +{ + XpsIntc *p = XILINX_INTC(dev); + + memory_region_init_io(&p->mmio, OBJECT(dev), + &pic_ops[p->little_endian_model], + p, "xlnx.xps-intc", + R_MAX * 4); +} + static const Property xilinx_intc_properties[] = { + DEFINE_PROP_BOOL("little-endian", XpsIntc, little_endian_model, true), DEFINE_PROP_UINT32("kind-of-intr", XpsIntc, c_kind_of_intr, 0), }; @@ -188,6 +211,7 @@ static void xilinx_intc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + dc->realize = xilinx_intc_realize; device_class_set_props(dc, xilinx_intc_properties); } diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index 8b44be75a22..cf3b9574db3 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -111,6 +111,7 @@ petalogix_ml605_init(MachineState *machine) dev = qdev_new("xlnx.xps-intc"); + qdev_prop_set_bit(dev, "little-endian", true); qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR); diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index 2c0d8c34cd2..0506497ad0a 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -95,6 +95,7 @@ petalogix_s3adsp1800_init(MachineState *machine) 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); dev = qdev_new("xlnx.xps-intc"); + qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); qdev_prop_set_uint32(dev, "kind-of-intr", 1 << ETHLITE_IRQ | 1 << UARTLITE_IRQ); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); From patchwork Thu Feb 6 11:33:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13962908 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 23C29C02194 for ; Thu, 6 Feb 2025 11:34:07 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tg08m-00076k-RM; Thu, 06 Feb 2025 06:33:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tg08X-00071Q-UD for qemu-devel@nongnu.org; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390d94d7c7sm51664645e9.14.2025.02.06.03.33.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:33:33 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 02/16] hw/net/xilinx_ethlite: Make device endianness configurable Date: Thu, 6 Feb 2025 12:33:07 +0100 Message-ID: <20250206113321.94906-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness on the single machine using the device. Signed-off-by: Philippe Mathieu-Daudé --- hw/microblaze/petalogix_s3adsp1800_mmu.c | 1 + hw/net/xilinx_ethlite.c | 20 ++++++++++++++------ 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index 0506497ad0a..fbf52ba8f2f 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -121,6 +121,7 @@ petalogix_s3adsp1800_init(MachineState *machine) sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); dev = qdev_new("xlnx.xps-ethernetlite"); + qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); qemu_configure_nic_device(dev, true, NULL); qdev_prop_set_uint32(dev, "tx-ping-pong", 0); qdev_prop_set_uint32(dev, "rx-ping-pong", 0); diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 14bf2b2e17a..103e53831a7 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -90,6 +90,7 @@ struct XlnxXpsEthLite NICState *nic; NICConf conf; + bool little_endian_model; uint32_t c_tx_pingpong; uint32_t c_rx_pingpong; unsigned int port_index; /* dual port RAM index */ @@ -183,10 +184,10 @@ static void port_tx_write(void *opaque, hwaddr addr, uint64_t value, } } -static const MemoryRegionOps eth_porttx_ops = { +static const MemoryRegionOps eth_porttx_ops[2] = { + [0 ... 1] = { .read = port_tx_read, .write = port_tx_write, - .endianness = DEVICE_NATIVE_ENDIAN, .impl = { .min_access_size = 4, .max_access_size = 4, @@ -195,6 +196,9 @@ static const MemoryRegionOps eth_porttx_ops = { .min_access_size = 4, .max_access_size = 4, }, + }, + [0].endianness = DEVICE_BIG_ENDIAN, + [1].endianness = DEVICE_LITTLE_ENDIAN, }; static uint64_t port_rx_read(void *opaque, hwaddr addr, unsigned int size) @@ -232,10 +236,10 @@ static void port_rx_write(void *opaque, hwaddr addr, uint64_t value, } } -static const MemoryRegionOps eth_portrx_ops = { +static const MemoryRegionOps eth_portrx_ops[2] = { + [0 ... 1] = { .read = port_rx_read, .write = port_rx_write, - .endianness = DEVICE_NATIVE_ENDIAN, .impl = { .min_access_size = 4, .max_access_size = 4, @@ -244,6 +248,9 @@ static const MemoryRegionOps eth_portrx_ops = { .min_access_size = 4, .max_access_size = 4, }, + }, + [0].endianness = DEVICE_BIG_ENDIAN, + [1].endianness = DEVICE_LITTLE_ENDIAN, }; static bool eth_can_rx(NetClientState *nc) @@ -328,7 +335,7 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp) BUFSZ_MAX, &error_abort); memory_region_add_subregion(&s->container, 0x0800 * i, &s->port[i].txbuf); memory_region_init_io(&s->port[i].txio, OBJECT(dev), - ð_porttx_ops, s, + ð_porttx_ops[s->little_endian_model], s, i ? "ethlite.tx[1]io" : "ethlite.tx[0]io", 4 * TX_MAX); memory_region_add_subregion(&s->container, i ? A_TX_BASE1 : A_TX_BASE0, @@ -340,7 +347,7 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(&s->container, 0x1000 + 0x0800 * i, &s->port[i].rxbuf); memory_region_init_io(&s->port[i].rxio, OBJECT(dev), - ð_portrx_ops, s, + ð_portrx_ops[s->little_endian_model], s, i ? "ethlite.rx[1]io" : "ethlite.rx[0]io", 4 * RX_MAX); memory_region_add_subregion(&s->container, i ? A_RX_BASE1 : A_RX_BASE0, @@ -363,6 +370,7 @@ static void xilinx_ethlite_init(Object *obj) } static const Property xilinx_ethlite_properties[] = { + DEFINE_PROP_BOOL("little-endian", XlnxXpsEthLite, little_endian_model, true), DEFINE_PROP_UINT32("tx-ping-pong", XlnxXpsEthLite, c_tx_pingpong, 1), DEFINE_PROP_UINT32("rx-ping-pong", XlnxXpsEthLite, c_rx_pingpong, 1), DEFINE_NIC_PROPERTIES(XlnxXpsEthLite, conf), From patchwork Thu Feb 6 11:33:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13962924 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6BD29C02194 for ; Thu, 6 Feb 2025 11:35:47 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tg08n-000776-Ug; Thu, 06 Feb 2025 06:33:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tg08c-00072n-7j for qemu-devel@nongnu.org; Thu, 06 Feb 2025 06:33:43 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tg08a-0000qE-8a for qemu-devel@nongnu.org; Thu, 06 Feb 2025 06:33:41 -0500 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-4361b6f9faeso4307695e9.1 for ; Thu, 06 Feb 2025 03:33:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738841618; x=1739446418; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4hjV9qje+F9WM+1u7JaIIDgc7g6v/WUaxTXGCOTYvnI=; b=VPaL2ME7+Jyvnt33FsYFz0VcSH5barU2RrW4u4ErW67S5PC6XdbxXx8PN8Lvd3q3Mz utUcJ1SBJm0YOJL+nHyM2N1a7zaiiDpupwOqkBKHLKV4EMa6/iwCwwWBXnsf0iqV1Y82 S7PM0GMDkET0TBvH3D9FrzHyKPAIkbrDCO8x8/znMyYr2x5HLYBWKFhVYgjr8TZ43M8m btgca6aUkj5zdqxhFI4I/ootefVvcGBXoZW9rvHnlekjCuWzjdjw5N0eDZsgkpzIQsgy 7FO6xXL1nH2nAZ13DogD3VyW5QKhM04uaFb8X4zb53UeTDQUQc0M9rpgvAPzU7RWmYPE ohuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738841618; x=1739446418; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4hjV9qje+F9WM+1u7JaIIDgc7g6v/WUaxTXGCOTYvnI=; b=Sq6ywV7sWwvaSa4GaDjCP++TktN7zotNgjCk231+Ue/aJJdrLAd7cxELS/rdvEt5EE cnsOodF5mr8YNxyqByVdZbjMaRDzwYwX4mfWc+QVUt9QlyA4z0I5rRcoVzduX145ujJN npRj2WJwCpYlVPyNYzdTxqMFjxmhjZ9NwZcbdw3Sz+4gCWX9dENzYXA5GyF3/km2ipu5 Hdc4/Vx187HqOhzSxGzz34sN11ypMzv9LuHQs9u5iEuZyshXA3tyt1K9d7BsYRqrbc1N Mq+4OD72gb8jQSRzG9/wlyBrJvYmaOKwpG7cGKQPASvGZ9s62Jem9X7xy30RS6U00TbX OcWA== X-Gm-Message-State: AOJu0YwUnmO9mnGKSH7RIfoCWzK2AYiiF7yG/v40JXmzqX28+xLkAjni nieb0cpzP6cOXFiwUfr2d8PFD79e1t2JJrAf5v9qxdSXzbAdcCsvY0D8l+N8vvZUDo97PlaKujj qnfo= X-Gm-Gg: ASbGncs1DBSaIw/4+ZZ1R3WF6taJG2jsmkA37HL9ujXqGhgeUwZbYT7CiBCn/mQhvB4 IYodvxBhCgz3zOd8uQt8RJ8Exxp6xV2GPhbZRLkA3d0BC2ldpqBUYK46uL7qedmd3kODJro7M8F vZ9cbA/0aaOM7X4ICLZWLzbmAiRXINOFuB5zubEa5vPX6zSrTo78JFVy7SBxY+C7Y4OR6RkYdt6 T5IqhswlXiAT18aeJbmhVaOsMFRPpd9S84NLMiOWq3rWGA5jvyX4b59Oehu5/xw+ZVuhdJAuJoe L1GLvE9JWcT7iZ93iTcybY7acbt108fiAhesUZ3/mHit/Hqi6lZKZAKPf/aycrkPHA== X-Google-Smtp-Source: AGHT+IFUNyBIFgj9CpRFxe2jRvx6kSil4t/OnSl/ZMH9t3+PUQAPrlZRTdAb+DOpSma1P8PpxgjNVA== X-Received: by 2002:a05:600c:4f50:b0:434:ffb2:f9cf with SMTP id 5b1f17b1804b1-43912d3f2f9mr20851085e9.14.1738841618150; Thu, 06 Feb 2025 03:33:38 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbde0fd00sm1497546f8f.78.2025.02.06.03.33.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:33:37 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 03/16] hw/timer/xilinx_timer: Make device endianness configurable Date: Thu, 6 Feb 2025 12:33:08 +0100 Message-ID: <20250206113321.94906-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness for each machine using the device. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/microblaze/petalogix_ml605_mmu.c | 1 + hw/microblaze/petalogix_s3adsp1800_mmu.c | 1 + hw/ppc/virtex_ml507.c | 1 + hw/timer/xilinx_timer.c | 35 +++++++++++++++--------- 4 files changed, 25 insertions(+), 13 deletions(-) diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index cf3b9574db3..bbda70aa93b 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -127,6 +127,7 @@ petalogix_ml605_init(MachineState *machine) /* 2 timers at irq 2 @ 100 Mhz. */ dev = qdev_new("xlnx.xps-timer"); + qdev_prop_set_bit(dev, "little-endian", true); qdev_prop_set_uint32(dev, "one-timer-only", 0); qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index fbf52ba8f2f..9d4316b4036 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -114,6 +114,7 @@ petalogix_s3adsp1800_init(MachineState *machine) /* 2 timers at irq 2 @ 62 Mhz. */ dev = qdev_new("xlnx.xps-timer"); + qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); qdev_prop_set_uint32(dev, "one-timer-only", 0); qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c index 23238119273..f87c221d076 100644 --- a/hw/ppc/virtex_ml507.c +++ b/hw/ppc/virtex_ml507.c @@ -230,6 +230,7 @@ static void virtex_init(MachineState *machine) /* 2 timers at irq 2 @ 62 Mhz. */ dev = qdev_new("xlnx.xps-timer"); + qdev_prop_set_bit(dev, "little-endian", false); qdev_prop_set_uint32(dev, "one-timer-only", 0); qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c index 6595cf5f517..d942ac226e6 100644 --- a/hw/timer/xilinx_timer.c +++ b/hw/timer/xilinx_timer.c @@ -3,6 +3,9 @@ * * Copyright (c) 2009 Edgar E. Iglesias. * + * DS573: https://docs.amd.com/v/u/en-US/xps_timer + * LogiCORE IP XPS Timer/Counter (v1.02a) + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights @@ -69,6 +72,7 @@ struct XpsTimerState { SysBusDevice parent_obj; + bool little_endian_model; MemoryRegion mmio; qemu_irq irq; uint8_t one_timer_only; @@ -189,18 +193,21 @@ timer_write(void *opaque, hwaddr addr, timer_update_irq(t); } -static const MemoryRegionOps timer_ops = { - .read = timer_read, - .write = timer_write, - .endianness = DEVICE_NATIVE_ENDIAN, - .impl = { - .min_access_size = 4, - .max_access_size = 4, +static const MemoryRegionOps timer_ops[2] = { + [0 ... 1] = { + .read = timer_read, + .write = timer_write, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, }, - .valid = { - .min_access_size = 4, - .max_access_size = 4 - } + [0].endianness = DEVICE_BIG_ENDIAN, + [1].endianness = DEVICE_LITTLE_ENDIAN, }; static void timer_hit(void *opaque) @@ -233,8 +240,9 @@ static void xilinx_timer_realize(DeviceState *dev, Error **errp) ptimer_transaction_commit(xt->ptimer); } - memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, "xlnx.xps-timer", - R_MAX * 4 * num_timers(t)); + memory_region_init_io(&t->mmio, OBJECT(t), + &timer_ops[t->little_endian_model], t, + "xlnx.xps-timer", R_MAX * 4 * num_timers(t)); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &t->mmio); } @@ -247,6 +255,7 @@ static void xilinx_timer_init(Object *obj) } static const Property xilinx_timer_properties[] = { + DEFINE_PROP_BOOL("little-endian", XpsTimerState, little_endian_model, true), DEFINE_PROP_UINT32("clock-frequency", XpsTimerState, freq_hz, 62 * 1000000), DEFINE_PROP_UINT8("one-timer-only", XpsTimerState, one_timer_only, 0), }; From patchwork Thu Feb 6 11:33:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13962910 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32CD8C02196 for ; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390d94d7d4sm53433895e9.10.2025.02.06.03.33.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:33:42 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 04/16] hw/char/xilinx_uartlite: Make device endianness configurable Date: Thu, 6 Feb 2025 12:33:09 +0100 Message-ID: <20250206113321.94906-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness on the single machine using the device. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/char/xilinx_uartlite.c | 27 ++++++++++++++---------- hw/microblaze/petalogix_s3adsp1800_mmu.c | 1 + 2 files changed, 17 insertions(+), 11 deletions(-) diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c index 56955e0d74a..948da4263b9 100644 --- a/hw/char/xilinx_uartlite.c +++ b/hw/char/xilinx_uartlite.c @@ -57,6 +57,7 @@ struct XilinxUARTLite { SysBusDevice parent_obj; + bool little_endian_model; MemoryRegion mmio; CharBackend chr; qemu_irq irq; @@ -166,17 +167,21 @@ uart_write(void *opaque, hwaddr addr, uart_update_irq(s); } -static const MemoryRegionOps uart_ops = { - .read = uart_read, - .write = uart_write, - .endianness = DEVICE_NATIVE_ENDIAN, - .valid = { - .min_access_size = 1, - .max_access_size = 4 - } +static const MemoryRegionOps uart_ops[2] = { + [0 ... 1] = { + .read = uart_read, + .write = uart_write, + .valid = { + .min_access_size = 1, + .max_access_size = 4, + }, + }, + [0].endianness = DEVICE_BIG_ENDIAN, + [1].endianness = DEVICE_LITTLE_ENDIAN, }; static const Property xilinx_uartlite_properties[] = { + DEFINE_PROP_BOOL("little-endian", XilinxUARTLite, little_endian_model, true), DEFINE_PROP_CHR("chardev", XilinxUARTLite, chr), }; @@ -214,6 +219,9 @@ static void xilinx_uartlite_realize(DeviceState *dev, Error **errp) { XilinxUARTLite *s = XILINX_UARTLITE(dev); + memory_region_init_io(&s->mmio, OBJECT(dev), + &uart_ops[s->little_endian_model], + s, "xlnx.xps-uartlite", R_MAX * 4); qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event, NULL, s, NULL, true); } @@ -223,9 +231,6 @@ static void xilinx_uartlite_init(Object *obj) XilinxUARTLite *s = XILINX_UARTLITE(obj); sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); - - memory_region_init_io(&s->mmio, obj, &uart_ops, s, - "xlnx.xps-uartlite", R_MAX * 4); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); } diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index 9d4316b4036..96aed4ed1a3 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -107,6 +107,7 @@ petalogix_s3adsp1800_init(MachineState *machine) } dev = qdev_new(TYPE_XILINX_UARTLITE); + qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); qdev_prop_set_chr(dev, "chardev", serial_hd(0)); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR); From patchwork Thu Feb 6 11:33:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13962925 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F20EC02194 for ; Thu, 6 Feb 2025 11:36:30 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tg08p-000779-K5; Thu, 06 Feb 2025 06:33:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tg08l-00076R-2g for qemu-devel@nongnu.org; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbdd3856fsm1476849f8f.28.2025.02.06.03.33.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:33:47 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 05/16] hw/ssi/xilinx_spi: Make device endianness configurable Date: Thu, 6 Feb 2025 12:33:10 +0100 Message-ID: <20250206113321.94906-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness on the single machine using the device. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/microblaze/petalogix_ml605_mmu.c | 1 + hw/ssi/xilinx_spi.c | 24 +++++++++++++++--------- 2 files changed, 16 insertions(+), 9 deletions(-) diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index bbda70aa93b..a795c6385b4 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -175,6 +175,7 @@ petalogix_ml605_init(MachineState *machine) SSIBus *spi; dev = qdev_new("xlnx.xps-spi"); + qdev_prop_set_bit(dev, "little-endian", true); qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES); busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c index fd1ff12eb1d..299004ff36d 100644 --- a/hw/ssi/xilinx_spi.c +++ b/hw/ssi/xilinx_spi.c @@ -83,6 +83,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XilinxSPI, XILINX_SPI) struct XilinxSPI { SysBusDevice parent_obj; + bool little_endian_model; MemoryRegion mmio; qemu_irq irq; @@ -313,14 +314,17 @@ done: xlx_spi_update_irq(s); } -static const MemoryRegionOps spi_ops = { - .read = spi_read, - .write = spi_write, - .endianness = DEVICE_NATIVE_ENDIAN, - .valid = { - .min_access_size = 4, - .max_access_size = 4 - } +static const MemoryRegionOps spi_ops[2] = { + [0 ... 1] = { + .read = spi_read, + .write = spi_write, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, + }, + [0].endianness = DEVICE_BIG_ENDIAN, + [1].endianness = DEVICE_LITTLE_ENDIAN, }; static void xilinx_spi_realize(DeviceState *dev, Error **errp) @@ -339,7 +343,8 @@ static void xilinx_spi_realize(DeviceState *dev, Error **errp) sysbus_init_irq(sbd, &s->cs_lines[i]); } - memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s, + memory_region_init_io(&s->mmio, OBJECT(s), + &spi_ops[s->little_endian_model], s, "xilinx-spi", R_MAX * 4); sysbus_init_mmio(sbd, &s->mmio); @@ -362,6 +367,7 @@ static const VMStateDescription vmstate_xilinx_spi = { }; static const Property xilinx_spi_properties[] = { + DEFINE_PROP_BOOL("little-endian", XilinxSPI, little_endian_model, true), DEFINE_PROP_UINT8("num-ss-bits", XilinxSPI, num_cs, 1), }; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbde31ccesm1506012f8f.98.2025.02.06.03.33.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:33:51 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 06/16] hw/arm/xlnx-zynqmp: Use &error_abort for programming errors Date: Thu, 6 Feb 2025 12:33:11 +0100 Message-ID: <20250206113321.94906-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When a property value is static (not provided by QMP or CLI), error shouldn't happen, otherwise it is a programming error. Therefore simplify and use &error_abort as this can't fail. Reported-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson --- hw/arm/xlnx-zynqmp.c | 38 ++++++++++++-------------------------- 1 file changed, 12 insertions(+), 26 deletions(-) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index bd5b0dd5e76..d6022ff2d3d 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -689,16 +689,10 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) * - SDIO Specification Version 3.0 * - eMMC Specification Version 4.51 */ - if (!object_property_set_uint(sdhci, "sd-spec-version", 3, errp)) { - return; - } - if (!object_property_set_uint(sdhci, "capareg", SDHCI_CAPABILITIES, - errp)) { - return; - } - if (!object_property_set_uint(sdhci, "uhs", UHS_I, errp)) { - return; - } + object_property_set_uint(sdhci, "sd-spec-version", 3, &error_abort); + object_property_set_uint(sdhci, "capareg", SDHCI_CAPABILITIES, + &error_abort); + object_property_set_uint(sdhci, "uhs", UHS_I, &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(sdhci), errp)) { return; } @@ -763,14 +757,10 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) xlnx_zynqmp_create_unimp_mmio(s); for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { - if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128, - errp)) { - return; - } - if (!object_property_set_link(OBJECT(&s->gdma[i]), "dma", - OBJECT(system_memory), errp)) { - return; - } + object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128, + &error_abort); + object_property_set_link(OBJECT(&s->gdma[i]), "dma", + OBJECT(system_memory), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), errp)) { return; } @@ -811,10 +801,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi_dma), 0, qdev_get_gpio_in(DEVICE(&s->qspi_irq_orgate), 0)); - if (!object_property_set_link(OBJECT(&s->qspi), "stream-connected-dma", - OBJECT(&s->qspi_dma), errp)) { - return; - } + object_property_set_link(OBJECT(&s->qspi), "stream-connected-dma", + OBJECT(&s->qspi_dma), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi), errp)) { return; } @@ -833,10 +821,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) } for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) { - if (!object_property_set_link(OBJECT(&s->usb[i].sysbus_xhci), "dma", - OBJECT(system_memory), errp)) { - return; - } + object_property_set_link(OBJECT(&s->usb[i].sysbus_xhci), "dma", + OBJECT(system_memory), &error_abort); qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "intrs", 4); qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "slots", 2); From patchwork Thu Feb 6 11:33:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13962918 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 84DB4C02196 for ; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391dca34a8sm16320255e9.16.2025.02.06.03.33.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:33:56 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= , Alistair Francis Subject: [PATCH v4 07/16] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx Date: Thu, 6 Feb 2025 12:33:12 +0100 Message-ID: <20250206113321.94906-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Extract the implicit MO_TE definition in order to replace it by runtime variable in the next commit. Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/microblaze); \ done Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/microblaze/translate.c | 36 +++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 24005f05b21..86efabb83b5 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -780,13 +780,13 @@ static bool trans_lbui(DisasContext *dc, arg_typeb *arg) static bool trans_lhu(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); } static bool trans_lhur(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); } static bool trans_lhuea(DisasContext *dc, arg_typea *arg) @@ -798,26 +798,26 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false); #endif } static bool trans_lhui(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); } static bool trans_lw(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); } static bool trans_lwr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); } static bool trans_lwea(DisasContext *dc, arg_typea *arg) @@ -829,14 +829,14 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false); #endif } static bool trans_lwi(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); } static bool trans_lwx(DisasContext *dc, arg_typea *arg) @@ -846,7 +846,7 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg) /* lwx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); - tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL); + tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TE | MO_UL); tcg_gen_mov_tl(cpu_res_addr, addr); if (arg->rd) { @@ -930,13 +930,13 @@ static bool trans_sbi(DisasContext *dc, arg_typeb *arg) static bool trans_sh(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); } static bool trans_shr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); } static bool trans_shea(DisasContext *dc, arg_typea *arg) @@ -948,26 +948,26 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false); #endif } static bool trans_shi(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); } static bool trans_sw(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); } static bool trans_swr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); } static bool trans_swea(DisasContext *dc, arg_typea *arg) @@ -979,14 +979,14 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false); #endif } static bool trans_swi(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); } static bool trans_swx(DisasContext *dc, arg_typea *arg) @@ -1015,7 +1015,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg) tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val, reg_for_write(dc, arg->rd), - dc->mem_index, MO_TEUL); + dc->mem_index, MO_TE | MO_UL); tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail); From patchwork Thu Feb 6 11:33:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13962911 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C0525C02194 for ; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbde0fb31sm1496293f8f.65.2025.02.06.03.34.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:34:01 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 08/16] target/microblaze: Set MO_TE once in do_load() / do_store() Date: Thu, 6 Feb 2025 12:33:13 +0100 Message-ID: <20250206113321.94906-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org All callers of do_load() / do_store() set MO_TE flag. Set it once in the callees. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/microblaze/translate.c | 36 +++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 86efabb83b5..0d51b2c468c 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -713,6 +713,8 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, { MemOp size = mop & MO_SIZE; + mop |= MO_TE; + /* * When doing reverse accesses we need to do two things. * @@ -780,13 +782,13 @@ static bool trans_lbui(DisasContext *dc, arg_typeb *arg) static bool trans_lhu(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } static bool trans_lhur(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); + return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, true); } static bool trans_lhuea(DisasContext *dc, arg_typea *arg) @@ -798,26 +800,26 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false); + return do_load(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false); #endif } static bool trans_lhui(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } static bool trans_lw(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false); } static bool trans_lwr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); + return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, true); } static bool trans_lwea(DisasContext *dc, arg_typea *arg) @@ -829,14 +831,14 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false); + return do_load(dc, arg->rd, addr, MO_UL, MMU_NOMMU_IDX, false); #endif } static bool trans_lwi(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false); } static bool trans_lwx(DisasContext *dc, arg_typea *arg) @@ -863,6 +865,8 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, { MemOp size = mop & MO_SIZE; + mop |= MO_TE; + /* * When doing reverse accesses we need to do two things. * @@ -930,13 +934,13 @@ static bool trans_sbi(DisasContext *dc, arg_typeb *arg) static bool trans_sh(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } static bool trans_shr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); + return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, true); } static bool trans_shea(DisasContext *dc, arg_typea *arg) @@ -948,26 +952,26 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false); + return do_store(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false); #endif } static bool trans_shi(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } static bool trans_sw(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, false); } static bool trans_swr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); + return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, true); } static bool trans_swea(DisasContext *dc, arg_typea *arg) @@ -979,14 +983,14 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false); + return do_store(dc, arg->rd, addr, MO_UL, MMU_NOMMU_IDX, false); #endif } static bool trans_swi(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, false); } static bool trans_swx(DisasContext *dc, arg_typea *arg) From patchwork Thu Feb 6 11:33:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13962917 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B0D9FC02196 for ; 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Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 09/16] target/microblaze: Introduce mo_endian() helper Date: Thu, 6 Feb 2025 12:33:14 +0100 Message-ID: <20250206113321.94906-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org mo_endian() returns the target endianness, currently static. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/microblaze/translate.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0d51b2c468c..b5389d65b2e 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -708,12 +708,17 @@ static void record_unaligned_ess(DisasContext *dc, int rd, } #endif +static inline MemOp mo_endian(DisasContext *dc) +{ + return MO_TE; +} + static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, int mem_index, bool rev) { MemOp size = mop & MO_SIZE; - mop |= MO_TE; + mop |= mo_endian(dc); /* * When doing reverse accesses we need to do two things. @@ -848,7 +853,8 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg) /* lwx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); - tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TE | MO_UL); + tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, + mo_endian(dc) | MO_UL); tcg_gen_mov_tl(cpu_res_addr, addr); if (arg->rd) { @@ -865,7 +871,7 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, { MemOp size = mop & MO_SIZE; - mop |= MO_TE; + mop |= mo_endian(dc); /* * When doing reverse accesses we need to do two things. @@ -1019,7 +1025,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg) tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val, reg_for_write(dc, arg->rd), - dc->mem_index, MO_TE | MO_UL); + dc->mem_index, mo_endian(dc) | MO_UL); tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail); From patchwork Thu Feb 6 11:33:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13962920 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0A993C02196 for ; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbde0fe37sm1515984f8f.69.2025.02.06.03.34.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:34:10 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 10/16] target/microblaze: Consider endianness while translating code Date: Thu, 6 Feb 2025 12:33:15 +0100 Message-ID: <20250206113321.94906-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Consider the CPU ENDI bit, swap instructions when the CPU endianness doesn't match the binary one. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/microblaze/cpu.h | 7 +++++++ target/microblaze/translate.c | 5 +++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index f6879eee352..e44ddd53078 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -414,6 +414,13 @@ void mb_translate_code(CPUState *cs, TranslationBlock *tb, /* Ensure there is no overlap between the two masks. */ QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK); +static inline bool mb_cpu_is_big_endian(CPUState *cs) +{ + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + + return !cpu->cfg.endi; +} + static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index b5389d65b2e..b54e5ac4b2f 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -710,7 +710,7 @@ static void record_unaligned_ess(DisasContext *dc, int rd, static inline MemOp mo_endian(DisasContext *dc) { - return MO_TE; + return dc->cfg->endi ? MO_LE : MO_BE; } static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, @@ -1647,7 +1647,8 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) dc->tb_flags_to_set = 0; - ir = translator_ldl(cpu_env(cs), &dc->base, dc->base.pc_next); + ir = translator_ldl_swap(cpu_env(cs), &dc->base, dc->base.pc_next, + mb_cpu_is_big_endian(cs) != TARGET_BIG_ENDIAN); if (!decode(dc, ir)) { trap_illegal(dc, true); } From patchwork Thu Feb 6 11:33:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13962927 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8C16DC02194 for ; Thu, 6 Feb 2025 11:36:41 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tg09I-0007co-3f; Thu, 06 Feb 2025 06:34:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tg09E-0007Zi-7N for qemu-devel@nongnu.org; Thu, 06 Feb 2025 06:34:20 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tg09C-0000so-8T for qemu-devel@nongnu.org; Thu, 06 Feb 2025 06:34:19 -0500 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-4361815b96cso5092035e9.1 for ; Thu, 06 Feb 2025 03:34:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738841655; x=1739446455; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y5yL8FD/exSYKs1rjCaM0CVY1gRhFjhBlCLpvUbDQjM=; b=YlteEe0mHXW82jDzWz7ujAhJlq+i5CAD515rgJC9szWMnAobmt38mrmCWT6WUEa4do jjPNn0PLn+cfca6aVGAWF9wqu2y+pvx8ZQi4ps8NslYDKEXz3v7wh1X7JMC3MhkMdlDE 4DpbmrLUR9if4dQOb8rc4cfmkF+fYACvpgPnFhkQkEFBBww0h8TdZJAjL7rLgj8Mscsd h89JyGDsKprGoJVZEiuFetChEbdfbDh9c3r24jekAtQNcjottN8CzSYGXX+cB56Rxv1e rpc9oOH6xVSYHPcIxDJkAmLFAMsyV6cbc36VtnmZja8JMJmMm3krzGSEIVMGA0oGFUxb 7CkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738841655; x=1739446455; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y5yL8FD/exSYKs1rjCaM0CVY1gRhFjhBlCLpvUbDQjM=; b=hSQlsBBh8JU8DChiQHd5MYlL7tE/338DouxNjtd4+rb4QnehjwgAce4j2ZgsFatIA5 UJUdPUcByckR4sEYuI8Dd6sAOmK11JDGz+S0MJ91nfcujtYmq3NauBE0SGlxKwloOo3y C2SZ9MA0ASsoFQ5HCRs5H1GCEJZB1UGythXrlJjQC5RXwdqfM9rG7PEv2ct99fn23pSE in98Wxv3BSvoeIGAn9K1xMBEsMuU+6Jhcf17iB/7dvaSnU1OTuu7mMPq0LQKd9OFfPEn 4L9fuFEIMPbkGHgiW+u/CEcKjvH3U/y4s2Fh+pOiS/Ud9eP13fiatgJ+Te5XiGzzhDmN 24BQ== X-Gm-Message-State: AOJu0Ywn56bWS2tAdn9nRHDvEYEfdIbBEWxnlWHzC9mhz71MjfgqYlR+ ugdRTrO7Snp3j3kWJMtxYi0ATps1x/0iMjhWam8pp/OaglQsizFfLO2cOSnxp6cS/uRWAl1wTl0 8yZg= X-Gm-Gg: ASbGncu/9LiBrt0DtdVK/Qj2rJ8zOlsJBrzyJiSyYY3GxRwG2fa3q2hlfu30O9d9xQ1 bcIt+8UY7bSSt/DIdktue3aY9qgPFOtumabRK6Vonjzj8s7vit5fsnMYrEj/LQbD7ns3YZ63Umc dbg/K7mgj+Np2od9kRmHJTKGbyiSL2PN4IXQ2F6V4YjL0mtnx6KBtKvx5YK88IeLCThmkHjMlJy HaqupWjSDvSVz9CwARH7qa+SgYV4AMOFzO9DyZn9LsLwS44svTVGxmMSkwDVnM4tc2FHgZ5zRDd a5SUqO7DhMX1V4/B5UruRfa6IcvPe3eN1hD14Wth3hxpNcNHhpMkvSxl4KJMoghbmg== X-Google-Smtp-Source: AGHT+IGLVU72q2D8Gs03X4N5ZobhxJO7FeJTwuX55ITlC2c4CIzY7odThd/k9jvm1lUhfKCmkuPdBQ== X-Received: by 2002:a05:600c:1d1e:b0:436:faeb:2a1b with SMTP id 5b1f17b1804b1-4390d43e579mr50763485e9.13.1738841655580; Thu, 06 Feb 2025 03:34:15 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbdd7f18bsm1518007f8f.60.2025.02.06.03.34.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:34:15 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 11/16] hw/microblaze: Support various endianness for s3adsp1800 machines Date: Thu, 6 Feb 2025 12:33:16 +0100 Message-ID: <20250206113321.94906-12-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Introduce an abstract machine parent class which defines the 'little_endian' property. Duplicate the current machine, which endian is tied to the binary endianness, to one big endian and a little endian machine; updating the machine description. Keep the current default machine for each binary. 'petalogix-s3adsp1800' machine is aliased as: - 'petalogix-s3adsp1800-be' on big-endian binary, - 'petalogix-s3adsp1800-le' on little-endian one. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/microblaze/petalogix_s3adsp1800_mmu.c | 62 +++++++++++++++++++----- 1 file changed, 51 insertions(+), 11 deletions(-) diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index 96aed4ed1a3..aea727eb7ee 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -55,8 +55,17 @@ #define ETHLITE_IRQ 1 #define UARTLITE_IRQ 3 +typedef struct PetalogixS3adsp1800MachineClass { + MachineClass parent_obj; + + bool little_endian; +} PetalogixS3adsp1800MachineClass; + #define TYPE_PETALOGIX_S3ADSP1800_MACHINE \ - MACHINE_TYPE_NAME("petalogix-s3adsp1800") + MACHINE_TYPE_NAME("petalogix-s3adsp1800-common") +DECLARE_CLASS_CHECKERS(PetalogixS3adsp1800MachineClass, + PETALOGIX_S3ADSP1800_MACHINE, + TYPE_PETALOGIX_S3ADSP1800_MACHINE) static void petalogix_s3adsp1800_init(MachineState *machine) @@ -71,11 +80,13 @@ petalogix_s3adsp1800_init(MachineState *machine) MemoryRegion *phys_ram = g_new(MemoryRegion, 1); qemu_irq irq[32]; MemoryRegion *sysmem = get_system_memory(); + PetalogixS3adsp1800MachineClass *pmc; + pmc = PETALOGIX_S3ADSP1800_MACHINE_GET_CLASS(machine); cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); object_property_set_str(OBJECT(cpu), "version", "7.10.d", &error_abort); object_property_set_bool(OBJECT(cpu), "little-endian", - !TARGET_BIG_ENDIAN, &error_abort); + pmc->little_endian, &error_abort); qdev_realize(DEVICE(cpu), NULL, &error_abort); /* Attach emulated BRAM through the LMB. */ @@ -95,7 +106,7 @@ petalogix_s3adsp1800_init(MachineState *machine) 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); dev = qdev_new("xlnx.xps-intc"); - qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); + qdev_prop_set_bit(dev, "little-endian", pmc->little_endian); qdev_prop_set_uint32(dev, "kind-of-intr", 1 << ETHLITE_IRQ | 1 << UARTLITE_IRQ); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -107,7 +118,7 @@ petalogix_s3adsp1800_init(MachineState *machine) } dev = qdev_new(TYPE_XILINX_UARTLITE); - qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); + qdev_prop_set_bit(dev, "little-endian", pmc->little_endian); qdev_prop_set_chr(dev, "chardev", serial_hd(0)); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR); @@ -115,7 +126,7 @@ petalogix_s3adsp1800_init(MachineState *machine) /* 2 timers at irq 2 @ 62 Mhz. */ dev = qdev_new("xlnx.xps-timer"); - qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); + qdev_prop_set_bit(dev, "little-endian", pmc->little_endian); qdev_prop_set_uint32(dev, "one-timer-only", 0); qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -123,7 +134,7 @@ petalogix_s3adsp1800_init(MachineState *machine) sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); dev = qdev_new("xlnx.xps-ethernetlite"); - qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); + qdev_prop_set_bit(dev, "little-endian", pmc->little_endian); qemu_configure_nic_device(dev, true, NULL); qdev_prop_set_uint32(dev, "tx-ping-pong", 0); qdev_prop_set_uint32(dev, "rx-ping-pong", 0); @@ -133,26 +144,55 @@ petalogix_s3adsp1800_init(MachineState *machine) create_unimplemented_device("xps_gpio", GPIO_BASEADDR, 0x10000); - microblaze_load_kernel(cpu, !TARGET_BIG_ENDIAN, ddr_base, ram_size, + microblaze_load_kernel(cpu, pmc->little_endian, ddr_base, ram_size, machine->initrd_filename, BINARY_DEVICE_TREE_FILE, NULL); } -static void petalogix_s3adsp1800_machine_class_init(ObjectClass *oc, void *data) +static void petalogix_s3adsp1800_machine_class_init(ObjectClass *oc, + bool little_endian) { MachineClass *mc = MACHINE_CLASS(oc); + PetalogixS3adsp1800MachineClass *pmc = PETALOGIX_S3ADSP1800_MACHINE_CLASS(oc); - mc->desc = "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800"; mc->init = petalogix_s3adsp1800_init; - mc->is_default = true; + pmc->little_endian = little_endian; + mc->desc = little_endian + ? "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800 (little endian)" + : "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800 (big endian)"; + if (little_endian == !TARGET_BIG_ENDIAN) { + mc->is_default = true; + mc->alias = "petalogix-s3adsp1800"; + } +} + +static void petalogix_s3adsp1800_machine_class_init_be(ObjectClass *oc, void *data) +{ + petalogix_s3adsp1800_machine_class_init(oc, false); +} + +static void petalogix_s3adsp1800_machine_class_init_le(ObjectClass *oc, void *data) +{ + petalogix_s3adsp1800_machine_class_init(oc, true); } static const TypeInfo petalogix_s3adsp1800_machine_types[] = { { .name = TYPE_PETALOGIX_S3ADSP1800_MACHINE, .parent = TYPE_MACHINE, - .class_init = petalogix_s3adsp1800_machine_class_init, + .abstract = true, + .class_size = sizeof(PetalogixS3adsp1800MachineClass), + }, + { + .name = MACHINE_TYPE_NAME("petalogix-s3adsp1800-be"), + .parent = TYPE_PETALOGIX_S3ADSP1800_MACHINE, + .class_init = petalogix_s3adsp1800_machine_class_init_be, + }, + { + .name = MACHINE_TYPE_NAME("petalogix-s3adsp1800-le"), + .parent = TYPE_PETALOGIX_S3ADSP1800_MACHINE, + .class_init = petalogix_s3adsp1800_machine_class_init_le, }, }; From patchwork Thu Feb 6 11:33:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13962916 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EE0D6C02194 for ; Thu, 6 Feb 2025 11:34:39 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tg09L-00080Y-3Y; Thu, 06 Feb 2025 06:34:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tg09I-0007qo-BH for qemu-devel@nongnu.org; Thu, 06 Feb 2025 06:34:24 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tg09G-0000tB-E6 for qemu-devel@nongnu.org; Thu, 06 Feb 2025 06:34:24 -0500 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-38dc5764fc0so38130f8f.3 for ; Thu, 06 Feb 2025 03:34:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738841660; x=1739446460; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2lrz/Z9U2Uf5jpDeQ6Q5rMzyggw9C9+W1C5t50i9qAk=; b=NAz9wARYgv/PzUKvKwRbyaH1JfknC+PQJclHCGM1CtTMSN4vqMwsk0LpLLI1XRrhvU yHDtsejuQjcXdxOM6PydYZU9vvBDplEYKobN6m+55jbyEalsThTTyv9i9cTdGpZUZO9e gLWAaibqvp2SoNO8wS8MTgQSOFC6ZnORmh6ParBbud3hNhH/CDOe0/cvGhSrrXO2TWN1 4qfO4XfLgaCOGARzQaQvRILgn0+MqE2Nhi77K4TLbeXUv+dwRpKUA3WxEpE84hBwCQOB Jrog7xvjtoq5yBxwBnaSXFITzIZl7PBJc/vsi5F9jhjUVCTPl8GuTp4S51kvxdUoR6VT fiQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738841660; x=1739446460; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2lrz/Z9U2Uf5jpDeQ6Q5rMzyggw9C9+W1C5t50i9qAk=; b=Wi5V24IS5BQIs9lwIvT7bk4XnKo1k4CqwE6l212xk0WCQAJXUDAecwvqdwZp+qn7w3 /tawJuAL2pk2e+k1GL+KXUuCgOUryTeI76iK4VL/1+xBhSudfjb/g6LESpeLvuppbtVw nBWo1jAiu8NVcB/UueDYY4HEBQn32PqAWdPpffTlMCOGDBP05TkPgJaT9Fa7CB/9iC18 VLd2SW1GGxdR4rEqNY3i2PC8RGmSUEdb2fHETWpUeKq1/VU9cE4J/KKJkhc6BRertT/h op9Bpie9KYY5Bj6yyvfdzzXorPb+1N/3Ld5DWLQ2W+Dco3d1gnUVcsqGKNff/aeqBBls fTIg== X-Gm-Message-State: AOJu0Yw7xbst/HO/dG8iaAXpA4Pl4Tax9xjdkn/lPRnHRd87pLNF8Jsz m/ZGBd2lrPKFiAcVl+2ZWbs63pwEJWuTcDvDcb9FlY0JdheWLTCMzeMrT7gGe95giPYjGtX5Ctl oBtU= X-Gm-Gg: ASbGncv5P5IeWpRQDvItU8j9pWuy3pUAzVaJ2iN+J+5fCEIN/ZyGaQMa470gFy0Ar/M qXJymgOZKuY1E6jTiTGKa7ntFj9wpOJtCg64FEayIpWg/wfn//TYAH+PQiJXcgc5+uGI3XCp1WG ZEqYs4PbW3VivKrn74CR0sd+G5uAO3rWpoEY7+IX1AcSkvdx4jztG3Jjdg15RGISN+AKG+z9fAE f0qnle1SY+iL/bT1b2/Xt7V7aq7tjglasx31g97kZvPxd/IvnEH8IyipP0T5JikTk5NSiFEsAUO YMyzmiQb0/m/f3Qv/Lrd/fT21RmzjwmlbwcVNxUtS2NUyOEIQdMHRqe9kJryqZlCmw== X-Google-Smtp-Source: AGHT+IHSDN8kBjQRCQ5mSO3oLw9OrLEYqGdwuk01GVJ2tJpjZEe4C415ElC+Zz1peCauC4IwLvRW7A== X-Received: by 2002:a5d:64a1:0:b0:38c:5e03:5d9 with SMTP id ffacd0b85a97d-38db48bce45mr5672009f8f.16.1738841660255; Thu, 06 Feb 2025 03:34:20 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dc33939f3sm487320f8f.17.2025.02.06.03.34.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:34:19 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 12/16] tests/functional: Explicit endianness of microblaze assets Date: Thu, 6 Feb 2025 12:33:17 +0100 Message-ID: <20250206113321.94906-13-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The archive used in test_microblaze_s3adsp1800.py (testing a big-endian target) contains a big-endian kernel. Rename using the _BE suffix. Similarly, the archive in test_microblazeel_s3adsp1800 (testing a little-endian target) contains a little-endian kernel. Rename using _LE suffix. These changes will help when adding cross-endian kernel tests. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth --- tests/functional/test_microblaze_s3adsp1800.py | 6 +++--- tests/functional/test_microblazeel_s3adsp1800.py | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/functional/test_microblaze_s3adsp1800.py b/tests/functional/test_microblaze_s3adsp1800.py index 2c4464bd05a..fac364b1ea9 100755 --- a/tests/functional/test_microblaze_s3adsp1800.py +++ b/tests/functional/test_microblaze_s3adsp1800.py @@ -15,14 +15,14 @@ class MicroblazeMachine(QemuSystemTest): timeout = 90 - ASSET_IMAGE = Asset( + ASSET_IMAGE_BE = Asset( ('https://qemu-advcal.gitlab.io/qac-best-of-multiarch/download/' 'day17.tar.xz'), '3ba7439dfbea7af4876662c97f8e1f0cdad9231fc166e4861d17042489270057') - def test_microblaze_s3adsp1800(self): + def test_microblaze_s3adsp1800_be(self): self.set_machine('petalogix-s3adsp1800') - self.archive_extract(self.ASSET_IMAGE) + self.archive_extract(self.ASSET_IMAGE_BE) self.vm.set_console() self.vm.add_args('-kernel', self.scratch_file('day17', 'ballerina.bin')) diff --git a/tests/functional/test_microblazeel_s3adsp1800.py b/tests/functional/test_microblazeel_s3adsp1800.py index c382afe6bfa..5d353dba5d2 100755 --- a/tests/functional/test_microblazeel_s3adsp1800.py +++ b/tests/functional/test_microblazeel_s3adsp1800.py @@ -17,14 +17,14 @@ class MicroblazeelMachine(QemuSystemTest): timeout = 90 - ASSET_IMAGE = Asset( + ASSET_IMAGE_LE = Asset( ('http://www.qemu-advent-calendar.org/2023/download/day13.tar.gz'), 'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22') - def test_microblazeel_s3adsp1800(self): + def test_microblazeel_s3adsp1800_le(self): self.require_netdev('user') self.set_machine('petalogix-s3adsp1800') - self.archive_extract(self.ASSET_IMAGE) + self.archive_extract(self.ASSET_IMAGE_LE) self.vm.set_console() self.vm.add_args('-kernel', self.scratch_file('day13', 'xmaton.bin')) tftproot = self.scratch_file('day13') From patchwork Thu Feb 6 11:33:18 2025 Content-Type: text/plain; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbdd4b154sm1521480f8f.38.2025.02.06.03.34.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:34:24 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 13/16] tests/functional: Allow microblaze tests to take a machine name argument Date: Thu, 6 Feb 2025 12:33:18 +0100 Message-ID: <20250206113321.94906-14-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Make microblaze tests a bit more generic. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- tests/functional/test_microblaze_s3adsp1800.py | 7 +++++-- tests/functional/test_microblazeel_s3adsp1800.py | 7 +++++-- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/tests/functional/test_microblaze_s3adsp1800.py b/tests/functional/test_microblaze_s3adsp1800.py index fac364b1ea9..c4226f49cf3 100755 --- a/tests/functional/test_microblaze_s3adsp1800.py +++ b/tests/functional/test_microblaze_s3adsp1800.py @@ -20,8 +20,8 @@ class MicroblazeMachine(QemuSystemTest): 'day17.tar.xz'), '3ba7439dfbea7af4876662c97f8e1f0cdad9231fc166e4861d17042489270057') - def test_microblaze_s3adsp1800_be(self): - self.set_machine('petalogix-s3adsp1800') + def do_ballerina_be_test(self, machine): + self.set_machine(machine) self.archive_extract(self.ASSET_IMAGE_BE) self.vm.set_console() self.vm.add_args('-kernel', @@ -34,5 +34,8 @@ def test_microblaze_s3adsp1800_be(self): # message, that's why we don't test for a later string here. This # needs some investigation by a microblaze wizard one day... + def test_microblaze_s3adsp1800_legacy_be(self): + self.do_ballerina_be_test('petalogix-s3adsp1800') + if __name__ == '__main__': QemuSystemTest.main() diff --git a/tests/functional/test_microblazeel_s3adsp1800.py b/tests/functional/test_microblazeel_s3adsp1800.py index 5d353dba5d2..715ef3f79ac 100755 --- a/tests/functional/test_microblazeel_s3adsp1800.py +++ b/tests/functional/test_microblazeel_s3adsp1800.py @@ -21,9 +21,9 @@ class MicroblazeelMachine(QemuSystemTest): ('http://www.qemu-advent-calendar.org/2023/download/day13.tar.gz'), 'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22') - def test_microblazeel_s3adsp1800_le(self): + def do_xmaton_le_test(self, machine): self.require_netdev('user') - self.set_machine('petalogix-s3adsp1800') + self.set_machine(machine) self.archive_extract(self.ASSET_IMAGE_LE) self.vm.set_console() self.vm.add_args('-kernel', self.scratch_file('day13', 'xmaton.bin')) @@ -38,5 +38,8 @@ def test_microblazeel_s3adsp1800_le(self): 'tftp -g -r xmaton.png 10.0.2.2 ; md5sum xmaton.png', '821cd3cab8efd16ad6ee5acc3642a8ea') + def test_microblaze_s3adsp1800_legacy_le(self): + self.do_xmaton_le_test('petalogix-s3adsp1800') + if __name__ == '__main__': QemuSystemTest.main() From patchwork Thu Feb 6 11:33:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13962921 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 60A81C0219D for ; Thu, 6 Feb 2025 11:35:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tg09d-000064-JR; Thu, 06 Feb 2025 06:34:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tg09R-0008Ho-Dx for qemu-devel@nongnu.org; Thu, 06 Feb 2025 06:34:33 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tg09P-0000tw-GN for qemu-devel@nongnu.org; Thu, 06 Feb 2025 06:34:33 -0500 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-38633b5dbcfso730232f8f.2 for ; Thu, 06 Feb 2025 03:34:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738841670; x=1739446470; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ppn20+OdDHYYHHj4mqusBuIEfs+xIwJ4iZjJotRYm4c=; b=joyjvxsv1FwPqbbxHnp8XsD7VhcOfbq2J5bYGl5bd5XeUKsB5+S3/u/M6A9YPsy15b fXL0OBFwv19sV0kpTghiq+cb6ActYw49vIwSvRNUHrY/IMsksuSChK5Ln8O8Pyn/OV/t iveYCVCztd8wfhePCqUOakfgEkjUEKwjcV9wiDp/tv1RiqymyS+o6OeI8FZNDBv1Jzlq lEo4djVp5PQQRh9i5c8FMD0FSksrolfy1eHrOhHuCDBuuSlFRJ+h0x8iCc6MRx0bdWbV FIZ+vYvuSKwM+Dh15DipiplAEum8N4jDZia+/veBmr11Xk2YuPKZh8kyz8EhaIC0Vboy zJIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738841670; x=1739446470; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ppn20+OdDHYYHHj4mqusBuIEfs+xIwJ4iZjJotRYm4c=; b=szedkpDSxboNvmujDpqN2iiehS3Wd8t1CrBFDps5QnH8v3fyXH0YNAQSohdMaK6Oil WBajM7Osw+lGo1MQRNTcAWG+Hh3+8Z8k6b0cEeKLevpT5CSMcfqA4zbjJqO4nBY3K6eL YPoTKlQPffb4mCgCOykimLcbgBXlc52qkRrm/dmED1ibhuyoafAP6pfNPJ9mdM28I3Xn oHR78agK+9gHh2A1AuuLG01ejkdiSmAnqrvzuS+CtWN6mqf3k7aRMjqWiQ/HlzwDStpS 4x8ctzPdPlpsYgG8O9MzRD2ig2HUDfEUIM6GZJMYgzqCmKtFMW4IIe/PGGE23QBuinu6 yZOw== X-Gm-Message-State: AOJu0YzOMGlMeMyz8OgXhHbX4xhvSohVtgKjS/mXMKi6/9dVd+/Pt+yY nRuHaKS7rA7hcJJrEdjz8i8bRAL8FMXYfZgO+JguY6kNp65gXnaPQ9xxl7nITxkCc+q0HdB2t5h PgYA= X-Gm-Gg: ASbGnctHpHtGYpeDfg4CLxNLnX7YVT7dnkLI5G9Z2AQItXJLVnjAVbEntTa41VL+tpU N8yc65xHO7NrEuQkn/96W607DFtT9jrNAsmlv97gUkeHzDIl3PexlY75x6l5c+GIFTqmdPZdLQt FKK48OyaPKZ4eUleHPshUWs+w8dy64QZqYrTim9RoFUwzZIl6gdoNKv2pBQ9wAzlCkdFa8KwhqZ 1k+u+RKdl9rWfXUKsWXvH4WFLvOq+31y9nOmYDcoPwcps+KohAuqyLm/u1rKHM+gqrDRc1s/U6E uNKzVtdcShYCWSuZ0SpWz97EZ8AqkWsg6Dj/eytMKn56OaaD+8CqCDrUG+gzzv3Kng== X-Google-Smtp-Source: AGHT+IHAQRrSCi+tR7QES1pKdhLqPnDoWgG/vvnnGvNajO00fDOm4PEIVaV1vFhM1MIrTvHxeIrp/g== X-Received: by 2002:a05:6000:144f:b0:38a:88ac:ed14 with SMTP id ffacd0b85a97d-38db489322dmr6016167f8f.19.1738841669620; Thu, 06 Feb 2025 03:34:29 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbdd5c87csm1531231f8f.52.2025.02.06.03.34.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:34:29 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 14/16] tests/functional: Have microblaze tests inherit common parent class Date: Thu, 6 Feb 2025 12:33:19 +0100 Message-ID: <20250206113321.94906-15-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Have the MicroblazeMachine class being common to both MicroblazeBigEndianMachine and MicroblazeLittleEndianMachine classes. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- tests/functional/test_microblaze_s3adsp1800.py | 2 ++ tests/functional/test_microblazeel_s3adsp1800.py | 5 ++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/tests/functional/test_microblaze_s3adsp1800.py b/tests/functional/test_microblaze_s3adsp1800.py index c4226f49cf3..2eff31f13a7 100755 --- a/tests/functional/test_microblaze_s3adsp1800.py +++ b/tests/functional/test_microblaze_s3adsp1800.py @@ -15,6 +15,8 @@ class MicroblazeMachine(QemuSystemTest): timeout = 90 +class MicroblazeBigEndianMachine(MicroblazeMachine): + ASSET_IMAGE_BE = Asset( ('https://qemu-advcal.gitlab.io/qac-best-of-multiarch/download/' 'day17.tar.xz'), diff --git a/tests/functional/test_microblazeel_s3adsp1800.py b/tests/functional/test_microblazeel_s3adsp1800.py index 715ef3f79ac..a3e8d7ca48e 100755 --- a/tests/functional/test_microblazeel_s3adsp1800.py +++ b/tests/functional/test_microblazeel_s3adsp1800.py @@ -12,10 +12,9 @@ from qemu_test import QemuSystemTest, Asset from qemu_test import wait_for_console_pattern +from test_microblaze_s3adsp1800 import MicroblazeMachine -class MicroblazeelMachine(QemuSystemTest): - - timeout = 90 +class MicroblazeLittleEndianMachine(MicroblazeMachine): ASSET_IMAGE_LE = Asset( ('http://www.qemu-advent-calendar.org/2023/download/day13.tar.gz'), From patchwork Thu Feb 6 11:33:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13962923 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EF957C02199 for ; Thu, 6 Feb 2025 11:35:28 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tg09g-0000de-LK; Thu, 06 Feb 2025 06:34:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tg09X-0008Rd-O1 for qemu-devel@nongnu.org; Thu, 06 Feb 2025 06:34:41 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tg09V-0000uB-Es for qemu-devel@nongnu.org; Thu, 06 Feb 2025 06:34:39 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-4362bae4d7dso5212515e9.1 for ; Thu, 06 Feb 2025 03:34:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738841674; x=1739446474; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yAMhBvq7A2sY4fwGEsHhx6BSBdhRyxbY21rGxZGSxvM=; b=ocTCYsG5vIN9FnMvPVEsJbgcjqie4rPjWP2D2lCxcB8PTy/46XRR188mOnKpGG6cTE 3D6jMePsh/4bezIQHCUyRLKv3a9ycXofNDZGaOOxmnQyfScDORsHE7+T7JZzrSLJjG3/ 7dWsQVfC276iTEFK0tTy+sxor8GhttXL149569XhxwL4E9SrUhUpn69k9rdWq+5T2+6g 4tgjpnM0g/yBt1+nVC0c3IPHOX+mF1NMceoW+Wxnpzr5rFZyKjgOiTyY6CUnmGlfh8S7 FCQF/pKa3LRPxuWSzqealzRX1+cB4Y/uMhozBpUcY5IC/2lKygST2II+W/5DlBZB0Urc 2BRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738841674; x=1739446474; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yAMhBvq7A2sY4fwGEsHhx6BSBdhRyxbY21rGxZGSxvM=; b=BSxz9Tzrdp4zIOhBDnyDkfSYduTgtoBJYN5fKpDswXa4+NKOblOFmi7FcO0KpO++wL 5Vio9MDhIUk3NL5NaauKjis2tToxvYXMkxMe1NKJRCmZqBDzXWhVJFZWGaeQMCiP/pWJ E+iTPbEjuXRsUa+5fKFTnLJlE+YujIKBTeVvzFS0NpNzo2HlF1rLGr8ZXMzIAWL/dJ3C gD0K5T2R9c1KV6/0aAYNl0p7YClh8yaDRaAKpK1N4Y0GS51n1Y/4l4exGzpXclEXOJKG feiylXmVyvbV8xxAyIfccI5+IdUrJKSedM4jMcbYdqcJ2ANcaXGK/2a+rsFjmW2vtEJl 44sg== X-Gm-Message-State: AOJu0YxFrj0Lv+TqfT1WPC5f6+XYozz+irL7WdYnIeHodU5FUKpCBOkN wPaiWHfJjTvnNBUnKZ6xXr+H42MwED0yFQ7hqj+AAfX/l2UNTWprjm0SvRO2DvIeSvm7Mtz5hNp MYu0= X-Gm-Gg: ASbGncuZxDKI9U+DOKGUCEv/aezBLvb4TNyvzC9F3WcFhs/dyvE7W3bP5w39G7QVRDu wNfIEAjtnFosRgu64RXfM5YoO29rYH6llOKQL2vq0pmkA6svwYIH/tSL2x+gWCZbTMERzfMqo0+ knWiW6l2YOrU6lIpke6AiSY+QopMAxyyow9EYPSQdAP+oBdV+BTHmxtlHMnDr6yrNn2z5YcuKYq hYY1Iek3ZCGxFGoWK5A0Zm7bDGm8ij/biypY9rtHzANJbAJwLBrSfU7XXMOjeMFT8xYDFYLJPTh SFXkd7x2o55LzftjbgiiJAgnyxlpJ5W9AZWvNWUfh6j+PPf4VMO43lqYoc3o9BHiYA== X-Google-Smtp-Source: AGHT+IEfGvV2b1BPGx53WX/PLS5iBl0xNOj9vyBurztjteOF2A9+qzHUiIYnL3G/zvkmUW40W+h2IQ== X-Received: by 2002:a05:600c:1c14:b0:434:fec5:4ef5 with SMTP id 5b1f17b1804b1-4390d43d8e1mr62990335e9.14.1738841674368; Thu, 06 Feb 2025 03:34:34 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391dfd8047sm16124075e9.33.2025.02.06.03.34.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:34:33 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 15/16] tests/functional: Move microblaze tests to common parent class Date: Thu, 6 Feb 2025 12:33:20 +0100 Message-ID: <20250206113321.94906-16-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Move the xmaton and ballerina tests to the parent class. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- .../functional/test_microblaze_s3adsp1800.py | 27 +++++++++++++++++-- .../test_microblazeel_s3adsp1800.py | 26 +----------------- 2 files changed, 26 insertions(+), 27 deletions(-) diff --git a/tests/functional/test_microblaze_s3adsp1800.py b/tests/functional/test_microblaze_s3adsp1800.py index 2eff31f13a7..0447097c048 100755 --- a/tests/functional/test_microblaze_s3adsp1800.py +++ b/tests/functional/test_microblaze_s3adsp1800.py @@ -7,6 +7,8 @@ # This work is licensed under the terms of the GNU GPL, version 2 or # later. See the COPYING file in the top-level directory. +import time +from qemu_test import exec_command, exec_command_and_wait_for_pattern from qemu_test import QemuSystemTest, Asset from qemu_test import wait_for_console_pattern @@ -15,13 +17,15 @@ class MicroblazeMachine(QemuSystemTest): timeout = 90 -class MicroblazeBigEndianMachine(MicroblazeMachine): - ASSET_IMAGE_BE = Asset( ('https://qemu-advcal.gitlab.io/qac-best-of-multiarch/download/' 'day17.tar.xz'), '3ba7439dfbea7af4876662c97f8e1f0cdad9231fc166e4861d17042489270057') + ASSET_IMAGE_LE = Asset( + ('http://www.qemu-advent-calendar.org/2023/download/day13.tar.gz'), + 'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22') + def do_ballerina_be_test(self, machine): self.set_machine(machine) self.archive_extract(self.ASSET_IMAGE_BE) @@ -36,6 +40,25 @@ def do_ballerina_be_test(self, machine): # message, that's why we don't test for a later string here. This # needs some investigation by a microblaze wizard one day... + def do_xmaton_le_test(self, machine): + self.require_netdev('user') + self.set_machine(machine) + self.archive_extract(self.ASSET_IMAGE_LE) + self.vm.set_console() + self.vm.add_args('-kernel', self.scratch_file('day13', 'xmaton.bin')) + tftproot = self.scratch_file('day13') + self.vm.add_args('-nic', f'user,tftp={tftproot}') + self.vm.launch() + wait_for_console_pattern(self, 'QEMU Advent Calendar 2023') + time.sleep(0.1) + exec_command(self, 'root') + time.sleep(0.1) + exec_command_and_wait_for_pattern(self, + 'tftp -g -r xmaton.png 10.0.2.2 ; md5sum xmaton.png', + '821cd3cab8efd16ad6ee5acc3642a8ea') + +class MicroblazeBigEndianMachine(MicroblazeMachine): + def test_microblaze_s3adsp1800_legacy_be(self): self.do_ballerina_be_test('petalogix-s3adsp1800') diff --git a/tests/functional/test_microblazeel_s3adsp1800.py b/tests/functional/test_microblazeel_s3adsp1800.py index a3e8d7ca48e..56645bd0bb2 100755 --- a/tests/functional/test_microblazeel_s3adsp1800.py +++ b/tests/functional/test_microblazeel_s3adsp1800.py @@ -7,36 +7,12 @@ # This work is licensed under the terms of the GNU GPL, version 2 or # later. See the COPYING file in the top-level directory. -import time -from qemu_test import exec_command, exec_command_and_wait_for_pattern -from qemu_test import QemuSystemTest, Asset -from qemu_test import wait_for_console_pattern +from qemu_test import QemuSystemTest from test_microblaze_s3adsp1800 import MicroblazeMachine class MicroblazeLittleEndianMachine(MicroblazeMachine): - ASSET_IMAGE_LE = Asset( - ('http://www.qemu-advent-calendar.org/2023/download/day13.tar.gz'), - 'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22') - - def do_xmaton_le_test(self, machine): - self.require_netdev('user') - self.set_machine(machine) - self.archive_extract(self.ASSET_IMAGE_LE) - self.vm.set_console() - self.vm.add_args('-kernel', self.scratch_file('day13', 'xmaton.bin')) - tftproot = self.scratch_file('day13') - self.vm.add_args('-nic', f'user,tftp={tftproot}') - self.vm.launch() - wait_for_console_pattern(self, 'QEMU Advent Calendar 2023') - time.sleep(0.1) - exec_command(self, 'root') - time.sleep(0.1) - exec_command_and_wait_for_pattern(self, - 'tftp -g -r xmaton.png 10.0.2.2 ; md5sum xmaton.png', - '821cd3cab8efd16ad6ee5acc3642a8ea') - def test_microblaze_s3adsp1800_legacy_le(self): self.do_xmaton_le_test('petalogix-s3adsp1800') From patchwork Thu Feb 6 11:33:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13962926 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6803FC02194 for ; Thu, 6 Feb 2025 11:36:33 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tg09e-0000Ri-T4; Thu, 06 Feb 2025 06:34:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tg09a-0008TZ-Gn for qemu-devel@nongnu.org; Thu, 06 Feb 2025 06:34:43 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tg09Y-0000yB-TV for qemu-devel@nongnu.org; Thu, 06 Feb 2025 06:34:42 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-436ce2ab251so4879845e9.1 for ; Thu, 06 Feb 2025 03:34:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738841679; x=1739446479; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mb4oxd/vwXhE6pcy1gQ3cwUL95fH15TJV9xJOH6RkVw=; b=PlPF0GDrcztjPDpBX21OWQqK+6nfc9HzPYg7Ka4Qmx86wWO99CfQNAWpotsaCp13a6 lNvaovYlpgdNcui8i2mAm+EbG/cEKvbfXaH+tXSUkSqSamnj0X9VfqYQPfZ6ZbK3WQ+I cOmJ/zGI4ly3MVrdeQVGnUAdQ8uh6AJ0G2Jglr56b20q5aHXkuqf6FYwQcj2qr3Cvt4T FhsM5OZ4JzbQ+ZamRAH9Y5b3ZGFrKPH/R3QjYwvQhiknX2eODgyP6+ImMRa05cqdNhy8 nwRCV746+CaJ03GX2xHSxucCKjDa2OH3pKZG2HnWSX45UsqTcQ+u/dB37TbtP35Vg7B0 1YAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738841679; x=1739446479; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mb4oxd/vwXhE6pcy1gQ3cwUL95fH15TJV9xJOH6RkVw=; b=eS5p36AuNBkmrYMYXuS29Tks0pD6IHuodk1NdH9J9Uwp2Sl9LNOJ1QqwL2biZyE2SP xOpxqVTzDDfGT2tCdL2xBr7t1z4ZBSLNCy+MAAFK6l+DCh0Ee3z9DhuTCqZ6AQLI/2ss iMW325I2XaXsprZbuepq3m+zPjNEoIQp6XQIaJFjxInWOrgMMKir4pjEKPZzC8MCEPJU FPOpN2NdMDzbYM6zu7T2YBwD8A602kxnn0BHZamTURu7W4EHvzDsQWVf1EZpesfFcoWD 3FFdWIB/xVU4gE8mQfCocSbQ9xfO3xmkVBDFCS8iQD9uxv3Pbe3peSp0oanmQlQcWRsj AKkQ== X-Gm-Message-State: AOJu0YxTFo2rh7XwE3BhiO4lwn5D40wyScagyEjdppN9p3QUIo9P8i1B kB12TLzB1UkF2zmWEYUEpgpmC+XmZuj9B30BgxgP3/LLP6uEWbAz1jMWeKk9dBJScpqiF/IWst9 avnk= X-Gm-Gg: ASbGncs5o1xcP6DjfGXwIDmGKWu7YYPJGP764GB9PZb3ubrkD/enY6jZ/6e3E3Q05/d 8emhRLghbv1uvgfDlLpf3pN8iCvU+6NHjv6YqI9Rd0R6bQ/+vVv+Ay0nlMvuJbUvtDATYMHejKR aQT2AGfpy3efn3+12x/gJN8qet/7BwdG0QRHf/sQTExoOSPpBE1ml8TCrJuTB1/a4rLptjFVcms kAg/lQAacJQ7QUstGEss/33td1e2Oec61RUeMzIgWpDVLrCNpXd0f9IlB0ipopc2bjTCuVPgtDH 9pFW5OT1wsrXu28CpHRaq0IH+yT4PpgXrvontEWj8A8fByYVGciaZHmzzYUEplAbLA== X-Google-Smtp-Source: AGHT+IGF9HvknI0edaGlbn1rCuTBPeqW2Y/LChlLFvTOSIh+PbJVZZHVr5CQm7+HJyUEG5X7mb4i1A== X-Received: by 2002:a5d:64a3:0:b0:385:fbb7:672d with SMTP id ffacd0b85a97d-38db48e4703mr4251893f8f.52.1738841679009; Thu, 06 Feb 2025 03:34:39 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbdd55656sm1517180f8f.50.2025.02.06.03.34.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 03:34:38 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Alistair Francis , Richard Henderson , Thomas Huth , Jason Wang , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v4 16/16] tests/functional: Run cross-endian microblaze tests Date: Thu, 6 Feb 2025 12:33:21 +0100 Message-ID: <20250206113321.94906-17-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206113321.94906-1-philmd@linaro.org> References: <20250206113321.94906-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Ensure microblaze machines can run cross-endianness by running all tests on all machines. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- tests/functional/test_microblaze_s3adsp1800.py | 6 ++++++ tests/functional/test_microblazeel_s3adsp1800.py | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/tests/functional/test_microblaze_s3adsp1800.py b/tests/functional/test_microblaze_s3adsp1800.py index 0447097c048..f955f6f4021 100755 --- a/tests/functional/test_microblaze_s3adsp1800.py +++ b/tests/functional/test_microblaze_s3adsp1800.py @@ -62,5 +62,11 @@ class MicroblazeBigEndianMachine(MicroblazeMachine): def test_microblaze_s3adsp1800_legacy_be(self): self.do_ballerina_be_test('petalogix-s3adsp1800') + def test_microblaze_s3adsp1800_be(self): + self.do_ballerina_be_test('petalogix-s3adsp1800-be') + + def test_microblaze_s3adsp1800_le(self): + self.do_xmaton_le_test('petalogix-s3adsp1800-le') + if __name__ == '__main__': QemuSystemTest.main() diff --git a/tests/functional/test_microblazeel_s3adsp1800.py b/tests/functional/test_microblazeel_s3adsp1800.py index 56645bd0bb2..b10944bbb0c 100755 --- a/tests/functional/test_microblazeel_s3adsp1800.py +++ b/tests/functional/test_microblazeel_s3adsp1800.py @@ -16,5 +16,11 @@ class MicroblazeLittleEndianMachine(MicroblazeMachine): def test_microblaze_s3adsp1800_legacy_le(self): self.do_xmaton_le_test('petalogix-s3adsp1800') + def test_microblaze_s3adsp1800_le(self): + self.do_xmaton_le_test('petalogix-s3adsp1800-le') + + def test_microblaze_s3adsp1800_be(self): + self.do_ballerina_be_test('petalogix-s3adsp1800-be') + if __name__ == '__main__': QemuSystemTest.main()