From patchwork Thu Feb 6 13:40:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13963101 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1B3BE1EA7E6; Thu, 6 Feb 2025 13:41:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738849277; cv=none; b=k0eKw5BCTihg3N+vaKRCC+h/aet7NhxfDZ1pPEFd0w1PPPrw2Oz2k0VY/HbJf5Ogu7syShAhwX9c03aX45Pdj6lFIWF9o9wprVBgfJfOna/KVXsbdYj9eqYJaARAD6Vx8Q9z3/L5irNbmmdGGNpOK8bTT9X/i/1BiFIxojZKk4Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738849277; c=relaxed/simple; bh=5UgH3I7aNcG/NdlWKu5bB/yhGM+ZYZ+h7XRAtybVB/w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=REQtHKBt2ITxT21VvPmZRv5oxQZwDH25UelTWp1SY9D86op9v62jZAIb+sniLUsjyynLIqA8hwloDL0XtepGhiS4pmj7CZ49GgAo5hLADVd5qWrBgNKc4W94J/kHodm2BQ4r0cV05Q2gA21s5v+pIV/AM0hnlU6Ol+Zkt5vSFxQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: R0fKXebyQL2qpE4wF/wvfA== X-CSE-MsgGUID: ev6sIeFoQsaKtigGp78dYQ== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 06 Feb 2025 22:41:06 +0900 Received: from localhost.localdomain (unknown [10.226.92.229]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 4F7D9401BEF2; Thu, 6 Feb 2025 22:40:54 +0900 (JST) From: Biju Das To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , Wolfram Sang , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Conor Dooley Subject: [PATCH v3 1/8] dt-bindings: mmc: renesas,sdhi: Document RZ/G3E support Date: Thu, 6 Feb 2025 13:40:25 +0000 Message-ID: <20250206134047.67866-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250206134047.67866-1-biju.das.jz@bp.renesas.com> References: <20250206134047.67866-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The SD/MMC block on the RZ/G3E ("R9A09G047") SoC is similar to that of the RZ/V2H, but the SD0 channel has only dedicated pins, so we must use SD_STATUS register to control voltage and power enable (internal regulator), for non-fixed voltage (SD) MMC interface. However, it is optional for fixed voltage MMC interface (eMMC). For SD1 and SD2 channels, we can either use gpio regulator or internal regulator (using SD_STATUS register) for voltage switching. Document RZ/G3E SDHI IP support with optional internal regulator for both RZ/G3E and RZ/V2H SoC. Signed-off-by: Biju Das Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven --- v2->v3: * Collected tags. v1->v2: * Dropped tags. * Documented internal regulator as optional property for both RZ/G3E and RZ/V2H SoCs. --- .../devicetree/bindings/mmc/renesas,sdhi.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml index af378b9ff3f4..773baa6c2656 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml @@ -68,6 +68,9 @@ properties: - renesas,sdhi-r9a08g045 # RZ/G3S - renesas,sdhi-r9a09g011 # RZ/V2M - const: renesas,rzg2l-sdhi + - items: + - const: renesas,sdhi-r9a09g047 # RZ/G3E + - const: renesas,sdhi-r9a09g057 # RZ/V2H(P) reg: maxItems: 1 @@ -211,6 +214,19 @@ allOf: sectioned off to be run by a separate second clock source to allow the main core clock to be turned off to save power. + - if: + properties: + compatible: + contains: + const: renesas,sdhi-r9a09g057 + then: + properties: + vqmmc-regulator: + type: object + description: VQMMC SD regulator + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + required: - compatible - reg From patchwork Thu Feb 6 13:40:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13963102 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1FFA41EA7FB; Thu, 6 Feb 2025 13:41:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738849279; cv=none; b=Pyd368bQFvAFwo6o5OD6dPrS8uNi9NZFY2LsIw0WGGNcwnuJoZ0sjglnbZZLmPlZrYKNydFdqAulxibRJXGuel54wKlASaqpxgBYAlby1JGyRc7Vnot6Okfa/BVBf+eRdRuOGKEEmJZKIIqYgwMcvZSF1Njy6gHWc8RhuWpGtdY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738849279; c=relaxed/simple; bh=meBUZVdj5HF5hOtr43+IkqxUQTyNQTg8dEQ1B8JhiMQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Q6GZa0D3jzurFu8qzB2rKzD8Ne4hZizOvOeFeJGFmmCc8x/dZxZl6Xj9xAGC98Z1rT2uFXZ36iAm4mvAlr5vAyU2OtNRPFT/izTVqXQZg/q68p2og5Up3BTogFCiHgihprRz1wLIGfdVEi2I82E2JcbpXxXSzLNEgxuavX7d+hk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: vRPdRUcQSbue9T6FyphwSw== X-CSE-MsgGUID: pacqQ75XRqG7wS6ivPQP4w== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 06 Feb 2025 22:41:14 +0900 Received: from localhost.localdomain (unknown [10.226.92.229]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id E6FAE401BEF4; Thu, 6 Feb 2025 22:40:58 +0900 (JST) From: Biju Das To: Ulf Hansson Cc: Biju Das , Wolfram Sang , linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , Tommaso Merciai Subject: [PATCH v3 2/8] mmc: renesas_sdhi: Arrange local variables in reverse xmas tree order Date: Thu, 6 Feb 2025 13:40:26 +0000 Message-ID: <20250206134047.67866-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250206134047.67866-1-biju.das.jz@bp.renesas.com> References: <20250206134047.67866-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Arrange local variables in reverse xmas tree for probe(). Reviewed-by: Tommaso Merciai Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v2->v3: * No change. v1->v2: * Collected tags. --- drivers/mmc/host/renesas_sdhi_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c index f73b84bae0c4..6ea651409774 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -910,8 +910,8 @@ int renesas_sdhi_probe(struct platform_device *pdev, const struct renesas_sdhi_quirks *quirks) { struct tmio_mmc_data *mmd = pdev->dev.platform_data; - struct tmio_mmc_data *mmc_data; struct renesas_sdhi_dma *dma_priv; + struct tmio_mmc_data *mmc_data; struct tmio_mmc_host *host; struct renesas_sdhi *priv; int num_irqs, irq, ret, i; From patchwork Thu Feb 6 13:40:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13963104 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 871341624C0; Thu, 6 Feb 2025 13:41:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738849280; cv=none; b=cQaOTPptG54qnNR7WCEZ7nP2bWGUvQ47UNaYTHlylrK1sLIXmFlRANYCDYWZeoq7v/lXwSiR4BkxRGltld8LyP5lKx4OVIEwB6ymxr9sAKY05SAenq3GrFHxbKKAYMMDiyHf9vKCETPtGzs6oC4q9Asrhe7QmhRgyG0vO0uWtgU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738849280; c=relaxed/simple; bh=PfxzXCzoOkraT1JWXG8zxbraZQK3Akz+pg775Hliqxg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=foShRStz5HQ8Jo23yQMskiglsn3mR4wLW6TNYDOgpp4MIDgyu3YsEfjMpZRsElX4Pmn6wwEJXTauyJT/P16pFEBvB5oGXFXs9zkh09Dx16JWRbUEHC7AOkS5FX5aKZ7vnNPPZERsBO8wiiaisgaWpGltQMAAXJfRhNTp/y2OLVg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: IHVM6+zQRVCpTq8y8fvqRQ== X-CSE-MsgGUID: G4bZRSedQXeaAkAPDYtHXw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 06 Feb 2025 22:41:09 +0900 Received: from localhost.localdomain (unknown [10.226.92.229]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 3D21E401D708; Thu, 6 Feb 2025 22:41:01 +0900 (JST) From: Biju Das To: Ulf Hansson Cc: Biju Das , Wolfram Sang , linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 3/8] mmc: renesas_sdhi: Add support for RZ/G3E SoC Date: Thu, 6 Feb 2025 13:40:27 +0000 Message-ID: <20250206134047.67866-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250206134047.67866-1-biju.das.jz@bp.renesas.com> References: <20250206134047.67866-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The SDHI/eMMC IPs in the RZ/G3E SoC are similar to those in R-Car Gen3. However, the RZ/G3E SD0 channel has Voltage level control and PWEN pin support via SD_STATUS register. internal regulator support is added to control the voltage levels of the SD pins via sd_iovs/sd_pwen bits in SD_STATUS register by populating vqmmc-regulator child node. SD1 and SD2 channels have gpio regulator support and internal regulator support. Selection of the regulator is based on the regulator phandle. Similar case for SD0 fixed voltage (eMMC) that uses fixed regulator and SD0 non-fixed voltage (SD0) that uses internal regulator. Signed-off-by: Biju Das --- v2->v3: * No change. v1->v2: * Updated commit description for regulator used in SD0 fixed and non-fixed voltage case. * As the node enabling of internal regulator is controlled through status, added a check for device availability. --- drivers/mmc/host/renesas_sdhi.h | 1 + drivers/mmc/host/renesas_sdhi_core.c | 134 +++++++++++++++++++++++++++ drivers/mmc/host/tmio_mmc.h | 5 + 3 files changed, 140 insertions(+) diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdhi.h index f12a87442338..291ddb4ad9be 100644 --- a/drivers/mmc/host/renesas_sdhi.h +++ b/drivers/mmc/host/renesas_sdhi.h @@ -95,6 +95,7 @@ struct renesas_sdhi { struct reset_control *rstc; struct tmio_mmc_host *host; + struct regulator_dev *rdev; }; #define host_to_priv(host) \ diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c index 6ea651409774..99700d89aa8c 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -32,6 +32,8 @@ #include #include #include +#include +#include #include #include #include @@ -581,12 +583,24 @@ static void renesas_sdhi_reset(struct tmio_mmc_host *host, bool preserve) if (!preserve) { if (priv->rstc) { + u32 sd_status; + /* + * HW reset might have toggled the regulator state in + * HW which regulator core might be unaware of so save + * and restore the regulator state during HW reset. + */ + if (priv->rdev) + sd_ctrl_read32_rep(host, CTL_SD_STATUS, &sd_status, 1); + reset_control_reset(priv->rstc); /* Unknown why but without polling reset status, it will hang */ read_poll_timeout(reset_control_status, ret, ret == 0, 1, 100, false, priv->rstc); /* At least SDHI_VER_GEN2_SDR50 needs manual release of reset */ sd_ctrl_write16(host, CTL_RESET_SD, 0x0001); + if (priv->rdev) + sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); + priv->needs_adjust_hs400 = false; renesas_sdhi_set_clock(host, host->clk_cache); @@ -904,15 +918,113 @@ static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) renesas_sdhi_sdbuf_width(host, enable ? width : 16); } +static const unsigned int renesas_sdhi_vqmmc_voltages[] = { + 3300000, 1800000 +}; + +static int renesas_sdhi_regulator_disable(struct regulator_dev *rdev) +{ + struct tmio_mmc_host *host = rdev_get_drvdata(rdev); + u32 sd_status; + + sd_ctrl_read32_rep(host, CTL_SD_STATUS, &sd_status, 1); + sd_status &= ~SD_STATUS_PWEN; + sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); + + return 0; +} + +static int renesas_sdhi_regulator_enable(struct regulator_dev *rdev) +{ + struct tmio_mmc_host *host = rdev_get_drvdata(rdev); + u32 sd_status; + + sd_ctrl_read32_rep(host, CTL_SD_STATUS, &sd_status, 1); + sd_status |= SD_STATUS_PWEN; + sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); + + return 0; +} + +static int renesas_sdhi_regulator_is_enabled(struct regulator_dev *rdev) +{ + struct tmio_mmc_host *host = rdev_get_drvdata(rdev); + u32 sd_status; + + sd_ctrl_read32_rep(host, CTL_SD_STATUS, &sd_status, 1); + + return (sd_status & SD_STATUS_PWEN) ? 1 : 0; +} + +static int renesas_sdhi_regulator_get_voltage(struct regulator_dev *rdev) +{ + struct tmio_mmc_host *host = rdev_get_drvdata(rdev); + u32 sd_status; + + sd_ctrl_read32_rep(host, CTL_SD_STATUS, &sd_status, 1); + + return (sd_status & SD_STATUS_IOVS) ? 1800000 : 3300000; +} + +static int renesas_sdhi_regulator_set_voltage(struct regulator_dev *rdev, + int min_uV, int max_uV, + unsigned int *selector) +{ + struct tmio_mmc_host *host = rdev_get_drvdata(rdev); + u32 sd_status; + + sd_ctrl_read32_rep(host, CTL_SD_STATUS, &sd_status, 1); + if (min_uV >= 1700000 && max_uV <= 1950000) { + sd_status |= SD_STATUS_IOVS; + *selector = 1; + } else { + sd_status &= ~SD_STATUS_IOVS; + *selector = 0; + } + sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); + + return 0; +} + +static int renesas_sdhi_regulator_list_voltage(struct regulator_dev *rdev, + unsigned int selector) +{ + if (selector >= ARRAY_SIZE(renesas_sdhi_vqmmc_voltages)) + return -EINVAL; + + return renesas_sdhi_vqmmc_voltages[selector]; +} + +static const struct regulator_ops renesas_sdhi_regulator_voltage_ops = { + .enable = renesas_sdhi_regulator_enable, + .disable = renesas_sdhi_regulator_disable, + .is_enabled = renesas_sdhi_regulator_is_enabled, + .list_voltage = renesas_sdhi_regulator_list_voltage, + .get_voltage = renesas_sdhi_regulator_get_voltage, + .set_voltage = renesas_sdhi_regulator_set_voltage, +}; + +static struct regulator_desc renesas_sdhi_vqmmc_regulator = { + .of_match = of_match_ptr("vqmmc-regulator"), + .owner = THIS_MODULE, + .type = REGULATOR_VOLTAGE, + .ops = &renesas_sdhi_regulator_voltage_ops, + .volt_table = renesas_sdhi_vqmmc_voltages, + .n_voltages = ARRAY_SIZE(renesas_sdhi_vqmmc_voltages), +}; + int renesas_sdhi_probe(struct platform_device *pdev, const struct tmio_mmc_dma_ops *dma_ops, const struct renesas_sdhi_of_data *of_data, const struct renesas_sdhi_quirks *quirks) { + struct regulator_config rcfg = { .dev = &pdev->dev, }; struct tmio_mmc_data *mmd = pdev->dev.platform_data; struct renesas_sdhi_dma *dma_priv; + struct device *dev = &pdev->dev; struct tmio_mmc_data *mmc_data; struct tmio_mmc_host *host; + struct regulator_dev *rdev; struct renesas_sdhi *priv; int num_irqs, irq, ret, i; struct resource *res; @@ -1053,6 +1165,28 @@ int renesas_sdhi_probe(struct platform_device *pdev, if (ret) goto efree; + rcfg.of_node = of_get_child_by_name(dev->of_node, "vqmmc-regulator"); + if (!of_device_is_available(rcfg.of_node)) { + of_node_put(rcfg.of_node); + rcfg.of_node = NULL; + } + + if (rcfg.of_node) { + rcfg.driver_data = priv->host; + + renesas_sdhi_vqmmc_regulator.name = "sdhi-vqmmc-regulator"; + renesas_sdhi_vqmmc_regulator.of_match = of_match_ptr("vqmmc-regulator"); + renesas_sdhi_vqmmc_regulator.type = REGULATOR_VOLTAGE; + renesas_sdhi_vqmmc_regulator.owner = THIS_MODULE; + rdev = devm_regulator_register(dev, &renesas_sdhi_vqmmc_regulator, &rcfg); + of_node_put(rcfg.of_node); + if (IS_ERR(rdev)) { + dev_err(dev, "regulator register failed err=%ld", PTR_ERR(rdev)); + goto efree; + } + priv->rdev = rdev; + } + ver = sd_ctrl_read16(host, CTL_VERSION); /* GEN2_SDR104 is first known SDHI to use 32bit block count */ if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX) diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h index a75755f31d31..5970ca598850 100644 --- a/drivers/mmc/host/tmio_mmc.h +++ b/drivers/mmc/host/tmio_mmc.h @@ -44,6 +44,7 @@ #define CTL_RESET_SD 0xe0 #define CTL_VERSION 0xe2 #define CTL_SDIF_MODE 0xe6 /* only known on R-Car 2+ */ +#define CTL_SD_STATUS 0xf2 /* only known on RZ/{G2L,G3E,V2H} */ /* Definitions for values the CTL_STOP_INTERNAL_ACTION register can take */ #define TMIO_STOP_STP BIT(0) @@ -103,6 +104,10 @@ /* Definitions for values the CTL_SDIF_MODE register can take */ #define SDIF_MODE_HS400 BIT(0) /* only known on R-Car 2+ */ +/* Definitions for values the CTL_SD_STATUS register can take */ +#define SD_STATUS_PWEN BIT(0) /* only known on RZ/{G3E,V2H} */ +#define SD_STATUS_IOVS BIT(16) /* only known on RZ/{G3E,V2H} */ + /* Define some IRQ masks */ /* This is the mask used at reset by the chip */ #define TMIO_MASK_ALL 0x837f031d From patchwork Thu Feb 6 13:40:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13963106 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7C7601EA7E6; Thu, 6 Feb 2025 13:41:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738849282; cv=none; b=lZqTkz1Z4rfq9fKC80slqPwnrhd0KQ1EeD2PLg9jOAo0mbqfzO5YzaNgWySguMkvx/qoJOKSjebTi0LCzqO4RtJ9Vmy8bNxxamGMwMSfx9x6CUV/NSbnhlmUPjsd4suroOjuTNdzATCZdzcliD9keNkaZywLmP5+IYcw0SLTBLs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738849282; c=relaxed/simple; bh=njQ0w/Q67Luy8msFHE6OWV345+7CejRyYFpOSIibU0E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IKjYTFHi+mbzAjSJaP5ow56ANsnhRQPjHuWrrORYPqf126AuaRx81s+/hI5Ox1Jzspb0pdsVjXeXPHEJoOqn0G73h0E5rFhmRSWXuxpVyP+cmqFv9CHsIaBtVpA+5ytpMZa4lbdRDuAjmwJ3Y0nq3Q0SVOFJn7qwGvJHOWwINts= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: rmPHV+egSpS9nfCpB35sCw== X-CSE-MsgGUID: YLb/JQR9QtWGYzF7Eytt4A== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 06 Feb 2025 22:41:20 +0900 Received: from localhost.localdomain (unknown [10.226.92.229]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 3ADE3401E51E; Thu, 6 Feb 2025 22:41:04 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 4/8] arm64: dts: renesas: r9a09g047: Add SDHI0-SDHI2 nodes Date: Thu, 6 Feb 2025 13:40:28 +0000 Message-ID: <20250206134047.67866-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250206134047.67866-1-biju.das.jz@bp.renesas.com> References: <20250206134047.67866-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add SDHI0-SDHI2 nodes to RZ/G3E ("R9A09G047") SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v2->v3: * Renamed internal regulator labels vqmmc_sdhi{0..2}->sdhi{0..2}_vqmmc. v1->v2: * Status of internal regulator is disabled in the SoC .dtsi. Override the status in the board DTS when needed. --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index c93aa16d0a6e..fe5eec87f2a5 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -410,6 +410,66 @@ gic: interrupt-controller@14900000 { interrupt-controller; interrupts = ; }; + + sdhi0: mmc@15c00000 { + compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; + reg = <0x0 0x15c00000 0 0x10000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, + <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg 0xa7>; + power-domains = <&cpg>; + status = "disabled"; + + sdhi0_vqmmc: vqmmc-regulator { + regulator-name = "SDHI0-VQMMC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; + }; + + sdhi1: mmc@15c10000 { + compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; + reg = <0x0 0x15c10000 0 0x10000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, + <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg 0xa8>; + power-domains = <&cpg>; + status = "disabled"; + + sdhi1_vqmmc: vqmmc-regulator { + regulator-name = "SDHI1-VQMMC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; + }; + + sdhi2: mmc@15c20000 { + compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; + reg = <0x0 0x15c20000 0 0x10000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, + <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg 0xa9>; + power-domains = <&cpg>; + status = "disabled"; + + sdhi2_vqmmc: vqmmc-regulator { + regulator-name = "SDHI2-VQMMC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; + }; }; timer { From patchwork Thu Feb 6 13:40:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13963103 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 47FA41EA7C2; Thu, 6 Feb 2025 13:41:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738849279; cv=none; b=pXqhvDFxbk5fUh8a6HDkZ77ETBgXXhWJSdTRI5Te/gV7A0RwgzeT02zRJwncwNbeInYYgmqJARNWggglu+7uc++j2xTCwEXeWPPPdE2kbUqnebQrzaBbgrW48EhfM+9QHqkvRfthjKhsijEYe39O2bWjSNQBenoexSD29HZgDiE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738849279; c=relaxed/simple; bh=8/Me2jyoOmL+lQ0+uhKz8sREYGOZnEtjhxKavj08+jY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aSvT8BAU7Dhr4ry+B3Ycl8rpER5FqNN80rgkc/kYTrH8jNxZHhBXkqg+dmgRu6EzBfEa3rMtOGiI7+aebHtiV/HccWu9spE4mEAuzqFtjst0KCOrPug0mJJ7ydtMirnuxt4a1PtYNpebvqqRIMyLL+h2GVik+JOO6/Itwlid8fE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: vCsnvaXzS1ivGy5h6lR0yw== X-CSE-MsgGUID: GDi92Ep9TmK7VOUObc6HpQ== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 06 Feb 2025 22:41:11 +0900 Received: from localhost.localdomain (unknown [10.226.92.229]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id C23814019C60; Thu, 6 Feb 2025 22:41:08 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 5/8] arm64: dts: renesas: r9a09g057: Add support for enabling SDHI internal regulator Date: Thu, 6 Feb 2025 13:40:29 +0000 Message-ID: <20250206134047.67866-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250206134047.67866-1-biju.das.jz@bp.renesas.com> References: <20250206134047.67866-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for enabling SDHI internal regulator, by overriding the status on the board DTS, when needed. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- * Updated commit description * Renamed internal regulator labels vqmmc_sdhi{0..2}->sdhi{0..2}_vqmmc. * Dropped renaming the gpio regulator label vqmmc_sdhi1->vqmmc_sdhi1_gpio. --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index f7a2f8ca864f..bdaab9ae10b8 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -602,6 +602,13 @@ sdhi0: mmc@15c00000 { resets = <&cpg 0xa7>; power-domains = <&cpg>; status = "disabled"; + + sdhi0_vqmmc: vqmmc-regulator { + regulator-name = "SDHI0-VQMMC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; }; sdhi1: mmc@15c10000 { @@ -615,6 +622,13 @@ sdhi1: mmc@15c10000 { resets = <&cpg 0xa8>; power-domains = <&cpg>; status = "disabled"; + + sdhi1_vqmmc: vqmmc-regulator { + regulator-name = "SDHI1-VQMMC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; }; sdhi2: mmc@15c20000 { @@ -628,6 +642,13 @@ sdhi2: mmc@15c20000 { resets = <&cpg 0xa9>; power-domains = <&cpg>; status = "disabled"; + + sdhi2_vqmmc: vqmmc-regulator { + regulator-name = "SDHI2-VQMMC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; }; }; From patchwork Thu Feb 6 13:40:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13963105 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6E5F21EA7E6; Thu, 6 Feb 2025 13:41:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738849280; cv=none; b=j39F4/jwMd+ZQFGQwo8PsTNUThjYdYCRlzWouEkKkgS8fXv9vg1I/2hW8eAwUyxYhWlm/IgcsyjONQpP7fLqLlSbZRYfi6/XsbQSgY4NN/mHMfzDaTERuMfRIgVxFSf9JOTo0fP7Er2J2Ehr3sPigCcpwp3+zD2hd1hVdbzCvM8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738849280; c=relaxed/simple; bh=f6jtMJfnZlcitHmz+gjpr3KcBjp3XBElrrxhWAD8ARk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=F7sXA/4DHbpyta1CKcIfe147MXPZNjTVDHGWOvtBM7J329vW2BHICWsf5aEMNN3vgjdYY285fhKn+Dlt5ytnAAC8hMzeu/ydQs3IqAH4OaCRjs3odS1wiZLGd7xn2v1n3z/Ad4hpEZxRsHYeRhhV/EcsR/2cjFhYHqEZd1iTr4U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: ucjM+kLjSq+mL5HMa7BsCg== X-CSE-MsgGUID: dX9NeaiPQHyX1r0pa9S++Q== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 06 Feb 2025 22:41:15 +0900 Received: from localhost.localdomain (unknown [10.226.92.229]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 4F2B04019C60; Thu, 6 Feb 2025 22:41:12 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 6/8] arm64: dts: renesas: rzg3e-smarc-som: Enable SDHI{0,2} Date: Thu, 6 Feb 2025 13:40:30 +0000 Message-ID: <20250206134047.67866-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250206134047.67866-1-biju.das.jz@bp.renesas.com> References: <20250206134047.67866-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enable eMMC on SDHI0 and SD on SDHI2 on RZ/G3E SMARC SoM. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v2->v3: * Renamed node sd0emmc->sd0-emmc * Renamed sd0-emmc-{ctrl,data,rst}->sd0-{ctrl,data,rst} * Dropped header file gpio.h. * Dropped overriding internal regulator name. * Updated regulator phandle. v1->v2: * Added missing header file gpio.h * Used fixed regulator for eMMC on SD0 and dropped sd0-iovs pins for eMMC. * Sorted pinctrl nodes for sd2 * Enabled internal regulator for SD2. --- .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi index f4ba050beb0d..fcbabe2cb003 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -8,17 +8,86 @@ / { compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047"; + aliases { + mmc0 = &sdhi0; + mmc2 = &sdhi2; + }; + memory@48000000 { device_type = "memory"; /* First 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0xf8000000>; }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; }; &audio_extal_clk { clock-frequency = <48000000>; }; +&pinctrl { + sdhi0_emmc_pins: sd0-emmc { + sd0-ctrl { + pins = "SD0CLK", "SD0CMD"; + renesas,output-impedance = <3>; + }; + + sd0-data { + pins = "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3", + "SD0DAT4", "SD0DAT5", "SD0DAT6", "SD0DAT7"; + renesas,output-impedance = <3>; + }; + + sd0-rst { + pins = "SD0RSTN"; + renesas,output-impedance = <3>; + }; + }; + + sdhi2_pins: sd2 { + sd2-cd { + pinmux = ; /* SD2CD */ + }; + + sd2-ctrl { + pinmux = , /* SD2CLK */ + ; /* SD2CMD */ + }; + + sd2-data { + pinmux = , /* SD2DAT0 */ + , /* SD2DAT1 */ + , /* SD2DAT2 */ + ; /* SD2DAT3 */ + }; + + sd2-iovs { + pinmux = ; /* SD2IOVS */ + }; + + sd2-pwen { + pinmux = ; /* SD2PWEN */ + }; + }; +}; + &qextal_clk { clock-frequency = <24000000>; }; @@ -27,6 +96,37 @@ &rtxin_clk { clock-frequency = <32768>; }; +&sdhi0 { + pinctrl-0 = <&sdhi0_emmc_pins>; + pinctrl-1 = <&sdhi0_emmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + status = "okay"; +}; + +&sdhi2 { + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&sdhi2_vqmmc>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdhi2_vqmmc { + status = "okay"; +}; + &wdt1 { status = "okay"; }; From patchwork Thu Feb 6 13:40:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13963108 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CA8611EA7C2; Thu, 6 Feb 2025 13:41:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738849294; cv=none; b=AXCtIaNSg4wViEZi1geDYZWS2MaAM0LB/2UI2nodrxJuknZbE0UUz9w9OPEvQMrJ/U14+yc7r0J7NNARpKdo2nd7/dYZh73W4buU78Y7NiJLB51+lg+082tOMm7vCDHH4ZwPiKMfAKX09sB+rkevaOZz8zdkEl0hgaA2nZdFcA0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738849294; c=relaxed/simple; bh=DpQ7hSKwv0ZE/L758XqYKwTUjKGPe5DIaMuEwu8SB5A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JmeGNmpnt5jckwMSv5MTl09KmSuFMUHl0Yz2jR5xTBtVriedD204qQjsXQ+TgM9OWCQi4fOj/4+6kK4y89p2ezdO4vItsPWPrad0fNEimQaevZpvOYiPFY8pu3jk3AAMzhIj/Z5LJzj1kyc4UILGFI0drlxzclYjrxUqtfNuSdw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: aemB5odvSn2ziB2hS+Rbnw== X-CSE-MsgGUID: MBM3H5b9RQOtjgTPPHcHCw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 06 Feb 2025 22:41:30 +0900 Received: from localhost.localdomain (unknown [10.226.92.229]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id D2893401BC08; Thu, 6 Feb 2025 22:41:15 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 7/8] arm64: dts: renesas: rzg3e-smarc-som: Add support for enable SD on SDHI0 Date: Thu, 6 Feb 2025 13:40:31 +0000 Message-ID: <20250206134047.67866-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250206134047.67866-1-biju.das.jz@bp.renesas.com> References: <20250206134047.67866-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for enabling SD on SDHI0 on RZ/G3E SMARC SoM. It is enabled by setting the macro SW_SD0_DEV_SEL to 1 in board DTS and setting the switch SYS.1 to ON position on the SoM. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v2->v3: * Dropped #if guard in pinctrl node for SDHI0 * Renamed the label/node sdhi0_pins: sd0->sdhi0_usd_pins: sd0-usd. * Dropped overriding regulator name. * Updated regulator phandle. v2: * New patch --- .../boot/dts/renesas/r9a09g047e57-smarc.dts | 3 ++ .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 54 +++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index c063d47e2952..152a00aa354b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -7,6 +7,9 @@ /dts-v1/; +/* Switch selection settings */ +#define SW_SD0_DEV_SEL 0 + #include #include "r9a09g047e57.dtsi" #include "rzg3e-smarc-som.dtsi" diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi index fcbabe2cb003..1966f2ce70b8 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -5,6 +5,15 @@ * Copyright (C) 2024 Renesas Electronics Corp. */ +/* + * Please set the switch position SYS.1 on the SoM and the corresponding macro + * SW_SD0_DEV_SEL on the board DTS: + * + * SW_SD0_DEV_SEL: + * 0 - SD0 is connected to eMMC (default) + * 1 - SD0 is connected to uSD0 card + */ + / { compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047"; @@ -43,6 +52,32 @@ &audio_extal_clk { }; &pinctrl { + sdhi0_usd_pins: sd0-usd { + sd0-cd { + pinmux = ; + }; + + sd0-ctrl { + pins = "SD0CLK", "SD0CMD"; + renesas,output-impedance = <3>; + }; + + sd0-data { + pins = "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3"; + renesas,output-impedance = <3>; + }; + + sd0-iovs { + pins = "SD0IOVS"; + renesas,output-impedance = <3>; + }; + + sd0-pwen { + pins = "SD0PWEN"; + renesas,output-impedance = <3>; + }; + }; + sdhi0_emmc_pins: sd0-emmc { sd0-ctrl { pins = "SD0CLK", "SD0CMD"; @@ -96,6 +131,24 @@ &rtxin_clk { clock-frequency = <32768>; }; +#if (SW_SD0_DEV_SEL) +&sdhi0 { + pinctrl-0 = <&sdhi0_usd_pins>; + pinctrl-1 = <&sdhi0_usd_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&sdhi0_vqmmc>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdhi0_vqmmc { + status = "okay"; +}; +#else &sdhi0 { pinctrl-0 = <&sdhi0_emmc_pins>; pinctrl-1 = <&sdhi0_emmc_pins>; @@ -109,6 +162,7 @@ &sdhi0 { fixed-emmc-driver-type = <1>; status = "okay"; }; +#endif &sdhi2 { pinctrl-0 = <&sdhi2_pins>; From patchwork Thu Feb 6 13:40:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13963107 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A3B541EA7E6; Thu, 6 Feb 2025 13:41:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738849284; cv=none; b=qXYJsI5ywEkUDvfwKERiUHUr5y5LO+mhZhiV3hvFEYs0Na8tiAahlOsywlHgxyWvzD6MjPVDvlF1JHCNd2hOUfwDl8B3lgEGlauh9FWeM6m3hfAKFJpRtxjxWGMGl954JpcxSUbkuyxCzDsCI9X4KkmjO37rbXNouh2pP0WNEOs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738849284; c=relaxed/simple; bh=3kz+7Vs0zqj/PvRtFzztlBaYM3X6IkOs6QTrXY46dZ0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=M0u1BQOLRcz5QUE62uXUa7dX3iVskKq/GNECxXRdQmYc/3weDxAa6vkvJ60k0YEFyarsYpJyOVQSdVoYq2jnTDJmU4U3A7/cdWby9jCz1yRimJ6vxvVvycWbSuR1IIaLPmfVHmKArvl+NbV4gm99XJpbMe86sPcGUJAeQT4tt6E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: EhVsAoveQMOtfsAIDaVbag== X-CSE-MsgGUID: 8cfiY52QS/mKy0B8YQ7X9g== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 06 Feb 2025 22:41:22 +0900 Received: from localhost.localdomain (unknown [10.226.92.229]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 63AAA4019C60; Thu, 6 Feb 2025 22:41:19 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 8/8] arm64: dts: renesas: r9a09g047e57-smarc: Enable SDHI1 Date: Thu, 6 Feb 2025 13:40:32 +0000 Message-ID: <20250206134047.67866-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250206134047.67866-1-biju.das.jz@bp.renesas.com> References: <20250206134047.67866-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enable SDHI1 on the RZ/G3E SMARC EVK platform using gpio regulator for voltage switching. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v2->v3: * Added header file gpio.h. v1->v2: * Replaced the regulator usd_vdd_3p3v->reg_3p3v. * Renamed the gpio-hog node sd1-pwr-en->sd1-pwr-en-hog. * Sorted sd1 pin ctrl nodes. --- .../boot/dts/renesas/r9a09g047e57-smarc.dts | 46 +++++++++++++++++++ .../boot/dts/renesas/renesas-smarc2.dtsi | 18 ++++++++ 2 files changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index 152a00aa354b..5d7983812c70 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -9,7 +9,9 @@ /* Switch selection settings */ #define SW_SD0_DEV_SEL 0 +#define SW_SDIO_M2E 0 +#include #include #include "r9a09g047e57.dtsi" #include "rzg3e-smarc-som.dtsi" @@ -19,6 +21,16 @@ / { model = "Renesas SMARC EVK version 2 based on r9a09g047e57"; compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047"; + + vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd { + compatible = "regulator-gpio"; + regulator-name = "SD1_PVDD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG3E_GPIO(1, 5) GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <3300000 0>, <1800000 1>; + }; }; &pinctrl { @@ -26,9 +38,43 @@ scif_pins: scif { pins = "SCIF_TXD", "SCIF_RXD"; renesas,output-impedance = <1>; }; + + sd1-pwr-en-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "sd1_pwr_en"; + }; + + sdhi1_pins: sd1 { + sd1-cd { + pinmux = ; /* SD1CD */ + }; + + sd1-ctrl { + pinmux = , /* SD1CLK */ + ; /* SD1CMD */ + }; + + sd1-data { + pinmux = , /* SD1DAT0 */ + , /* SD1DAT1 */ + , /* SD1DAT2 */ + ; /* SD1DAT3 */ + }; + }; }; &scif0 { pinctrl-0 = <&scif_pins>; pinctrl-names = "default"; }; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vqmmc_sd1_pvdd>; +}; diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi index e378d55e6e9b..fd82df8adc1e 100644 --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi @@ -5,6 +5,15 @@ * Copyright (C) 2024 Renesas Electronics Corp. */ +/* + * Please set the switch position SW_OPT_MUX.1 on the carrier board and the + * corresponding macro SW_SDIO_M2E on the board DTS: + * + * SW_SDIO_M2E: + * 0 - SMARC SDIO signal is connected to uSD1 + * 1 - SMARC SDIO signal is connected to M.2 Key E connector + */ + / { model = "Renesas RZ SMARC Carrier-II Board"; compatible = "renesas,smarc2-evk"; @@ -16,9 +25,18 @@ chosen { aliases { serial3 = &scif0; + mmc1 = &sdhi1; }; }; &scif0 { status = "okay"; }; + +&sdhi1 { + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + + status = "okay"; +};